1993e3fafSRobert Mustacchi /* 2993e3fafSRobert Mustacchi * Copyright (c) 2014 Martin Pieuchot. All rights reserved. 3993e3fafSRobert Mustacchi * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4*672fc84aSRobert Mustacchi * Copyright (c) 2018, Joyent, Inc. 5993e3fafSRobert Mustacchi * 6993e3fafSRobert Mustacchi * Redistribution and use in source and binary forms, with or without 7993e3fafSRobert Mustacchi * modification, are permitted provided that the following conditions 8993e3fafSRobert Mustacchi * are met: 9993e3fafSRobert Mustacchi * 1. Redistributions of source code must retain the above copyright 10993e3fafSRobert Mustacchi * notice, this list of conditions and the following disclaimer. 11993e3fafSRobert Mustacchi * 2. Redistributions in binary form must reproduce the above copyright 12993e3fafSRobert Mustacchi * notice, this list of conditions and the following disclaimer in the 13993e3fafSRobert Mustacchi * documentation and/or other materials provided with the distribution. 14993e3fafSRobert Mustacchi * 15993e3fafSRobert Mustacchi * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16993e3fafSRobert Mustacchi * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17993e3fafSRobert Mustacchi * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18993e3fafSRobert Mustacchi * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19993e3fafSRobert Mustacchi * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20993e3fafSRobert Mustacchi * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21993e3fafSRobert Mustacchi * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22993e3fafSRobert Mustacchi * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23993e3fafSRobert Mustacchi * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24993e3fafSRobert Mustacchi * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25993e3fafSRobert Mustacchi * SUCH DAMAGE. 26993e3fafSRobert Mustacchi */ 27993e3fafSRobert Mustacchi 28993e3fafSRobert Mustacchi #ifndef _SYS_USB_HCD_XHCI_XHCIREG_H 29993e3fafSRobert Mustacchi #define _SYS_USB_HCD_XHCI_XHCIREG_H 30993e3fafSRobert Mustacchi 31993e3fafSRobert Mustacchi /* 32993e3fafSRobert Mustacchi * xHCI Register and Field Definitions 33993e3fafSRobert Mustacchi */ 34993e3fafSRobert Mustacchi 35993e3fafSRobert Mustacchi #ifdef __cplusplus 36993e3fafSRobert Mustacchi extern "C" { 37993e3fafSRobert Mustacchi #endif 38993e3fafSRobert Mustacchi 39993e3fafSRobert Mustacchi /* 40993e3fafSRobert Mustacchi * xHCI PCI config registers 41993e3fafSRobert Mustacchi */ 42993e3fafSRobert Mustacchi #define PCI_XHCI_CBMEM 0x10 /* configuration base MEM */ 43993e3fafSRobert Mustacchi #define PCI_XHCI_USBREV 0x60 /* RO USB protocol revision */ 44993e3fafSRobert Mustacchi #define PCI_USB_REV_3_0 0x30 /* USB 3.0 */ 45993e3fafSRobert Mustacchi #define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ 46993e3fafSRobert Mustacchi 47993e3fafSRobert Mustacchi #define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */ 48993e3fafSRobert Mustacchi #define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */ 49993e3fafSRobert Mustacchi #define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */ 50993e3fafSRobert Mustacchi #define PCI_XHCI_INTEL_USB3PRM 0xDC /* Intel USB3 Port Routing Mask */ 51993e3fafSRobert Mustacchi 52993e3fafSRobert Mustacchi /* 53993e3fafSRobert Mustacchi * xHCI capability registers 54993e3fafSRobert Mustacchi */ 55993e3fafSRobert Mustacchi #define XHCI_CAPLENGTH 0x00 /* RO capability */ 56993e3fafSRobert Mustacchi #define XHCI_RESERVED 0x01 /* Reserved */ 57993e3fafSRobert Mustacchi #define XHCI_HCIVERSION 0x02 /* RO Interface version number */ 58993e3fafSRobert Mustacchi #define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ 59993e3fafSRobert Mustacchi #define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ 60993e3fafSRobert Mustacchi 616f2302d2SRobert Mustacchi #define XHCI_VERSION_MASK(x) (((x) >> 16) & 0xffff) 626f2302d2SRobert Mustacchi 63993e3fafSRobert Mustacchi /* 64993e3fafSRobert Mustacchi * Structural Parameters 1 - xHCI 1.1 / 5.3.3 65993e3fafSRobert Mustacchi */ 66993e3fafSRobert Mustacchi #define XHCI_HCSPARAMS1 0x04 67993e3fafSRobert Mustacchi #define XHCI_HCS1_DEVSLOT_MAX(x) ((x) & 0xFF) 68993e3fafSRobert Mustacchi #define XHCI_HCS1_IRQ_MAX(x) (((x) >> 8) & 0x3FF) 69993e3fafSRobert Mustacchi #define XHCI_HCS1_N_PORTS(x) (((x) >> 24) & 0xFF) 70993e3fafSRobert Mustacchi 71993e3fafSRobert Mustacchi /* 72993e3fafSRobert Mustacchi * Structural Parameters 2 - xHCI 1.1 / 5.3.4 73993e3fafSRobert Mustacchi */ 74993e3fafSRobert Mustacchi #define XHCI_HCSPARAMS2 0x08 75993e3fafSRobert Mustacchi #define XHCI_HCS2_IST(x) ((x) & 0x7) 76993e3fafSRobert Mustacchi #define XHCI_HCS2_IST_MICRO(x) (!((x) & 0x8)) 77993e3fafSRobert Mustacchi #define XHCI_HCS2_ERST_MAX(x) (((x) >> 4) & 0xF) 78993e3fafSRobert Mustacchi #define XHCI_HCS2_SPR(x) (((x) >> 24) & 0x1) 79993e3fafSRobert Mustacchi #define XHCI_HCS2_SPB_MAX(x) ((((x) >> 16) & 0x3e0) | (((x) >> 27) & 0x1f)) 80993e3fafSRobert Mustacchi 81993e3fafSRobert Mustacchi /* 82993e3fafSRobert Mustacchi * Structural Parameters 3 - xHCI 1.1 / 5.3.5 83993e3fafSRobert Mustacchi */ 84993e3fafSRobert Mustacchi #define XHCI_HCSPARAMS3 0x0C 85993e3fafSRobert Mustacchi #define XHCI_HCS3_U1_DEL(x) ((x) & 0xFF) 86993e3fafSRobert Mustacchi #define XHCI_HCS3_U2_DEL(x) (((x) >> 16) & 0xFFFF) 87993e3fafSRobert Mustacchi 88993e3fafSRobert Mustacchi /* 89993e3fafSRobert Mustacchi * Capability Parameters 1 - xHCI 1.1 / 5.3.6 90993e3fafSRobert Mustacchi */ 91993e3fafSRobert Mustacchi #define XHCI_HCCPARAMS1 0x10 92993e3fafSRobert Mustacchi #define XHCI_HCC1_FLAGS_MASK(x) ((x) & 0x7FF) 93993e3fafSRobert Mustacchi #define XHCI_HCC1_PSA_SZ_MAX(x) (((x) >> 12) & 0xF) 94993e3fafSRobert Mustacchi #define XHCI_HCC1_XECP(x) (((x) >> 16) & 0xFFFF) 95993e3fafSRobert Mustacchi 96993e3fafSRobert Mustacchi /* 97993e3fafSRobert Mustacchi * Capability Parameters 1 - xHCI 1.1 / 5.3.9 98993e3fafSRobert Mustacchi */ 99993e3fafSRobert Mustacchi #define XHCI_HCCPARAMS2 0x1C 100993e3fafSRobert Mustacchi #define XHCI_HCC2_FLAGS_MASK(x) ((x) & 0x3F) 101993e3fafSRobert Mustacchi 102993e3fafSRobert Mustacchi #define XHCI_DBOFF 0x14 /* RO doorbell offset */ 103993e3fafSRobert Mustacchi #define XHCI_RTSOFF 0x18 /* RO runtime register space offset */ 104993e3fafSRobert Mustacchi 105993e3fafSRobert Mustacchi /* 106993e3fafSRobert Mustacchi * xHCI operational registers. 107993e3fafSRobert Mustacchi * Offset given by XHCI_CAPLENGTH register 108993e3fafSRobert Mustacchi */ 109993e3fafSRobert Mustacchi #define XHCI_USBCMD 0x00 /* XHCI command */ 110993e3fafSRobert Mustacchi #define XHCI_CMD_RS 0x00000001 /* RW Run/Stop */ 111993e3fafSRobert Mustacchi #define XHCI_CMD_HCRST 0x00000002 /* RW HC Reset */ 112993e3fafSRobert Mustacchi #define XHCI_CMD_INTE 0x00000004 /* RW Interrupter Enable */ 113993e3fafSRobert Mustacchi #define XHCI_CMD_HSEE 0x00000008 /* RW System Error Enable */ 114993e3fafSRobert Mustacchi #define XHCI_CMD_LHCRST 0x00000080 /* RW Light HC Reset */ 115993e3fafSRobert Mustacchi #define XHCI_CMD_CSS 0x00000100 /* RW Controller Save */ 116993e3fafSRobert Mustacchi #define XHCI_CMD_CRS 0x00000200 /* RW Controller Restore */ 117993e3fafSRobert Mustacchi #define XHCI_CMD_EWE 0x00000400 /* RW Enable Wrap Event */ 118993e3fafSRobert Mustacchi #define XHCI_CMD_EU3S 0x00000800 /* RW Enable U3 MFINDEX Stop */ 119993e3fafSRobert Mustacchi 120993e3fafSRobert Mustacchi 121993e3fafSRobert Mustacchi #define XHCI_USBSTS 0x04 /* XHCI status */ 122993e3fafSRobert Mustacchi #define XHCI_STS_HCH 0x00000001 /* RO - HC Halted */ 123993e3fafSRobert Mustacchi #define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */ 124993e3fafSRobert Mustacchi #define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */ 125993e3fafSRobert Mustacchi #define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */ 126993e3fafSRobert Mustacchi #define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */ 127993e3fafSRobert Mustacchi #define XHCI_STS_RSS 0x00000200 /* RO - Restore State Status */ 128993e3fafSRobert Mustacchi #define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */ 129993e3fafSRobert Mustacchi #define XHCI_STS_CNR 0x00000800 /* RO - Controller Not Ready */ 130993e3fafSRobert Mustacchi #define XHCI_STS_HCE 0x00001000 /* RO - HC Error */ 131993e3fafSRobert Mustacchi 132993e3fafSRobert Mustacchi #define XHCI_PAGESIZE 0x08 /* XHCI page size mask */ 133993e3fafSRobert Mustacchi #define XHCI_PAGESIZE_4K 0x00000001 /* 4K Page Size */ 134993e3fafSRobert Mustacchi #define XHCI_PAGESIZE_8K 0x00000002 /* 8K Page Size */ 135993e3fafSRobert Mustacchi #define XHCI_PAGESIZE_16K 0x00000004 /* 16K Page Size */ 136993e3fafSRobert Mustacchi #define XHCI_PAGESIZE_32K 0x00000008 /* 32K Page Size */ 137993e3fafSRobert Mustacchi #define XHCI_PAGESIZE_64K 0x00000010 /* 64K Page Size */ 138993e3fafSRobert Mustacchi 139993e3fafSRobert Mustacchi #define XHCI_DNCTRL 0x14 /* XHCI device notification control */ 140993e3fafSRobert Mustacchi #define XHCI_DNCTRL_MASK(n) (1U << (n)) 141993e3fafSRobert Mustacchi 142993e3fafSRobert Mustacchi #define XHCI_CRCR 0x18 /* XHCI command ring control */ 143993e3fafSRobert Mustacchi #define XHCI_CRCR_RCS 0x00000001 /* RW - consumer cycle state */ 144993e3fafSRobert Mustacchi #define XHCI_CRCR_CS 0x00000002 /* RW - command stop */ 145993e3fafSRobert Mustacchi #define XHCI_CRCR_CA 0x00000004 /* RW - command abort */ 146993e3fafSRobert Mustacchi #define XHCI_CRCR_CRR 0x00000008 /* RW - command ring running */ 147993e3fafSRobert Mustacchi #define XHCI_CRCR_MASK 0x0000000F 148993e3fafSRobert Mustacchi 149993e3fafSRobert Mustacchi /* 150993e3fafSRobert Mustacchi * Device context base address pointer register. 151993e3fafSRobert Mustacchi */ 152993e3fafSRobert Mustacchi #define XHCI_DCBAAP 0x30 153993e3fafSRobert Mustacchi 154993e3fafSRobert Mustacchi #define XHCI_CONFIG 0x38 155993e3fafSRobert Mustacchi #define XHCI_CONFIG_SLOTS_MASK 0x000000FF 156993e3fafSRobert Mustacchi 157993e3fafSRobert Mustacchi /* 158993e3fafSRobert Mustacchi * xHCI Port Status Registers and bits. See xHCI 1.1 / 5.4.8. 159993e3fafSRobert Mustacchi */ 160993e3fafSRobert Mustacchi #define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) /* XHCI port status */ 161993e3fafSRobert Mustacchi #define XHCI_PS_CCS 0x00000001 /* RO - current connect status */ 162993e3fafSRobert Mustacchi #define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */ 163993e3fafSRobert Mustacchi #define XHCI_PS_OCA 0x00000008 /* RO - over current active */ 164993e3fafSRobert Mustacchi #define XHCI_PS_PR 0x00000010 /* RW - port reset */ 165993e3fafSRobert Mustacchi #define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */ 166993e3fafSRobert Mustacchi #define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */ 167993e3fafSRobert Mustacchi #define XHCI_PS_PP 0x00000200 /* RW - port power */ 168993e3fafSRobert Mustacchi #define XHCI_PS_SPEED_GET(x) (((x) >> 10) & 0xF) /* RO - port speed */ 169993e3fafSRobert Mustacchi #define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */ 170993e3fafSRobert Mustacchi #define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */ 171993e3fafSRobert Mustacchi #define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */ 172993e3fafSRobert Mustacchi #define XHCI_PS_CSC 0x00020000 /* RW - connect status change */ 173993e3fafSRobert Mustacchi #define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */ 174993e3fafSRobert Mustacchi #define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */ 175993e3fafSRobert Mustacchi #define XHCI_PS_OCC 0x00100000 /* RW - over-current change */ 176993e3fafSRobert Mustacchi #define XHCI_PS_PRC 0x00200000 /* RW - port reset change */ 177993e3fafSRobert Mustacchi #define XHCI_PS_PLC 0x00400000 /* RW - port link state change */ 178993e3fafSRobert Mustacchi #define XHCI_PS_CEC 0x00800000 /* RW - config error change */ 179993e3fafSRobert Mustacchi #define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */ 180993e3fafSRobert Mustacchi #define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */ 181993e3fafSRobert Mustacchi #define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */ 182993e3fafSRobert Mustacchi #define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */ 183993e3fafSRobert Mustacchi #define XHCI_PS_DR 0x40000000 /* RO - device removable */ 184993e3fafSRobert Mustacchi #define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */ 185993e3fafSRobert Mustacchi #define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */ 186993e3fafSRobert Mustacchi #define XHCI_PS_INDPORT(x) ((x) & 0xFF) 187993e3fafSRobert Mustacchi #define XHCI_PS_INDVAL(x) (((x) & 0xFF00) >> 8) 188993e3fafSRobert Mustacchi 189993e3fafSRobert Mustacchi /* 190993e3fafSRobert Mustacchi * xHCI Port Power Management and Control Register. See xHCI 1.1 / 5.4.9. 191993e3fafSRobert Mustacchi */ 192993e3fafSRobert Mustacchi #define XHCI_PORTPMSC(n) (0x3F4 + (0x10 * (n))) 193993e3fafSRobert Mustacchi #define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */ 194993e3fafSRobert Mustacchi #define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */ 195993e3fafSRobert Mustacchi #define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */ 196993e3fafSRobert Mustacchi #define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */ 197993e3fafSRobert Mustacchi #define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */ 198993e3fafSRobert Mustacchi #define XHCI_PM2_L1S_GET(x) (((x) >> 0) & 0x7) /* RO - L1 status */ 199993e3fafSRobert Mustacchi #define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */ 200993e3fafSRobert Mustacchi /* RW - host initiated resume durations */ 201993e3fafSRobert Mustacchi #define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) 202993e3fafSRobert Mustacchi #define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) 203993e3fafSRobert Mustacchi #define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */ 204993e3fafSRobert Mustacchi #define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */ 205993e3fafSRobert Mustacchi #define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */ 206993e3fafSRobert Mustacchi #define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* RO - port link info */ 207993e3fafSRobert Mustacchi #define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errs */ 208993e3fafSRobert Mustacchi #define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */ 209993e3fafSRobert Mustacchi 210993e3fafSRobert Mustacchi /* 211993e3fafSRobert Mustacchi * xHCI runtime registers - xHCI 1.1 / 5.5. 212993e3fafSRobert Mustacchi * Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers. 213993e3fafSRobert Mustacchi */ 214993e3fafSRobert Mustacchi #define XHCI_MFINDEX 0x0000 /* RO - microframe index */ 215993e3fafSRobert Mustacchi #define XHCI_MFINDEX_GET(x) ((x) & 0x3FFF) 216993e3fafSRobert Mustacchi #define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) /* XHCI interrupt */ 217993e3fafSRobert Mustacchi /* management */ 218993e3fafSRobert Mustacchi #define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */ 219993e3fafSRobert Mustacchi #define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */ 220993e3fafSRobert Mustacchi 221993e3fafSRobert Mustacchi /* 222993e3fafSRobert Mustacchi * XHCI Interrupt moderation 223993e3fafSRobert Mustacchi */ 224993e3fafSRobert Mustacchi #define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) 225993e3fafSRobert Mustacchi 226993e3fafSRobert Mustacchi /* 227993e3fafSRobert Mustacchi * XHCI event ring segment table size 228993e3fafSRobert Mustacchi */ 229993e3fafSRobert Mustacchi #define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) 230993e3fafSRobert Mustacchi #define XHCI_ERSTS_MASK 0xffff 231993e3fafSRobert Mustacchi #define XHCI_ERSTS_SET(x) ((x) & XHCI_ERSTS_MASK) 232993e3fafSRobert Mustacchi 233993e3fafSRobert Mustacchi /* 234993e3fafSRobert Mustacchi * XHCI event ring segment table BA 235993e3fafSRobert Mustacchi */ 236993e3fafSRobert Mustacchi #define XHCI_ERSTBA(n) (0x0030 + (0x20 * (n))) 237993e3fafSRobert Mustacchi 238993e3fafSRobert Mustacchi /* 239993e3fafSRobert Mustacchi * XHCI event ring dequeue pointer 240993e3fafSRobert Mustacchi */ 241993e3fafSRobert Mustacchi #define XHCI_ERDP(n) (0x0038 + (0x20 * (n))) 242993e3fafSRobert Mustacchi #define XHCI_ERDP_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */ 243993e3fafSRobert Mustacchi #define XHCI_ERDP_BUSY 0x00000008 /* RW - event handler busy */ 244993e3fafSRobert Mustacchi 245993e3fafSRobert Mustacchi /* 246993e3fafSRobert Mustacchi * XHCI doorbell registers - xHCI 1.1 / 5.6. 247993e3fafSRobert Mustacchi * Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers 248993e3fafSRobert Mustacchi */ 249993e3fafSRobert Mustacchi #define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 250993e3fafSRobert Mustacchi #define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) 251993e3fafSRobert Mustacchi #define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) 252993e3fafSRobert Mustacchi #define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) 253993e3fafSRobert Mustacchi #define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) 254993e3fafSRobert Mustacchi 255993e3fafSRobert Mustacchi /* 256993e3fafSRobert Mustacchi * XHCI capability IDs - xHCI 1.1 / 7 - Table 146 257993e3fafSRobert Mustacchi */ 258993e3fafSRobert Mustacchi #define XHCI_ID_XECP_DONE 0x0000 259993e3fafSRobert Mustacchi #define XHCI_ID_USB_LEGACY 0x0001 260993e3fafSRobert Mustacchi #define XHCI_ID_PROTOCOLS 0x0002 261993e3fafSRobert Mustacchi #define XHCI_ID_POWER_MGMT 0x0003 262993e3fafSRobert Mustacchi #define XHCI_ID_VIRTUALIZATION 0x0004 263993e3fafSRobert Mustacchi #define XHCI_ID_MSG_IRQ 0x0005 264993e3fafSRobert Mustacchi #define XHCI_ID_USB_LOCAL_MEM 0x0006 265993e3fafSRobert Mustacchi #define XHCI_ID_DEBUG 0x000A 266993e3fafSRobert Mustacchi #define XHCI_ID_EXT_MSG_IRQ 0x0011 267993e3fafSRobert Mustacchi 268993e3fafSRobert Mustacchi #define XHCI_XECP_ID(x) ((x) & 0xFF) 269993e3fafSRobert Mustacchi #define XHCI_XECP_NEXT(x) (((x) >> 8) & 0xFF) 270993e3fafSRobert Mustacchi 271993e3fafSRobert Mustacchi /* 272993e3fafSRobert Mustacchi * xHCI USB Legacy Support Capability - xHCI 1.1 / 7.1. 273993e3fafSRobert Mustacchi */ 274993e3fafSRobert Mustacchi #define XHCI_BIOS_OWNED (1 << 16) 275993e3fafSRobert Mustacchi #define XHCI_OS_OWNED (1 << 24) 276993e3fafSRobert Mustacchi 277993e3fafSRobert Mustacchi /* 278993e3fafSRobert Mustacchi * These definitions manipulate the generation of SMIs. Note that the contents 279993e3fafSRobert Mustacchi * of reserved registers are required to be preserved. In addition, Several of 280993e3fafSRobert Mustacchi * the bits require you to write one to clear. 281993e3fafSRobert Mustacchi */ 282993e3fafSRobert Mustacchi #define XHCI_XECP_LEGCTLSTS 0x04 283993e3fafSRobert Mustacchi #define XHCI_XECP_SMI_MASK (0x7 << 1) + (0xff << 5) + (0x7UL << 17) 284993e3fafSRobert Mustacchi #define XHCI_XECP_CLEAR_SMI (0x7UL << 29) 285993e3fafSRobert Mustacchi 286993e3fafSRobert Mustacchi /* 287993e3fafSRobert Mustacchi * xHCI Supported Protocol Capability. See xHCI 1.1 / 7.2. 288993e3fafSRobert Mustacchi */ 289*672fc84aSRobert Mustacchi #define XHCI_XECP_PROT_MAJOR(x) (((x) >> 24) & 0xff) 290*672fc84aSRobert Mustacchi #define XHCI_XECP_PROT_MINOR(x) (((x) >> 16) & 0xff) 291*672fc84aSRobert Mustacchi #define XHCI_XECP_PROT_PCOUNT(x) (((x) >> 8) & 0xff) 292*672fc84aSRobert Mustacchi #define XHCI_XECP_PROT_FPORT(x) ((x) & 0xff) 293993e3fafSRobert Mustacchi 294993e3fafSRobert Mustacchi /* 295993e3fafSRobert Mustacchi * xHCI Slot Context definitions - xHCI 1.1 / 6.2.2. 296993e3fafSRobert Mustacchi */ 297993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_ROUTE(x) ((x) & 0xfffff) 298993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_ROUTE(x) ((x) & 0xfffff) 299993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_SPEED(x) (((x) >> 20) & 0xf) 300993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_SPEED(x) (((x) & 0xf) << 20) 301993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_MTT(x) (((x) >> 25) & 0x1) 302993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_MTT(x) (((x) & 0x1) << 25) 303993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_HUB(x) (((x) >> 26) & 0x1) 304993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_HUB(x) (((x) & 0x1) << 26) 305993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_DCI(x) (((x) >> 27) & 0x1f) 306993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_DCI(x) (((x) & 0x1f) << 27) 307993e3fafSRobert Mustacchi #define XHCI_SCTX_DCI_MASK (0x1fUL << 27) 308993e3fafSRobert Mustacchi 309993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_MAX_EL(x) ((x) & 0xffff) 310993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_MAX_EL(x) ((x) & 0xffff) 311993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_RHPORT(x) (((x) >> 16) & 0xff) 312993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_RHPORT(x) (((x) & 0xff) << 16) 313993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_NPORTS(x) (((x) >> 24) & 0xff) 314993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_NPORTS(x) (((x) & 0xff) << 24) 315993e3fafSRobert Mustacchi 316993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_TT_HUB_SID(x) ((x) & 0xff) 317993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_TT_HUB_SID(x) ((x) & 0xff) 318993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_TT_PORT_NUM(x) (((x) >> 8) & 0xff) 319993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_TT_PORT_NUM(x) (((x) & 0xff) << 8) 320993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_TT_THINK_TIME(x) (((x) >> 16) & 0x3) 321993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_TT_THINK_TIME(x) (((x) & 0x3) << 16) 322993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_IRQ_TARGET(x) (((x) & 0x3ff) << 22) 323993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_IRQ_TARGET(x) (((x) >> 22) & 0x3ff) 324993e3fafSRobert Mustacchi 325993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_DEV_ADDR(x) ((x) & 0xff) 326993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_SLOT_STATE(x) (((x) >> 27) & 0x1f) 327993e3fafSRobert Mustacchi 328993e3fafSRobert Mustacchi #define XHCI_SLOT_DIS_ENAB 0 329993e3fafSRobert Mustacchi #define XHCI_SLOT_DEFAULT 1 330993e3fafSRobert Mustacchi #define XHCI_SLOT_ADDRESSED 2 331993e3fafSRobert Mustacchi #define XHCI_SLOT_CONFIGURED 3 332993e3fafSRobert Mustacchi 333993e3fafSRobert Mustacchi /* 334993e3fafSRobert Mustacchi * xHCI Slot Context definitions - xHCI 1.1 / 6.2.3. 335993e3fafSRobert Mustacchi */ 336993e3fafSRobert Mustacchi #define XHCI_EPCTX_STATE(x) ((x) & 0x7) 337993e3fafSRobert Mustacchi #define XHCI_EP_DISABLED 0x0 338993e3fafSRobert Mustacchi #define XHCI_EP_RUNNING 0x1 339993e3fafSRobert Mustacchi #define XHCI_EP_HALTED 0x2 340993e3fafSRobert Mustacchi #define XHCI_EP_STOPPED 0x3 341993e3fafSRobert Mustacchi #define XHCI_EP_ERROR 0x4 342993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_MULT(x) (((x) & 0x3) << 8) 343993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_MULT(x) (((x) >> 8) & 0x3) 344993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_MAXP_STREAMS(x) (((x) & 0x1F) << 10) 345993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_MAXP_STREAMS(x) (((x) >> 10) & 0x1F) 346993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_LSA(x) (((x) & 0x1) << 15) 347993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_LSA(x) (((x) >> 15) & 0x1) 348993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_IVAL(x) (((x) & 0xff) << 16) 349993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_IVAL(x) (((x) >> 16) & 0xFF) 350993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_MAX_ESIT_HI(x) ((((x) >> 24) & 0xFF) << 16) 351993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_MAX_ESIT_HI(x) ((((x) >> 16) & 0xFF) << 24) 352993e3fafSRobert Mustacchi 353993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_CERR(x) (((x) >> 1) & 0x3) 354993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_CERR(x) (((x) & 0x3) << 1) 355993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_EPTYPE(x) (((x) & 0x7) << 3) 356993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_EPTYPE(x) (((x) >> 3) & 0x7) 357993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_HID(x) (((x) & 0x1) << 7) 358993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_HID(x) (((x) >> 7) & 0x1) 359993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_MAXB(x) (((x) & 0xff) << 8) 360993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_MAXB(x) (((x) >> 8) & 0xff) 361993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_MPS(x) (((x) & 0xffff) << 16) 362993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_MPS(x) (((x) >> 16) & 0xffff) 363993e3fafSRobert Mustacchi #define XHCI_SPEED_FULL 1 364993e3fafSRobert Mustacchi #define XHCI_SPEED_LOW 2 365993e3fafSRobert Mustacchi #define XHCI_SPEED_HIGH 3 366993e3fafSRobert Mustacchi #define XHCI_SPEED_SUPER 4 367993e3fafSRobert Mustacchi 368993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_ISOCH_OUT (1) 369993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_BULK_OUT (2) 370993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_INTR_OUT (3) 371993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_CTRL (4) 372993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_ISOCH_IN (5) 373993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_BULK_IN (6) 374993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_INTR_IN (7) 375993e3fafSRobert Mustacchi 376993e3fafSRobert Mustacchi #define XHCI_EPCTX_AVG_TRB_LEN(x) ((x) & 0xffff) 377993e3fafSRobert Mustacchi #define XHCI_EPCTX_MAX_ESIT_PAYLOAD(x) (((x) & 0xffff) << 16) 378993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_MAX_ESIT_PAYLOAD(x) (((x) >> 16) & 0xffff) 379993e3fafSRobert Mustacchi 380993e3fafSRobert Mustacchi #define XHCI_INCTX_MASK_DCI(n) (0x1 << (n)) 381993e3fafSRobert Mustacchi 382993e3fafSRobert Mustacchi /* 383993e3fafSRobert Mustacchi * Transfer Request Block definitions. 384993e3fafSRobert Mustacchi */ 385993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_MASK 0xfc00 386993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE(x) (((x) & XHCI_TRB_TYPE_MASK) >> 10) 387993e3fafSRobert Mustacchi #define XHCI_TRB_PORTID(x) (((x) & (0xffUL << 24)) >> 24) /* Port ID */ 388993e3fafSRobert Mustacchi #define XHCI_TRB_MAXSIZE (64 * 1024) 389993e3fafSRobert Mustacchi 390993e3fafSRobert Mustacchi #define XHCI_TRB_GET_CODE(x) (((x) >> 24) & 0xff) /* Get TRB code */ 391993e3fafSRobert Mustacchi #define XHCI_TRB_TDREM(x) (((x) & 0x1f) << 17) /* Set TD remaining len. */ 392993e3fafSRobert Mustacchi #define XHCI_TRB_GET_TDREM(x) (((x) >> 17) & 0x1f) /* Get TD remaining len. */ 393993e3fafSRobert Mustacchi #define XHCI_TRB_REMAIN(x) ((x) & 0xffffff) /* Remaining length */ 394993e3fafSRobert Mustacchi #define XHCI_TRB_LEN(x) ((x) & 0x1ffff) /* Transfer length */ 395993e3fafSRobert Mustacchi #define XHCI_TRB_INTR(x) (((x) & 0x3ff) << 22) /* Set MSI-X target */ 396993e3fafSRobert Mustacchi #define XHCI_TRB_GET_INTR(x) (((x) >> 22) & 0x3ff) /* Get MSI-X target */ 397993e3fafSRobert Mustacchi 398993e3fafSRobert Mustacchi /* 399993e3fafSRobert Mustacchi * TRB flags that are used between different different TRB types. 400993e3fafSRobert Mustacchi */ 401*672fc84aSRobert Mustacchi #define XHCI_TRB_CYCLE (1 << 0) /* Enqueue point of xfer ring */ 402993e3fafSRobert Mustacchi #define XHCI_TRB_ENT (1 << 1) /* Evaluate next TRB */ 403993e3fafSRobert Mustacchi #define XHCI_TRB_LINKSEG XHCI_TRB_ENT /* Link to next segment */ 404993e3fafSRobert Mustacchi #define XHCI_TRB_ISP (1 << 2) /* Interrupt on short packet */ 405993e3fafSRobert Mustacchi #define XHCI_TRB_NOSNOOP (1 << 3) /* PCIe no snoop */ 406993e3fafSRobert Mustacchi #define XHCI_TRB_CHAIN (1 << 4) /* Chained with next TRB */ 407993e3fafSRobert Mustacchi #define XHCI_TRB_IOC (1 << 5) /* Interrupt On Completion */ 408993e3fafSRobert Mustacchi #define XHCI_TRB_IDT (1 << 6) /* Immediate Data */ 409993e3fafSRobert Mustacchi #define XHCI_TRB_GET_TBC(x) (((x) >> 7) & 0x3) /* Get/Set Transfer */ 410993e3fafSRobert Mustacchi #define XHCI_TRB_SET_TBC(x) (((x) & 0x3) << 7) /* Burst Count */ 411993e3fafSRobert Mustacchi #define XHCI_TRB_BSR (1 << 9) /* Block Set Address */ 412993e3fafSRobert Mustacchi #define XHCI_TRB_DCEP (1 << 9) /* Deconfigure endpoint */ 413993e3fafSRobert Mustacchi #define XHCI_TRB_TSP (1 << 9) /* Transfer State Preserve */ 414993e3fafSRobert Mustacchi #define XHCI_TRB_BEI (1 << 9) /* Block Event Interrupt */ 415993e3fafSRobert Mustacchi #define XHCI_TRB_DIR_IN (1 << 16) 416993e3fafSRobert Mustacchi #define XHCI_TRB_TRT_OUT (2 << 16) 417993e3fafSRobert Mustacchi #define XHCI_TRB_TRT_IN (3 << 16) 418993e3fafSRobert Mustacchi #define XHCI_TRB_GET_CYCLE(x) ((x) & 0x1) 419993e3fafSRobert Mustacchi #define XHCI_TRB_GET_ED(x) (((x) >> 2) & 0x1) 420993e3fafSRobert Mustacchi #define XHCI_TRB_GET_FLAGS(x) ((x) & 0x1ff) 421993e3fafSRobert Mustacchi #define XHCI_TRB_GET_TYPE(x) (((x) >> 10) & 0x3f) 422993e3fafSRobert Mustacchi #define XHCI_TRB_GET_EP(x) (((x) >> 16) & 0x1f) 423993e3fafSRobert Mustacchi #define XHCI_TRB_SET_EP(x) (((x) & 0x1f) << 16) 424993e3fafSRobert Mustacchi #define XHCI_TRB_GET_STYPE(x) (((x) >> 16) & 0x1f) 425993e3fafSRobert Mustacchi #define XHCI_TRB_SET_STYPE(x) (((x) & 0x1f) << 16) 426993e3fafSRobert Mustacchi #define XHCI_TRB_GET_SLOT(x) (((x) >> 24) & 0xff) 427993e3fafSRobert Mustacchi #define XHCI_TRB_SET_SLOT(x) (((x) & 0xff) << 24) 428993e3fafSRobert Mustacchi 429993e3fafSRobert Mustacchi /* 430993e3fafSRobert Mustacchi * Isochronous specific fields. See xHCI 1.1 / 6.4.1.3. 431993e3fafSRobert Mustacchi */ 432993e3fafSRobert Mustacchi #define XHCI_TRB_GET_TLBPC(x) (((x) >> 16) & 0xf) 433993e3fafSRobert Mustacchi #define XHCI_TRB_SET_TLBPC(x) (((x) & 0xf) << 16) 434993e3fafSRobert Mustacchi #define XHCI_TRB_GET_FRAME(x) (((x) >> 20) & 0x7ff) 435993e3fafSRobert Mustacchi #define XHCI_TRB_SET_FRAME(x) (((x) & 0x7ff) << 20) 436993e3fafSRobert Mustacchi #define XHCI_TRB_SIA (1UL << 31) /* Start Isoch ASAP */ 437993e3fafSRobert Mustacchi 438993e3fafSRobert Mustacchi /* 439993e3fafSRobert Mustacchi * TRB Types. See xHCI 1.1 / 6.4.6. 440993e3fafSRobert Mustacchi */ 441993e3fafSRobert Mustacchi 442993e3fafSRobert Mustacchi /* Transfer Ring Types */ 443993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_NORMAL (1 << 10) 444993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_SETUP (2 << 10) 445993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_DATA (3 << 10) 446993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_STATUS (4 << 10) 447993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_ISOCH (5 << 10) 448993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_LINK (6 << 10) 449993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_EVENT (7 << 10) 450993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_NOOP (8 << 10) 451993e3fafSRobert Mustacchi 452993e3fafSRobert Mustacchi /* Command ring Types */ 453993e3fafSRobert Mustacchi #define XHCI_CMD_ENABLE_SLOT (9 << 10) 454993e3fafSRobert Mustacchi #define XHCI_CMD_DISABLE_SLOT (10 << 10) 455993e3fafSRobert Mustacchi #define XHCI_CMD_ADDRESS_DEVICE (11 << 10) 456993e3fafSRobert Mustacchi #define XHCI_CMD_CONFIG_EP (12 << 10) 457993e3fafSRobert Mustacchi #define XHCI_CMD_EVAL_CTX (13 << 10) 458993e3fafSRobert Mustacchi #define XHCI_CMD_RESET_EP (14 << 10) 459993e3fafSRobert Mustacchi #define XHCI_CMD_STOP_EP (15 << 10) 460993e3fafSRobert Mustacchi #define XHCI_CMD_SET_TR_DEQ (16 << 10) 461993e3fafSRobert Mustacchi #define XHCI_CMD_RESET_DEV (17 << 10) 462993e3fafSRobert Mustacchi #define XHCI_CMD_FEVENT (18 << 10) 463993e3fafSRobert Mustacchi #define XHCI_CMD_NEG_BW (19 << 10) 464*672fc84aSRobert Mustacchi #define XHCI_CMD_SET_LT (20 << 10) 465993e3fafSRobert Mustacchi #define XHCI_CMD_GET_BW (21 << 10) 466993e3fafSRobert Mustacchi #define XHCI_CMD_FHEADER (22 << 10) 467993e3fafSRobert Mustacchi #define XHCI_CMD_NOOP (23 << 10) 468993e3fafSRobert Mustacchi 469993e3fafSRobert Mustacchi /* Event ring Types */ 470993e3fafSRobert Mustacchi #define XHCI_EVT_XFER (32 << 10) 471993e3fafSRobert Mustacchi #define XHCI_EVT_CMD_COMPLETE (33 << 10) 472993e3fafSRobert Mustacchi #define XHCI_EVT_PORT_CHANGE (34 << 10) 473993e3fafSRobert Mustacchi #define XHCI_EVT_BW_REQUEST (35 << 10) 474993e3fafSRobert Mustacchi #define XHCI_EVT_DOORBELL (36 << 10) 475993e3fafSRobert Mustacchi #define XHCI_EVT_HOST_CTRL (37 << 10) 476993e3fafSRobert Mustacchi #define XHCI_EVT_DEVICE_NOTIFY (38 << 10) 477993e3fafSRobert Mustacchi #define XHCI_EVT_MFINDEX_WRAP (39 << 10) 478993e3fafSRobert Mustacchi 479993e3fafSRobert Mustacchi #define XHCI_RING_TYPE_SHIFT(x) ((x) << 10) 480993e3fafSRobert Mustacchi 481993e3fafSRobert Mustacchi /* 482993e3fafSRobert Mustacchi * TRB Completion Codes. See xHCI 1.1 / 6.4.5. 483993e3fafSRobert Mustacchi */ 484993e3fafSRobert Mustacchi #define XHCI_CODE_INVALID 0 /* Producer didn't update the code. */ 485993e3fafSRobert Mustacchi #define XHCI_CODE_SUCCESS 1 /* Badaboum, plaf, plouf, yeepee! */ 486993e3fafSRobert Mustacchi #define XHCI_CODE_DATA_BUF 2 /* Overrun or underrun */ 487993e3fafSRobert Mustacchi #define XHCI_CODE_BABBLE 3 /* Device is "babbling" */ 488993e3fafSRobert Mustacchi #define XHCI_CODE_TXERR 4 /* USB Transaction error */ 489993e3fafSRobert Mustacchi #define XHCI_CODE_TRB 5 /* Invalid TRB */ 490993e3fafSRobert Mustacchi #define XHCI_CODE_STALL 6 /* Stall condition */ 491993e3fafSRobert Mustacchi #define XHCI_CODE_RESOURCE 7 /* No resource available for the cmd */ 492993e3fafSRobert Mustacchi #define XHCI_CODE_BANDWIDTH 8 /* Not enough bandwidth for the cmd */ 493993e3fafSRobert Mustacchi #define XHCI_CODE_NO_SLOTS 9 /* MaxSlots limit reached */ 494993e3fafSRobert Mustacchi #define XHCI_CODE_STREAM_TYPE 10 /* Stream Context Type value detected */ 495993e3fafSRobert Mustacchi #define XHCI_CODE_SLOT_NOT_ON 11 /* Related device slot is disabled */ 496993e3fafSRobert Mustacchi #define XHCI_CODE_ENDP_NOT_ON 12 /* Related enpoint is disabled */ 497993e3fafSRobert Mustacchi #define XHCI_CODE_SHORT_XFER 13 /* Short packet */ 498993e3fafSRobert Mustacchi #define XHCI_CODE_RING_UNDERRUN 14 /* Empty ring when transmitting isoc */ 499993e3fafSRobert Mustacchi #define XHCI_CODE_RING_OVERRUN 15 /* Empty ring when receiving isoc */ 500993e3fafSRobert Mustacchi #define XHCI_CODE_VF_RING_FULL 16 /* VF's event ring is full */ 501993e3fafSRobert Mustacchi #define XHCI_CODE_PARAMETER 17 /* Context parameter is invalid */ 502*672fc84aSRobert Mustacchi #define XHCI_CODE_BW_OVERRUN 18 /* TD exceeds the bandwidth */ 503993e3fafSRobert Mustacchi #define XHCI_CODE_CONTEXT_STATE 19 /* Transition from illegal ctx state */ 504993e3fafSRobert Mustacchi #define XHCI_CODE_NO_PING_RESP 20 /* Unable to complete periodic xfer */ 505993e3fafSRobert Mustacchi #define XHCI_CODE_EV_RING_FULL 21 /* Unable to post an evt to the ring */ 506993e3fafSRobert Mustacchi #define XHCI_CODE_INCOMPAT_DEV 22 /* Device cannot be accessed */ 507993e3fafSRobert Mustacchi #define XHCI_CODE_MISSED_SRV 23 /* Unable to service isoc EP in ESIT */ 508*672fc84aSRobert Mustacchi #define XHCI_CODE_CMD_RING_STOP 24 /* Command Stop (CS) requested */ 509*672fc84aSRobert Mustacchi #define XHCI_CODE_CMD_ABORTED 25 /* Command Abort (CA) operation */ 510*672fc84aSRobert Mustacchi #define XHCI_CODE_XFER_STOPPED 26 /* xfer terminated by a stop endpoint */ 511*672fc84aSRobert Mustacchi #define XHCI_CODE_XFER_STOPINV 27 /* TRB transfer length invalid */ 512*672fc84aSRobert Mustacchi #define XHCI_CODE_XFER_STOPSHORT 28 /* Stopped before end of TD */ 513993e3fafSRobert Mustacchi #define XHCI_CODE_MELAT 29 /* Max Exit Latency too large */ 514993e3fafSRobert Mustacchi #define XHCI_CODE_RESERVED 30 515993e3fafSRobert Mustacchi #define XHCI_CODE_ISOC_OVERRUN 31 /* IN data buffer < Max ESIT Payload */ 516*672fc84aSRobert Mustacchi #define XHCI_CODE_EVENT_LOST 32 /* Internal overrun - impl. specific */ 517*672fc84aSRobert Mustacchi #define XHCI_CODE_UNDEFINED 33 /* Fatal error - impl. specific */ 518*672fc84aSRobert Mustacchi #define XHCI_CODE_INVALID_SID 34 /* Invalid stream ID received */ 519*672fc84aSRobert Mustacchi #define XHCI_CODE_SEC_BW 35 /* Cannot alloc secondary BW Domain */ 520*672fc84aSRobert Mustacchi #define XHCI_CODE_SPLITERR 36 /* USB2 split transaction */ 521993e3fafSRobert Mustacchi 522993e3fafSRobert Mustacchi #ifdef __cplusplus 523993e3fafSRobert Mustacchi } 524993e3fafSRobert Mustacchi #endif 525993e3fafSRobert Mustacchi 526993e3fafSRobert Mustacchi #endif /* _SYS_USB_HCD_XHCI_XHCIREG_H */ 527