1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_USB_OHCID_H
27 #define	_SYS_USB_OHCID_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 /*
36  * Open Host Controller Driver (OHCI)
37  *
38  * The USB Open Host Controller driver is a software driver which interfaces
39  * to the Universal Serial Bus layer (USBA) and the USB Open Host Controller.
40  * The interface to USB Open Host Controller is defined by the OpenHCI  Host
41  * Controller Interface.
42  *
43  * This header file describes the data structures required for the USB Open
44  * Host Controller Driver to maintain state of USB Open Host Controller, to
45  * perform different USB transfers and for the bandwidth allocations.
46  */
47 
48 #include <sys/usb/hcd/openhci/ohci.h>
49 #include <sys/usb/hcd/openhci/ohci_hub.h>
50 
51 /*
52  * OpenHCI interrupt status information structure
53  *
54  * The Host Controller Driver (HCD) has to maintain two different sets of
55  * Host Controller (HC) state information that includes HC registers, the
56  * interrupt tables etc.. for the normal and polled modes.  In	addition,
57  * suppose if we switched to polled mode while ohci  interrupt handler is
58  * executing in the normal mode then we need to save the interrupt status
59  * information that includes interrupts for which ohci interrupt  handler
60  * is called and HCCA done head list in the polled mode. This infromation
61  * will be used later in normal mode to  service those missed interrupts.
62  * This will avoid race conditions like missing of normal mode's ohci SOF
63  * and WriteDoneHead interrupts because of this polled switch.
64  */
65 typedef struct ohci_save_intr_sts {
66 	/*
67 	 * The following field has set of flags & these flags will be set
68 	 * in the ohci interrupt handler to indicate that currently  ohci
69 	 * interrupt handler is in execution and also while critical code
70 	 * execution within the ohci interrupt handler.  These flags will
71 	 * be verified in polled mode while saving the normal mode's ohci
72 	 * interrupt status information.
73 	 */
74 	uint_t		ohci_intr_flag;		/* Intr handler flags */
75 
76 	/*
77 	 * The following fields will be used to save the interrupt status
78 	 * and the HCCA done head list that the ohci interrupt handler is
79 	 * currently handling.
80 	 */
81 	uint_t		ohci_curr_intr_sts;	/* Current interrupts */
82 	ohci_td_t	*ohci_curr_done_lst;	/* Current done head  */
83 
84 	/*
85 	 * The following fields will be used to save the interrupt status
86 	 * and the HCCA done list currently being handled by the critical
87 	 * section of the ohci interrupt handler..
88 	 */
89 	uint_t		ohci_critical_intr_sts;	/* Critical interrupts */
90 	ohci_td_t	*ohci_critical_done_lst; /* Critical done head */
91 
92 	/*
93 	 * The following fields will be used to save the interrupt status
94 	 * and HCCA done head list by the polled code if an  interrupt is
95 	 * pending when polled code is entered. These missed interrupts &
96 	 * done list will be serviced either in current  normal mode ohci
97 	 * interrupt handler execution or during the next  ohci interrupt
98 	 * handler execution.
99 	 */
100 	uint_t		ohci_missed_intr_sts;	/* Missed interrupts */
101 	ohci_td_t	*ohci_missed_done_lst;	/* Missed done head  */
102 } ohci_save_intr_sts_t;
103 
104 /*
105  * These flags will be set in the the normal mode ohci	interrupt handler
106  * to indicate that currently ohci interrupt handler is in  execution and
107  * also while critical code  execution within the ohci interrupt handler.
108  * These flags will be verified in the polled mode while saving the normal
109  * mode's ohci interrupt status infromation.
110  */
111 #define		OHCI_INTR_HANDLING	0x01	/* Handling ohci intrs */
112 #define		OHCI_INTR_CRITICAL	0x02	/* Critical intr code  */
113 
114 
115 /*
116  * OpenHCI Host Controller state structure
117  *
118  * The Host Controller Driver (HCD) maintains the state of Host Controller
119  * (HC). There is an ohci_state structure per instance	of the OpenHCI
120  * host controller.
121  */
122 
123 typedef struct ohci_state {
124 	dev_info_t		*ohci_dip;		/* Dip of HC */
125 	uint_t			ohci_instance;
126 	usba_hcdi_ops_t		*ohci_hcdi_ops;		/* HCDI structure */
127 	uint_t			ohci_flags;		/* Used for cleanup */
128 	uint16_t		ohci_vendor_id;		/* chip vendor */
129 	uint16_t		ohci_device_id;		/* chip device */
130 	uint8_t			ohci_rev_id;		/* chip revison */
131 
132 	ohci_regs_t		*ohci_regsp;		/* Host ctlr regs */
133 	ddi_acc_handle_t	ohci_regs_handle;	/* Reg handle */
134 
135 	ddi_acc_handle_t	ohci_config_handle;	/* Config space hndle */
136 	uint_t			ohci_frame_interval;	/* Frme inter reg */
137 	ddi_dma_attr_t		ohci_dma_attr;		/* DMA attributes */
138 
139 	ddi_intr_handle_t	*ohci_htable;		/* intr handle */
140 	int			ohci_intr_type;		/* intr type used */
141 	int			ohci_intr_cnt;		/* # of intrs inuse */
142 	uint_t			ohci_intr_pri;		/* intr priority */
143 	int			ohci_intr_cap;		/* intr capabilities */
144 	kmutex_t		ohci_int_mutex;		/* Mutex for struct */
145 
146 	/* HCCA area */
147 	ohci_hcca_t		*ohci_hccap;		/* Virtual HCCA ptr */
148 	ddi_dma_cookie_t	ohci_hcca_cookie;	/* DMA cookie */
149 	ddi_dma_handle_t	ohci_hcca_dma_handle;	/* DMA handle */
150 	ddi_acc_handle_t	ohci_hcca_mem_handle;	/* Memory handle */
151 
152 	/*
153 	 * There are two pools of memory. One pool contains the memory for
154 	 * the transfer descriptors and other pool contains the memory for
155 	 * the endpoint descriptors. The advantage of the pools is that it's
156 	 * easy to go back and forth between the iommu and the cpu addresses.
157 	 *
158 	 * The pools are protected by the ohci_int_mutex because the memory
159 	 * in the pools may be accessed by either the host controller or the
160 	 * host controller driver.
161 	 */
162 
163 	/* General transfer descriptor pool */
164 	ohci_td_t		*ohci_td_pool_addr;	/* Start of the pool */
165 	ddi_dma_cookie_t	ohci_td_pool_cookie;	/* DMA cookie */
166 	ddi_dma_handle_t	ohci_td_pool_dma_handle;	/* DMA hndle */
167 	ddi_acc_handle_t	ohci_td_pool_mem_handle;	/* Mem hndle */
168 
169 	/* Endpoint descriptor pool */
170 	ohci_ed_t		*ohci_ed_pool_addr;	/* Start of the pool */
171 	ddi_dma_cookie_t	ohci_ed_pool_cookie;	/* DMA cookie */
172 	ddi_dma_handle_t	ohci_ed_pool_dma_handle;	/* DMA handle */
173 	ddi_acc_handle_t	ohci_ed_pool_mem_handle;	/* Mem handle */
174 	uint_t			ohci_dma_addr_bind_flag;	/* DMA flag */
175 
176 	/* Condition variables */
177 	kcondvar_t		ohci_SOF_cv;		/* SOF variable */
178 
179 	/* Semaphore to serialize opens and closes */
180 	ksema_t			ohci_ocsem;
181 
182 	/*
183 	 * Bandwidth fields
184 	 *
185 	 * The ohci_bandwidth array keeps track of the allocated bandwidth
186 	 * for this host controller. The total bandwidth allocated for least
187 	 * allocated list out of the 32 periodic lists is represented by the
188 	 * ohci_periodic_minimum_bandwidth field.
189 	 */
190 	uint_t			ohci_periodic_minimum_bandwidth;
191 	uint_t			ohci_periodic_bandwidth[NUM_INTR_ED_LISTS];
192 
193 	/* Different transfer open pipe counts */
194 	uint_t			ohci_open_pipe_count;
195 	uint_t			ohci_open_ctrl_pipe_count;
196 	uint_t			ohci_open_bulk_pipe_count;
197 	uint_t			ohci_open_periodic_pipe_count;
198 	uint_t			ohci_open_isoch_pipe_count;
199 	/*
200 	 * Endpoint Reclamation List
201 	 *
202 	 * The interrupt or isochronous list processing cannot be stopped
203 	 * when a periodic endpoint is removed from the list. The endpoints
204 	 * are detached from the interrupt lattice tree and put on to the
205 	 * reclaimation list. On next SOF interrupt all those endpoints,
206 	 * which are on the reclaimation list will be deallocated.
207 	 */
208 	ohci_ed_t		*ohci_reclaim_list;	/* Reclaimation list */
209 
210 	ohci_root_hub_t		ohci_root_hub;		/* Root hub info */
211 
212 	/*
213 	 * Global transfer timeout handling & this transfer timeout handling
214 	 * will be per USB Host Controller.
215 	 */
216 	struct ohci_trans_wrapper *ohci_timeout_list;	/* Timeout List */
217 	timeout_id_t		ohci_timer_id;		/* Timer id  */
218 
219 	/* Frame number overflow information */
220 	usb_frame_number_t	ohci_fno;
221 
222 	/* For Schedule Overrun error counter */
223 	uint_t			ohci_so_error;
224 
225 	/* For host controller error counter */
226 	uint_t			ohci_hc_error;
227 
228 	/* For SOF interrupt event */
229 	boolean_t		ohci_sof_flag;
230 
231 	/* Openhci Host Controller Software State information */
232 	uint_t			ohci_hc_soft_state;
233 
234 	/*
235 	 * ohci_save_intr_stats is used to save the normal mode interrupt
236 	 * status information while executing interrupt handler & also by
237 	 * the polled code if an interrupt is pending for the normal mode
238 	 * when polled code is entered.
239 	 */
240 	ohci_save_intr_sts_t	ohci_save_intr_sts;
241 
242 	/*
243 	 * Saved copy of the ohci registers of the normal mode & change
244 	 * required ohci registers values for the polled mode operation.
245 	 * Before returning from the polled mode to normal mode replace
246 	 * the required current registers with this saved ohci registers
247 	 * copy.
248 	 */
249 	ohci_regs_t	ohci_polled_save_regs;
250 
251 	/*
252 	 * Saved copy of the interrupt table used in normal ohci mode and
253 	 * replace this table by another interrupt table that used in the
254 	 * POLLED mode.
255 	 */
256 	ohci_ed_t	*ohci_polled_save_IntTble[NUM_INTR_ED_LISTS];
257 
258 	/* ohci polled mode enter counter for the input devices */
259 	uint_t			ohci_polled_enter_count;
260 
261 	/*
262 	 * Counter for polled mode and used in suspend mode to see if
263 	 * there is a input device connected.
264 	 */
265 	uint_t			ohci_polled_kbd_count;
266 
267 	/* Done list for the Polled mode */
268 	ohci_td_t		*ohci_polled_done_list;
269 
270 	/* Log handle for debug, console, log messages */
271 	usb_log_handle_t	ohci_log_hdl;
272 
273 	/* Kstat structures */
274 	kstat_t			*ohci_intrs_stats;
275 	kstat_t			*ohci_total_stats;
276 	kstat_t			*ohci_count_stats[USB_N_COUNT_KSTATS];
277 } ohci_state_t;
278 
279 typedef struct ohci_intrs_stats {
280 	struct kstat_named	ohci_hcr_intr_so;
281 	struct kstat_named	ohci_hcr_intr_wdh;
282 	struct kstat_named	ohci_hcr_intr_sof;
283 	struct kstat_named	ohci_hcr_intr_rd;
284 	struct kstat_named	ohci_hcr_intr_ue;
285 	struct kstat_named	ohci_hcr_intr_fno;
286 	struct kstat_named	ohci_hcr_intr_rhsc;
287 	struct kstat_named	ohci_hcr_intr_oc;
288 	struct kstat_named	ohci_hcr_intr_not_claimed;
289 	struct kstat_named	ohci_hcr_intr_total;
290 } ohci_intrs_stats_t;
291 
292 /*
293  * ohci kstat defines
294  */
295 #define	OHCI_INTRS_STATS(ohci)	((ohci)->ohci_intrs_stats)
296 #define	OHCI_INTRS_STATS_DATA(ohci)	\
297 	((ohci_intrs_stats_t *)OHCI_INTRS_STATS((ohci))->ks_data)
298 
299 #define	OHCI_TOTAL_STATS(ohci)	((ohci)->ohci_total_stats)
300 #define	OHCI_TOTAL_STATS_DATA(ohci)	(KSTAT_IO_PTR((ohci)->ohci_total_stats))
301 #define	OHCI_CTRL_STATS(ohci)	\
302 	(KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_CONTROL]))
303 #define	OHCI_BULK_STATS(ohci)	\
304 	(KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_BULK]))
305 #define	OHCI_INTR_STATS(ohci)	\
306 	(KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_INTR]))
307 #define	OHCI_ISOC_STATS(ohci)	\
308 	(KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_ISOCH]))
309 
310 /* warlock directives, stable data */
311 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_state_t))
312 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_intr_pri))
313 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_dip))
314 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_regsp))
315 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_instance))
316 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_vendor_id))
317 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_device_id))
318 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_rev_id))
319 
320 /* this may not be stable data in the future */
321 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_addr))
322 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_mem_handle))
323 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_addr))
324 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_mem_handle))
325 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_cookie))
326 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_cookie))
327 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_hcca_mem_handle))
328 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_hccap))
329 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_dma_addr_bind_flag))
330 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_log_hdl))
331 
332 _NOTE(LOCK_ORDER(ohci_state::ohci_int_mutex \
333 		usba_pipe_handle_data::p_mutex \
334 		usba_device::usb_mutex \
335 		usba_ph_impl::usba_ph_mutex))
336 
337 /*
338  * Host Contoller Software States
339  *
340  * OHCI_CTLR_INIT_STATE:
341  *	The host controller soft state will be set to this during the
342  *	ohci_attach.
343  *
344  * OHCI_CTLR_SUSPEND_STATE:
345  *	The host controller soft state will be set to this during the
346  *	ohci_cpr_suspend.
347  *
348  * OHCI_CTLR_OPERATIONAL_STATE:
349  *	The host controller soft state will be set to this after moving
350  *	host controller to operational state and host controller start
351  *	generating SOF successfully.
352  *
353  * OHCI_CTLR_ERROR_STATE:
354  *	The host controller soft state will be set to this during the
355  *	no SOF or UE error conditions.
356  *
357  *	Under this state or condition, only pipe stop polling, pipe reset
358  *	and pipe close are allowed. But all other entry points like  pipe
359  *	open, get/set pipe policy, cotrol send/receive, bulk send/receive
360  *	isoch send/receive, start polling etc. will fail.
361  *
362  * State Diagram for the host controller software state
363  *
364  *
365  * ohci_attach->[INIT_STATE]
366  *	|
367  *	|	-------->----[ERROR_STATE]--<-----------<---
368  *	|      |      Failure (UE/no SOF condition)	    |
369  *	|      ^					    ^
370  *	V      |      Success				    |
371  * ohci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ohci_send/recv/polling
372  *	^					    |
373  *	|					    |
374  *	|					    V
375  *	-<-ohci_cpr_resume--[SUSPEND_STATE]-<-ohci_cpr_suspend
376  */
377 #define	OHCI_CTLR_INIT_STATE		0	/* Initilization state */
378 #define	OHCI_CTLR_SUSPEND_STATE		1	/* Suspend state */
379 #define	OHCI_CTLR_OPERATIONAL_STATE	2	/* Operational state */
380 #define	OHCI_CTLR_ERROR_STATE		3	/* Ue error or no sof state */
381 
382 /*
383  * Define all ohci's Vendor-id and Device-id Here
384  */
385 #define	RIO_VENDOR	0x108e
386 #define	RIO_DEVICE	0x1103
387 #define	OHCI_IS_RIO(ohcip)	(ohcip->ohci_vendor_id == RIO_VENDOR)
388 
389 /*
390  * Periodic and non-periodic macros
391  */
392 #define	OHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
393 				USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\
394 				((endpoint->bmAttributes &\
395 				USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH))
396 
397 #define	OHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
398 				USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\
399 				((endpoint->bmAttributes &\
400 				USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK))
401 
402 /*
403  * OHCI ED and TD Pool sizes.
404  */
405 #define	OHCI_ED_POOL_SIZE	100
406 #define	OHCI_TD_POOL_SIZE	200
407 
408 /*
409  * ohci_dma_addr_bind_flag values
410  *
411  * This flag indicates if the various DMA addresses allocated by the OHCI
412  * have been bound to their respective handles. This is needed to recover
413  * without errors from ohci_cleanup when it calls ddi_dma_unbind_handle()
414  */
415 #define	OHCI_TD_POOL_BOUND	0x01	/* For TD pools  */
416 #define	OHCI_ED_POOL_BOUND	0x02	/* For ED pools  */
417 #define	OHCI_HCCA_DMA_BOUND	0x04	/* For HCCA area */
418 
419 /*
420  * Maximum SOF wait count
421  */
422 #define	MAX_SOF_WAIT_COUNT	2	/* Wait for maximum SOF frames */
423 
424 
425 /*
426  * Pipe private structure
427  *
428  * There is an instance of this structure per pipe.  This structure holds
429  * HCD specific pipe information.  A pointer to this structure is kept in
430  * the USBA pipe handle (usba_pipe_handle_data_t).
431  */
432 typedef struct ohci_pipe_private {
433 	usba_pipe_handle_data_t	*pp_pipe_handle;	/* Back ptr to handle */
434 	ohci_ed_t		*pp_ept;		/* Pipe's ept */
435 
436 	/* State of the pipe */
437 	uint_t			pp_state;		/* See below */
438 
439 	/* Local copy of the pipe policy */
440 	usb_pipe_policy_t	pp_policy;
441 
442 	/* For Periodic Pipes Only */
443 	uint_t			pp_node;		/* Node in lattice */
444 	uint_t			pp_cur_periodic_req_cnt; /* Curr req count */
445 	uint_t			pp_max_periodic_req_cnt; /* Max req count */
446 
447 	/* For isochronous pipe only */
448 	usb_frame_number_t	pp_next_frame_number;	/* Next frame no */
449 
450 	/*
451 	 * Each pipe may have multiple transfer wrappers. Each transfer
452 	 * wrapper represents a USB transfer on the bus.  A transfer is
453 	 * made up of one or more transactions.
454 	 */
455 	struct ohci_trans_wrapper *pp_tw_head;	/* Head of the list */
456 	struct ohci_trans_wrapper *pp_tw_tail;	/* Tail of the list */
457 
458 	/* Done td count */
459 	uint_t			pp_count_done_tds;	/* Done td count */
460 
461 	/* Errors */
462 	usb_cr_t		pp_error;		/* Pipe error */
463 
464 	/* Flags */
465 	uint_t			pp_flag;		/* Flags */
466 
467 	/* Condition variable for transfers completion event */
468 	kcondvar_t		pp_xfer_cmpl_cv;	/* Xfer completion */
469 
470 	/*
471 	 * HCD gets Interrupt/Isochronous IN polling request only once and
472 	 * it has to insert next polling requests after completion of first
473 	 * request until either stop polling/pipe close is called. So  HCD
474 	 * has to take copy of the original Interrupt/Isochronous IN request.
475 	 */
476 	usb_opaque_t		pp_client_periodic_in_reqp;
477 } ohci_pipe_private_t;
478 
479 /* warlock directives, stable data */
480 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_pipe_private_t))
481 
482 /*
483  * Pipe states
484  *
485  * ohci pipe states will be similar to usba. Refer usbai.h.
486  */
487 #define	OHCI_PIPE_STATE_IDLE		1	/* Pipe is in ready state */
488 #define	OHCI_PIPE_STATE_ACTIVE		2	/* Pipe is in busy state */
489 #define	OHCI_PIPE_STATE_ERROR		3	/* Pipe is in error state */
490 
491 /* Additional ohci pipe states for the ohci_pipe_cleanup */
492 #define	OHCI_PIPE_STATE_CLOSE		4	/* Pipe close */
493 #define	OHCI_PIPE_STATE_RESET		5	/* Pipe reset */
494 #define	OHCI_PIPE_STATE_STOP_POLLING	6	/* Pipe stop polling */
495 
496 /*
497  * Pipe specific Flags
498  */
499 #define	OHCI_ISOC_XFER_CONTINUE	1	/* For isoc transfers */
500 
501 /*
502  * The maximum allowable usb isochronous data transfer size or maximum
503  * number of isochronous data packets.
504  *
505  * Each usb isochronous request must not exceed multiples of isochronous
506  * endpoint packet size and OHCI_MAX_ISOC_PKTS_PER_XFER.
507  *
508  * Ex: usb isochronous endpoint maximum packet size is 64 bytes
509  *     maximum usb isochronous request will be OHCI_MAX_ISOC_PKTS_PER_XFER
510  *     * 64 bytes
511  */
512 #define		OHCI_MAX_ISOC_PKTS_PER_XFER	256	/* Max pkts per req */
513 
514 /*
515  * The ohci supports maximum of eight isochronous data packets per transfer
516  * descriptor.
517  */
518 #define		OHCI_ISOC_PKTS_PER_TD		8	/* Packets per TD */
519 
520 /*
521  * USB frame offset
522  *
523  * Add appropriate frame offset to the current usb frame number and use it
524  * as a starting frame number for a given usb isochronous request.
525  */
526 #define		OHCI_FRAME_OFFSET		2	/* Frame offset */
527 
528 /*
529  * Default usb isochronous receive packets per request before ohci will do
530  * callback.
531  */
532 #define		OHCI_DEFAULT_ISOC_RCV_PKTS	1	/* isoc pkts per req */
533 
534 /*
535  * Different interrupt polling intervals supported
536  */
537 #define		INTR_1MS_POLL	1
538 #define		INTR_2MS_POLL	2
539 #define		INTR_4MS_POLL	4
540 #define		INTR_8MS_POLL	8
541 #define		INTR_16MS_POLL	16
542 #define		INTR_32MS_POLL	32
543 
544 /*
545  * Number of interrupt/isochronous transfer requests that should
546  * be maintained on the interrupt/isochronous endpoint corresponding
547  * to different polling intervals supported.
548  */
549 #define		INTR_1MS_REQS	4	/* 1ms polling interval */
550 #define		INTR_2MS_REQS	2	/* 2ms polling interval */
551 #define		INTR_XMS_REQS	1	/* Between 4ms and 32ms */
552 
553 /* Function prototype */
554 typedef void (*ohci_handler_function_t)(
555 	ohci_state_t			*ohcip,
556 	ohci_pipe_private_t		*pp,
557 	struct ohci_trans_wrapper	*tw,
558 	ohci_td_t			*td,
559 	void				*ohci_handle_callback_value);
560 
561 
562 /*
563  * Transfer wrapper
564  *
565  * The transfer wrapper represents a USB transfer on the bus and there
566  * is one instance per USB transfer.  A transfer is made up of one or
567  * more transactions. OHCI uses one TD for one transaction. So one
568  * transfer wrapper may have one or more TDs associated.
569  *
570  * Control and bulk pipes will have one transfer wrapper per transfer
571  * and where as Isochronous and Interrupt pipes will only have one
572  * transfer wrapper. The transfers wrapper are continually reused for
573  * the Interrupt and Isochronous pipes as those pipes are polled.
574  *
575  * Control, bulk and interrupt transfers will have one DMA buffer per
576  * transfer. The data to be transferred are contained in the DMA buffer
577  * which is virtually contiguous but physically discontiguous. When
578  * preparing the TDs for a USB transfer, the DMA cookies contained in
579  * the buffer need to be walked through to retrieve the DMA addresses.
580  *
581  * Isochronous transfers may have multiple DMA buffers per transfer
582  * with each isoc TD having a DMA buffer. And one isoc TD may hold up to
583  * eight isoc packets, but two cookies at most.
584  */
585 typedef struct ohci_trans_wrapper {
586 	struct ohci_trans_wrapper	*tw_next;	/* Next wrapper */
587 	ohci_pipe_private_t		*tw_pipe_private; /* Back ptr */
588 	ddi_dma_handle_t		tw_dmahandle;	/* DMA handle */
589 	ddi_acc_handle_t		tw_accesshandle; /* Acc hndle */
590 	ddi_dma_cookie_t		tw_cookie;	/* DMA cookie */
591 	uint32_t			tw_id;		/* 32bit ID */
592 	size_t				tw_length;	/* Txfer length */
593 	char				*tw_buf;	/* Buffer for Xfer */
594 	uint_t				tw_ncookies;	/* DMA cookie count */
595 	uint_t				tw_cookie_idx;	/* DMA cookie index */
596 	size_t				tw_dma_offs;	/* DMA buffer offset */
597 	usb_flags_t			tw_flags;	/* Flags */
598 	uint_t				tw_num_tds;	/* Number of TDs */
599 	ohci_td_t			*tw_hctd_head;	/* Head TD */
600 	ohci_td_t			*tw_hctd_tail;	/* Tail TD */
601 	uint_t				tw_direction;	/* Direction of TD */
602 
603 	/* We preallocate all the td's for each tw and place them here */
604 	ohci_td_t			*tw_hctd_free_list;
605 
606 	/* Current transfer request pointer */
607 	usb_opaque_t			tw_curr_xfer_reqp;
608 
609 	/* Current isochronous packet descriptor pointer */
610 	usb_isoc_pkt_descr_t		*tw_curr_isoc_pktp;
611 
612 	/* Isochronous DMA handlers and buffer pointers are stored here */
613 	ohci_isoc_buf_t			*tw_isoc_bufs;
614 	size_t				tw_isoc_strtlen;
615 
616 	/* Transfer timeout information */
617 	uint_t				tw_timeout;	/* Timeout value */
618 	struct ohci_trans_wrapper	*tw_timeout_next; /* Xfer Timeout Q */
619 
620 	/*
621 	 * This is the function to call when this td is done. This way
622 	 * we don't have to look in the td to figure out what kind it is.
623 	 */
624 	ohci_handler_function_t		tw_handle_td;
625 
626 	/*
627 	 * This is the callback value used when processing a done td.
628 	 */
629 	usb_opaque_t			tw_handle_callback_value;
630 } ohci_trans_wrapper_t;
631 
632 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_trans_wrapper))
633 
634 
635 /*
636  * Time waits for the different OHCI specific operations.
637  * These timeout values are specified in terms of microseconds.
638  */
639 #define	OHCI_RESET_TIMEWAIT	10000	/* HC reset waiting time */
640 #define	OHCI_RESUME_TIMEWAIT	40000	/* HC resume waiting time */
641 #define	OHCI_TIMEWAIT		10000	/* HC any other waiting time */
642 
643 /* These timeout values are specified in seconds */
644 #define	OHCI_DEFAULT_XFER_TIMEOUT	5 /* Default transfer timeout */
645 #define	OHCI_MAX_SOF_TIMEWAIT		3 /* Maximum SOF waiting time */
646 #define	OHCI_XFER_CMPL_TIMEWAIT		3 /* Xfers completion timewait */
647 
648 /* OHCI flags for general use */
649 #define	OHCI_FLAGS_NOSLEEP	0x000	/* Don't wait for SOF */
650 #define	OHCI_FLAGS_SLEEP	0x100	/* Wait for SOF */
651 #define	OHCI_FLAGS_DMA_SYNC	0x200	/* Call ddi_dma_sync */
652 
653 /*
654  * Maximum allowable data transfer  size per transaction as supported
655  * by OHCI is 8k. (See Open Host Controller Interface Spec rev 1.0a)
656  */
657 #define	OHCI_MAX_TD_XFER_SIZE	0x2000	/* Maxmum data per transaction */
658 
659 /*
660  * One OHCI TD allows two physically discontiguous pages. The page size
661  * is 4k.
662  */
663 #define	OHCI_MAX_TD_BUF_SIZE	0x1000
664 
665 /*
666  * The maximum allowable bulk data transfer size. It can be different
667  * from OHCI_MAX_TD_XFER_SIZE and if it is more then ohci driver will
668  * take care of  breaking a bulk data request into  multiples of ohci
669  * OHCI_MAX_TD_XFER_SIZE  until request is satisfied.  Currently this
670  * value is set to 256k bytes.
671  */
672 #define	OHCI_MAX_BULK_XFER_SIZE	0x40000	/* Maximum bulk transfer size */
673 
674 /*
675  * Timeout flags
676  *
677  * These flags will be used to stop the timer before timeout handler
678  * gets executed.
679  */
680 #define	OHCI_REMOVE_XFER_IFLAST	1	/* Stop the timer if  it is last TD */
681 #define	OHCI_REMOVE_XFER_ALWAYS	2	/* Stop the timer without condition */
682 
683 
684 /*
685  * Bandwidth allocation
686  *
687  * The following definitions are  used during  bandwidth calculations
688  * for a given endpoint maximum packet size.
689  */
690 #define	MAX_USB_BUS_BANDWIDTH	1500	/* Up to 1500 bytes per frame */
691 #define	MAX_POLL_INTERVAL	255	/* Maximum polling interval */
692 #define	MIN_POLL_INTERVAL	1	/* Minimum polling interval */
693 #define	SOF			6	/* Length in bytes of SOF */
694 #define	EOF			4	/* Length in bytes of EOF */
695 #define	TREE_HEIGHT		5	/* Log base 2 of 32 */
696 
697 /*
698  * Minimum polling interval for low speed endpoint
699  *
700  * According USB Specifications, a full-speed endpoint can specify
701  * a desired polling interval 1ms to 255ms and a low speed endpoints
702  * are limited to specifying only 10ms to 255ms. But some old keyboards
703  * and mice uses polling interval of 8ms. For compatibility purpose,
704  * we are using polling interval between 8ms and 255ms for low speed
705  * endpoints. But ohci driver will reject any low speed endpoints which
706  * request polling interval less than 8ms.
707  */
708 #define	MIN_LOW_SPEED_POLL_INTERVAL	8
709 
710 /*
711  * For non-periodic transfers, reserve atleast for one low-speed device
712  * transaction. According to USB Bandwidth Analysis white paper and also
713  * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed
714  * transaction takes 0x628h full speed bits (197 bytes), which comes to
715  * around 13% of USB frame time.
716  *
717  * The periodic transfers will  get around 87% of USB frame time.
718  */
719 #define	MAX_NON_PERIODIC_BANDWIDTH	197
720 #define	MAX_PERIODIC_BANDWIDTH		(MAX_USB_BUS_BANDWIDTH - SOF - \
721 					EOF - MAX_NON_PERIODIC_BANDWIDTH)
722 
723 /*
724  * The USB periodic transfers like interrupt and isochronous transfers
725  * after completion of SOF and USB non-periodic transfers.
726  */
727 #define	PERIODIC_XFER_STARTS		(MAX_USB_BUS_BANDWIDTH - \
728 					SOF - MAX_NON_PERIODIC_BANDWIDTH)
729 
730 /* Number of Bits Per Byte */
731 #define	BITS_PER_BYTE			8
732 
733 /*
734  * The following are the protocol overheads in terms of Bytes for the
735  * different transfer types.  All these protocol overhead  values are
736  * derived from the 5.9.3 section of USB Specification	and  with the
737  * help of Bandwidth Analysis white paper which is posted on the  USB
738  * developer forum.
739  */
740 #define	FS_NON_ISOC_PROTO_OVERHEAD	14
741 #define	FS_ISOC_INPUT_PROTO_OVERHEAD	11
742 #define	FS_ISOC_OUTPUT_PROTO_OVERHEAD	10
743 #define	LOW_SPEED_PROTO_OVERHEAD	97
744 #define	HUB_LOW_SPEED_PROTO_OVERHEAD	01
745 
746 /*
747  * The Host Controller (HC) delays are the USB host controller specific
748  * delays. The value shown below is the host  controller delay for  the
749  * RIO USB host controller.  This value was calculated and  given by the
750  * Sun USB hardware people.
751  */
752 #define	HOST_CONTROLLER_DELAY		18
753 
754 /*
755  * The low speed clock below represents that to transmit one low-speed
756  * bit takes eight times more than one full speed bit time.
757  */
758 #define	LOW_SPEED_CLOCK			8
759 
760 
761 /*
762  * Macros for setting/getting information
763  */
764 #define	Get_ED(addr)		ddi_get32(ohcip->ohci_ed_pool_mem_handle, \
765 					(uint32_t *)&addr)
766 
767 #define	Set_ED(addr, val)	ddi_put32(ohcip->ohci_ed_pool_mem_handle,  \
768 					((uint32_t *)&addr), \
769 					((int32_t)(val)))
770 
771 #define	Get_TD(addr)		ddi_get32(ohcip->ohci_td_pool_mem_handle, \
772 					(uint32_t *)&addr)
773 
774 #define	Set_TD(addr, val)	ddi_put32(ohcip->ohci_td_pool_mem_handle, \
775 					((uint32_t *)&addr), \
776 					((uint32_t)(uintptr_t)(val)))
777 
778 #define	Get_HCCA(addr)		ddi_get32(ohcip->ohci_hcca_mem_handle, \
779 					(uint32_t *)&addr)
780 
781 #define	Set_HCCA(addr, val)	ddi_put32(ohcip->ohci_hcca_mem_handle, \
782 					((uint32_t *)&addr), \
783 					((int32_t)(val)))
784 
785 #define	Get_OpReg(addr)		ddi_get32(ohcip->ohci_regs_handle, \
786 					(uint32_t *)&ohcip->ohci_regsp->addr)
787 
788 #define	Set_OpReg(addr, val)	ddi_put32(ohcip->ohci_regs_handle, \
789 				((uint32_t *)&ohcip->ohci_regsp->addr), \
790 					((int32_t)(val)))
791 
792 #define	Sync_HCCA(ohcip)	(void) ddi_dma_sync( \
793 				ohcip->ohci_hcca_dma_handle, \
794 				0, sizeof (ohci_hcca_t), \
795 				DDI_DMA_SYNC_FORCPU);
796 
797 #define	Sync_ED_TD_Pool(ohcip)	(void) ddi_dma_sync( \
798 				ohcip->ohci_ed_pool_dma_handle, \
799 				0, OHCI_ED_POOL_SIZE * sizeof (ohci_ed_t), \
800 				DDI_DMA_SYNC_FORCPU); \
801 				(void) ddi_dma_sync( \
802 				ohcip->ohci_td_pool_dma_handle, \
803 				0, OHCI_TD_POOL_SIZE * sizeof (ohci_td_t), \
804 				DDI_DMA_SYNC_FORCPU);
805 
806 #define	Sync_IO_Buffer(dma_handle, length) \
807 				(void) ddi_dma_sync(dma_handle, \
808 				0, length, DDI_DMA_SYNC_FORCPU);
809 
810 /*
811  * Macros to speed handling of 32bit IDs
812  */
813 #define	OHCI_GET_ID(x)		id32_alloc((void *)(x), KM_SLEEP)
814 #define	OHCI_LOOKUP_ID(x)	id32_lookup((x))
815 #define	OHCI_FREE_ID(x)		id32_free((x))
816 
817 
818 /*
819  * Miscellaneous definitions.
820  */
821 
822 /* Data toggle bits */
823 #define	DATA0		0
824 #define	DATA1		1
825 
826 /* sKip bit actions */
827 #define	CLEAR_sKip	0
828 #define	SET_sKip	1
829 
830 typedef uint_t		skip_bit_t;
831 
832 /*
833  * Setup Packet
834  */
835 typedef struct setup_pkt {
836 	uchar_t	bmRequestType;
837 	uchar_t	bRequest;
838 	ushort_t wValue;
839 	ushort_t wIndex;
840 	ushort_t wLength;
841 }setup_pkt_t;
842 
843 #define	SETUP_SIZE		8	/* Setup packet is always 8 bytes */
844 
845 #define	REQUEST_TYPE_OFFSET	0
846 #define	REQUEST_OFFSET		1
847 #define	VALUE_OFFSET		2
848 #define	INDEX_OFFSET		4
849 #define	LENGTH_OFFSET		6
850 
851 #define	TYPE_DEV_TO_HOST	0x80000000
852 #define	DEVICE			0x00000001
853 #define	CONFIGURATION		0x00000002
854 
855 /*
856  * The following are used in attach to	 indicate
857  * what has been succesfully allocated, so detach
858  * can remove them.
859  */
860 #define	OHCI_ATTACH		0x01	/* ohci driver initilization */
861 #define	OHCI_ZALLOC		0x02	/* Memory for ohci state structure */
862 #define	OHCI_INTR		0x04	/* Interrupt handler registered */
863 #define	OHCI_USBAREG		0x08	/* USBA registered */
864 #define	OHCI_RHREG		0x10	/* Root hub driver loaded */
865 
866 #define	OHCI_UNIT(dev)	(getminor((dev)) & ~HUBD_IS_ROOT_HUB)
867 
868 /*
869  * Debug printing
870  * Masks
871  */
872 #define	PRINT_MASK_ATTA		0x00000001	/* Attach time */
873 #define	PRINT_MASK_LISTS	0x00000002	/* List management */
874 #define	PRINT_MASK_ROOT_HUB	0x00000004	/* Root hub stuff */
875 #define	PRINT_MASK_ALLOC	0x00000008	/* Alloc/dealloc descr */
876 #define	PRINT_MASK_INTR		0x00000010	/* Interrupt handling */
877 #define	PRINT_MASK_BW		0x00000020	/* Bandwidth */
878 #define	PRINT_MASK_CBOPS	0x00000040	/* CB-OPS */
879 #define	PRINT_MASK_HCDI		0x00000080	/* HCDI entry points */
880 #define	PRINT_MASK_DUMPING	0x00000100	/* Dump ohci info */
881 #define	PRINT_MASK_ALL		0xFFFFFFFF
882 
883 
884 /* Polling support */
885 int		ohci_hcdi_polled_input_init(
886 				usba_pipe_handle_data_t	*ph,
887 				uchar_t			**polled_buf,
888 				usb_console_info_impl_t	*info);
889 int		ohci_hcdi_polled_input_enter(
890 				usb_console_info_impl_t	*info);
891 int		ohci_hcdi_polled_read(
892 				usb_console_info_impl_t	*info,
893 				uint_t			*num_characters);
894 int		ohci_hcdi_polled_input_exit(
895 				usb_console_info_impl_t	*info);
896 int		ohci_hcdi_polled_input_fini(
897 				usb_console_info_impl_t	*info);
898 
899 /* Root hub related functions */
900 int		ohci_init_root_hub(
901 				ohci_state_t		*ohcip);
902 int		ohci_load_root_hub_driver(
903 				ohci_state_t		*ohcip);
904 int		ohci_unload_root_hub_driver(
905 				ohci_state_t		*ohcip);
906 int		ohci_handle_root_hub_pipe_open(
907 				usba_pipe_handle_data_t	*ph,
908 				usb_flags_t		flags);
909 int		ohci_handle_root_hub_pipe_close(
910 				usba_pipe_handle_data_t	*ph);
911 int		ohci_handle_root_hub_pipe_reset(
912 				usba_pipe_handle_data_t	*ph,
913 				usb_flags_t		flags);
914 int		ohci_handle_root_hub_request(
915 				ohci_state_t		*ohcip,
916 				usba_pipe_handle_data_t	*ph,
917 				usb_ctrl_req_t		*ctrl_reqp);
918 int		ohci_handle_root_hub_pipe_start_intr_polling(
919 				usba_pipe_handle_data_t	*ph,
920 				usb_intr_req_t		*intr_reqp,
921 				usb_flags_t		flags);
922 void		ohci_handle_root_hub_pipe_stop_intr_polling(
923 				usba_pipe_handle_data_t	*ph,
924 				usb_flags_t		flags);
925 void		ohci_handle_root_hub_status_change(void *arg);
926 
927 /* Endpoint Descriptor (ED) related functions */
928 ohci_ed_t	*ohci_alloc_hc_ed(
929 				ohci_state_t		*ohcip,
930 				usba_pipe_handle_data_t	*ph);
931 void		ohci_deallocate_ed(
932 				ohci_state_t		*ohcip,
933 				ohci_ed_t		*old_ed);
934 uint32_t	ohci_ed_cpu_to_iommu(
935 				ohci_state_t		*ohcip,
936 				ohci_ed_t		*addr);
937 
938 /* Transfer Descriptor (TD) related functions */
939 int		ohci_start_periodic_pipe_polling(
940 				ohci_state_t		*ohcip,
941 				usba_pipe_handle_data_t	*ph,
942 				usb_opaque_t		periodic_in_reqp,
943 				usb_flags_t		flags);
944 void		ohci_traverse_tds(
945 				ohci_state_t		*ohcip,
946 				usba_pipe_handle_data_t	*ph);
947 void		ohci_deallocate_td(
948 				ohci_state_t		*ohcip,
949 				ohci_td_t		*old_td);
950 uint32_t	ohci_td_cpu_to_iommu(
951 				ohci_state_t		*ohcip,
952 				ohci_td_t		*addr);
953 ohci_td_t	*ohci_td_iommu_to_cpu(
954 				ohci_state_t		*ohcip,
955 				uintptr_t		addr);
956 size_t		ohci_get_td_residue(
957 				ohci_state_t		*ohcip,
958 				ohci_td_t		*td);
959 void		ohci_init_td(
960 				ohci_state_t		*ohcip,
961 				ohci_trans_wrapper_t	*tw,
962 				uint32_t		hctd_dma_offs,
963 				size_t			hctd_length,
964 				ohci_td_t		*td);
965 
966 /* Transfer Wrapper (TW) functions */
967 void		ohci_deallocate_tw_resources(
968 				ohci_state_t		*ohcip,
969 				ohci_pipe_private_t	*pp,
970 				ohci_trans_wrapper_t	*tw);
971 
972 /* Interrupt Handling functions */
973 void		ohci_handle_frame_number_overflow(
974 				ohci_state_t		*ohcip);
975 
976 /* Miscillaneous functions */
977 ohci_state_t	*ohci_obtain_state(
978 				dev_info_t		*dip);
979 int		ohci_state_is_operational(
980 				ohci_state_t		*ohcip);
981 int		ohci_do_soft_reset(
982 				ohci_state_t		*ohcip);
983 usb_frame_number_t ohci_get_current_frame_number(
984 				ohci_state_t		*ohcip);
985 void		ohci_handle_outstanding_requests(
986 				ohci_state_t		*ohcip,
987 				ohci_pipe_private_t	*pp);
988 
989 #ifdef __cplusplus
990 }
991 #endif
992 
993 #endif /* _SYS_USB_OHCID_H */
994