1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_USB_EHCI_H 28 #define _SYS_USB_EHCI_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Enhanced Host Controller Driver (EHCI) 38 * 39 * The EHCI driver is a software driver which interfaces to the Universal 40 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 41 * the Host Controller is defined by the EHCI Host Controller Interface. 42 * 43 * This header file describes the registers and data structures shared by 44 * the EHCI USB controller (HC) and the EHCI Driver. 45 */ 46 47 #include <sys/types.h> 48 #include <sys/pci.h> 49 #include <sys/sunddi.h> 50 #include <sys/sunndi.h> 51 #include <sys/ndi_impldefs.h> 52 #include <sys/disp.h> 53 54 #include <sys/usb/usba.h> 55 56 #include <sys/usb/usba/hcdi.h> 57 58 #include <sys/usb/hubd/hub.h> 59 #include <sys/usb/usba/hubdi.h> 60 #include <sys/usb/hubd/hubdvar.h> 61 62 #include <sys/id32.h> 63 64 #define EHCI_MAX_RH_PORTS 31 /* Maximum root hub ports */ 65 66 67 /* 68 * Each EHCI buffer can hold upto 4k bytes of data. Hence there is a 69 * restriction of 4k alignment while allocating a dma buffer. 70 */ 71 #define EHCI_4K_ALIGN 0x1000 72 73 /* 74 * USB Host controller DMA scatter gather list defines for 75 * Sparc and non-sparc architectures. 76 */ 77 #if defined(__sparc) 78 #define EHCI_DMA_ATTR_MAX_XFER 0xffffffffull 79 #define EHCI_DMA_ATTR_COUNT_MAX 0xffffffffull 80 #define EHCI_DMA_ATTR_GRANULAR 512 81 #define EHCI_DMA_ATTR_ALIGNMENT EHCI_4K_ALIGN 82 #else 83 #define EHCI_DMA_ATTR_MAX_XFER 0x00ffffffull 84 #define EHCI_DMA_ATTR_COUNT_MAX 0x00ffffffull 85 #define EHCI_DMA_ATTR_GRANULAR 1 86 #define EHCI_DMA_ATTR_ALIGNMENT 1 87 #endif 88 89 /* Set the default data structure (QTD,QH,SITD,ITD) to a 32 byte alignment */ 90 #define EHCI_DMA_ATTR_TD_QH_ALIGNMENT 0x0020 91 #define EHCI_DMA_ATTR_PFL_ALIGNMENT EHCI_4K_ALIGN 92 93 /* 94 * EHCI Capability Registers 95 * 96 * The registers specify the limits, restrictions and capabilities of the 97 * specific EHCI Host Controller implementation. 98 */ 99 typedef volatile struct ehci_caps { 100 uint8_t ehci_caps_length; /* Capability register length */ 101 uint8_t ehci_pad; /* Reserved */ 102 uint16_t ehci_version; /* Interface version number */ 103 uint32_t ehci_hcs_params; /* Structural paramters */ 104 uint32_t ehci_hcc_params; /* Capability paramters */ 105 uint8_t ehci_port_route[8]; /* Companion port route */ 106 } ehci_caps_t; 107 108 /* 109 * EHCI revision 110 * 111 * EHCI driver supports EHCI host controllers compliant to 0.95 and higher 112 * revisions of EHCI specifications. 113 */ 114 #define EHCI_REVISION_0_95 0x95 /* Revision 0.95 */ 115 116 /* EHCI HCS Params Register Bits */ 117 #define EHCI_HCS_PORT_INDICATOR 0x00010000 /* Port indicator control */ 118 #define EHCI_HCS_NUM_COMP_CTRLS 0x0000F000 /* No of companion ctrls */ 119 #define EHCI_HCS_NUM_COMP_CTRL_SHIFT 12 120 #define EHCI_HCS_NUM_PORTS_CC 0x00000F00 /* Ports per classic ctrls */ 121 #define EHCI_HCS_NUM_PORTS_CC_SHIFT 8 122 #define EHCI_HCS_PORT_ROUTING_RULES 0x00000080 /* Port routing rules */ 123 #define EHCI_HCS_PORT_POWER_CONTROL 0x00000010 /* Port power control */ 124 #define EHCI_HCS_NUM_PORTS 0x0000000F /* No of root hub ports */ 125 126 /* EHCI HCC Params Register Bits */ 127 #define EHCI_HCC_EECP 0x0000FF00 /* Extended capbilities */ 128 #define EHCI_HCC_EECP_SHIFT 8 129 #define EHCI_HCC_EECP_MIN_OFFSET 0x00000040 /* Minimum valid offset */ 130 #define EHCI_HCC_ISOCH_SCHED_THRESHOLD 0x000000F0 /* Isoch sched threshold */ 131 #define EHCI_HCC_ASYNC_SCHED_PARK_CAP 0x00000004 /* Async schedule park cap */ 132 #define EHCI_HCC_PROG_FRAME_LIST_FLAG 0x00000002 /* Prog frame list flag */ 133 #define EHCI_HCC_64BIT_ADDR_CAP 0x00000001 /* 64bit addr capability */ 134 135 /* EHCI Port Route Register Bits */ 136 #define EHCI_PORT_ROUTE_EVEN 0x0F /* Classic even port route */ 137 #define EHCI_PORT_ROUTE_ODD 0xF0 /* Classic odd port route */ 138 #define EHCI_PORT_ROUTE_ODD_SHIFT 4 139 140 141 /* 142 * EHCI Operational Registers 143 * 144 * The EHCI Host Controller contains a set of on-chip operational registers 145 * which are mapped into a non-cacheable portion of the system addressable 146 * space. These registers are also used by the EHCI Host Controller Driver. 147 * This structure must be aligned to 32 byte boundary. 148 */ 149 typedef volatile struct ehci_regs { 150 /* Control and status registers */ 151 uint32_t ehci_command; /* USB commands */ 152 uint32_t ehci_status; /* USB status */ 153 uint32_t ehci_interrupt; /* Interrupt enable */ 154 uint32_t ehci_frame_index; /* Frame index */ 155 156 /* Memory pointer registers */ 157 uint32_t ehci_ctrl_segment; /* Control data segment */ 158 uint32_t ehci_periodic_list_base; /* Period frm list base addr */ 159 uint32_t ehci_async_list_addr; /* Async list base address */ 160 uint32_t ehci_pad[9]; /* Head of the bulk list */ 161 162 /* Root hub registers */ 163 uint32_t ehci_config_flag; /* Config Flag */ 164 uint32_t ehci_rh_port_status[EHCI_MAX_RH_PORTS]; 165 /* Root hub port status and control information */ 166 } ehci_regs_t; 167 168 /* EHCI Command Register Bits */ 169 #define EHCI_CMD_INTR_THRESHOLD 0x00FF0000 /* Intr threshold control */ 170 #define EHCI_CMD_INTR_SHIFT 16 171 #define EHCI_CMD_01_INTR 0x00010000 /* 01 micro-frame */ 172 #define EHCI_CMD_02_INTR 0x00020000 /* 02 micro-frames */ 173 #define EHCI_CMD_04_INTR 0x00040000 /* 04 micro-frames */ 174 #define EHCI_CMD_08_INTR 0x00080000 /* 08 micro-frames */ 175 #define EHCI_CMD_16_INTR 0x00100000 /* 16 micro-frames */ 176 #define EHCI_CMD_32_INTR 0x00200000 /* 32 micro-frames */ 177 #define EHCI_CMD_64_INTR 0x00400000 /* 64 micro-frames */ 178 179 #define EHCI_CMD_ASYNC_PARK_ENABLE 0x00000800 /* Async sched park enable */ 180 #define EHCI_CMD_ASYNC_PARK_COUNT 0x00000300 /* Async sched park count */ 181 #define EHCI_CMD_ASYNC_PARK_COUNT_1 0x00000100 /* Async sched park cnt 1 */ 182 #define EHCI_CMD_ASYNC_PARK_COUNT_2 0x00000200 /* Async sched park cnt 2 */ 183 #define EHCI_CMD_ASYNC_PARK_COUNT_3 0x00000300 /* Async sched park cnt 3 */ 184 #define EHCI_CMD_ASYNC_PARK_SHIFT 8 185 #define EHCI_CMD_LIGHT_HC_RESET 0x00000080 /* Light host ctrl reset */ 186 #define EHCI_CMD_INTR_ON_ASYNC_ADVANCE 0x00000040 /* Async advance doorbell */ 187 #define EHCI_CMD_ASYNC_SCHED_ENABLE 0x00000020 /* Async schedule enable */ 188 #define EHCI_CMD_PERIODIC_SCHED_ENABLE 0x00000010 /* Periodic sched enable */ 189 #define EHCI_CMD_FRAME_LIST_SIZE 0x0000000C /* Frame list size */ 190 #define EHCI_CMD_FRAME_LIST_SIZE_SHIFT 2 191 #define EHCI_CMD_FRAME_1024_SIZE 0x00000000 /* 1024 frame list size */ 192 #define EHCI_CMD_FRAME_512_SIZE 0x00000004 /* 512 frame list size */ 193 #define EHCI_CMD_FRAME_256_SIZE 0X00000008 /* 256 frame list size */ 194 #define EHCI_CMD_HOST_CTRL_RESET 0x00000002 /* Host controller reset */ 195 #define EHCI_CMD_HOST_CTRL_RS 0x00000001 /* Host ctrl run or stop */ 196 #define EHCI_CMD_HOST_CTRL_RUN 0x00000001 /* Host controller run */ 197 #define EHCI_CMD_HOST_CTRL_STOP 0x00000000 /* Host controller stop */ 198 199 /* EHCI Status Register Bits */ 200 #define EHCI_STS_ASYNC_SCHED_STATUS 0x00008000 /* Async schedule status */ 201 #define EHCI_STS_PERIODIC_SCHED_STATUS 0x00004000 /* Periodic sched status */ 202 #define EHCI_STS_EMPTY_ASYNC_SCHEDULE 0x00002000 /* Empty async schedule */ 203 #define EHCI_STS_HOST_CTRL_HALTED 0x00001000 /* Host controller Halted */ 204 #define EHCI_STS_ASYNC_ADVANCE_INTR 0x00000020 /* Intr on async advance */ 205 #define EHCI_STS_HOST_SYSTEM_ERROR_INTR 0x00000010 /* Host system error */ 206 #define EHCI_STS_FRM_LIST_ROLLOVER_INTR 0x00000008 /* Frame list rollover */ 207 #define EHCI_STS_RH_PORT_CHANGE_INTR 0x00000004 /* Port change detect */ 208 #define EHCI_STS_USB_ERROR_INTR 0x00000002 /* USB error interrupt */ 209 #define EHCI_STS_USB_INTR 0x00000001 /* USB interrupt */ 210 211 /* EHCI Interrupt Register Bits */ 212 #define EHCI_INTR_ASYNC_ADVANCE 0x00000020 /* Async advance interrupt */ 213 #define EHCI_INTR_HOST_SYSTEM_ERROR 0x00000010 /* Host system error intr */ 214 #define EHCI_INTR_FRAME_LIST_ROLLOVER 0x00000008 /* Framelist rollover intr */ 215 #define EHCI_INTR_RH_PORT_CHANGE 0x00000004 /* Port change interrupt */ 216 #define EHCI_INTR_USB_ERROR 0x00000002 /* USB error interrupt */ 217 #define EHCI_INTR_USB 0x00000001 /* USB interrupt */ 218 219 /* EHCI Frame Index Register Bits */ 220 #define EHCI_FRAME_INDEX 0x00003FFF /* Frame index */ 221 #define EHCI_FRAME_1024 0x00003FFF /* 1024 elements */ 222 #define EHCI_FRAME_0512 0x00001FFF /* 512 elements */ 223 #define EHCI_FRAME_0256 0x00000FFF /* 256 elements */ 224 225 /* EHCI Control Data Structure Segment Register Bits */ 226 /* Most significant 32 bits for all EHCI data structures in 64bit addressing */ 227 #define EHCI_CTRLD_SEGMENT 0xFFFFFFFF /* Control data segment */ 228 229 /* EHCI Periodic Frame List Base Address Register Bits */ 230 #define EHCI_PERIODIC_LIST_BASE 0xFFFFF000 /* Periodic framelist addr */ 231 #define EHCI_PERIODIC_LIST_BASE_SHIFT 12 232 233 /* EHCI Asynchronous List Address Register Bits */ 234 #define EHCI_ASYNC_LIST_ADDR 0xFFFFFFE0 /* Async list address */ 235 #define EHCI_ASYNC_LIST_ADDR_SHIFT 5 236 237 /* EHCI Config Flag Register Bits */ 238 #define EHCI_CONFIG_FLAG 0x00000001 /* Route host controllers */ 239 #define EHCI_CONFIG_FLAG_CLASSIC 0x00000000 /* Route to Classic ctrl */ 240 #define EHCI_CONFIG_FLAG_EHCI 0x00000001 /* Route to EHCI ctrl */ 241 242 /* EHCI Root Hub Port Status and Control Register Bits */ 243 #define EHCI_RH_PORT_OVER_CURENT_ENABLE 0x00400000 /* Over current enable */ 244 #define EHCI_RH_PORT_DISCONNECT_ENABLE 0x00200000 /* Disconnect enable */ 245 #define EHCI_RH_PORT_CONNECT_ENABLE 0x00100000 /* Connect enable */ 246 #define EHCI_RH_PORT_INDICATOR 0x0000C000 /* Port indicator control */ 247 #define EHCI_RH_PORT_IND_SHIFT 14 248 #define EHCI_RH_PORT_IND_OFF 0x00000000 /* Port indicators off */ 249 #define EHCI_RH_PORT_IND_AMBER 0x00004000 /* Amber port indicator */ 250 #define EHCI_RH_PORT_IND_GREEN 0x00008000 /* Green port indicator */ 251 #define EHCI_RH_PORT_OWNER 0x00002000 /* Port ownership */ 252 #define EHCI_RH_PORT_OWNER_CLASSIC 0x00002000 /* Classic port ownership */ 253 #define EHCI_RH_PORT_OWNER_EHCI 0x00000000 /* EHCI port ownership */ 254 #define EHCI_RH_PORT_POWER 0x00001000 /* Port power */ 255 #define EHCI_RH_PORT_LINE_STATUS 0x00000C00 /* USB speed line status */ 256 #define EHCI_RH_PORT_LOW_SPEED 0x00000400 /* Low speed */ 257 #define EHCI_RH_PORT_RESET 0x00000100 /* Port reset */ 258 #define EHCI_RH_PORT_SUSPEND 0x00000080 /* Port suspend */ 259 #define EHCI_RH_PORT_RESUME 0x00000040 /* Port resume */ 260 #define EHCI_RH_PORT_OVER_CURR_CHANGE 0x00000020 /* Over current change */ 261 #define EHCI_RH_PORT_OVER_CURR_ACTIVE 0x00000010 /* Over current active */ 262 #define EHCI_RH_PORT_ENABLE_CHANGE 0x00000008 /* Port enable change */ 263 #define EHCI_RH_PORT_ENABLE 0x00000004 /* Port enable */ 264 #define EHCI_RH_PORT_CONNECT_STS_CHANGE 0x00000002 /* Connect status change */ 265 #define EHCI_RH_PORT_CONNECT_STATUS 0x00000001 /* Connect status */ 266 267 /* Root hub port change bits mask */ 268 #define EHCI_RH_PORT_CLEAR_MASK 0x0000002A /* Clear bits mask */ 269 270 271 /* 272 * EHCI Extended Capability Registers 273 * 274 * Currently this register only specifies BIOS handoff information. 275 */ 276 #define EHCI_EX_CAP_SPECIFICS 0xFFFF0000 277 #define EHCI_EX_CAP_SPECIFICS_SHIFT 16 278 #define EHCI_EX_CAP_NEXT_PTR 0x0000FF00 279 #define EHCI_EX_CAP_NEXT_PTR_SHIFT 8 280 #define EHCI_EX_CAP_ID 0x000000FF 281 #define EHCI_EX_CAP_ID_SHIFT 0 282 #define EHCI_EX_CAP_ID_BIOS_HANDOFF 1 283 284 #define EHCI_LEGSUP_OS_OWNED_SEM 0x01000000 285 #define EHCI_LEGSUP_BIOS_OWNED_SEM 0x00010000 286 287 288 /* 289 * Host Controller Periodic Frame List Area 290 * 291 * The Host Controller Periodic Frame List Area is a 4K structre of system 292 * memory that is established by the Host Controller Driver (HCD) and this 293 * structre is used for communication between HCD and HC. The HCD maintains 294 * a pointer to this structure in the Host Controller (HC). This structure 295 * must be aligned to a 4K boundary. There are 1024 periodic frame list 296 * entries. 297 */ 298 299 #define EHCI_NUM_INTR_QH_LISTS 32 /* No of intr lists */ 300 #define EHCI_NUM_STATIC_NODES 63 /* No of static QHs */ 301 #define EHCI_NUM_PERIODIC_FRAME_LISTS 1024 /* No of entries */ 302 303 typedef volatile struct ehci_periodic_frame_list { 304 uint32_t ehci_periodic_frame_list_table[ 305 EHCI_NUM_PERIODIC_FRAME_LISTS]; /* 1024 lists */ 306 } ehci_periodic_frame_list_t; 307 308 309 /* 310 * Host Controller Queue Head 311 * 312 * An Queue Head (QH) is a memory structure that describes the information 313 * necessary for the Host Controller to communicate with a device endpoint 314 * except High Speed and Full Speed Isochronous's endpoints. An QH includes 315 * a Queue Element Transfer Descriptor (QTD) pointer. This structure must 316 * be aligned to a 32 byte boundary. 317 */ 318 typedef volatile struct ehci_qh { 319 /* Endpoint capabilities or characteristics */ 320 uint32_t qh_link_ptr; /* Next QH or ITD or SITD */ 321 uint32_t qh_ctrl; /* Generic control information */ 322 uint32_t qh_split_ctrl; /* Split transaction control info */ 323 uint32_t qh_curr_qtd; /* Current QTD */ 324 325 /* Tranfer overlay */ 326 uint32_t qh_next_qtd; /* Next QTD */ 327 uint32_t qh_alt_next_qtd; /* Next alternate QTD */ 328 uint32_t qh_status; /* Status of current QTD */ 329 uint32_t qh_buf[5]; /* Buffer pointers */ 330 uint32_t qh_buf_high[5]; /* For 64 bit addressing */ 331 332 /* HCD private fields */ 333 uint32_t qh_dummy_qtd; /* Current dummy qtd */ 334 uint32_t qh_prev; /* Prevous QH */ 335 uint32_t qh_state; /* QH's state */ 336 uint32_t qh_reclaim_next; /* Next QH on reclaim list */ 337 uint32_t qh_reclaim_frame; /* Reclaim usb frame number */ 338 uint8_t qh_pad[8]; /* Required padding */ 339 } ehci_qh_t; 340 341 /* 342 * qh_link_ptr control bits. 343 */ 344 #define EHCI_QH_LINK_PTR 0xFFFFFFE0 /* QH link ptr mask */ 345 #define EHCI_QH_LINK_REF 0x00000006 /* Ref to QH/ITD/SITD */ 346 #define EHCI_QH_LINK_REF_ITD 0x00000000 /* Isoch QTD pointer */ 347 #define EHCI_QH_LINK_REF_QH 0x00000002 /* QH pointer */ 348 #define EHCI_QH_LINK_REF_SITD 0x00000004 /* SIQTD pointer */ 349 #define EHCI_QH_LINK_REF_FSTN 0x00000006 /* FSTN pointer */ 350 #define EHCI_QH_LINK_PTR_VALID 0x00000001 /* Link ptr validity */ 351 352 /* 353 * qh_ctrl control bits. 354 */ 355 #define EHCI_QH_CTRL_NC_RL 0xF0000000 /* Nak count reload */ 356 #define EHCI_QH_CTRL_NC_RL_SHIFT 28 /* NC reload shift */ 357 #define EHCI_QH_CTRL_MAX_NC 0xF0000000 /* Max Nak counts */ 358 #define EHCI_QH_CTRL_CONTROL_ED_FLAG 0x08000000 /* Ctrl endpoint flag */ 359 #define EHCI_QH_CTRL_MAXPKTSZ 0x07FF0000 /* Max packet length */ 360 #define EHCI_QH_CTRL_MAXPKTSZ_SHIFT 16 /* Max packet shift */ 361 #define EHCI_QH_CTRL_RECLAIM_HEAD 0x00008000 /* Head reclaim list */ 362 #define EHCI_QH_CTRL_DATA_TOGGLE 0x00004000 /* Data toggle */ 363 #define EHCI_QH_CTRL_ED_SPEED 0x00003000 /* Endpoint speed */ 364 #define EHCI_QH_CTRL_ED_FULL_SPEED 0x00000000 /* FullSpeed endpoint */ 365 #define EHCI_QH_CTRL_ED_LOW_SPEED 0x00001000 /* LowSpeed endpoint */ 366 #define EHCI_QH_CTRL_ED_HIGH_SPEED 0x00002000 /* HighSpeed endpoint */ 367 #define EHCI_QH_CTRL_ED_SPEED_SHIFT 12 /* ED speed shift */ 368 #define EHCI_QH_CTRL_ED_NUMBER 0x00000F00 /* Endpoint number */ 369 #define EHCI_QH_CTRL_ED_NUMBER_SHIFT 8 /* ED number shift */ 370 #define EHCI_QH_CTRL_ED_INACTIVATE 0x00000080 /* Inctivate endpoint */ 371 #define EHCI_QH_CTRL_DEVICE_ADDRESS 0x0000007F /* Device address */ 372 373 /* 374 * q_split_ctrl control bits. 375 */ 376 #define EHCI_QH_SPLIT_CTRL_MULT 0xC0000000 /* HB multiplier */ 377 #define EHCI_QH_SPLIT_CTRL_MULT_SHIFT 30 /* HB mult Shift */ 378 #define EHCI_QH_SPLIT_CTRL_1_XACTS 0x40000000 /* 1 Xacts per uFrame */ 379 #define EHCI_QH_SPLIT_CTRL_2_XACTS 0x80000000 /* 2 Xacts per uFrame */ 380 #define EHCI_QH_SPLIT_CTRL_3_XACTS 0xC0000000 /* 3 Xacts per uFrame */ 381 #define EHCI_QH_SPLIT_CTRL_HUB_PORT 0x3F800000 /* HS hub port number */ 382 #define EHCI_QH_SPLIT_CTRL_HUB_PORT_SHIFT 23 /* HS hubport no shft */ 383 #define EHCI_QH_SPLIT_CTRL_HUB_ADDR 0x007F0000 /* HS hub address */ 384 #define EHCI_QH_SPLIT_CTRL_HUB_ADDR_SHIFT 16 /* HS hub addr mask */ 385 #define EHCI_QH_SPLIT_CTRL_COMP_MASK 0x0000FF00 /* Split comp mask */ 386 #define EHCI_QH_SPLIT_CTRL_COMP_SHIFT 8 /* Split comp shift */ 387 #define EHCI_QH_SPLIT_CTRL_INTR_MASK 0x000000FF /* Intr schedule mask */ 388 389 /* 390 * qh_curr_qtd control bits. 391 */ 392 #define EHCI_QH_CURR_QTD_PTR 0xFFFFFFE0 /* Curr element QTD */ 393 394 /* 395 * qh_next_qtd control bits. 396 */ 397 #define EHCI_QH_NEXT_QTD_PTR 0xFFFFFFE0 /* Next QTD */ 398 #define EHCI_QH_NEXT_QTD_PTR_VALID 0x00000001 /* Next QTD validity */ 399 400 /* 401 * qh_alt_next_qtd control bits. 402 */ 403 #define EHCI_QH_ALT_NEXT_QTD_PTR 0xFFFFFFE0 /* Alternate next QTD */ 404 #define EHCI_QH_ALT_NEXT_QTD_PTR_VALID 0x00000001 /* Alt QTD validity */ 405 #define EHCI_QH_ALT_NEXT_QTD_NAKCNT 0x0000001E /* NAK counter */ 406 407 /* 408 * qh_status control bits. 409 */ 410 #define EHCI_QH_STS_DATA_TOGGLE 0x80000000 /* Data toggle */ 411 #define EHCI_QH_STS_BYTES_TO_XFER 0x7FFF0000 /* Bytes to transfer */ 412 #define EHCI_QH_STS_BYTES_TO_XFER_SHIFT 16 /* Bytes to xfer mask */ 413 #define EHCI_QH_STS_INTR_ON_COMPLETE 0x00008000 /* Intr on complete */ 414 #define EHCI_QH_STS_C_PAGE 0x00007000 /* C page */ 415 #define EHCI_QH_STS_ERROR_COUNTER 0x00000C00 /* Error counter */ 416 #define EHCI_QH_STS_ERROR_COUNT_MASK 0x00000C00 /* Error count mask */ 417 #define EHCI_QH_STS_PID_CODE 0x00000300 /* PID code */ 418 #define EHCI_QH_STS_XACT_STATUS 0x000000FF /* Xact Status */ 419 #define EHCI_QH_STS_HS_XACT_STATUS 0x000000F8 /* HS Xact status */ 420 #define EHCI_QH_STS_NON_HS_XACT_STATUS 0x000000FD /* Non HS Xact status */ 421 #define EHCI_QH_STS_NO_ERROR 0x00000000 /* No error */ 422 #define EHCI_QH_STS_ACTIVE 0x00000080 /* Active */ 423 #define EHCI_QH_STS_HALTED 0x00000040 /* Halted */ 424 #define EHCI_QH_STS_DATA_BUFFER_ERR 0x00000020 /* Data buffer error */ 425 #define EHCI_QH_STS_BABBLE_DETECTED 0x00000010 /* Babble detected */ 426 #define EHCI_QH_STS_XACT_ERROR 0x00000008 /* Transaction error */ 427 #define EHCI_QH_STS_MISSED_uFRAME 0x00000004 /* Missed micro frame */ 428 #define EHCI_QH_STS_SPLIT_XSTATE 0x00000002 /* Split xact state */ 429 #define EHCI_QH_STS_DO_START_SPLIT 0x00000000 /* Do start split */ 430 #define EHCI_QH_STS_DO_COMPLETE_SPLIT 0x00000002 /* Do complete split */ 431 #define EHCI_QH_STS_PING_STATE 0x00000001 /* Ping state */ 432 #define EHCI_QH_STS_DO_OUT 0x00000000 /* Do OUT */ 433 #define EHCI_QH_STS_DO_PING 0x00000001 /* Do PING */ 434 #define EHCI_QH_STS_PRD_SPLIT_XACT_ERR 0x00000001 /* Periodic split err */ 435 436 /* 437 * qh_buf[X] control bits. 438 */ 439 #define EHCI_QH_BUF_PTR 0xFFFFF000 /* Buffer pointer */ 440 #define EHCI_QH_BUF_CURR_OFFSET 0x00000FFF /* Current offset */ 441 #define EHCI_QH_BUF_CPROG_MASK 0x000000FF /* Split progress */ 442 #define EHCI_QH_BUF_SBYTES 0x00000FE0 /* Software S bytes */ 443 #define EHCI_QH_BUF_FRAME_TAG 0x0000001F /* Split xct frametag */ 444 445 /* 446 * qh_buf_high[X] control bits. 447 */ 448 #define EHCI_QH_BUF_HIGH_PTR 0xFFFFFFFF /* For 64 addressing */ 449 450 /* 451 * qh_state 452 * 453 * QH States 454 */ 455 #define EHCI_QH_FREE 1 /* Free QH */ 456 #define EHCI_QH_STATIC 2 /* Static QH */ 457 #define EHCI_QH_ACTIVE 3 /* Active QH */ 458 459 460 /* 461 * Host Controller Queue Element Transfer Descriptor 462 * 463 * A Queue Element Transfer Descriptor (QTD) is a memory structure that 464 * describes the information necessary for the Host Controller (HC) to 465 * transfer a block of data to or from a device endpoint except High 466 * Speed and Full Speed Isochronous's endpoints. These QTD's will be 467 * attached to a Queue Head (QH). This structure must be aligned to a 468 * 32 byte boundary. 469 */ 470 typedef volatile struct ehci_qtd { 471 uint32_t qtd_next_qtd; /* Next QTD */ 472 uint32_t qtd_alt_next_qtd; /* Next alternate QTD */ 473 uint32_t qtd_ctrl; /* Control information */ 474 uint32_t qtd_buf[5]; /* Buffer pointers */ 475 uint32_t qtd_buf_high[5]; /* For 64 bit addressing */ 476 477 /* HCD private fields */ 478 uint32_t qtd_trans_wrapper; /* Transfer wrapper */ 479 uint32_t qtd_tw_next_qtd; /* Next qtd on TW */ 480 uint32_t qtd_active_qtd_next; /* Next QTD on active list */ 481 uint32_t qtd_active_qtd_prev; /* Prev QTD on active list */ 482 uint32_t qtd_state; /* QTD state */ 483 uint32_t qtd_ctrl_phase; /* Control xfer phase info */ 484 uint32_t qtd_xfer_addr; /* Starting buffer address */ 485 uint32_t qtd_xfer_len; /* Transfer length */ 486 uint8_t qtd_pad[12]; /* Required padding */ 487 } ehci_qtd_t; 488 489 /* 490 * qtd_next_qtd control bits. 491 */ 492 #define EHCI_QTD_NEXT_QTD_PTR 0xFFFFFFE0 /* Next QTD pointer */ 493 #define EHCI_QTD_NEXT_QTD_PTR_VALID 0x00000001 /* Next QTD validity */ 494 495 /* 496 * qtd_alt_next_qtd control bits. 497 */ 498 #define EHCI_QTD_ALT_NEXT_QTD_PTR 0xFFFFFFE0 /* Alt QTD pointer */ 499 #define EHCI_QTD_ALT_NEXT_QTD_PTR_VALID 0x00000001 /* Alt QTD validity */ 500 501 /* 502 * qtd_ctrl control bits. 503 */ 504 #define EHCI_QTD_CTRL_DATA_TOGGLE 0x80000000 /* Data toggle */ 505 #define EHCI_QTD_CTRL_DATA_TOGGLE_0 0x00000000 /* Data toggle 0 */ 506 #define EHCI_QTD_CTRL_DATA_TOGGLE_1 0x80000000 /* Data toggle 1 */ 507 #define EHCI_QTD_CTRL_BYTES_TO_XFER 0x7FFF0000 /* Bytes to xfer */ 508 #define EHCI_QTD_CTRL_BYTES_TO_XFER_SHIFT 16 /* Bytes xfer mask */ 509 #define EHCI_QTD_CTRL_INTR_ON_COMPLETE 0x00008000 /* Intr on complete */ 510 #define EHCI_QTD_CTRL_C_PAGE 0x00007000 /* Current page */ 511 #define EHCI_QTD_CTRL_MAX_ERR_COUNTS 0x00000C00 /* Max error counts */ 512 #define EHCI_QTD_CTRL_PID_CODE 0x00000300 /* PID code */ 513 #define EHCI_QTD_CTRL_OUT_PID 0x00000000 /* OUT token */ 514 #define EHCI_QTD_CTRL_IN_PID 0x00000100 /* IN token */ 515 #define EHCI_QTD_CTRL_SETUP_PID 0x00000200 /* SETUP token */ 516 #define EHCI_QTD_CTRL_XACT_STATUS 0x000000FF /* Xact status */ 517 #define EHCI_QTD_CTRL_HS_XACT_STATUS 0x000000F8 /* HS Xact status */ 518 #define EHCI_QTD_CTRL_NON_HS_XACT_STATUS 0x000000FD /* Non HS Xact status */ 519 #define EHCI_QTD_CTRL_NO_ERROR 0x00000000 /* No error */ 520 #define EHCI_QTD_CTRL_ACTIVE_XACT 0x00000080 /* Active xact */ 521 #define EHCI_QTD_CTRL_HALTED_XACT 0x00000040 /* Halted due to err */ 522 #define EHCI_QTD_CTRL_DATA_BUFFER_ERROR 0x00000020 /* Data buffer error */ 523 #define EHCI_QTD_CTRL_ERR_COUNT_MASK 0x00000C00 /* Error count */ 524 #define EHCI_QTD_CTRL_BABBLE_DETECTED 0x00000010 /* Babble detected */ 525 #define EHCI_QTD_CTRL_XACT_ERROR 0x00000008 /* Transaction error */ 526 #define EHCI_QTD_CTRL_MISSED_uFRAME 0x00000004 /* Missed uFrame */ 527 #define EHCI_QTD_CTRL_SPLIT_XACT_STATE 0x00000002 /* Split xact state */ 528 #define EHCI_QTD_CTRL_DO_START_SPLIT 0x00000000 /* Do start split */ 529 #define EHCI_QTD_CTRL_DO_COMPLETE_SPLIT 0x00000002 /* Do complete split */ 530 #define EHCI_QTD_CTRL_PING_STATE 0x00000001 /* Ping state */ 531 #define EHCI_QTD_CTRL_DO_OUT 0x00000000 /* Do OUT */ 532 #define EHCI_QTD_CTRL_DO_PING 0x00000001 /* Do PING */ 533 #define EHCI_QTD_CTRL_PRD_SPLIT_XACT_ERR 0x00000001 /* Periodic split err */ 534 535 /* 536 * qtd_buf[X] control bits. 537 */ 538 #define EHCI_QTD_BUF_PTR 0xFFFFF000 /* Buffer pointer */ 539 #define EHCI_QTD_BUF_CURR_OFFSET 0x00000FFF /* Current offset */ 540 541 /* 542 * qtd_buf_high[X] control bits. 543 */ 544 #define EHCI_QTD_BUF_HIGH_PTR 0xFFFFFFFF /* 64 bit addressing */ 545 546 /* 547 * qtd_state 548 * 549 * QTD States 550 */ 551 #define EHCI_QTD_FREE 1 /* Free QTD */ 552 #define EHCI_QTD_DUMMY 2 /* Dummy QTD */ 553 #define EHCI_QTD_ACTIVE 3 /* Active QTD */ 554 #define EHCI_QTD_RECLAIM 4 /* Reclaim QTD */ 555 556 /* 557 * qtd_ctrl_phase 558 * 559 * Control Transfer Phase information 560 */ 561 #define EHCI_CTRL_SETUP_PHASE 1 /* Setup phase */ 562 #define EHCI_CTRL_DATA_PHASE 2 /* Data phase */ 563 #define EHCI_CTRL_STATUS_PHASE 3 /* Status phase */ 564 565 /* 566 * Host Controller Split Isochronous Transfer Descripter 567 * 568 * iTD/siTD is a memory structure that describes the information necessary for 569 * the Host Controller (HC) to transfer a block of data to or from a 570 * 1.1 isochronous device end point. The iTD/siTD will be inserted between 571 * the periodic frame list and the interrupt tree lattice. This structure 572 * must be aligned to a 32 byte boundary. 573 */ 574 typedef volatile struct ehci_itd { 575 uint32_t itd_link_ptr; /* Next TD */ 576 uint32_t itd_body[15]; /* iTD and siTD body */ 577 578 /* Padding required */ 579 uint32_t itd_pad[8]; 580 581 /* HCD private fields */ 582 uint32_t itd_trans_wrapper; /* Transfer wrapper */ 583 uint32_t itd_itw_next_itd; /* Next iTD on TW */ 584 uint32_t itd_next_active_itd; /* Next iTD in active list */ 585 uint32_t itd_state; /* iTD state */ 586 uint64_t itd_frame_number; /* Frame iTD exists */ 587 uint64_t itd_reclaim_number; /* Frame iTD is reclaimed */ 588 } ehci_itd_t; 589 590 /* 591 * Generic Link Ptr Bits 592 * EHCI_TD_LINK_PTR : Points to the next data object to be processed 593 * EHCI_TD_LINK_PTR_TYPE : Type of reference this descriptor is 594 * EHCI_TD_LINK_PTR_VALID : Is this link pointer valid 595 */ 596 #define EHCI_ITD_LINK_PTR 0xFFFFFFE0 /* TD link ptr mask */ 597 #define EHCI_ITD_LINK_REF 0x00000006 /* Ref to TD/ITD/SITD */ 598 #define EHCI_ITD_LINK_REF_ITD 0x00000000 /* ITD pointer */ 599 #define EHCI_ITD_LINK_REF_QH 0x00000002 /* QH pointer */ 600 #define EHCI_ITD_LINK_REF_SITD 0x00000004 /* SITD pointer */ 601 #define EHCI_ITD_LINK_REF_FSTN 0x00000006 /* FSTN pointer */ 602 #define EHCI_ITD_LINK_PTR_INVALID 0x00000001 /* Link ptr validity */ 603 604 #define EHCI_ITD_CTRL0 0 /* Status and Ctrl List */ 605 #define EHCI_ITD_CTRL1 1 606 #define EHCI_ITD_CTRL2 2 607 #define EHCI_ITD_CTRL3 3 608 #define EHCI_ITD_CTRL4 4 609 #define EHCI_ITD_CTRL5 5 610 #define EHCI_ITD_CTRL6 6 611 #define EHCI_ITD_CTRL7 7 612 #define EHCI_ITD_BUFFER0 8 /* Buffer Page Ptr List */ 613 #define EHCI_ITD_BUFFER1 9 614 #define EHCI_ITD_BUFFER2 10 615 #define EHCI_ITD_BUFFER3 11 616 #define EHCI_ITD_BUFFER4 12 617 #define EHCI_ITD_BUFFER5 13 618 #define EHCI_ITD_BUFFER6 14 619 620 #define EHCI_SITD_CTRL 0 621 #define EHCI_SITD_UFRAME_SCHED 1 622 #define EHCI_SITD_XFER_STATE 2 623 #define EHCI_SITD_BUFFER0 3 624 #define EHCI_SITD_BUFFER1 4 625 #define EHCI_SITD_PREV_SITD 5 626 627 /* 628 * sitd_ctrl bits 629 * EHCI_SITD_CTRL_DIR : Direction of transaction 630 * EHCI_SITD_CTRL_PORT_MASK : Port # of recipient transaction translator(TT) 631 * EHCI_SITD_CTRL_HUB_MASK : Device address of the TT's hub 632 * EHCI_SITD_CTRL_END_PT_MASK : Endpoint # on device serving as data source/sink 633 * EHCI_SITD_CTRL_DEVICE_MASK : Address of device serving as data source/sink 634 */ 635 #define EHCI_SITD_CTRL_DIR 0x80000000 636 #define EHCI_SITD_CTRL_DIR_IN 0x80000000 637 #define EHCI_SITD_CTRL_DIR_OUT 0x00000000 638 #define EHCI_SITD_CTRL_PORT_MASK 0x7F000000 639 #define EHCI_SITD_CTRL_PORT_SHIFT 24 640 #define EHCI_SITD_CTRL_HUB_MASK 0x007F0000 641 #define EHCI_SITD_CTRL_HUB_SHIFT 16 642 #define EHCI_SITD_CTRL_END_PT_MASK 0x00000F00 643 #define EHCI_SITD_CTRL_END_PT_SHIFT 8 644 #define EHCI_SITD_CTRL_DEVICE_MASK 0x0000007F 645 #define EHCI_SITD_CTRL_DEVICE_SHIFT 0 646 647 /* 648 * sitd_uframe_sched bits 649 * EHCI_SITD_UFRAME_CMASK_MASK : Determines which uFrame the HC executes CSplit 650 * EHCI_SITD_UFRAME_SMASK_MASK : Determines which uFrame the HC executes SSplit 651 */ 652 #define EHCI_SITD_UFRAME_CMASK_MASK 0x0000FF00 653 #define EHCI_SITD_UFRAME_CMASK_SHIFT 8 654 #define EHCI_SITD_UFRAME_SMASK_MASK 0x000000FF 655 #define EHCI_SITD_UFRAME_SMASK_SHIFT 0 656 657 /* 658 * sitd_xfer_state bits 659 * EHCI_SITD_XFER_IOC_MASK : Interrupt when transaction is complete. 660 * EHCI_SITD_XFER_PAGE_MASK : Which data page pointer should be concatenated 661 * with the CurrentOffset to construct a data 662 * buffer pointer 663 * EHCI_SITD_XFER_TOTAL_MASK : Total number of bytes expected in xfer(1023 Max). 664 * EHCI_SITD_XFER_CPROG_MASK : HC tracks which CSplit has been executed. 665 * EHCI_SITD_XFER_STATUS_MASK : Status of xfer 666 */ 667 #define EHCI_SITD_XFER_IOC_MASK 0x80000000 668 #define EHCI_SITD_XFER_IOC_ON 0x80000000 669 #define EHCI_SITD_XFER_IOC_OFF 0x00000000 670 #define EHCI_SITD_XFER_PAGE_MASK 0x40000000 671 #define EHCI_SITD_XFER_PAGE_0 0x00000000 672 #define EHCI_SITD_XFER_PAGE_1 0x40000000 673 #define EHCI_SITD_XFER_TOTAL_MASK 0x03FF0000 674 #define EHCI_SITD_XFER_TOTAL_SHIFT 16 675 #define EHCI_SITD_XFER_CPROG_MASK 0x0000FF00 676 #define EHCI_SITD_XFER_CPROG_SHIFT 8 677 #define EHCI_SITD_XFER_STATUS_MASK 0x000000FF 678 #define EHCI_SITD_XFER_STATUS_SHIFT 0 679 #define EHCI_SITD_XFER_ACTIVE 0x80 680 #define EHCI_SITD_XFER_ERROR 0x40 681 #define EHCI_SITD_XFER_DATA_BUFFER_ERR 0x20 682 #define EHCI_SITD_XFER_BABBLE 0x10 683 #define EHCI_SITD_XFER_XACT_ERROR 0x08 684 #define EHCI_SITD_XFER_MISSED_UFRAME 0x04 685 #define EHCI_SITD_XFER_SPLIT_XACT_STATE 0x02 686 #define EHCI_SITD_XFER_SSPLIT_STATE 0x00 687 #define EHCI_SITD_XFER_CSPLIT_STATE 0x02 688 689 /* 690 * sitd_xfer_buffer0/1 691 * EHCI_SITD_XFER_BUFFER_MASK : Buffer Pointer List 692 * EHCI_SITD_XFER_OFFSET_MASK : Current byte offset 693 * EHCI_SITD_XFER_TP_MASK : Transaction position 694 * EHCI_SITD_XFER_TCOUNT_MASK : Transaction count 695 */ 696 #define EHCI_SITD_XFER_BUFFER_MASK 0xFFFFF000 697 #define EHCI_SITD_XFER_BUFFER_SHIFT 12 698 #define EHCI_SITD_XFER_OFFSET_MASK 0x00000FFF 699 #define EHCI_SITD_XFER_OFFSET_SHIFT 0 700 #define EHCI_SITD_XFER_TP_MASK 0x00000018 701 #define EHCI_SITD_XFER_TP_ALL 0x0 702 #define EHCI_SITD_XFER_TP_BEGIN 0x1 703 #define EHCI_SITD_XFER_TP_MID 0x2 704 #define EHCI_SITD_XFER_TP_END 0x3 705 #define EHCI_SITD_XFER_TCOUNT_MASK 0x00000007 706 #define EHCI_SITD_XFER_TCOUNT_SHIFT 0 707 708 /* 709 * qtd_state 710 * 711 * ITD States 712 */ 713 #define EHCI_ITD_FREE 1 /* Free ITD */ 714 #define EHCI_ITD_DUMMY 2 /* Dummy ITD */ 715 #define EHCI_ITD_ACTIVE 3 /* Active ITD */ 716 #define EHCI_ITD_RECLAIM 4 /* Reclaim ITD */ 717 718 #ifdef __cplusplus 719 } 720 #endif 721 722 #endif /* _SYS_USB_EHCI_H */ 723