xref: /illumos-gate/usr/src/uts/common/sys/usb/hcd/ehci/ehci.h (revision 3304303f)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_USB_EHCI_H
27 #define	_SYS_USB_EHCI_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 /*
36  * Enhanced Host Controller Driver (EHCI)
37  *
38  * The EHCI driver is a software driver which interfaces to the Universal
39  * Serial Bus layer (USBA) and the Host Controller (HC). The interface to
40  * the Host Controller is defined by the EHCI Host Controller Interface.
41  *
42  * This header file describes the registers and data structures shared by
43  * the EHCI USB controller (HC) and the EHCI Driver.
44  */
45 
46 #include <sys/types.h>
47 #include <sys/pci.h>
48 #include <sys/sunddi.h>
49 #include <sys/sunndi.h>
50 #include <sys/ndi_impldefs.h>
51 #include <sys/disp.h>
52 
53 #include <sys/usb/usba.h>
54 
55 #include <sys/usb/usba/hcdi.h>
56 
57 #include <sys/usb/hubd/hub.h>
58 #include <sys/usb/usba/hubdi.h>
59 #include <sys/usb/hubd/hubdvar.h>
60 
61 #include <sys/id32.h>
62 
63 #define	EHCI_MAX_RH_PORTS	31	/* Maximum root hub ports */
64 
65 
66 /*
67  * Each EHCI buffer can hold upto 4k bytes of data. Hence there is a
68  * restriction of 4k alignment while allocating a dma buffer.
69  */
70 #define	EHCI_4K_ALIGN			0x1000
71 
72 /*
73  * USB Host controller DMA scatter gather list defines for
74  * Sparc and non-sparc architectures.
75  */
76 #if defined(__sparc)
77 #define	EHCI_DMA_ATTR_MAX_XFER		0xffffffffull
78 #define	EHCI_DMA_ATTR_COUNT_MAX		0xffffffffull
79 #define	EHCI_DMA_ATTR_GRANULAR		512
80 #define	EHCI_DMA_ATTR_ALIGNMENT		EHCI_4K_ALIGN
81 #else
82 #define	EHCI_DMA_ATTR_MAX_XFER		0x00ffffffull
83 #define	EHCI_DMA_ATTR_COUNT_MAX		0x00ffffffull
84 #define	EHCI_DMA_ATTR_GRANULAR		1
85 #define	EHCI_DMA_ATTR_ALIGNMENT		EHCI_4K_ALIGN
86 #endif
87 
88 /* Set the default data structure (QTD,QH,SITD,ITD) to a 32 byte alignment */
89 #define	EHCI_DMA_ATTR_TD_QH_ALIGNMENT	0x0020
90 #define	EHCI_DMA_ATTR_PFL_ALIGNMENT	EHCI_4K_ALIGN
91 
92 /* TW scatter/gatter list defines */
93 #define	EHCI_DMA_ATTR_TW_SGLLEN		0x7fffffff
94 
95 /*
96  * EHCI Capability Registers
97  *
98  * The registers specify the limits, restrictions and capabilities of the
99  * specific EHCI Host Controller implementation.
100  */
101 typedef	volatile struct	ehci_caps {
102 	uint8_t		ehci_caps_length;	/* Capability register length */
103 	uint8_t		ehci_pad;		/* Reserved */
104 	uint16_t	ehci_version;		/* Interface version number */
105 	uint32_t	ehci_hcs_params;	/* Structural paramters */
106 	uint32_t	ehci_hcc_params;	/* Capability paramters */
107 	uint8_t		ehci_port_route[8];	/* Companion port route */
108 } ehci_caps_t;
109 
110 /*
111  * EHCI revision
112  *
113  * EHCI driver supports EHCI host controllers compliant to 0.95 and higher
114  * revisions of EHCI specifications.
115  */
116 #define	EHCI_REVISION_0_95		0x95	   /* Revision 0.95 */
117 
118 /* EHCI HCS Params Register Bits */
119 #define	EHCI_HCS_PORT_INDICATOR		0x00010000 /* Port indicator control */
120 #define	EHCI_HCS_NUM_COMP_CTRLS		0x0000F000 /* No of companion ctrls */
121 #define	EHCI_HCS_NUM_COMP_CTRL_SHIFT	12
122 #define	EHCI_HCS_NUM_PORTS_CC		0x00000F00 /* Ports per classic ctrls */
123 #define	EHCI_HCS_NUM_PORTS_CC_SHIFT	8
124 #define	EHCI_HCS_PORT_ROUTING_RULES	0x00000080 /* Port routing rules */
125 #define	EHCI_HCS_PORT_POWER_CONTROL	0x00000010 /* Port power control */
126 #define	EHCI_HCS_NUM_PORTS		0x0000000F /* No of root hub ports */
127 
128 /* EHCI HCC Params Register Bits */
129 #define	EHCI_HCC_EECP			0x0000FF00 /* Extended capbilities */
130 #define	EHCI_HCC_EECP_SHIFT		8
131 #define	EHCI_HCC_EECP_MIN_OFFSET	0x00000040 /* Minimum valid offset */
132 #define	EHCI_HCC_ISOCH_SCHED_THRESHOLD	0x000000F0 /* Isoch sched threshold */
133 #define	EHCI_HCC_ASYNC_SCHED_PARK_CAP	0x00000004 /* Async schedule park cap */
134 #define	EHCI_HCC_PROG_FRAME_LIST_FLAG	0x00000002 /* Prog frame list flag */
135 #define	EHCI_HCC_64BIT_ADDR_CAP		0x00000001 /* 64bit addr capability */
136 
137 /* EHCI Port Route Register Bits */
138 #define	EHCI_PORT_ROUTE_EVEN		0x0F	   /* Classic even port route */
139 #define	EHCI_PORT_ROUTE_ODD		0xF0	   /* Classic odd port route */
140 #define	EHCI_PORT_ROUTE_ODD_SHIFT	4
141 
142 
143 /*
144  * EHCI Operational Registers
145  *
146  * The EHCI Host Controller contains a set of on-chip operational registers
147  * which are mapped into a non-cacheable portion  of the system addressable
148  * space. These registers are also used by the EHCI Host Controller Driver.
149  * This structure must be aligned to 32 byte boundary.
150  */
151 typedef volatile struct ehci_regs {
152 	/* Control and status registers */
153 	uint32_t	ehci_command;		 /* USB commands */
154 	uint32_t	ehci_status;		 /* USB status */
155 	uint32_t	ehci_interrupt;		 /* Interrupt enable */
156 	uint32_t	ehci_frame_index;	 /* Frame index */
157 
158 	/* Memory pointer registers */
159 	uint32_t	ehci_ctrl_segment;	 /* Control data segment */
160 	uint32_t	ehci_periodic_list_base; /* Period frm list base addr */
161 	uint32_t	ehci_async_list_addr;	 /* Async list base address */
162 	uint32_t	ehci_pad[9];		 /* Head of the bulk list */
163 
164 	/* Root hub registers */
165 	uint32_t	ehci_config_flag;	 /* Config Flag */
166 	uint32_t	ehci_rh_port_status[EHCI_MAX_RH_PORTS];
167 			/* Root hub port status and control information */
168 } ehci_regs_t;
169 
170 /* EHCI Command Register Bits */
171 #define	EHCI_CMD_INTR_THRESHOLD		0x00FF0000 /* Intr threshold control */
172 #define	EHCI_CMD_INTR_SHIFT		16
173 #define	EHCI_CMD_01_INTR		0x00010000 /* 01 micro-frame */
174 #define	EHCI_CMD_02_INTR		0x00020000 /* 02 micro-frames */
175 #define	EHCI_CMD_04_INTR		0x00040000 /* 04 micro-frames */
176 #define	EHCI_CMD_08_INTR		0x00080000 /* 08 micro-frames */
177 #define	EHCI_CMD_16_INTR		0x00100000 /* 16 micro-frames */
178 #define	EHCI_CMD_32_INTR		0x00200000 /* 32 micro-frames */
179 #define	EHCI_CMD_64_INTR		0x00400000 /* 64 micro-frames */
180 
181 #define	EHCI_CMD_ASYNC_PARK_ENABLE	0x00000800 /* Async sched park enable */
182 #define	EHCI_CMD_ASYNC_PARK_COUNT	0x00000300 /* Async sched park count */
183 #define	EHCI_CMD_ASYNC_PARK_COUNT_1	0x00000100 /* Async sched park cnt 1 */
184 #define	EHCI_CMD_ASYNC_PARK_COUNT_2	0x00000200 /* Async sched park cnt 2 */
185 #define	EHCI_CMD_ASYNC_PARK_COUNT_3	0x00000300 /* Async sched park cnt 3 */
186 #define	EHCI_CMD_ASYNC_PARK_SHIFT	8
187 #define	EHCI_CMD_LIGHT_HC_RESET		0x00000080 /* Light host ctrl reset */
188 #define	EHCI_CMD_INTR_ON_ASYNC_ADVANCE	0x00000040 /* Async advance doorbell */
189 #define	EHCI_CMD_ASYNC_SCHED_ENABLE	0x00000020 /* Async schedule enable */
190 #define	EHCI_CMD_PERIODIC_SCHED_ENABLE	0x00000010 /* Periodic sched enable */
191 #define	EHCI_CMD_FRAME_LIST_SIZE	0x0000000C /* Frame list size */
192 #define	EHCI_CMD_FRAME_LIST_SIZE_SHIFT	2
193 #define	EHCI_CMD_FRAME_1024_SIZE	0x00000000 /* 1024 frame list size */
194 #define	EHCI_CMD_FRAME_512_SIZE		0x00000004 /* 512 frame list size */
195 #define	EHCI_CMD_FRAME_256_SIZE		0X00000008 /* 256 frame list size */
196 #define	EHCI_CMD_HOST_CTRL_RESET	0x00000002 /* Host controller reset */
197 #define	EHCI_CMD_HOST_CTRL_RS		0x00000001 /* Host ctrl run or stop */
198 #define	EHCI_CMD_HOST_CTRL_RUN		0x00000001 /* Host controller run */
199 #define	EHCI_CMD_HOST_CTRL_STOP		0x00000000 /* Host controller stop */
200 
201 /* EHCI Status Register Bits */
202 #define	EHCI_STS_ASYNC_SCHED_STATUS	0x00008000 /* Async schedule status */
203 #define	EHCI_STS_PERIODIC_SCHED_STATUS	0x00004000 /* Periodic sched status */
204 #define	EHCI_STS_EMPTY_ASYNC_SCHEDULE	0x00002000 /* Empty async schedule */
205 #define	EHCI_STS_HOST_CTRL_HALTED	0x00001000 /* Host controller Halted */
206 #define	EHCI_STS_ASYNC_ADVANCE_INTR	0x00000020 /* Intr on async advance */
207 #define	EHCI_STS_HOST_SYSTEM_ERROR_INTR	0x00000010 /* Host system error */
208 #define	EHCI_STS_FRM_LIST_ROLLOVER_INTR	0x00000008 /* Frame list rollover */
209 #define	EHCI_STS_RH_PORT_CHANGE_INTR	0x00000004 /* Port change detect */
210 #define	EHCI_STS_USB_ERROR_INTR		0x00000002 /* USB error interrupt */
211 #define	EHCI_STS_USB_INTR		0x00000001 /* USB interrupt */
212 
213 /* EHCI Interrupt Register Bits */
214 #define	EHCI_INTR_ASYNC_ADVANCE		0x00000020 /* Async advance interrupt */
215 #define	EHCI_INTR_HOST_SYSTEM_ERROR	0x00000010 /* Host system error intr */
216 #define	EHCI_INTR_FRAME_LIST_ROLLOVER	0x00000008 /* Framelist rollover intr */
217 #define	EHCI_INTR_RH_PORT_CHANGE	0x00000004 /* Port change interrupt */
218 #define	EHCI_INTR_USB_ERROR		0x00000002 /* USB error interrupt */
219 #define	EHCI_INTR_USB			0x00000001 /* USB interrupt */
220 
221 /* EHCI Frame Index Register Bits */
222 #define	EHCI_FRAME_INDEX		0x00003FFF /* Frame index */
223 #define	EHCI_FRAME_1024			0x00003FFF /* 1024 elements */
224 #define	EHCI_FRAME_0512			0x00001FFF /* 512 elements */
225 #define	EHCI_FRAME_0256			0x00000FFF /* 256 elements */
226 
227 /* EHCI Control Data Structure Segment Register Bits */
228 /* Most significant 32 bits for all EHCI data structures in 64bit addressing */
229 #define	EHCI_CTRLD_SEGMENT		0xFFFFFFFF /* Control data segment */
230 
231 /* EHCI Periodic Frame List Base Address Register Bits */
232 #define	EHCI_PERIODIC_LIST_BASE		0xFFFFF000 /* Periodic framelist addr */
233 #define	EHCI_PERIODIC_LIST_BASE_SHIFT	12
234 
235 /* EHCI Asynchronous List Address Register Bits */
236 #define	EHCI_ASYNC_LIST_ADDR		0xFFFFFFE0 /* Async list address */
237 #define	EHCI_ASYNC_LIST_ADDR_SHIFT	5
238 
239 /* EHCI Config Flag Register Bits */
240 #define	EHCI_CONFIG_FLAG		0x00000001 /* Route host controllers */
241 #define	EHCI_CONFIG_FLAG_CLASSIC	0x00000000 /* Route to Classic ctrl */
242 #define	EHCI_CONFIG_FLAG_EHCI		0x00000001 /* Route to EHCI ctrl */
243 
244 /* EHCI Root Hub Port Status and Control Register Bits */
245 #define	EHCI_RH_PORT_OVER_CURENT_ENABLE	0x00400000 /* Over current enable */
246 #define	EHCI_RH_PORT_DISCONNECT_ENABLE	0x00200000 /* Disconnect enable */
247 #define	EHCI_RH_PORT_CONNECT_ENABLE	0x00100000 /* Connect enable */
248 #define	EHCI_RH_PORT_INDICATOR		0x0000C000 /* Port indicator control */
249 #define	EHCI_RH_PORT_IND_SHIFT		14
250 #define	EHCI_RH_PORT_IND_OFF		0x00000000 /* Port indicators off */
251 #define	EHCI_RH_PORT_IND_AMBER		0x00004000 /* Amber port indicator */
252 #define	EHCI_RH_PORT_IND_GREEN		0x00008000 /* Green port indicator */
253 #define	EHCI_RH_PORT_OWNER		0x00002000 /* Port ownership */
254 #define	EHCI_RH_PORT_OWNER_CLASSIC	0x00002000 /* Classic port ownership */
255 #define	EHCI_RH_PORT_OWNER_EHCI		0x00000000 /* EHCI port ownership */
256 #define	EHCI_RH_PORT_POWER		0x00001000 /* Port power */
257 #define	EHCI_RH_PORT_LINE_STATUS	0x00000C00 /* USB speed line status */
258 #define	EHCI_RH_PORT_LOW_SPEED		0x00000400 /* Low speed */
259 #define	EHCI_RH_PORT_RESET		0x00000100 /* Port reset */
260 #define	EHCI_RH_PORT_SUSPEND		0x00000080 /* Port suspend */
261 #define	EHCI_RH_PORT_RESUME		0x00000040 /* Port resume */
262 #define	EHCI_RH_PORT_OVER_CURR_CHANGE	0x00000020 /* Over current change */
263 #define	EHCI_RH_PORT_OVER_CURR_ACTIVE	0x00000010 /* Over current active */
264 #define	EHCI_RH_PORT_ENABLE_CHANGE	0x00000008 /* Port enable change */
265 #define	EHCI_RH_PORT_ENABLE		0x00000004 /* Port enable */
266 #define	EHCI_RH_PORT_CONNECT_STS_CHANGE	0x00000002 /* Connect status change */
267 #define	EHCI_RH_PORT_CONNECT_STATUS	0x00000001 /* Connect status */
268 
269 /* Root hub port change bits mask */
270 #define	EHCI_RH_PORT_CLEAR_MASK		0x0000002A /* Clear bits mask */
271 
272 
273 /*
274  * EHCI Extended Capability Registers
275  *
276  * Currently this register only specifies BIOS handoff information.
277  */
278 #define	EHCI_EX_CAP_SPECIFICS		0xFFFF0000
279 #define	EHCI_EX_CAP_SPECIFICS_SHIFT	16
280 #define	EHCI_EX_CAP_NEXT_PTR		0x0000FF00
281 #define	EHCI_EX_CAP_NEXT_PTR_SHIFT	8
282 #define	EHCI_EX_CAP_ID			0x000000FF
283 #define	EHCI_EX_CAP_ID_SHIFT		0
284 #define	EHCI_EX_CAP_ID_BIOS_HANDOFF	1
285 
286 #define	EHCI_LEGSUP_OS_OWNED_SEM	0x01000000
287 #define	EHCI_LEGSUP_BIOS_OWNED_SEM	0x00010000
288 
289 
290 /*
291  * Host Controller Periodic Frame List Area
292  *
293  * The Host Controller Periodic Frame List Area is a 4K structre of system
294  * memory that is established by the Host Controller Driver (HCD) and this
295  * structre is used for communication between HCD and HC. The HCD maintains
296  * a pointer to this structure in the Host Controller (HC). This structure
297  * must be aligned to a 4K boundary. There are 1024 periodic frame list
298  * entries.
299  */
300 
301 #define	EHCI_NUM_INTR_QH_LISTS		32	/* No of intr lists */
302 #define	EHCI_NUM_STATIC_NODES		63	/* No of static QHs */
303 #define	EHCI_NUM_PERIODIC_FRAME_LISTS	1024	/* No of entries */
304 
305 typedef volatile struct ehci_periodic_frame_list {
306 	uint32_t	ehci_periodic_frame_list_table[
307 			    EHCI_NUM_PERIODIC_FRAME_LISTS]; /* 1024 lists */
308 } ehci_periodic_frame_list_t;
309 
310 
311 /*
312  * Host Controller Queue Head
313  *
314  * An Queue Head (QH) is a memory structure that describes the information
315  * necessary for the Host Controller to communicate with a device endpoint
316  * except High Speed and Full Speed Isochronous's endpoints. An QH includes
317  * a Queue Element Transfer Descriptor (QTD) pointer.  This structure must
318  * be aligned to a 32 byte boundary.
319  */
320 typedef volatile struct ehci_qh {
321 	/* Endpoint capabilities or characteristics */
322 	uint32_t	qh_link_ptr;	  /* Next QH or ITD or SITD */
323 	uint32_t	qh_ctrl;	  /* Generic control information */
324 	uint32_t	qh_split_ctrl;	  /* Split transaction control info */
325 	uint32_t	qh_curr_qtd;	  /* Current QTD */
326 
327 	/* Tranfer overlay */
328 	uint32_t	qh_next_qtd;	  /* Next QTD */
329 	uint32_t	qh_alt_next_qtd;  /* Next alternate QTD */
330 	uint32_t	qh_status;	  /* Status of current QTD */
331 	uint32_t	qh_buf[5];	  /* Buffer pointers */
332 	uint32_t	qh_buf_high[5];	  /* For 64 bit addressing */
333 
334 	/* HCD private fields */
335 	uint32_t	qh_dummy_qtd;	  /* Current dummy qtd */
336 	uint32_t	qh_prev;	  /* Prevous QH */
337 	uint32_t	qh_state;	  /* QH's state */
338 	uint32_t	qh_reclaim_next;  /* Next QH on reclaim list */
339 	uint32_t	qh_reclaim_frame; /* Reclaim usb frame number */
340 	uint8_t		qh_pad[8];	  /* Required padding */
341 } ehci_qh_t;
342 
343 /*
344  * qh_link_ptr control bits.
345  */
346 #define	EHCI_QH_LINK_PTR		0xFFFFFFE0	/* QH link ptr mask */
347 #define	EHCI_QH_LINK_REF		0x00000006	/* Ref to QH/ITD/SITD */
348 #define	EHCI_QH_LINK_REF_ITD		0x00000000	/* Isoch QTD pointer */
349 #define	EHCI_QH_LINK_REF_QH		0x00000002	/* QH pointer */
350 #define	EHCI_QH_LINK_REF_SITD		0x00000004	/* SIQTD pointer */
351 #define	EHCI_QH_LINK_REF_FSTN		0x00000006	/* FSTN pointer */
352 #define	EHCI_QH_LINK_PTR_VALID		0x00000001	/* Link ptr validity */
353 
354 /*
355  * qh_ctrl control bits.
356  */
357 #define	EHCI_QH_CTRL_NC_RL		0xF0000000	/* Nak count reload */
358 #define	EHCI_QH_CTRL_NC_RL_SHIFT	28		/* NC reload shift */
359 #define	EHCI_QH_CTRL_MAX_NC		0xF0000000	/* Max Nak counts */
360 #define	EHCI_QH_CTRL_CONTROL_ED_FLAG	0x08000000	/* Ctrl endpoint flag */
361 #define	EHCI_QH_CTRL_MAXPKTSZ		0x07FF0000	/* Max packet length */
362 #define	EHCI_QH_CTRL_MAXPKTSZ_SHIFT	16		/* Max packet shift */
363 #define	EHCI_QH_CTRL_RECLAIM_HEAD	0x00008000	/* Head reclaim list */
364 #define	EHCI_QH_CTRL_DATA_TOGGLE	0x00004000	/* Data toggle */
365 #define	EHCI_QH_CTRL_ED_SPEED		0x00003000	/* Endpoint speed */
366 #define	EHCI_QH_CTRL_ED_FULL_SPEED	0x00000000	/* FullSpeed endpoint */
367 #define	EHCI_QH_CTRL_ED_LOW_SPEED	0x00001000	/* LowSpeed endpoint */
368 #define	EHCI_QH_CTRL_ED_HIGH_SPEED	0x00002000	/* HighSpeed endpoint */
369 #define	EHCI_QH_CTRL_ED_SPEED_SHIFT	12		/* ED speed shift */
370 #define	EHCI_QH_CTRL_ED_NUMBER		0x00000F00	/* Endpoint number */
371 #define	EHCI_QH_CTRL_ED_NUMBER_SHIFT	8		/* ED number shift */
372 #define	EHCI_QH_CTRL_ED_INACTIVATE	0x00000080	/* Inctivate endpoint */
373 #define	EHCI_QH_CTRL_DEVICE_ADDRESS	0x0000007F	/* Device address */
374 
375 /*
376  * q_split_ctrl control bits.
377  */
378 #define	EHCI_QH_SPLIT_CTRL_MULT		0xC0000000	/* HB multiplier */
379 #define	EHCI_QH_SPLIT_CTRL_MULT_SHIFT	30		/* HB mult Shift */
380 #define	EHCI_QH_SPLIT_CTRL_1_XACTS	0x40000000	/* 1 Xacts per uFrame */
381 #define	EHCI_QH_SPLIT_CTRL_2_XACTS	0x80000000	/* 2 Xacts per uFrame */
382 #define	EHCI_QH_SPLIT_CTRL_3_XACTS	0xC0000000	/* 3 Xacts per uFrame */
383 #define	EHCI_QH_SPLIT_CTRL_HUB_PORT	0x3F800000	/* HS hub port number */
384 #define	EHCI_QH_SPLIT_CTRL_HUB_PORT_SHIFT 23		/* HS hubport no shft */
385 #define	EHCI_QH_SPLIT_CTRL_HUB_ADDR	0x007F0000	/* HS hub address */
386 #define	EHCI_QH_SPLIT_CTRL_HUB_ADDR_SHIFT 16		/* HS hub addr mask */
387 #define	EHCI_QH_SPLIT_CTRL_COMP_MASK	0x0000FF00	/* Split comp mask */
388 #define	EHCI_QH_SPLIT_CTRL_COMP_SHIFT	8		/* Split comp shift */
389 #define	EHCI_QH_SPLIT_CTRL_INTR_MASK	0x000000FF	/* Intr schedule mask */
390 
391 /*
392  * qh_curr_qtd control bits.
393  */
394 #define	EHCI_QH_CURR_QTD_PTR		0xFFFFFFE0	/* Curr element QTD */
395 
396 /*
397  * qh_next_qtd control bits.
398  */
399 #define	EHCI_QH_NEXT_QTD_PTR		0xFFFFFFE0	/* Next QTD */
400 #define	EHCI_QH_NEXT_QTD_PTR_VALID	0x00000001	/* Next QTD validity */
401 
402 /*
403  * qh_alt_next_qtd control bits.
404  */
405 #define	EHCI_QH_ALT_NEXT_QTD_PTR	0xFFFFFFE0	/* Alternate next QTD */
406 #define	EHCI_QH_ALT_NEXT_QTD_PTR_VALID	0x00000001	/* Alt QTD validity */
407 #define	EHCI_QH_ALT_NEXT_QTD_NAKCNT	0x0000001E	/* NAK counter */
408 
409 /*
410  * qh_status control bits.
411  */
412 #define	EHCI_QH_STS_DATA_TOGGLE		0x80000000	/* Data toggle */
413 #define	EHCI_QH_STS_BYTES_TO_XFER	0x7FFF0000	/* Bytes to transfer */
414 #define	EHCI_QH_STS_BYTES_TO_XFER_SHIFT	16		/* Bytes to xfer mask */
415 #define	EHCI_QH_STS_INTR_ON_COMPLETE	0x00008000	/* Intr on complete */
416 #define	EHCI_QH_STS_C_PAGE		0x00007000	/* C page */
417 #define	EHCI_QH_STS_ERROR_COUNTER	0x00000C00	/* Error counter */
418 #define	EHCI_QH_STS_ERROR_COUNT_MASK	0x00000C00	/* Error count mask */
419 #define	EHCI_QH_STS_PID_CODE		0x00000300	/* PID code */
420 #define	EHCI_QH_STS_XACT_STATUS		0x000000FF	/* Xact Status */
421 #define	EHCI_QH_STS_HS_XACT_STATUS	0x000000F8	/* HS Xact status */
422 #define	EHCI_QH_STS_NON_HS_XACT_STATUS	0x000000FD	/* Non HS Xact status */
423 #define	EHCI_QH_STS_NO_ERROR		0x00000000	/* No error */
424 #define	EHCI_QH_STS_ACTIVE		0x00000080	/* Active */
425 #define	EHCI_QH_STS_HALTED		0x00000040	/* Halted */
426 #define	EHCI_QH_STS_DATA_BUFFER_ERR	0x00000020	/* Data buffer error */
427 #define	EHCI_QH_STS_BABBLE_DETECTED	0x00000010	/* Babble detected */
428 #define	EHCI_QH_STS_XACT_ERROR		0x00000008	/* Transaction error */
429 #define	EHCI_QH_STS_MISSED_uFRAME	0x00000004	/* Missed micro frame */
430 #define	EHCI_QH_STS_SPLIT_XSTATE	0x00000002	/* Split xact state */
431 #define	EHCI_QH_STS_DO_START_SPLIT	0x00000000	/* Do start split */
432 #define	EHCI_QH_STS_DO_COMPLETE_SPLIT	0x00000002	/* Do complete split */
433 #define	EHCI_QH_STS_PING_STATE		0x00000001	/* Ping state */
434 #define	EHCI_QH_STS_DO_OUT		0x00000000	/* Do OUT */
435 #define	EHCI_QH_STS_DO_PING		0x00000001	/* Do PING */
436 #define	EHCI_QH_STS_PRD_SPLIT_XACT_ERR	0x00000001	/* Periodic split err */
437 
438 /*
439  * qh_buf[X] control bits.
440  */
441 #define	EHCI_QH_BUF_PTR			0xFFFFF000	/* Buffer pointer */
442 #define	EHCI_QH_BUF_CURR_OFFSET		0x00000FFF	/* Current offset */
443 #define	EHCI_QH_BUF_CPROG_MASK		0x000000FF	/* Split progress */
444 #define	EHCI_QH_BUF_SBYTES		0x00000FE0	/* Software S bytes */
445 #define	EHCI_QH_BUF_FRAME_TAG		0x0000001F	/* Split xct frametag */
446 
447 /*
448  * qh_buf_high[X] control bits.
449  */
450 #define	EHCI_QH_BUF_HIGH_PTR		0xFFFFFFFF	/* For 64 addressing */
451 
452 /*
453  * qh_state
454  *
455  * QH States
456  */
457 #define	EHCI_QH_FREE			1		/* Free QH */
458 #define	EHCI_QH_STATIC			2		/* Static QH */
459 #define	EHCI_QH_ACTIVE			3		/* Active QH */
460 
461 
462 /*
463  * Host Controller Queue Element Transfer Descriptor
464  *
465  * A Queue Element Transfer Descriptor (QTD) is a memory structure that
466  * describes the information necessary for the Host Controller	(HC) to
467  * transfer a block  of data to or from a device endpoint except High
468  * Speed and Full Speed Isochronous's endpoints. These QTD's will be
469  * attached to a Queue Head (QH). This structure must be aligned to a
470  * 32 byte boundary.
471  */
472 typedef	volatile struct ehci_qtd {
473 	uint32_t	qtd_next_qtd;		/* Next QTD */
474 	uint32_t	qtd_alt_next_qtd;	/* Next alternate QTD */
475 	uint32_t	qtd_ctrl;		/* Control information */
476 	uint32_t	qtd_buf[5];		/* Buffer pointers */
477 	uint32_t	qtd_buf_high[5];	/* For 64 bit addressing */
478 
479 	/* HCD private fields */
480 	uint32_t	qtd_trans_wrapper;	/* Transfer wrapper */
481 	uint32_t	qtd_tw_next_qtd;	/* Next qtd on TW */
482 	uint32_t	qtd_active_qtd_next;	/* Next QTD on active list */
483 	uint32_t	qtd_active_qtd_prev;	/* Prev QTD on active list */
484 	uint32_t	qtd_state;		/* QTD state */
485 	uint32_t	qtd_ctrl_phase;		/* Control xfer phase info */
486 	uint32_t	qtd_xfer_offs;		/* Starting buffer offset */
487 	uint32_t	qtd_xfer_len;		/* Transfer length */
488 	uint8_t		qtd_pad[12];		/* Required padding */
489 } ehci_qtd_t;
490 
491 /*
492  * qtd_next_qtd control bits.
493  */
494 #define	EHCI_QTD_NEXT_QTD_PTR		0xFFFFFFE0	/* Next QTD pointer */
495 #define	EHCI_QTD_NEXT_QTD_PTR_VALID	0x00000001	/* Next QTD validity */
496 
497 /*
498  * qtd_alt_next_qtd control bits.
499  */
500 #define	EHCI_QTD_ALT_NEXT_QTD_PTR	0xFFFFFFE0	/* Alt QTD pointer */
501 #define	EHCI_QTD_ALT_NEXT_QTD_PTR_VALID 0x00000001	/* Alt QTD validity */
502 
503 /*
504  * qtd_ctrl control bits.
505  */
506 #define	EHCI_QTD_CTRL_DATA_TOGGLE	0x80000000	/* Data toggle */
507 #define	EHCI_QTD_CTRL_DATA_TOGGLE_0	0x00000000	/* Data toggle 0 */
508 #define	EHCI_QTD_CTRL_DATA_TOGGLE_1	0x80000000	/* Data toggle 1 */
509 #define	EHCI_QTD_CTRL_BYTES_TO_XFER	0x7FFF0000	/* Bytes to xfer */
510 #define	EHCI_QTD_CTRL_BYTES_TO_XFER_SHIFT 16		/* Bytes xfer mask */
511 #define	EHCI_QTD_CTRL_INTR_ON_COMPLETE	0x00008000	/* Intr on complete */
512 #define	EHCI_QTD_CTRL_C_PAGE		0x00007000	/* Current page */
513 #define	EHCI_QTD_CTRL_MAX_ERR_COUNTS	0x00000C00	/* Max error counts */
514 #define	EHCI_QTD_CTRL_PID_CODE		0x00000300	/* PID code */
515 #define	EHCI_QTD_CTRL_OUT_PID		0x00000000	/* OUT token */
516 #define	EHCI_QTD_CTRL_IN_PID		0x00000100	/* IN token */
517 #define	EHCI_QTD_CTRL_SETUP_PID		0x00000200	/* SETUP token */
518 #define	EHCI_QTD_CTRL_XACT_STATUS	0x000000FF	/* Xact status */
519 #define	EHCI_QTD_CTRL_HS_XACT_STATUS	0x000000F8	/* HS Xact status */
520 #define	EHCI_QTD_CTRL_NON_HS_XACT_STATUS 0x000000FD	/* Non HS Xact status */
521 #define	EHCI_QTD_CTRL_NO_ERROR		0x00000000	/* No error */
522 #define	EHCI_QTD_CTRL_ACTIVE_XACT	0x00000080	/* Active xact */
523 #define	EHCI_QTD_CTRL_HALTED_XACT	0x00000040	/* Halted due to err */
524 #define	EHCI_QTD_CTRL_DATA_BUFFER_ERROR	0x00000020	/* Data buffer error */
525 #define	EHCI_QTD_CTRL_ERR_COUNT_MASK	0x00000C00	/* Error count */
526 #define	EHCI_QTD_CTRL_BABBLE_DETECTED	0x00000010	/* Babble detected */
527 #define	EHCI_QTD_CTRL_XACT_ERROR	0x00000008	/* Transaction error */
528 #define	EHCI_QTD_CTRL_MISSED_uFRAME	0x00000004	/* Missed uFrame */
529 #define	EHCI_QTD_CTRL_SPLIT_XACT_STATE	0x00000002	/* Split xact state */
530 #define	EHCI_QTD_CTRL_DO_START_SPLIT	0x00000000	/* Do start split */
531 #define	EHCI_QTD_CTRL_DO_COMPLETE_SPLIT	0x00000002	/* Do complete split */
532 #define	EHCI_QTD_CTRL_PING_STATE	0x00000001	/* Ping state */
533 #define	EHCI_QTD_CTRL_DO_OUT		0x00000000	/* Do OUT */
534 #define	EHCI_QTD_CTRL_DO_PING		0x00000001	/* Do PING */
535 #define	EHCI_QTD_CTRL_PRD_SPLIT_XACT_ERR 0x00000001	/* Periodic split err */
536 
537 /*
538  * qtd_buf[X] control bits.
539  */
540 #define	EHCI_QTD_BUF_PTR		0xFFFFF000	/* Buffer pointer */
541 #define	EHCI_QTD_BUF_CURR_OFFSET	0x00000FFF	/* Current offset */
542 
543 /*
544  * qtd_buf_high[X] control bits.
545  */
546 #define	EHCI_QTD_BUF_HIGH_PTR		0xFFFFFFFF	/* 64 bit addressing */
547 
548 /*
549  * qtd_state
550  *
551  * QTD States
552  */
553 #define	EHCI_QTD_FREE			1		/* Free QTD */
554 #define	EHCI_QTD_DUMMY			2		/* Dummy QTD */
555 #define	EHCI_QTD_ACTIVE			3		/* Active QTD */
556 #define	EHCI_QTD_RECLAIM		4		/* Reclaim QTD */
557 
558 /*
559  * qtd_ctrl_phase
560  *
561  * Control Transfer Phase information
562  */
563 #define	EHCI_CTRL_SETUP_PHASE		1		/* Setup phase */
564 #define	EHCI_CTRL_DATA_PHASE		2		/* Data phase */
565 #define	EHCI_CTRL_STATUS_PHASE		3		/* Status phase */
566 
567 /*
568  * Host Controller Split Isochronous Transfer Descripter
569  *
570  * iTD/siTD is a memory structure that describes the information necessary for
571  * the Host Controller (HC) to transfer a block of data to or from a
572  * 1.1 isochronous device end point.  The iTD/siTD will be inserted between
573  * the periodic frame list and the interrupt tree lattice.  This structure
574  * must be aligned to a 32 byte boundary.
575  */
576 typedef	volatile struct ehci_itd {
577 	uint32_t	itd_link_ptr;		/* Next TD */
578 	uint32_t	itd_body[15];		/* iTD and siTD body */
579 
580 	/* Padding required */
581 	uint32_t	itd_pad[8];
582 
583 	/* HCD private fields */
584 	uint32_t	itd_trans_wrapper;	/* Transfer wrapper */
585 	uint32_t	itd_itw_next_itd;	/* Next iTD on TW */
586 	uint32_t	itd_next_active_itd;	/* Next iTD in active list */
587 	uint32_t	itd_state;		/* iTD state */
588 	uint64_t	itd_frame_number;	/* Frame iTD exists */
589 	uint64_t	itd_reclaim_number;	/* Frame iTD is reclaimed */
590 } ehci_itd_t;
591 
592 /*
593  * Generic Link Ptr Bits
594  * EHCI_TD_LINK_PTR : Points to the next data object to be processed
595  * EHCI_TD_LINK_PTR_TYPE : Type of reference this descriptor is
596  * EHCI_TD_LINK_PTR_VALID : Is this link pointer valid
597  */
598 #define	EHCI_ITD_LINK_PTR		0xFFFFFFE0	/* TD link ptr mask */
599 #define	EHCI_ITD_LINK_REF		0x00000006	/* Ref to TD/ITD/SITD */
600 #define	EHCI_ITD_LINK_REF_ITD		0x00000000	/* ITD pointer */
601 #define	EHCI_ITD_LINK_REF_QH		0x00000002	/* QH pointer */
602 #define	EHCI_ITD_LINK_REF_SITD		0x00000004	/* SITD pointer */
603 #define	EHCI_ITD_LINK_REF_FSTN		0x00000006	/* FSTN pointer */
604 #define	EHCI_ITD_LINK_PTR_INVALID	0x00000001	/* Link ptr validity */
605 
606 #define	EHCI_ITD_CTRL0			0	/* Status and Ctrl List */
607 #define	EHCI_ITD_CTRL1			1
608 #define	EHCI_ITD_CTRL2			2
609 #define	EHCI_ITD_CTRL3			3
610 #define	EHCI_ITD_CTRL4			4
611 #define	EHCI_ITD_CTRL5			5
612 #define	EHCI_ITD_CTRL6			6
613 #define	EHCI_ITD_CTRL7			7
614 #define	EHCI_ITD_BUFFER0		8	/* Buffer Page Ptr List */
615 #define	EHCI_ITD_BUFFER1		9
616 #define	EHCI_ITD_BUFFER2		10
617 #define	EHCI_ITD_BUFFER3		11
618 #define	EHCI_ITD_BUFFER4		12
619 #define	EHCI_ITD_BUFFER5		13
620 #define	EHCI_ITD_BUFFER6		14
621 
622 #define	EHCI_SITD_CTRL			0
623 #define	EHCI_SITD_UFRAME_SCHED		1
624 #define	EHCI_SITD_XFER_STATE		2
625 #define	EHCI_SITD_BUFFER0		3
626 #define	EHCI_SITD_BUFFER1		4
627 #define	EHCI_SITD_PREV_SITD		5
628 
629 /*
630  * sitd_ctrl bits
631  * EHCI_SITD_CTRL_DIR : Direction of transaction
632  * EHCI_SITD_CTRL_PORT_MASK : Port # of recipient transaction translator(TT)
633  * EHCI_SITD_CTRL_HUB_MASK : Device address of the TT's hub
634  * EHCI_SITD_CTRL_END_PT_MASK : Endpoint # on device serving as data source/sink
635  * EHCI_SITD_CTRL_DEVICE_MASK : Address of device serving as data source/sink
636  */
637 #define	EHCI_SITD_CTRL_DIR		0x80000000
638 #define	EHCI_SITD_CTRL_DIR_IN		0x80000000
639 #define	EHCI_SITD_CTRL_DIR_OUT		0x00000000
640 #define	EHCI_SITD_CTRL_PORT_MASK	0x7F000000
641 #define	EHCI_SITD_CTRL_PORT_SHIFT	24
642 #define	EHCI_SITD_CTRL_HUB_MASK		0x007F0000
643 #define	EHCI_SITD_CTRL_HUB_SHIFT	16
644 #define	EHCI_SITD_CTRL_END_PT_MASK	0x00000F00
645 #define	EHCI_SITD_CTRL_END_PT_SHIFT	8
646 #define	EHCI_SITD_CTRL_DEVICE_MASK	0x0000007F
647 #define	EHCI_SITD_CTRL_DEVICE_SHIFT	0
648 
649 /*
650  * sitd_uframe_sched bits
651  * EHCI_SITD_UFRAME_CMASK_MASK : Determines which uFrame the HC executes CSplit
652  * EHCI_SITD_UFRAME_SMASK_MASK : Determines which uFrame the HC executes SSplit
653  */
654 #define	EHCI_SITD_UFRAME_CMASK_MASK	0x0000FF00
655 #define	EHCI_SITD_UFRAME_CMASK_SHIFT	8
656 #define	EHCI_SITD_UFRAME_SMASK_MASK	0x000000FF
657 #define	EHCI_SITD_UFRAME_SMASK_SHIFT	0
658 
659 /*
660  * sitd_xfer_state bits
661  * EHCI_SITD_XFER_IOC_MASK : Interrupt when transaction is complete.
662  * EHCI_SITD_XFER_PAGE_MASK : Which data page pointer should be concatenated
663  *				with the CurrentOffset to construct a data
664  *				buffer pointer
665  * EHCI_SITD_XFER_TOTAL_MASK : Total number of bytes expected in xfer(1023 Max).
666  * EHCI_SITD_XFER_CPROG_MASK : HC tracks which CSplit has been executed.
667  * EHCI_SITD_XFER_STATUS_MASK : Status of xfer
668  */
669 #define	EHCI_SITD_XFER_IOC_MASK		0x80000000
670 #define	EHCI_SITD_XFER_IOC_ON		0x80000000
671 #define	EHCI_SITD_XFER_IOC_OFF		0x00000000
672 #define	EHCI_SITD_XFER_PAGE_MASK	0x40000000
673 #define	EHCI_SITD_XFER_PAGE_0		0x00000000
674 #define	EHCI_SITD_XFER_PAGE_1		0x40000000
675 #define	EHCI_SITD_XFER_TOTAL_MASK	0x03FF0000
676 #define	EHCI_SITD_XFER_TOTAL_SHIFT	16
677 #define	EHCI_SITD_XFER_CPROG_MASK	0x0000FF00
678 #define	EHCI_SITD_XFER_CPROG_SHIFT	8
679 #define	EHCI_SITD_XFER_STATUS_MASK	0x000000FF
680 #define	EHCI_SITD_XFER_STATUS_SHIFT	0
681 #define	EHCI_SITD_XFER_ACTIVE		0x80
682 #define	EHCI_SITD_XFER_ERROR		0x40
683 #define	EHCI_SITD_XFER_DATA_BUFFER_ERR	0x20
684 #define	EHCI_SITD_XFER_BABBLE		0x10
685 #define	EHCI_SITD_XFER_XACT_ERROR	0x08
686 #define	EHCI_SITD_XFER_MISSED_UFRAME	0x04
687 #define	EHCI_SITD_XFER_SPLIT_XACT_STATE	0x02
688 #define	EHCI_SITD_XFER_SSPLIT_STATE	0x00
689 #define	EHCI_SITD_XFER_CSPLIT_STATE	0x02
690 
691 /*
692  * sitd_xfer_buffer0/1
693  * EHCI_SITD_XFER_BUFFER_MASK : Buffer Pointer List
694  * EHCI_SITD_XFER_OFFSET_MASK : Current byte offset
695  * EHCI_SITD_XFER_TP_MASK : Transaction position
696  * EHCI_SITD_XFER_TCOUNT_MASK : Transaction count
697  */
698 #define	EHCI_SITD_XFER_BUFFER_MASK	0xFFFFF000
699 #define	EHCI_SITD_XFER_BUFFER_SHIFT	12
700 #define	EHCI_SITD_XFER_OFFSET_MASK	0x00000FFF
701 #define	EHCI_SITD_XFER_OFFSET_SHIFT	0
702 #define	EHCI_SITD_XFER_TP_MASK		0x00000018
703 #define	EHCI_SITD_XFER_TP_ALL		0x0
704 #define	EHCI_SITD_XFER_TP_BEGIN		0x1
705 #define	EHCI_SITD_XFER_TP_MID		0x2
706 #define	EHCI_SITD_XFER_TP_END		0x3
707 #define	EHCI_SITD_XFER_TCOUNT_MASK	0x00000007
708 #define	EHCI_SITD_XFER_TCOUNT_SHIFT	0
709 
710 /*
711  * qtd_state
712  *
713  * ITD States
714  */
715 #define	EHCI_ITD_FREE			1		/* Free ITD */
716 #define	EHCI_ITD_DUMMY			2		/* Dummy ITD */
717 #define	EHCI_ITD_ACTIVE			3		/* Active ITD */
718 #define	EHCI_ITD_RECLAIM		4		/* Reclaim ITD */
719 
720 #ifdef __cplusplus
721 }
722 #endif
723 
724 #endif	/* _SYS_USB_EHCI_H */
725