xref: /illumos-gate/usr/src/uts/common/sys/smbios.h (revision bbf21555)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved.
24  * Copyright (c) 2018, Joyent, Inc.
25  * Copyright 2021 Oxide Computer Company
26  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
27  * Use is subject to license terms.
28  */
29 
30 /*
31  * This header file defines the interfaces available from the SMBIOS access
32  * library, libsmbios, and an equivalent kernel module.  This API can be used
33  * to access DMTF SMBIOS data from a device, file, or raw memory buffer.
34  *
35  * This is NOT a Public interface, and should be considered Unstable, as it is
36  * subject to change without notice as the DMTF SMBIOS specification evolves.
37  * Therefore, be aware that any program linked with this API in this
38  * instance of illumos is almost guaranteed to break in the next release.
39  */
40 
41 #ifndef	_SYS_SMBIOS_H
42 #define	_SYS_SMBIOS_H
43 
44 #include <sys/types.h>
45 
46 #ifdef	__cplusplus
47 extern "C" {
48 #endif
49 
50 typedef enum smbios_entry_point_type {
51 	SMBIOS_ENTRY_POINT_21,
52 	SMBIOS_ENTRY_POINT_30
53 } smbios_entry_point_t;
54 
55 /*
56  * SMBIOS Structure Table Entry Point.  See DSP0134 5.2.1 for more information.
57  * The structure table entry point is located by searching for the anchor.
58  */
59 #pragma pack(1)
60 
61 typedef struct smbios_21_entry {
62 	char smbe_eanchor[4];		/* anchor tag (SMB_ENTRY_EANCHOR) */
63 	uint8_t smbe_ecksum;		/* checksum of entry point structure */
64 	uint8_t smbe_elen;		/* length in bytes of entry point */
65 	uint8_t smbe_major;		/* major version of the SMBIOS spec */
66 	uint8_t smbe_minor;		/* minor version of the SMBIOS spec */
67 	uint16_t smbe_maxssize;		/* maximum size in bytes of a struct */
68 	uint8_t smbe_revision;		/* entry point structure revision */
69 	uint8_t smbe_format[5];		/* entry point revision-specific data */
70 	char smbe_ianchor[5];		/* intermed. tag (SMB_ENTRY_IANCHOR) */
71 	uint8_t smbe_icksum;		/* intermed. checksum */
72 	uint16_t smbe_stlen;		/* length in bytes of structure table */
73 	uint32_t smbe_staddr;		/* physical addr of structure table */
74 	uint16_t smbe_stnum;		/* number of structure table entries */
75 	uint8_t smbe_bcdrev;		/* BCD value representing DMI version */
76 } smbios_21_entry_t;
77 
78 /*
79  * The 64-bit SMBIOS 3.0 Entry Point.  See DSP0134 5.2.2 for more information.
80  * The structure table entry point is located by searching for the anchor.
81  */
82 
83 typedef struct smbios_30_entry {
84 	char smbe_eanchor[5];		/* anchor tag (SMB3_ENTRY_EANCHOR) */
85 	uint8_t smbe_ecksum;		/* checksum of entry point structure */
86 	uint8_t smbe_elen;		/* length in bytes of entry point */
87 	uint8_t smbe_major;		/* major version of the SMBIOS spec */
88 	uint8_t smbe_minor;		/* minor version of the SMBIOS spec */
89 	uint8_t smbe_docrev;		/* specification docrev */
90 	uint8_t smbe_revision;		/* entry point structure revision */
91 	uint8_t smbe_reserved;
92 	uint32_t smbe_stlen;		/* length in bytes of structure table */
93 	uint64_t smbe_staddr;		/* physical addr of structure table */
94 } smbios_30_entry_t;
95 
96 typedef union {
97 	smbios_21_entry_t ep21;
98 	smbios_30_entry_t ep30;
99 } smbios_entry_t;
100 
101 #pragma pack()
102 
103 #define	SMB_ENTRY_EANCHOR	"_SM_"	/* structure table entry point anchor */
104 #define	SMB_ENTRY_EANCHORLEN	4	/* length of entry point anchor */
105 #define	SMB3_ENTRY_EANCHOR	"_SM3_"	/* structure table entry point anchor */
106 #define	SMB3_ENTRY_EANCHORLEN	5	/* length of entry point anchor */
107 #define	SMB_ENTRY_IANCHOR	"_DMI_"	/* intermediate anchor string */
108 #define	SMB_ENTRY_IANCHORLEN	5	/* length of intermediate anchor */
109 #define	SMB_ENTRY_MAXLEN	255	/* maximum length of entry point */
110 
111 /*
112  * Structure type codes.  The comments next to each type include an (R) note to
113  * indicate a structure that is required as of SMBIOS v2.8 and an (O) note to
114  * indicate a structure that is obsolete as of SMBIOS v2.8.
115  */
116 #define	SMB_TYPE_BIOS		0	/* BIOS information (R) */
117 #define	SMB_TYPE_SYSTEM		1	/* system information (R) */
118 #define	SMB_TYPE_BASEBOARD	2	/* base board */
119 #define	SMB_TYPE_CHASSIS	3	/* system enclosure or chassis (R) */
120 #define	SMB_TYPE_PROCESSOR	4	/* processor (R) */
121 #define	SMB_TYPE_MEMCTL		5	/* memory controller (O) */
122 #define	SMB_TYPE_MEMMOD		6	/* memory module (O) */
123 #define	SMB_TYPE_CACHE		7	/* processor cache (R) */
124 #define	SMB_TYPE_PORT		8	/* port connector */
125 #define	SMB_TYPE_SLOT		9	/* upgradeable system slot (R) */
126 #define	SMB_TYPE_OBDEVS		10	/* on-board devices (O) */
127 #define	SMB_TYPE_OEMSTR		11	/* OEM string table */
128 #define	SMB_TYPE_SYSCONFSTR	12	/* system configuration string table */
129 #define	SMB_TYPE_LANG		13	/* BIOS language information */
130 #define	SMB_TYPE_GROUP		14	/* group associations */
131 #define	SMB_TYPE_EVENTLOG	15	/* system event log */
132 #define	SMB_TYPE_MEMARRAY	16	/* physical memory array (R) */
133 #define	SMB_TYPE_MEMDEVICE	17	/* memory device (R) */
134 #define	SMB_TYPE_MEMERR32	18	/* 32-bit memory error information */
135 #define	SMB_TYPE_MEMARRAYMAP	19	/* memory array mapped address (R) */
136 #define	SMB_TYPE_MEMDEVICEMAP	20	/* memory device mapped address */
137 #define	SMB_TYPE_POINTDEV	21	/* built-in pointing device */
138 #define	SMB_TYPE_BATTERY	22	/* portable battery */
139 #define	SMB_TYPE_RESET		23	/* system reset settings */
140 #define	SMB_TYPE_SECURITY	24	/* hardware security settings */
141 #define	SMB_TYPE_POWERCTL	25	/* system power controls */
142 #define	SMB_TYPE_VPROBE		26	/* voltage probe */
143 #define	SMB_TYPE_COOLDEV	27	/* cooling device */
144 #define	SMB_TYPE_TPROBE		28	/* temperature probe */
145 #define	SMB_TYPE_IPROBE		29	/* current probe */
146 #define	SMB_TYPE_OOBRA		30	/* out-of-band remote access facility */
147 #define	SMB_TYPE_BIS		31	/* boot integrity services */
148 #define	SMB_TYPE_BOOT		32	/* system boot status (R) */
149 #define	SMB_TYPE_MEMERR64	33	/* 64-bit memory error information */
150 #define	SMB_TYPE_MGMTDEV	34	/* management device */
151 #define	SMB_TYPE_MGMTDEVCP	35	/* management device component */
152 #define	SMB_TYPE_MGMTDEVDATA	36	/* management device threshold data */
153 #define	SMB_TYPE_MEMCHAN	37	/* memory channel */
154 #define	SMB_TYPE_IPMIDEV	38	/* IPMI device information */
155 #define	SMB_TYPE_POWERSUP	39	/* system power supply */
156 #define	SMB_TYPE_ADDINFO	40	/* additional information */
157 #define	SMB_TYPE_OBDEVEXT	41	/* on-board device extended info */
158 #define	SMB_TYPE_MCHI		42	/* mgmt controller host interface */
159 #define	SMB_TYPE_TPM		43	/* TPM device */
160 #define	SMB_TYPE_PROCESSOR_INFO	44	/* Processor Additional Information */
161 #define	SMB_TYPE_FWINFO		45	/* Firmware Inventory Information */
162 #define	SMB_TYPE_STRPROP	46	/* String Property */
163 #define	SMB_TYPE_INACTIVE	126	/* inactive table entry */
164 #define	SMB_TYPE_EOT		127	/* end of table */
165 
166 #define	SMB_TYPE_OEM_LO		128	/* start of OEM-specific type range */
167 #define	SUN_OEM_EXT_PROCESSOR	132	/* processor extended info */
168 #define	SUN_OEM_EXT_PORT	136	/* port extended info */
169 #define	SUN_OEM_PCIEXRC		138	/* PCIE RootComplex/RootPort info */
170 #define	SUN_OEM_EXT_MEMARRAY	144	/* phys memory array extended info */
171 #define	SUN_OEM_EXT_MEMDEVICE	145	/* memory device extended info */
172 #define	SMB_TYPE_OEM_HI		256	/* end of OEM-specific type range */
173 
174 /*
175  * OEM string indicating "Platform Resource Management Specification"
176  * compliance.
177  */
178 #define	SMB_PRMS1	"SUNW-PRMS-1"
179 
180 /*
181  * Some default values set by BIOS vendor
182  */
183 #define	SMB_DEFAULT1	"To Be Filled By O.E.M."
184 #define	SMB_DEFAULT2	"Not Available"
185 #define	SMB_DEFAULT3	"Default string"
186 
187 /*
188  * SMBIOS Common Information.  These structures do not correspond to anything
189  * in the SMBIOS specification, but allow library clients to more easily read
190  * information that is frequently encoded into the various SMBIOS structures.
191  */
192 typedef struct smbios_info {
193 	const char *smbi_manufacturer;	/* manufacturer */
194 	const char *smbi_product;	/* product name */
195 	const char *smbi_version;	/* version */
196 	const char *smbi_serial;	/* serial number */
197 	const char *smbi_asset;		/* asset tag */
198 	const char *smbi_location;	/* location tag */
199 	const char *smbi_part;		/* part number */
200 } smbios_info_t;
201 
202 typedef struct smbios_version {
203 	uint8_t smbv_major;		/* version major number */
204 	uint8_t smbv_minor;		/* version minor number */
205 } smbios_version_t;
206 
207 #define	SMB_CONT_MAX	255		/* maximum contained objects */
208 
209 /*
210  * SMBIOS Bios Information.  See DSP0134 Section 7.1 for more information.
211  * smbb_romsize is converted from the implementation format into bytes. Note, if
212  * we do not have an extended BIOS ROM size, it is filled in with the default
213  * BIOS ROM size.
214  */
215 typedef struct smbios_bios {
216 	const char *smbb_vendor;	/* bios vendor string */
217 	const char *smbb_version;	/* bios version string */
218 	const char *smbb_reldate;	/* bios release date */
219 	uint32_t smbb_segment;		/* bios address segment location */
220 	uint32_t smbb_romsize;		/* bios rom size in bytes */
221 	uint32_t smbb_runsize;		/* bios image size in bytes */
222 	uint64_t smbb_cflags;		/* bios characteristics */
223 	const uint8_t *smbb_xcflags;	/* bios characteristics extensions */
224 	size_t smbb_nxcflags;		/* number of smbb_xcflags[] bytes */
225 	smbios_version_t smbb_biosv;	/* bios version */
226 	smbios_version_t smbb_ecfwv;	/* bios embedded ctrl f/w version */
227 	uint64_t smbb_extromsize;	/* Extended bios ROM Size */
228 } smbios_bios_t;
229 
230 #define	SMB_BIOSFL_RSV0		0x00000001	/* reserved bit zero */
231 #define	SMB_BIOSFL_RSV1		0x00000002	/* reserved bit one */
232 #define	SMB_BIOSFL_UNKNOWN	0x00000004	/* unknown */
233 #define	SMB_BIOSFL_BCNOTSUP	0x00000008	/* BIOS chars not supported */
234 #define	SMB_BIOSFL_ISA		0x00000010	/* ISA is supported */
235 #define	SMB_BIOSFL_MCA		0x00000020	/* MCA is supported */
236 #define	SMB_BIOSFL_EISA		0x00000040	/* EISA is supported */
237 #define	SMB_BIOSFL_PCI		0x00000080	/* PCI is supported */
238 #define	SMB_BIOSFL_PCMCIA	0x00000100	/* PCMCIA is supported */
239 #define	SMB_BIOSFL_PLUGNPLAY	0x00000200	/* Plug and Play is supported */
240 #define	SMB_BIOSFL_APM		0x00000400	/* APM is supported */
241 #define	SMB_BIOSFL_FLASH	0x00000800	/* BIOS is Flash Upgradeable */
242 #define	SMB_BIOSFL_SHADOW	0x00001000	/* BIOS shadowing is allowed */
243 #define	SMB_BIOSFL_VLVESA	0x00002000	/* VL-VESA is supported */
244 #define	SMB_BIOSFL_ESCD		0x00004000	/* ESCD support is available */
245 #define	SMB_BIOSFL_CDBOOT	0x00008000	/* Boot from CD is supported */
246 #define	SMB_BIOSFL_SELBOOT	0x00010000	/* Selectable Boot supported */
247 #define	SMB_BIOSFL_ROMSOCK	0x00020000	/* BIOS ROM is socketed */
248 #define	SMB_BIOSFL_PCMBOOT	0x00040000	/* Boot from PCMCIA supported */
249 #define	SMB_BIOSFL_EDD		0x00080000	/* EDD Spec is supported */
250 #define	SMB_BIOSFL_NEC9800	0x00100000	/* int 0x13 NEC 9800 floppy */
251 #define	SMB_BIOSFL_TOSHIBA	0x00200000	/* int 0x13 Toshiba floppy */
252 #define	SMB_BIOSFL_525_360K	0x00400000	/* int 0x13 5.25" 360K floppy */
253 #define	SMB_BIOSFL_525_12M	0x00800000	/* int 0x13 5.25" 1.2M floppy */
254 #define	SMB_BIOSFL_35_720K	0x01000000	/* int 0x13 3.5" 720K floppy */
255 #define	SMB_BIOSFL_35_288M	0x02000000	/* int 0x13 3.5" 2.88M floppy */
256 #define	SMB_BIOSFL_I5_PRINT	0x04000000	/* int 0x5 print screen svcs */
257 #define	SMB_BIOSFL_I9_KBD	0x08000000	/* int 0x9 8042 keyboard svcs */
258 #define	SMB_BIOSFL_I14_SER	0x10000000	/* int 0x14 serial svcs */
259 #define	SMB_BIOSFL_I17_PRINTER	0x20000000	/* int 0x17 printer svcs */
260 #define	SMB_BIOSFL_I10_CGA	0x40000000	/* int 0x10 CGA svcs */
261 #define	SMB_BIOSFL_NEC_PC98	0x80000000	/* NEC PC-98 */
262 
263 /*
264  * These values are used to allow consumers to have raw access to the extended
265  * characteristic flags. We explicitly don't include the extended BIOS
266  * information from section 3.1 as part of this as it has its own member.
267  */
268 #define	SMB_BIOSXB_1		0	/* bios extension byte 1 (7.1.2.1) */
269 #define	SMB_BIOSXB_2		1	/* bios extension byte 2 (7.1.2.2) */
270 #define	SMB_BIOSXB_BIOS_MAJ	2	/* bios major version */
271 #define	SMB_BIOSXB_BIOS_MIN	3	/* bios minor version */
272 #define	SMB_BIOSXB_ECFW_MAJ	4	/* extended ctlr f/w major version */
273 #define	SMB_BIOSXB_ECFW_MIN	5	/* extended ctlr f/w minor version */
274 
275 #define	SMB_BIOSXB1_ACPI	0x01	/* ACPI is supported */
276 #define	SMB_BIOSXB1_USBL	0x02	/* USB legacy is supported */
277 #define	SMB_BIOSXB1_AGP		0x04	/* AGP is supported */
278 #define	SMB_BIOSXB1_I20		0x08	/* I2O boot is supported */
279 #define	SMB_BIOSXB1_LS120	0x10	/* LS-120 boot is supported */
280 #define	SMB_BIOSXB1_ATZIP	0x20	/* ATAPI ZIP drive boot is supported */
281 #define	SMB_BIOSXB1_1394	0x40	/* 1394 boot is supported */
282 #define	SMB_BIOSXB1_SMBAT	0x80	/* Smart Battery is supported */
283 
284 #define	SMB_BIOSXB2_BBOOT	0x01	/* BIOS Boot Specification supported */
285 #define	SMB_BIOSXB2_FKNETSVC	0x02	/* F-key Network Svc boot supported */
286 #define	SMB_BIOSXB2_ETCDIST	0x04	/* Enable Targeted Content Distrib. */
287 #define	SMB_BIOSXB2_UEFI	0x08	/* UEFI Specification supported */
288 #define	SMB_BIOSXB2_VM		0x10	/* SMBIOS table describes a VM */
289 #define	SMB_BIOSXB2_MFG_MODE	0x20	/* Manufacturing mode is supported */
290 #define	SMB_BIOSXB2_MFG_EN	0x40	/* Manufacturing mode is enabled */
291 
292 /*
293  * SMBIOS System Information.  See DSP0134 Section 7.2 for more information.
294  * The current set of smbs_wakeup values is defined after the structure.
295  */
296 typedef struct smbios_system {
297 	const uint8_t *smbs_uuid;	/* UUID byte array */
298 	uint8_t smbs_uuidlen;		/* UUID byte array length */
299 	uint8_t smbs_wakeup;		/* wake-up event */
300 	const char *smbs_sku;		/* SKU number */
301 	const char *smbs_family;	/* family */
302 } smbios_system_t;
303 
304 #define	SMB_WAKEUP_RSV0		0x00	/* reserved */
305 #define	SMB_WAKEUP_OTHER	0x01	/* other */
306 #define	SMB_WAKEUP_UNKNOWN	0x02	/* unknown */
307 #define	SMB_WAKEUP_APM		0x03	/* APM timer */
308 #define	SMB_WAKEUP_MODEM	0x04	/* modem ring */
309 #define	SMB_WAKEUP_LAN		0x05	/* LAN remote */
310 #define	SMB_WAKEUP_SWITCH	0x06	/* power switch */
311 #define	SMB_WAKEUP_PCIPME	0x07	/* PCI PME# */
312 #define	SMB_WAKEUP_AC		0x08	/* AC power restored */
313 
314 /*
315  * SMBIOS Base Board description.  See DSP0134 Section 7.3 for more
316  * information.  smbb_flags and smbb_type definitions are below.
317  */
318 typedef struct smbios_bboard {
319 	id_t smbb_chassis;		/* chassis containing this board */
320 	uint8_t smbb_flags;		/* flags (see below) */
321 	uint8_t smbb_type;		/* board type (see below) */
322 	uint8_t smbb_contn;		/* number of contained object hdls */
323 } smbios_bboard_t;
324 
325 #define	SMB_BBFL_MOTHERBOARD	0x01	/* board is a motherboard */
326 #define	SMB_BBFL_NEEDAUX	0x02	/* auxiliary card or daughter req'd */
327 #define	SMB_BBFL_REMOVABLE	0x04	/* board is removable */
328 #define	SMB_BBFL_REPLACABLE	0x08	/* board is field-replaceable */
329 #define	SMB_BBFL_HOTSWAP	0x10	/* board is hot-swappable */
330 
331 #define	SMB_BBT_UNKNOWN		0x1	/* unknown */
332 #define	SMB_BBT_OTHER		0x2	/* other */
333 #define	SMB_BBT_SBLADE		0x3	/* server blade */
334 #define	SMB_BBT_CSWITCH		0x4	/* connectivity switch */
335 #define	SMB_BBT_SMM		0x5	/* system management module */
336 #define	SMB_BBT_PROC		0x6	/* processor module */
337 #define	SMB_BBT_IO		0x7	/* i/o module */
338 #define	SMB_BBT_MEM		0x8	/* memory module */
339 #define	SMB_BBT_DAUGHTER	0x9	/* daughterboard */
340 #define	SMB_BBT_MOTHER		0xA	/* motherboard */
341 #define	SMB_BBT_PROCMEM		0xB	/* processor/memory module */
342 #define	SMB_BBT_PROCIO		0xC	/* processor/i/o module */
343 #define	SMB_BBT_INTER		0xD	/* interconnect board */
344 
345 /*
346  * SMBIOS Chassis description.  See DSP0134 Section 7.4 for more information.
347  * We move the lock bit of the type field into smbc_lock for easier processing.
348  */
349 typedef struct smbios_chassis {
350 	uint32_t smbc_oemdata;		/* OEM-specific data */
351 	uint8_t smbc_lock;		/* lock present? */
352 	uint8_t smbc_type;		/* type */
353 	uint8_t smbc_bustate;		/* boot-up state */
354 	uint8_t smbc_psstate;		/* power supply state */
355 	uint8_t smbc_thstate;		/* thermal state */
356 	uint8_t smbc_security;		/* security status */
357 	uint8_t smbc_uheight;		/* enclosure height in U's */
358 	uint8_t smbc_cords;		/* number of power cords */
359 	uint8_t smbc_elems;		/* number of element records (n) */
360 	uint8_t smbc_elemlen;		/* length of contained element (m) */
361 	const char *smbc_sku;		/* SKU number (as a string) */
362 } smbios_chassis_t;
363 
364 #define	SMB_CHT_OTHER		0x01	/* other */
365 #define	SMB_CHT_UNKNOWN		0x02	/* unknown */
366 #define	SMB_CHT_DESKTOP		0x03	/* desktop */
367 #define	SMB_CHT_LPDESKTOP	0x04	/* low-profile desktop */
368 #define	SMB_CHT_PIZZA		0x05	/* pizza box */
369 #define	SMB_CHT_MINITOWER	0x06	/* mini-tower */
370 #define	SMB_CHT_TOWER		0x07	/* tower */
371 #define	SMB_CHT_PORTABLE	0x08	/* portable */
372 #define	SMB_CHT_LAPTOP		0x09	/* laptop */
373 #define	SMB_CHT_NOTEBOOK	0x0A	/* notebook */
374 #define	SMB_CHT_HANDHELD	0x0B	/* hand-held */
375 #define	SMB_CHT_DOCK		0x0C	/* docking station */
376 #define	SMB_CHT_ALLIN1		0x0D	/* all-in-one */
377 #define	SMB_CHT_SUBNOTE		0x0E	/* sub-notebook */
378 #define	SMB_CHT_SPACESAVE	0x0F	/* space-saving */
379 #define	SMB_CHT_LUNCHBOX	0x10	/* lunchbox */
380 #define	SMB_CHT_MAIN		0x11	/* main server chassis */
381 #define	SMB_CHT_EXPANSION	0x12	/* expansion chassis */
382 #define	SMB_CHT_SUB		0x13	/* sub-chassis */
383 #define	SMB_CHT_BUS		0x14	/* bus expansion chassis */
384 #define	SMB_CHT_PERIPHERAL	0x15	/* peripheral chassis */
385 #define	SMB_CHT_RAID		0x16	/* raid chassis */
386 #define	SMB_CHT_RACK		0x17	/* rack mount chassis */
387 #define	SMB_CHT_SEALED		0x18	/* sealed case pc */
388 #define	SMB_CHT_MULTI		0x19	/* multi-system chassis */
389 #define	SMB_CHT_CPCI		0x1A	/* compact PCI */
390 #define	SMB_CHT_ATCA		0x1B	/* advanced TCA */
391 #define	SMB_CHT_BLADE		0x1C	/* blade */
392 #define	SMB_CHT_BLADEENC	0x1D	/* blade enclosure */
393 #define	SMB_CHT_TABLET		0x1E	/* tablet */
394 #define	SMB_CHT_CONVERTIBLE	0x1F	/* convertible */
395 #define	SMB_CHT_DETACHABLE	0x20	/* detachable */
396 #define	SMB_CHT_IOTGW		0x21	/* IoT Gateway */
397 #define	SMB_CHT_EMBEDPC		0x22	/* Embedded PC */
398 #define	SMB_CHT_MINIPC		0x23	/* Mini PC */
399 #define	SMB_CHT_STICKPC		0x24	/* Stick PC */
400 
401 #define	SMB_CHST_OTHER		0x01	/* other */
402 #define	SMB_CHST_UNKNOWN	0x02	/* unknown */
403 #define	SMB_CHST_SAFE		0x03	/* safe */
404 #define	SMB_CHST_WARNING	0x04	/* warning */
405 #define	SMB_CHST_CRITICAL	0x05	/* critical */
406 #define	SMB_CHST_NONREC		0x06	/* non-recoverable */
407 
408 #define	SMB_CHSC_OTHER		0x01	/* other */
409 #define	SMB_CHSC_UNKNOWN	0x02	/* unknown */
410 #define	SMB_CHSC_NONE		0x03	/* none */
411 #define	SMB_CHSC_EILOCK		0x04	/* external interface locked out */
412 #define	SMB_CHSC_EIENAB		0x05	/* external interface enabled */
413 
414 /*
415  * Chassis element record types
416  */
417 typedef struct smbios_chassis_entry {
418 	uint8_t	smbce_type;		/* Type of elt */
419 	uint8_t	smbce_elt;		/* Containing Element */
420 	uint8_t	smbce_min;		/* minimum number of elt */
421 	uint8_t	smbce_max;		/* minimum number of elt */
422 } smbios_chassis_entry_t;
423 
424 #define	SMB_CELT_BBOARD		0	/* smbce_elt is a base board type */
425 #define	SMB_CELT_SMBIOS		1	/* smbce_elt is an smbios type */
426 
427 /*
428  * SMBIOS Processor description.  See DSP0134 Section 7.5 for more details.
429  * If the L1, L2, or L3 cache handle is -1, the cache information is unknown.
430  * If the handle refers to something of size 0, that type of cache is absent.
431  *
432  * NOTE: Although SMBIOS exports a 64-bit CPUID result, this value should not
433  * be used for any purpose other than BIOS debugging.  illumos itself computes
434  * its own CPUID value and applies knowledge of additional errata and processor
435  * specific CPUID variations, so this value should not be used for anything.
436  */
437 typedef struct smbios_processor {
438 	uint64_t smbp_cpuid;		/* processor cpuid information */
439 	uint32_t smbp_family;		/* processor family */
440 	uint8_t smbp_type;		/* processor type (SMB_PRT_*) */
441 	uint8_t smbp_voltage;		/* voltage (SMB_PRV_*) */
442 	uint8_t smbp_status;		/* status (SMB_PRS_*) */
443 	uint8_t smbp_upgrade;		/* upgrade (SMB_PRU_*) */
444 	uint32_t smbp_clkspeed;		/* external clock speed in MHz */
445 	uint32_t smbp_maxspeed;		/* maximum speed in MHz */
446 	uint32_t smbp_curspeed;		/* current speed in MHz */
447 	id_t smbp_l1cache;		/* L1 cache handle */
448 	id_t smbp_l2cache;		/* L2 cache handle */
449 	id_t smbp_l3cache;		/* L3 cache handle */
450 	uint32_t smbp_corecount;
451 		/* number of cores per processor socket */
452 	uint32_t smbp_coresenabled;
453 		/* number of enabled cores per processor socket */
454 	uint32_t smbp_threadcount;
455 		/* number of threads per processor socket */
456 	uint16_t smbp_cflags;
457 		/* processor characteristics (SMB_PRC_*) */
458 } smbios_processor_t;
459 
460 #define	SMB_PRT_OTHER		0x01	/* other */
461 #define	SMB_PRT_UNKNOWN		0x02	/* unknown */
462 #define	SMB_PRT_CENTRAL		0x03	/* central processor */
463 #define	SMB_PRT_MATH		0x04	/* math processor */
464 #define	SMB_PRT_DSP		0x05	/* DSP processor */
465 #define	SMB_PRT_VIDEO		0x06	/* video processor */
466 
467 #define	SMB_PRV_LEGACY(v)	(!((v) & 0x80))	/* legacy voltage mode */
468 #define	SMB_PRV_FIXED(v)	((v) & 0x80)	/* fixed voltage mode */
469 
470 #define	SMB_PRV_5V		0x01	/* 5V is supported */
471 #define	SMB_PRV_33V		0x02	/* 3.3V is supported */
472 #define	SMB_PRV_29V		0x04	/* 2.9V is supported */
473 
474 #define	SMB_PRV_VOLTAGE(v)	((v) & 0x7f)
475 
476 #define	SMB_PRSTATUS_PRESENT(s)	((s) & 0x40)	/* socket is populated */
477 #define	SMB_PRSTATUS_STATUS(s)	((s) & 0x07)	/* status (see below) */
478 
479 #define	SMB_PRS_UNKNOWN		0x0	/* unknown */
480 #define	SMB_PRS_ENABLED		0x1	/* enabled */
481 #define	SMB_PRS_BDISABLED	0x2	/* disabled in bios user setup */
482 #define	SMB_PRS_PDISABLED	0x3	/* disabled in bios from post error */
483 #define	SMB_PRS_IDLE		0x4	/* waiting to be enabled */
484 #define	SMB_PRS_OTHER		0x7	/* other */
485 
486 #define	SMB_PRU_OTHER		0x01	/* other */
487 #define	SMB_PRU_UNKNOWN		0x02	/* unknown */
488 #define	SMB_PRU_DAUGHTER	0x03	/* daughter board */
489 #define	SMB_PRU_ZIF		0x04	/* ZIF socket */
490 #define	SMB_PRU_PIGGY		0x05	/* replaceable piggy back */
491 #define	SMB_PRU_NONE		0x06	/* none */
492 #define	SMB_PRU_LIF		0x07	/* LIF socket */
493 #define	SMB_PRU_SLOT1		0x08	/* slot 1 */
494 #define	SMB_PRU_SLOT2		0x09	/* slot 2 */
495 #define	SMB_PRU_370PIN		0x0A	/* 370-pin socket */
496 #define	SMB_PRU_SLOTA		0x0B	/* slot A */
497 #define	SMB_PRU_SLOTM		0x0C	/* slot M */
498 #define	SMB_PRU_423		0x0D	/* socket 423 */
499 #define	SMB_PRU_A		0x0E	/* socket A (socket 462) */
500 #define	SMB_PRU_478		0x0F	/* socket 478 */
501 #define	SMB_PRU_754		0x10	/* socket 754 */
502 #define	SMB_PRU_940		0x11	/* socket 940 */
503 #define	SMB_PRU_939		0x12	/* socket 939 */
504 #define	SMB_PRU_MPGA604		0x13	/* mPGA604 */
505 #define	SMB_PRU_LGA771		0x14	/* LGA771 */
506 #define	SMB_PRU_LGA775		0x15	/* LGA775 */
507 #define	SMB_PRU_S1		0x16	/* socket S1 */
508 #define	SMB_PRU_AM2		0x17	/* socket AM2 */
509 #define	SMB_PRU_F		0x18	/* socket F */
510 #define	SMB_PRU_LGA1366		0x19	/* LGA1366 */
511 #define	SMB_PRU_G34		0x1A	/* socket G34 */
512 #define	SMB_PRU_AM3		0x1B	/* socket AM3 */
513 #define	SMB_PRU_C32		0x1C	/* socket C32 */
514 #define	SMB_PRU_LGA1156		0x1D	/* LGA1156 */
515 #define	SMB_PRU_LGA1567		0x1E	/* LGA1567 */
516 #define	SMB_PRU_PGA988A		0x1F	/* PGA988A */
517 #define	SMB_PRU_BGA1288		0x20	/* BGA1288 */
518 #define	SMB_PRU_RPGA988B	0x21	/* rPGA988B */
519 #define	SMB_PRU_BGA1023		0x22	/* BGA1023 */
520 #define	SMB_PRU_BGA1224		0x23	/* BGA1224 */
521 #define	SMB_PRU_LGA1155		0x24	/* LGA1155 */
522 #define	SMB_PRU_LGA1356		0x25	/* LGA1356 */
523 #define	SMB_PRU_LGA2011		0x26	/* LGA2011 */
524 #define	SMB_PRU_FS1		0x27	/* socket FS1 */
525 #define	SMB_PRU_FS2		0x28	/* socket FS2 */
526 #define	SMB_PRU_FM1		0x29	/* socket FM1 */
527 #define	SMB_PRU_FM2		0x2A	/* socket FM2 */
528 #define	SMB_PRU_LGA20113	0x2B	/* LGA2011-3 */
529 #define	SMB_PRU_LGA13563	0x2C	/* LGA1356-3 */
530 #define	SMB_PRU_LGA1150		0x2D	/* LGA1150 */
531 #define	SMB_PRU_BGA1168		0x2E	/* BGA1168 */
532 #define	SMB_PRU_BGA1234		0x2F	/* BGA1234 */
533 #define	SMB_PRU_BGA1364		0x30	/* BGA1364 */
534 #define	SMB_PRU_AM4		0x31	/* socket AM4 */
535 #define	SMB_PRU_LGA1151		0x32	/* LGA1151 */
536 #define	SMB_PRU_BGA1356		0x33	/* BGA1356 */
537 #define	SMB_PRU_BGA1440		0x34	/* BGA1440 */
538 #define	SMB_PRU_BGA1515		0x35	/* BGA1515 */
539 #define	SMB_PRU_LGA36471	0x36	/* LGA3647-1 */
540 #define	SMB_PRU_SP3		0x37	/* socket SP3 */
541 #define	SMB_PRU_SP3r2		0x38	/* socket SP3r2 */
542 #define	SMB_PRU_LGA2066		0x39	/* Socket LGA2066 */
543 #define	SMB_PRU_BGA1392		0x3A	/* Socket BGA1392 */
544 #define	SMB_PRU_BGA1510		0x3B	/* Socket BGA1510 */
545 #define	SMB_PRU_BGA1528		0x3C	/* Socket BGA1528 */
546 #define	SMB_PRU_LGA4189		0x3D	/* Socket LGA4189 */
547 #define	SMB_PRU_LGA1200		0x3E	/* Socket LGA1200 */
548 #define	SMB_PRU_LGA4677		0x3F	/* Socket LGA4677 */
549 
550 #define	SMB_PRC_RESERVED	0x0001	/* reserved */
551 #define	SMB_PRC_UNKNOWN		0x0002	/* unknown */
552 #define	SMB_PRC_64BIT		0x0004	/* 64-bit capable */
553 #define	SMB_PRC_MC		0x0008	/* multi-core */
554 #define	SMB_PRC_HT		0x0010	/* hardware thread */
555 #define	SMB_PRC_NX		0x0020	/* execution protection */
556 #define	SMB_PRC_VT		0x0040	/* enhanced virtualization */
557 #define	SMB_PRC_PM		0x0080	/* power/performance control */
558 #define	SMB_PRC_128BIT		0x0100	/* 128-bit capable */
559 
560 #define	SMB_PRF_OTHER		0x01	/* other */
561 #define	SMB_PRF_UNKNOWN		0x02	/* unknown */
562 #define	SMB_PRF_8086		0x03	/* 8086 */
563 #define	SMB_PRF_80286		0x04	/* 80286 */
564 #define	SMB_PRF_I386		0x05	/* Intel 386 */
565 #define	SMB_PRF_I486		0x06	/* Intel 486 */
566 #define	SMB_PRF_8087		0x07	/* 8087 */
567 #define	SMB_PRF_80287		0x08	/* 80287 */
568 #define	SMB_PRF_80387		0x09	/* 80387 */
569 #define	SMB_PRF_80487		0x0A	/* 80487 */
570 #define	SMB_PRF_PENTIUM		0x0B	/* Pentium Family */
571 #define	SMB_PRF_PENTIUMPRO	0x0C	/* Pentium Pro */
572 #define	SMB_PRF_PENTIUMII	0x0D	/* Pentium II */
573 #define	SMB_PRF_PENTIUM_MMX	0x0E	/* Pentium w/ MMX */
574 #define	SMB_PRF_CELERON		0x0F	/* Celeron */
575 #define	SMB_PRF_PENTIUMII_XEON	0x10	/* Pentium II Xeon */
576 #define	SMB_PRF_PENTIUMIII	0x11	/* Pentium III */
577 #define	SMB_PRF_M1		0x12	/* M1 */
578 #define	SMB_PRF_M2		0x13	/* M2 */
579 #define	SMB_PRF_CELERON_M	0x14	/* Celeron M */
580 #define	SMB_PRF_PENTIUMIV_HT	0x15	/* Pentium 4 HT */
581 #define	SMB_PRF_DURON		0x18	/* AMD Duron */
582 #define	SMB_PRF_K5		0x19	/* K5 */
583 #define	SMB_PRF_K6		0x1A	/* K6 */
584 #define	SMB_PRF_K6_2		0x1B	/* K6-2 */
585 #define	SMB_PRF_K6_3		0x1C	/* K6-3 */
586 #define	SMB_PRF_ATHLON		0x1D	/* Athlon */
587 #define	SMB_PRF_2900		0x1E	/* AMD 2900 */
588 #define	SMB_PRF_K6_2PLUS	0x1F	/* K6-2+ */
589 #define	SMB_PRF_PPC		0x20	/* PowerPC */
590 #define	SMB_PRF_PPC_601		0x21	/* PowerPC 601 */
591 #define	SMB_PRF_PPC_603		0x22	/* PowerPC 603 */
592 #define	SMB_PRF_PPC_603PLUS	0x23	/* PowerPC 603+ */
593 #define	SMB_PRF_PPC_604		0x24	/* PowerPC 604 */
594 #define	SMB_PRF_PPC_620		0x25	/* PowerPC 620 */
595 #define	SMB_PRF_PPC_704		0x26	/* PowerPC x704 */
596 #define	SMB_PRF_PPC_750		0x27	/* PowerPC 750 */
597 #define	SMB_PRF_CORE_DUO	0x28	/* Core Duo */
598 #define	SMB_PRF_CORE_DUO_M	0x29	/* Core Duo mobile */
599 #define	SMB_PRF_CORE_SOLO_M	0x2A	/* Core Solo mobile */
600 #define	SMB_PRF_ATOM		0x2B	/* Intel Atom */
601 #define	SMB_PRF_CORE_M		0x2C	/* Intel Core M */
602 #define	SMB_PRF_CORE_M3		0x2D	/* Intel Core m3 */
603 #define	SMB_PRF_CORE_M5		0x2E	/* Intel Core m5 */
604 #define	SMB_PRF_CORE_M7		0x2F	/* Intel Core m7 */
605 #define	SMB_PRF_ALPHA		0x30	/* Alpha */
606 #define	SMB_PRF_ALPHA_21064	0x31	/* Alpha 21064 */
607 #define	SMB_PRF_ALPHA_21066	0x32	/* Alpha 21066 */
608 #define	SMB_PRF_ALPHA_21164	0x33	/* Alpha 21164 */
609 #define	SMB_PRF_ALPHA_21164PC	0x34	/* Alpha 21164PC */
610 #define	SMB_PRF_ALPHA_21164A	0x35	/* Alpha 21164a */
611 #define	SMB_PRF_ALPHA_21264	0x36	/* Alpha 21264 */
612 #define	SMB_PRF_ALPHA_21364	0x37	/* Alpha 21364 */
613 #define	SMB_PRF_TURION2U_2C_MM	0x38
614 			/* AMD Turion II Ultra Dual-Core Mobile M */
615 #define	SMB_PRF_TURION2_2C_MM	0x39	/* AMD Turion II Dual-Core Mobile M */
616 #define	SMB_PRF_ATHLON2_2C_M	0x3A	/* AMD Athlon II Dual-Core M */
617 #define	SMB_PRF_OPTERON_6100	0x3B	/* AMD Opteron 6100 series */
618 #define	SMB_PRF_OPTERON_4100	0x3C	/* AMD Opteron 4100 series */
619 #define	SMB_PRF_OPTERON_6200	0x3D	/* AMD Opteron 6200 series */
620 #define	SMB_PRF_OPTERON_4200	0x3E	/* AMD Opteron 4200 series */
621 #define	SMB_PRF_AMD_FX		0x3F	/* AMD FX series */
622 #define	SMB_PRF_MIPS		0x40	/* MIPS */
623 #define	SMB_PRF_MIPS_R4000	0x41	/* MIPS R4000 */
624 #define	SMB_PRF_MIPS_R4200	0x42	/* MIPS R4200 */
625 #define	SMB_PRF_MIPS_R4400	0x43	/* MIPS R4400 */
626 #define	SMB_PRF_MIPS_R4600	0x44	/* MIPS R4600 */
627 #define	SMB_PRF_MIPS_R10000	0x45	/* MIPS R10000 */
628 #define	SMB_PRF_AMD_C		0x46	/* AMD C-series */
629 #define	SMB_PRF_AMD_E		0x47	/* AMD E-series */
630 #define	SMB_PRF_AMD_A		0x48	/* AMD A-series */
631 #define	SMB_PRF_AMD_G		0x49	/* AMD G-series */
632 #define	SMB_PRF_AMD_Z		0x4A	/* AMD Z-series */
633 #define	SMB_PRF_AMD_R		0x4B	/* AMD R-series */
634 #define	SMB_PRF_OPTERON_4300	0x4C	/* AMD Opteron 4300 series */
635 #define	SMB_PRF_OPTERON_6300	0x4D	/* AMD Opteron 6300 series */
636 #define	SMB_PRF_OPTERON_3300	0x4E	/* AMD Opteron 3300 series */
637 #define	SMB_PRF_AMD_FIREPRO	0x4F	/* AMD FirePro series */
638 #define	SMB_PRF_SPARC		0x50	/* SPARC */
639 #define	SMB_PRF_SUPERSPARC	0x51	/* SuperSPARC */
640 #define	SMB_PRF_MICROSPARCII	0x52	/* microSPARC II */
641 #define	SMB_PRF_MICROSPARCIIep	0x53	/* microSPARC IIep */
642 #define	SMB_PRF_ULTRASPARC	0x54	/* UltraSPARC */
643 #define	SMB_PRF_USII		0x55	/* UltraSPARC II */
644 #define	SMB_PRF_USIIi		0x56	/* UltraSPARC IIi */
645 #define	SMB_PRF_USIII		0x57	/* UltraSPARC III */
646 #define	SMB_PRF_USIIIi		0x58	/* UltraSPARC IIIi */
647 #define	SMB_PRF_68040		0x60	/* 68040 */
648 #define	SMB_PRF_68XXX		0x61	/* 68XXX */
649 #define	SMB_PRF_68000		0x62	/* 68000 */
650 #define	SMB_PRF_68010		0x63	/* 68010 */
651 #define	SMB_PRF_68020		0x64	/* 68020 */
652 #define	SMB_PRF_68030		0x65	/* 68030 */
653 #define	SMB_PRF_ATHLON_X4	0x66	/* AMD Athlon X4 Quad-Core */
654 #define	SMB_PRF_OPTERON_X1K	0x67	/* AMD Opteron X1000 */
655 #define	SMB_PRF_OPTERON_X2K	0x68	/* AMD Opteron X2000 APU */
656 #define	SMB_PRF_OPTERON_A	0x69	/* AMD Opteron A Series */
657 #define	SMB_PRF_OPTERON_X3K	0x6A	/* AMD Opteron X3000 APU */
658 #define	SMB_PRF_ZEN		0x6B	/* AMD Zen Processor Family */
659 #define	SMB_PRF_HOBBIT		0x70	/* Hobbit */
660 #define	SMB_PRF_TM5000		0x78	/* Crusoe TM5000 */
661 #define	SMB_PRF_TM3000		0x79	/* Crusoe TM3000 */
662 #define	SMB_PRF_TM8000		0x7A	/* Efficeon TM8000 */
663 #define	SMB_PRF_WEITEK		0x80	/* Weitek */
664 #define	SMB_PRF_ITANIC		0x82	/* Itanium */
665 #define	SMB_PRF_ATHLON64	0x83	/* Athlon64 */
666 #define	SMB_PRF_OPTERON		0x84	/* Opteron */
667 #define	SMB_PRF_SEMPRON		0x85    /* Sempron */
668 #define	SMB_PRF_TURION64_M	0x86	/* Turion 64 Mobile */
669 #define	SMB_PRF_OPTERON_2C	0x87	/* AMD Opteron Dual-Core */
670 #define	SMB_PRF_ATHLON64_X2_2C	0x88	/* AMD Athlon 64 X2 Dual-Core */
671 #define	SMB_PRF_TURION64_X2_M	0x89	/* AMD Turion 64 X2 Mobile */
672 #define	SMB_PRF_OPTERON_4C	0x8A	/* AMD Opteron Quad-Core */
673 #define	SMB_PRF_OPTERON_3G	0x8B	/* AMD Opteron 3rd Generation */
674 #define	SMB_PRF_PHENOM_FX_4C	0x8C	/* AMD Phenom FX Quad-Core */
675 #define	SMB_PRF_PHENOM_X4_4C	0x8D	/* AMD Phenom X4 Quad-Core */
676 #define	SMB_PRF_PHENOM_X2_2C	0x8E	/* AMD Phenom X2 Dual-Core */
677 #define	SMB_PRF_ATHLON_X2_2C	0x8F	/* AMD Athlon X2 Dual-Core */
678 #define	SMB_PRF_PA		0x90	/* PA-RISC */
679 #define	SMB_PRF_PA8500		0x91	/* PA-RISC 8500 */
680 #define	SMB_PRF_PA8000		0x92	/* PA-RISC 8000 */
681 #define	SMB_PRF_PA7300LC	0x93	/* PA-RISC 7300LC */
682 #define	SMB_PRF_PA7200		0x94	/* PA-RISC 7200 */
683 #define	SMB_PRF_PA7100LC	0x95	/* PA-RISC 7100LC */
684 #define	SMB_PRF_PA7100		0x96	/* PA-RISC 7100 */
685 #define	SMB_PRF_V30		0xA0	/* V30 */
686 #define	SMB_PRF_XEON_4C_3200	0xA1	/* Xeon Quad Core 3200 */
687 #define	SMB_PRF_XEON_2C_3000	0xA2	/* Xeon Dual Core 3000 */
688 #define	SMB_PRF_XEON_4C_5300	0xA3	/* Xeon Quad Core 5300 */
689 #define	SMB_PRF_XEON_2C_5100	0xA4	/* Xeon Dual Core 5100 */
690 #define	SMB_PRF_XEON_2C_5000	0xA5	/* Xeon Dual Core 5000 */
691 #define	SMB_PRF_XEON_2C_LV	0xA6	/* Xeon Dual Core LV */
692 #define	SMB_PRF_XEON_2C_ULV	0xA7	/* Xeon Dual Core ULV */
693 #define	SMB_PRF_XEON_2C_7100	0xA8	/* Xeon Dual Core 7100 */
694 #define	SMB_PRF_XEON_4C_5400	0xA9	/* Xeon Quad Core 5400 */
695 #define	SMB_PRF_XEON_4C		0xAA	/* Xeon Quad Core */
696 #define	SMB_PRF_XEON_2C_5200	0xAB	/* Xeon Dual Core 5200 */
697 #define	SMB_PRF_XEON_2C_7200	0xAC	/* Xeon Dual Core 7200 */
698 #define	SMB_PRF_XEON_4C_7300	0xAD	/* Xeon Quad Core 7300 */
699 #define	SMB_PRF_XEON_4C_7400	0xAE	/* Xeon Quad Core 7400 */
700 #define	SMB_PRF_XEON_XC_7400	0xAF	/* Xeon Multi Core 7400 */
701 #define	SMB_PRF_PENTIUMIII_XEON	0xB0	/* Pentium III Xeon */
702 #define	SMB_PRF_PENTIUMIII_SS	0xB1	/* Pentium III with SpeedStep */
703 #define	SMB_PRF_P4		0xB2	/* Pentium 4 */
704 #define	SMB_PRF_XEON		0xB3	/* Intel Xeon */
705 #define	SMB_PRF_AS400		0xB4	/* AS400 */
706 #define	SMB_PRF_XEON_MP		0xB5	/* Intel Xeon MP */
707 #define	SMB_PRF_ATHLON_XP	0xB6	/* AMD Athlon XP */
708 #define	SMB_PRF_ATHLON_MP	0xB7	/* AMD Athlon MP */
709 #define	SMB_PRF_ITANIC2		0xB8	/* Itanium 2 */
710 #define	SMB_PRF_PENTIUM_M	0xB9	/* Pentium M */
711 #define	SMB_PRF_CELERON_D	0xBA	/* Celeron D */
712 #define	SMB_PRF_PENTIUM_D	0xBB	/* Pentium D */
713 #define	SMB_PRF_PENTIUM_EE	0xBC	/* Pentium Extreme Edition */
714 #define	SMB_PRF_CORE_SOLO	0xBD	/* Intel Core Solo */
715 #define	SMB_PRF_CORE2_DUO	0xBF	/* Intel Core 2 Duo */
716 #define	SMB_PRF_CORE2_SOLO	0xC0	/* Intel Core 2 Solo */
717 #define	SMB_PRF_CORE2_EX	0xC1	/* Intel Core 2 Extreme */
718 #define	SMB_PRF_CORE2_QUAD	0xC2	/* Intel Core 2 Quad */
719 #define	SMB_PRF_CORE2_EX_M	0xC3	/* Intel Core 2 Extreme mobile */
720 #define	SMB_PRF_CORE2_DUO_M	0xC4	/* Intel Core 2 Duo mobile */
721 #define	SMB_PRF_CORE2_SOLO_M	0xC5	/* Intel Core 2 Solo mobile */
722 #define	SMB_PRF_CORE_I7		0xC6	/* Intel Core i7 */
723 #define	SMB_PRF_CELERON_2C	0xC7	/* Celeron Dual-Core */
724 #define	SMB_PRF_IBM390		0xC8	/* IBM 390 */
725 #define	SMB_PRF_G4		0xC9	/* G4 */
726 #define	SMB_PRF_G5		0xCA	/* G5 */
727 #define	SMB_PRF_ESA390		0xCB	/* ESA390 */
728 #define	SMB_PRF_ZARCH		0xCC	/* z/Architecture */
729 #define	SMB_PRF_CORE_I5		0xCD	/* Intel Core i5 */
730 #define	SMB_PRF_CORE_I3		0xCE	/* Intel Core i3 */
731 #define	SMB_PRF_CORE_I9		0xCF	/* Intel Core i9 */
732 #define	SMB_PRF_C7M		0xD2	/* VIA C7-M */
733 #define	SMB_PRF_C7D		0xD3	/* VIA C7-D */
734 #define	SMB_PRF_C7		0xD4	/* VIA C7 */
735 #define	SMB_PRF_EDEN		0xD5	/* VIA Eden */
736 #define	SMB_PRF_XEON_XC		0xD6	/* Intel Xeon Multi-Core */
737 #define	SMB_PRF_XEON_2C_3XXX	0xD7	/* Intel Xeon Dual-Core 3xxx */
738 #define	SMB_PRF_XEON_4C_3XXX	0xD8	/* Intel Xeon Quad-Core 3xxx */
739 #define	SMB_PRF_VIA_NANO	0xD9	/* VIA Nano */
740 #define	SMB_PRF_XEON_2C_5XXX	0xDA	/* Intel Xeon Dual-Core 5xxx */
741 #define	SMB_PRF_XEON_4C_5XXX	0xDB	/* Intel Xeon Quad-Core 5xxx */
742 #define	SMB_PRF_XEON_2C_7XXX	0xDD	/* Intel Xeon Dual-Core 7xxx */
743 #define	SMB_PRF_XEON_4C_7XXX	0xDE	/* Intel Xeon Quad-Core 7xxx */
744 #define	SMB_PRF_XEON_XC_7XXX	0xDF	/* Intel Xeon Multi-Core 7xxx */
745 #define	SMB_PRF_XEON_XC_3400	0xE0	/* Intel Xeon Multi-Core 3400 */
746 #define	SMB_PRF_OPTERON_3000	0xE4	/* AMD Opteron 3000 */
747 #define	SMB_PRF_SEMPRON_II	0xE5	/* AMD Sempron II */
748 #define	SMB_PRF_OPTERON_4C_EM	0xE6	/* AMD Opteron Quad-Core embedded */
749 #define	SMB_PRF_PHENOM_3C	0xE7	/* AMD Phenom Triple-Core */
750 #define	SMB_PRF_TURIONU_2C_M	0xE8	/* AMD Turion Ultra Dual-Core mobile */
751 #define	SMB_PRF_TURION_2C_M	0xE9	/* AMD Turion Dual-Core mobile */
752 #define	SMB_PRF_ATHLON_2C	0xEA	/* AMD Athlon Dual-Core */
753 #define	SMB_PRF_SEMPRON_SI	0xEB	/* AMD Sempron SI */
754 #define	SMB_PRF_PHENOM_II	0xEC	/* AMD Phenom II */
755 #define	SMB_PRF_ATHLON_II	0xED	/* AMD Athlon II */
756 #define	SMB_PRF_OPTERON_6C	0xEE	/* AMD Opteron Six-Core */
757 #define	SMB_PRF_SEMPRON_M	0xEF	/* AMD Sempron M */
758 #define	SMB_PRF_I860		0xFA	/* i860 */
759 #define	SMB_PRF_I960		0xFB	/* i960 */
760 #define	SMB_PRF_ARMv7		0x100	/* ARMv7 */
761 #define	SMB_PRF_ARMv8		0x101	/* ARMv8 */
762 #define	SMB_PRF_SH3		0x104	/* SH-3 */
763 #define	SMB_PRF_SH4		0x105	/* SH-4 */
764 #define	SMB_PRF_ARM		0x118	/* ARM */
765 #define	SMB_PRF_SARM		0x119	/* StrongARM */
766 #define	SMB_PRF_6X86		0x12C	/* 6x86 */
767 #define	SMB_PRF_MEDIAGX		0x12D	/* MediaGX */
768 #define	SMB_PRF_MII		0x12E	/* MII */
769 #define	SMB_PRF_WINCHIP		0x140	/* WinChip */
770 #define	SMB_PRF_DSP		0x15E	/* DSP */
771 #define	SMB_PRF_VIDEO		0x1F4	/* Video Processor */
772 #define	SMB_PRF_RV32		0x200	/* RISC-V RV32 */
773 #define	SMB_PRF_RV64		0x201	/* RISC-V RV64 */
774 #define	SMB_PRF_RV128		0x202	/* RISC-V RV128 */
775 
776 /*
777  * SMBIOS Cache Information.  See DSP0134 Section 7.8 for more information.
778  * If smba_size is zero, this indicates the specified cache is not present.
779  *
780  * SMBIOS 3.1 added extended cache sizes. Unfortunately, we had already baked in
781  * the uint32_t sizes, so we added extended uint64_t's that correspond to the
782  * new fields. To make life easier for consumers, we always make sure that the
783  * _maxsize2 and _size2 members are filled in with the old value if no other
784  * value is present.
785  */
786 typedef struct smbios_cache {
787 	uint32_t smba_maxsize;		/* maximum installed size in bytes */
788 	uint32_t smba_size;		/* installed size in bytes */
789 	uint16_t smba_stype;		/* supported SRAM types (SMB_CAT_*) */
790 	uint16_t smba_ctype;		/* current SRAM type (SMB_CAT_*) */
791 	uint8_t smba_speed;		/* speed in nanoseconds */
792 	uint8_t smba_etype;		/* error correction type (SMB_CAE_*) */
793 	uint8_t smba_ltype;		/* logical cache type (SMB_CAG_*) */
794 	uint8_t smba_assoc;		/* associativity (SMB_CAA_*) */
795 	uint8_t smba_level;		/* cache level */
796 	uint8_t smba_mode;		/* cache mode (SMB_CAM_*) */
797 	uint8_t smba_location;		/* cache location (SMB_CAL_*) */
798 	uint8_t smba_flags;		/* cache flags (SMB_CAF_*) */
799 	uint64_t smba_maxsize2;		/* maximum installed size in bytes */
800 	uint64_t smba_size2;		/* installed size in bytes */
801 } smbios_cache_t;
802 
803 #define	SMB_CAT_OTHER		0x0001		/* other */
804 #define	SMB_CAT_UNKNOWN		0x0002		/* unknown */
805 #define	SMB_CAT_NONBURST	0x0004		/* non-burst */
806 #define	SMB_CAT_BURST		0x0008		/* burst */
807 #define	SMB_CAT_PBURST		0x0010		/* pipeline burst */
808 #define	SMB_CAT_SYNC		0x0020		/* synchronous */
809 #define	SMB_CAT_ASYNC		0x0040		/* asynchronous */
810 
811 #define	SMB_CAE_OTHER		0x01		/* other */
812 #define	SMB_CAE_UNKNOWN		0x02		/* unknown */
813 #define	SMB_CAE_NONE		0x03		/* none */
814 #define	SMB_CAE_PARITY		0x04		/* parity */
815 #define	SMB_CAE_SBECC		0x05		/* single-bit ECC */
816 #define	SMB_CAE_MBECC		0x06		/* multi-bit ECC */
817 
818 #define	SMB_CAG_OTHER		0x01		/* other */
819 #define	SMB_CAG_UNKNOWN		0x02		/* unknown */
820 #define	SMB_CAG_INSTR		0x03		/* instruction */
821 #define	SMB_CAG_DATA		0x04		/* data */
822 #define	SMB_CAG_UNIFIED		0x05		/* unified */
823 
824 #define	SMB_CAA_OTHER		0x01		/* other */
825 #define	SMB_CAA_UNKNOWN		0x02		/* unknown */
826 #define	SMB_CAA_DIRECT		0x03		/* direct mapped */
827 #define	SMB_CAA_2WAY		0x04		/* 2-way set associative */
828 #define	SMB_CAA_4WAY		0x05		/* 4-way set associative */
829 #define	SMB_CAA_FULL		0x06		/* fully associative */
830 #define	SMB_CAA_8WAY		0x07		/* 8-way set associative */
831 #define	SMB_CAA_16WAY		0x08		/* 16-way set associative */
832 #define	SMB_CAA_12WAY		0x09		/* 12-way set associative */
833 #define	SMB_CAA_24WAY		0x0A		/* 24-way set associative */
834 #define	SMB_CAA_32WAY		0x0B		/* 32-way set associative */
835 #define	SMB_CAA_48WAY		0x0C		/* 48-way set associative */
836 #define	SMB_CAA_64WAY		0x0D		/* 64-way set associative */
837 #define	SMB_CAA_20WAY		0x0E		/* 20-way set associative */
838 
839 #define	SMB_CAM_WT		0x00		/* write-through */
840 #define	SMB_CAM_WB		0x01		/* write-back */
841 #define	SMB_CAM_VARY		0x02		/* varies by address */
842 #define	SMB_CAM_UNKNOWN		0x03		/* unknown */
843 
844 #define	SMB_CAL_INTERNAL	0x00		/* internal */
845 #define	SMB_CAL_EXTERNAL	0x01		/* external */
846 #define	SMB_CAL_RESERVED	0x02		/* reserved */
847 #define	SMB_CAL_UNKNOWN		0x03		/* unknown */
848 
849 #define	SMB_CAF_ENABLED		0x01		/* enabled at boot time */
850 #define	SMB_CAF_SOCKETED	0x02		/* cache is socketed */
851 
852 /*
853  * SMBIOS Port Information.  See DSP0134 Section 7.9 for more information.
854  * The internal reference designator string is also mapped to the location.
855  */
856 typedef struct smbios_port {
857 	const char *smbo_iref;	/* internal reference designator */
858 	const char *smbo_eref;	/* external reference designator */
859 	uint8_t smbo_itype;	/* internal connector type (SMB_POC_*) */
860 	uint8_t smbo_etype;	/* external connector type (SMB_POC_*) */
861 	uint8_t smbo_ptype;	/* port type (SMB_POT_*) */
862 	uint8_t smbo_pad;	/* padding */
863 } smbios_port_t;
864 
865 #define	SMB_POC_NONE		0x00		/* none */
866 #define	SMB_POC_CENT		0x01		/* Centronics */
867 #define	SMB_POC_MINICENT	0x02		/* Mini-Centronics */
868 #define	SMB_POC_PROPRIETARY	0x03		/* proprietary */
869 #define	SMB_POC_DB25M		0x04		/* DB-25 pin male */
870 #define	SMB_POC_DB25F		0x05		/* DB-25 pin female */
871 #define	SMB_POC_DB15M		0x06		/* DB-15 pin male */
872 #define	SMB_POC_DB15F		0x07		/* DB-15 pin female */
873 #define	SMB_POC_DB9M		0x08		/* DB-9 pin male */
874 #define	SMB_POC_DB9F		0x09		/* DB-9 pin female */
875 #define	SMB_POC_RJ11		0x0A		/* RJ-11 */
876 #define	SMB_POC_RJ45		0x0B		/* RJ-45 */
877 #define	SMB_POC_MINISCSI	0x0C		/* 50-pin MiniSCSI */
878 #define	SMB_POC_MINIDIN		0x0D		/* Mini-DIN */
879 #define	SMB_POC_MICRODIN	0x0E		/* Micro-DIN */
880 #define	SMB_POC_PS2		0x0F		/* PS/2 */
881 #define	SMB_POC_IR		0x10		/* Infrared */
882 #define	SMB_POC_HPHIL		0x11		/* HP-HIL */
883 #define	SMB_POC_USB		0x12		/* USB */
884 #define	SMB_POC_SSA		0x13		/* SSA SCSI */
885 #define	SMB_POC_DIN8M		0x14		/* Circular DIN-8 male */
886 #define	SMB_POC_DIN8F		0x15		/* Circular DIN-8 female */
887 #define	SMB_POC_OBIDE		0x16		/* on-board IDE */
888 #define	SMB_POC_OBFLOPPY	0x17		/* on-board floppy */
889 #define	SMB_POC_DI9		0x18		/* 9p dual inline (p10 cut) */
890 #define	SMB_POC_DI25		0x19		/* 25p dual inline (p26 cut) */
891 #define	SMB_POC_DI50		0x1A		/* 50p dual inline */
892 #define	SMB_POC_DI68		0x1B		/* 68p dual inline */
893 #define	SMB_POC_CDROM		0x1C		/* on-board sound from CDROM */
894 #define	SMB_POC_MINI14		0x1D		/* Mini-Centronics Type 14 */
895 #define	SMB_POC_MINI26		0x1E		/* Mini-Centronics Type 26 */
896 #define	SMB_POC_MINIJACK	0x1F		/* Mini-jack (headphones) */
897 #define	SMB_POC_BNC		0x20		/* BNC */
898 #define	SMB_POC_1394		0x21		/* 1394 */
899 #define	SMB_POC_SATA		0x22		/* SAS/SATA plug receptacle */
900 #define	SMB_POC_USB_C		0x23		/* USB Type-C receptacle */
901 #define	SMB_POC_PC98		0xA0		/* PC-98 */
902 #define	SMB_POC_PC98HR		0xA1		/* PC-98Hireso */
903 #define	SMB_POC_PCH98		0xA2		/* PC-H98 */
904 #define	SMB_POC_PC98NOTE	0xA3		/* PC-98Note */
905 #define	SMB_POC_PC98FULL	0xA4		/* PC-98Full */
906 #define	SMB_POC_OTHER		0xFF		/* other */
907 
908 #define	SMB_POT_NONE		0x00		/* none */
909 #define	SMB_POT_PP_XTAT		0x01		/* Parallel Port XT/AT compat */
910 #define	SMB_POT_PP_PS2		0x02		/* Parallel Port PS/2 */
911 #define	SMB_POT_PP_ECP		0x03		/* Parallel Port ECP */
912 #define	SMB_POT_PP_EPP		0x04		/* Parallel Port EPP */
913 #define	SMB_POT_PP_ECPEPP	0x05		/* Parallel Port ECP/EPP */
914 #define	SMB_POT_SP_XTAT		0x06		/* Serial Port XT/AT compat */
915 #define	SMB_POT_SP_16450	0x07		/* Serial Port 16450 compat */
916 #define	SMB_POT_SP_16550	0x08		/* Serial Port 16550 compat */
917 #define	SMB_POT_SP_16550A	0x09		/* Serial Port 16550A compat */
918 #define	SMB_POT_SCSI		0x0A		/* SCSI port */
919 #define	SMB_POT_MIDI		0x0B		/* MIDI port */
920 #define	SMB_POT_JOYSTICK	0x0C		/* Joystick port */
921 #define	SMB_POT_KEYBOARD	0x0D		/* Keyboard port */
922 #define	SMB_POT_MOUSE		0x0E		/* Mouse port */
923 #define	SMB_POT_SSA		0x0F		/* SSA SCSI */
924 #define	SMB_POT_USB		0x10		/* USB */
925 #define	SMB_POT_FIREWIRE	0x11		/* FireWrite (IEEE P1394) */
926 #define	SMB_POT_PCMII		0x12		/* PCMCIA Type II */
927 #define	SMB_POT_PCMIIa		0x13		/* PCMCIA Type II (alternate) */
928 #define	SMB_POT_PCMIII		0x14		/* PCMCIA Type III */
929 #define	SMB_POT_CARDBUS		0x15		/* Cardbus */
930 #define	SMB_POT_ACCESS		0x16		/* Access Bus Port */
931 #define	SMB_POT_SCSI2		0x17		/* SCSI II */
932 #define	SMB_POT_SCSIW		0x18		/* SCSI Wide */
933 #define	SMB_POT_PC98		0x19		/* PC-98 */
934 #define	SMB_POT_PC98HR		0x1A		/* PC-98Hireso */
935 #define	SMB_POT_PCH98		0x1B		/* PC-H98 */
936 #define	SMB_POT_VIDEO		0x1C		/* Video port */
937 #define	SMB_POT_AUDIO		0x1D		/* Audio port */
938 #define	SMB_POT_MODEM		0x1E		/* Modem port */
939 #define	SMB_POT_NETWORK		0x1F		/* Network port */
940 #define	SMB_POT_SATA		0x20		/* SATA */
941 #define	SMB_POT_SAS		0x21		/* SAS */
942 #define	SMB_POT_MFDP		0x22	/* MFDP (Multi-Function Display Port) */
943 #define	SMB_POT_THUNDERBOLT	0x23		/* Thunderbolt */
944 #define	SMB_POT_8251		0xA0		/* 8251 compatible */
945 #define	SMB_POT_8251F		0xA1		/* 8251 FIFO compatible */
946 #define	SMB_POT_OTHER		0xFF		/* other */
947 
948 /*
949  * SMBIOS Slot Information.  See DSP0134 Section 7.10 for more information.
950  * See DSP0134 7.10.5 for how to interpret the value of smbl_id.
951  */
952 typedef struct smbios_slot {
953 	const char *smbl_name;		/* reference designation */
954 	uint8_t smbl_type;		/* slot type */
955 	uint8_t smbl_width;		/* slot data bus width */
956 	uint8_t smbl_usage;		/* current usage */
957 	uint8_t smbl_length;		/* slot length */
958 	uint16_t smbl_id;		/* slot ID */
959 	uint8_t smbl_ch1;		/* slot characteristics 1 */
960 	uint8_t smbl_ch2;		/* slot characteristics 2 */
961 	uint16_t smbl_sg;		/* segment group number */
962 	uint8_t smbl_bus;		/* bus number */
963 	uint8_t smbl_df;		/* device/function number */
964 	uint8_t smbl_dbw;		/* data bus width */
965 	uint8_t smbl_npeers;		/* PCIe bifurcation peers */
966 	uint8_t smbl_info;		/* slot info */
967 	uint8_t smbl_pwidth;		/* slot physical width */
968 	uint32_t smbl_pitch;		/* slot pitch in 10um */
969 	uint8_t smbl_height;		/* slot height */
970 } smbios_slot_t;
971 
972 #define	SMB_SLT_OTHER		0x01	/* other */
973 #define	SMB_SLT_UNKNOWN		0x02	/* unknown */
974 #define	SMB_SLT_ISA		0x03	/* ISA */
975 #define	SMB_SLT_MCA		0x04	/* MCA */
976 #define	SMB_SLT_EISA		0x05	/* EISA */
977 #define	SMB_SLT_PCI		0x06	/* PCI */
978 #define	SMB_SLT_PCMCIA		0x07	/* PCMCIA */
979 #define	SMB_SLT_VLVESA		0x08	/* VL-VESA */
980 #define	SMB_SLT_PROPRIETARY	0x09	/* proprietary */
981 #define	SMB_SLT_PROC		0x0A	/* processor card slot */
982 #define	SMB_SLT_MEM		0x0B	/* proprietary memory card slot */
983 #define	SMB_SLT_IOR		0x0C	/* I/O riser card slot */
984 #define	SMB_SLT_NUBUS		0x0D	/* NuBus */
985 #define	SMB_SLT_PCI66		0x0E	/* PCI (66MHz capable) */
986 #define	SMB_SLT_AGP		0x0F	/* AGP */
987 #define	SMB_SLT_AGP2X		0x10	/* AGP 2X */
988 #define	SMB_SLT_AGP4X		0x11	/* AGP 4X */
989 #define	SMB_SLT_PCIX		0x12	/* PCI-X */
990 #define	SMB_SLT_AGP8X		0x13	/* AGP 8X */
991 #define	SMB_SLT_M2_1DP		0x14	/* M.2 Socket 1-DP (Mechanical Key A) */
992 #define	SMB_SLT_M2_1SD		0x15	/* M.2 Socket 1-SD (Mechanical Key E) */
993 #define	SMB_SLT_M2_2		0x16	/* M.2 Socket 2 (Mechanical Key B) */
994 #define	SMB_SLT_M2_3		0x17	/* M.2 Socket 3 (Mechanical Key M) */
995 #define	SMB_SLT_MXM_I		0x18	/* MXM Type I */
996 #define	SMB_SLT_MXM_II		0x19	/* MXM Type II */
997 #define	SMB_SLT_MXM_III		0x1A	/* MXM Type III (standard connector) */
998 #define	SMB_SLT_MXM_III_HE	0x1B	/* MXM Type III (HE connector) */
999 #define	SMB_SLT_MXM_V		0x1C	/* MXM Type IV */
1000 #define	SMB_SLT_MXM3_A		0x1D	/* MXM 3.0 Type A */
1001 #define	SMB_SLT_MXM3_B		0x1E	/* MXM 3.0 Type B */
1002 #define	SMB_SLT_PCIEG2_SFF	0x1F	/* PCI Express Gen 2 SFF-8639 (U.2) */
1003 #define	SMB_SLT_PCIEG3_SFF	0x20	/* PCI Express Gen 3 SFF-8639 (U.2) */
1004 /*
1005  * These lines must be on one line for the string generating code.
1006  */
1007 /* BEGIN CSTYLED */
1008 #define	SMB_SLT_PCIE_M52_WBSKO	0x21	/* PCI Express Mini 52-pin with bottom-side keep-outs */
1009 #define	SMB_SLT_PCIE_M52_WOBSKO	0x22	/* PCI Express Mini 52-pin without bottom-side keep-outs */
1010 /* END CSTYLED */
1011 #define	SMB_SLT_PCIE_M76	0x23	/* PCI Express Mini 72-pin */
1012 #define	SMB_SLT_PCIEG4_SFF	0x24	/* PCI Express Gen 4 SFF-8639 (U.2) */
1013 #define	SMB_SLT_PCIEG5_SFF	0x25	/* PCI Express Gen 5 SFF-8639 (U.2) */
1014 #define	SMB_SLT_OCP3_SFF	0x26	/* OCP NIC 3.0 Small Form Factor */
1015 #define	SMB_SLT_OCP3_LFF	0x27	/* OCP NIC 3.0 Large Form Factor */
1016 #define	SMB_SLT_OCP_PRE		0x28	/* OCP NIC prior to 3.0 */
1017 #define	SMB_SLT_CXL1		0x30	/* CXL Flexbus 1.0 */
1018 #define	SMB_SLT_PC98_C20	0xA0	/* PC-98/C20 */
1019 #define	SMB_SLT_PC98_C24	0xA1	/* PC-98/C24 */
1020 #define	SMB_SLT_PC98_E		0xA2	/* PC-98/E */
1021 #define	SMB_SLT_PC98_LB		0xA3	/* PC-98/Local Bus */
1022 #define	SMB_SLT_PC98_C		0xA4	/* PC-98/Card */
1023 #define	SMB_SLT_PCIE		0xA5	/* PCI Express */
1024 #define	SMB_SLT_PCIE1		0xA6	/* PCI Express x1 */
1025 #define	SMB_SLT_PCIE2		0xA7	/* PCI Express x2 */
1026 #define	SMB_SLT_PCIE4		0xA8	/* PCI Express x4 */
1027 #define	SMB_SLT_PCIE8		0xA9	/* PCI Express x8 */
1028 #define	SMB_SLT_PCIE16		0xAA	/* PCI Express x16 */
1029 #define	SMB_SLT_PCIE2G		0xAB	/* PCI Exp. Gen 2 */
1030 #define	SMB_SLT_PCIE2G1		0xAC	/* PCI Exp. Gen 2 x1 */
1031 #define	SMB_SLT_PCIE2G2		0xAD	/* PCI Exp. Gen 2 x2 */
1032 #define	SMB_SLT_PCIE2G4		0xAE	/* PCI Exp. Gen 2 x4 */
1033 #define	SMB_SLT_PCIE2G8		0xAF	/* PCI Exp. Gen 2 x8 */
1034 #define	SMB_SLT_PCIE2G16	0xB0	/* PCI Exp. Gen 2 x16 */
1035 #define	SMB_SLT_PCIE3G		0xB1	/* PCI Exp. Gen 3 */
1036 #define	SMB_SLT_PCIE3G1		0xB2	/* PCI Exp. Gen 3 x1 */
1037 #define	SMB_SLT_PCIE3G2		0xB3	/* PCI Exp. Gen 3 x2 */
1038 #define	SMB_SLT_PCIE3G4		0xB4	/* PCI Exp. Gen 3 x4 */
1039 #define	SMB_SLT_PCIE3G8		0xB5	/* PCI Exp. Gen 3 x8 */
1040 #define	SMB_SLT_PCIE3G16	0xB6	/* PCI Exp. Gen 3 x16 */
1041 #define	SMB_SLT_PCIE4G		0xB8	/* PCI Exp. Gen 4 */
1042 #define	SMB_SLT_PCIE4G1		0xB9	/* PCI Exp. Gen 4 x1 */
1043 #define	SMB_SLT_PCIE4G2		0xBA	/* PCI Exp. Gen 4 x2 */
1044 #define	SMB_SLT_PCIE4G4		0xBB	/* PCI Exp. Gen 4 x4 */
1045 #define	SMB_SLT_PCIE4G8		0xBC	/* PCI Exp. Gen 4 x8 */
1046 #define	SMB_SLT_PCIE4G16	0xBD	/* PCI Exp. Gen 4 x16 */
1047 #define	SMB_SLT_PCIE5G		0xBE	/* PCI Exp. Gen 5 */
1048 #define	SMB_SLT_PCIE5G1		0xBF	/* PCI Exp. Gen 5 x1 */
1049 #define	SMB_SLT_PCIE5G2		0xC0	/* PCI Exp. Gen 5 x2 */
1050 #define	SMB_SLT_PCIE5G4		0xC1	/* PCI Exp. Gen 5 x4 */
1051 #define	SMB_SLT_PCIE5G8		0xC2	/* PCI Exp. Gen 5 x8 */
1052 #define	SMB_SLT_PCIE5G16	0xC3	/* PCI Exp. Gen 5 x16 */
1053 #define	SMB_SLT_PCIEG6P		0xC4	/* PCI Exp. Gen 6+ */
1054 #define	SMB_SLT_EDSFF_E1	0xC5	/* Ent. and DC 1U E1 Form Factor */
1055 #define	SMB_SLT_EDSFF_E3	0xC6	/* Ent. and DC 3" E3 Form Factor */
1056 
1057 #define	SMB_SLW_OTHER		0x01	/* other */
1058 #define	SMB_SLW_UNKNOWN		0x02	/* unknown */
1059 #define	SMB_SLW_8		0x03	/* 8 bit */
1060 #define	SMB_SLW_16		0x04	/* 16 bit */
1061 #define	SMB_SLW_32		0x05	/* 32 bit */
1062 #define	SMB_SLW_64		0x06	/* 64 bit */
1063 #define	SMB_SLW_128		0x07	/* 128 bit */
1064 #define	SMB_SLW_1X		0x08	/* 1x or x1 */
1065 #define	SMB_SLW_2X		0x09	/* 2x or x2 */
1066 #define	SMB_SLW_4X		0x0A	/* 4x or x4 */
1067 #define	SMB_SLW_8X		0x0B	/* 8x or x8 */
1068 #define	SMB_SLW_12X		0x0C	/* 12x or x12 */
1069 #define	SMB_SLW_16X		0x0D	/* 16x or x16 */
1070 #define	SMB_SLW_32X		0x0E	/* 32x or x32 */
1071 
1072 #define	SMB_SLU_OTHER		0x01	/* other */
1073 #define	SMB_SLU_UNKNOWN		0x02	/* unknown */
1074 #define	SMB_SLU_AVAIL		0x03	/* available */
1075 #define	SMB_SLU_INUSE		0x04	/* in use */
1076 
1077 #define	SMB_SLL_OTHER		0x01	/* other */
1078 #define	SMB_SLL_UNKNOWN		0x02	/* unknown */
1079 #define	SMB_SLL_SHORT		0x03	/* short length */
1080 #define	SMB_SLL_LONG		0x04	/* long length */
1081 #define	SMB_SLL_2IN5		0x05	/* 2.5" drive form factor */
1082 #define	SMB_SLL_3IN5		0x06	/* 3.5" drive form factor */
1083 
1084 #define	SMB_SLCH1_UNKNOWN	0x01	/* characteristics unknown */
1085 #define	SMB_SLCH1_5V		0x02	/* provides 5.0V */
1086 #define	SMB_SLCH1_33V		0x04	/* provides 3.3V */
1087 #define	SMB_SLCH1_SHARED	0x08	/* opening shared with other slot */
1088 #define	SMB_SLCH1_PC16		0x10	/* slot supports PC Card-16 */
1089 #define	SMB_SLCH1_PCCB		0x20	/* slot supports CardBus */
1090 #define	SMB_SLCH1_PCZV		0x40	/* slot supports Zoom Video */
1091 #define	SMB_SLCH1_PCMRR		0x80	/* slot supports Modem Ring Resume */
1092 
1093 #define	SMB_SLCH2_PME		0x01	/* slot supports PME# signal */
1094 #define	SMB_SLCH2_HOTPLUG	0x02	/* slot supports hot-plug devices */
1095 #define	SMB_SLCH2_SMBUS		0x04	/* slot supports SMBus signal */
1096 #define	SMB_SLCH2_BIFUR		0x08	/* slot supports PCIe bifurcation */
1097 #define	SMB_SLCH2_SURPREM	0x10	/* slot supports surprise removal */
1098 #define	SMB_SLCH2_CXL1		0x20	/* Flexbus slot, CXL 1.0 capable */
1099 #define	SMB_SLCH2_CXL2		0x40	/* Flexbus slot, CXL 2.0 capable */
1100 
1101 #define	SMB_SLHT_NA		0x00	/* not applicable */
1102 #define	SMB_SLHT_OTHER		0x01	/* other */
1103 #define	SMB_SLHT_UNKNOWN	0x02	/* unknown */
1104 #define	SMB_SLHT_FULL		0x03	/* full height */
1105 #define	SMB_SLHT_LP		0x04	/* low profile */
1106 
1107 /*
1108  * SMBIOS 7.10.9 Slot Peer Devices
1109  *
1110  * This structure represents an optional peer device that may be part of an
1111  * SMBIOS 3.2 slot.
1112  */
1113 typedef struct smbios_slot_peer {
1114 	uint16_t smblp_group;		/* peer segment group number */
1115 	uint8_t smblp_bus;		/* peer bus number */
1116 	uint8_t smblp_device;		/* peer device number */
1117 	uint8_t smblp_function;		/* peer function number */
1118 	uint8_t	smblp_data_width;	/* peer data bus width */
1119 } smbios_slot_peer_t;
1120 
1121 /*
1122  * SMBIOS On-Board Device Information.  See DSP0134 Section 7.11 for more
1123  * information.  Any number of on-board device sections may be present, each
1124  * containing one or more records.  The smbios_info_obdevs() function permits
1125  * the caller to retrieve one or more of the records from a given section.
1126  */
1127 typedef struct smbios_obdev {
1128 	const char *smbd_name;		/* description string for this device */
1129 	uint8_t smbd_type;		/* type code (SMB_OBT_*) */
1130 	uint8_t smbd_enabled;		/* boolean (device is enabled) */
1131 } smbios_obdev_t;
1132 
1133 #define	SMB_OBT_OTHER		0x01	/* other */
1134 #define	SMB_OBT_UNKNOWN		0x02	/* unknown */
1135 #define	SMB_OBT_VIDEO		0x03	/* video */
1136 #define	SMB_OBT_SCSI		0x04	/* scsi */
1137 #define	SMB_OBT_ETHERNET	0x05	/* ethernet */
1138 #define	SMB_OBT_TOKEN		0x06	/* token ring */
1139 #define	SMB_OBT_SOUND		0x07	/* sound */
1140 #define	SMB_OBT_PATA		0x08	/* pata */
1141 #define	SMB_OBT_SATA		0x09	/* sata */
1142 #define	SMB_OBT_SAS		0x0A	/* sas */
1143 
1144 /*
1145  * SMBIOS BIOS Language Information.  See DSP0134 Section 7.14 for more
1146  * information.  The smbios_info_strtab() function can be applied using a
1147  * count of smbla_num to retrieve the other possible language settings.
1148  */
1149 typedef struct smbios_lang {
1150 	const char *smbla_cur;		/* current language setting */
1151 	uint_t smbla_fmt;		/* language name format (see below) */
1152 	uint_t smbla_num;		/* number of installed languages */
1153 } smbios_lang_t;
1154 
1155 #define	SMB_LFMT_LONG	0		/* <ISO639>|<ISO3166>|Encoding Method */
1156 #define	SMB_LFMT_SHORT	1		/* <ISO930><ISO3166> */
1157 
1158 /*
1159  * SMBIOS System Event Log Information.  See DSP0134 Section 7.16 for more
1160  * information.  Accessing the event log itself requires additional interfaces.
1161  */
1162 typedef struct smbios_evtype {
1163 	uint8_t smbevt_ltype;		/* log type */
1164 	uint8_t smbevt_dtype;		/* variable data format type */
1165 } smbios_evtype_t;
1166 
1167 typedef struct smbios_evlog {
1168 	size_t smbev_size;		/* size in bytes of log area */
1169 	size_t smbev_hdr;		/* offset or index of header */
1170 	size_t smbev_data;		/* offset or index of data */
1171 	uint8_t smbev_method;		/* data access method (see below) */
1172 	uint8_t smbev_flags;		/* flags (see below) */
1173 	uint8_t smbev_format;		/* log header format (see below) */
1174 	uint8_t smbev_pad;		/* padding */
1175 	uint32_t smbev_token;		/* data update change token */
1176 	union {
1177 		struct {
1178 			uint16_t evi_iaddr; /* index address */
1179 			uint16_t evi_daddr; /* data address */
1180 		} eva_io;		/* i/o address for SMB_EVM_XxY */
1181 		uint32_t eva_addr;	/* address for SMB_EVM_MEM32 */
1182 		uint16_t eva_gpnv;	/* handle for SMB_EVM_GPNV */
1183 	} smbev_addr;
1184 	uint32_t smbev_typec;		/* number of type descriptors */
1185 	const smbios_evtype_t *smbev_typev; /* type descriptor array */
1186 } smbios_evlog_t;
1187 
1188 #define	SMB_EVM_1x1i_1x1d	0	/* I/O: 1 1b idx port, 1 1b data port */
1189 #define	SMB_EVM_2x1i_1x1d	1	/* I/O: 2 1b idx port, 1 1b data port */
1190 #define	SMB_EVM_1x2i_1x1d	2	/* I/O: 1 2b idx port, 1 1b data port */
1191 #define	SMB_EVM_MEM32		3	/* Memory-Mapped 32-bit Physical Addr */
1192 #define	SMB_EVM_GPNV		4	/* GP Non-Volatile API Access */
1193 
1194 #define	SMB_EVFL_VALID		0x1	/* log area valid */
1195 #define	SMB_EVFL_FULL		0x2	/* log area full */
1196 
1197 #define	SMB_EVHF_NONE		0	/* no log headers used */
1198 #define	SMB_EVHF_F1		1	/* DMTF log header type 1 */
1199 
1200 /*
1201  * SMBIOS Physical Memory Array Information.  See DSP0134 Section 7.17 for
1202  * more information.  This describes a collection of physical memory devices.
1203  */
1204 typedef struct smbios_memarray {
1205 	uint8_t smbma_location;		/* physical device location */
1206 	uint8_t smbma_use;		/* physical device functional purpose */
1207 	uint8_t smbma_ecc;		/* error detect/correct mechanism */
1208 	uint8_t smbma_pad0;		/* padding */
1209 	uint32_t smbma_pad1;		/* padding */
1210 	uint32_t smbma_ndevs;		/* number of slots or sockets */
1211 	id_t smbma_err;			/* handle of error (if any) */
1212 	uint64_t smbma_size;		/* maximum capacity in bytes */
1213 } smbios_memarray_t;
1214 
1215 #define	SMB_MAL_OTHER		0x01	/* other */
1216 #define	SMB_MAL_UNKNOWN		0x02	/* unknown */
1217 #define	SMB_MAL_SYSMB		0x03	/* system board or motherboard */
1218 #define	SMB_MAL_ISA		0x04	/* ISA add-on card */
1219 #define	SMB_MAL_EISA		0x05	/* EISA add-on card */
1220 #define	SMB_MAL_PCI		0x06	/* PCI add-on card */
1221 #define	SMB_MAL_MCA		0x07	/* MCA add-on card */
1222 #define	SMB_MAL_PCMCIA		0x08	/* PCMCIA add-on card */
1223 #define	SMB_MAL_PROP		0x09	/* proprietary add-on card */
1224 #define	SMB_MAL_NUBUS		0x0A	/* NuBus */
1225 #define	SMB_MAL_PC98C20		0xA0	/* PC-98/C20 add-on card */
1226 #define	SMB_MAL_PC98C24		0xA1	/* PC-98/C24 add-on card */
1227 #define	SMB_MAL_PC98E		0xA2	/* PC-98/E add-on card */
1228 #define	SMB_MAL_PC98LB		0xA3	/* PC-98/Local bus add-on card */
1229 #define	SMB_MAL_CXL1		0xA4	/* CXL add-on card */
1230 
1231 #define	SMB_MAU_OTHER		0x01	/* other */
1232 #define	SMB_MAU_UNKNOWN		0x02	/* unknown */
1233 #define	SMB_MAU_SYSTEM		0x03	/* system memory */
1234 #define	SMB_MAU_VIDEO		0x04	/* video memory */
1235 #define	SMB_MAU_FLASH		0x05	/* flash memory */
1236 #define	SMB_MAU_NVRAM		0x06	/* non-volatile RAM */
1237 #define	SMB_MAU_CACHE		0x07	/* cache memory */
1238 
1239 #define	SMB_MAE_OTHER		0x01	/* other */
1240 #define	SMB_MAE_UNKNOWN		0x02	/* unknown */
1241 #define	SMB_MAE_NONE		0x03	/* none */
1242 #define	SMB_MAE_PARITY		0x04	/* parity */
1243 #define	SMB_MAE_SECC		0x05	/* single-bit ECC */
1244 #define	SMB_MAE_MECC		0x06	/* multi-bit ECC */
1245 #define	SMB_MAE_CRC		0x07	/* CRC */
1246 
1247 /*
1248  * SMBIOS Memory Device Information.  See DSP0134 Section 7.18 for more
1249  * information.  One or more of these structures are associated with each
1250  * smbios_memarray_t.  A structure is present even for unpopulated sockets.
1251  * Unknown values are set to -1.  A smbmd_size of 0 indicates unpopulated.
1252  * WARNING: Some BIOSes appear to export the *maximum* size of the device
1253  * that can appear in the corresponding socket as opposed to the current one.
1254  */
1255 typedef struct smbios_memdevice {
1256 	id_t smbmd_array;		/* handle of physical memory array */
1257 	id_t smbmd_error;		/* handle of memory error data */
1258 	uint32_t smbmd_twidth;		/* total width in bits including ecc */
1259 	uint32_t smbmd_dwidth;		/* data width in bits */
1260 	uint64_t smbmd_size;		/* size in bytes (see note above) */
1261 	uint8_t smbmd_form;		/* form factor */
1262 	uint8_t smbmd_set;		/* set (0x00=none, 0xFF=unknown) */
1263 	uint8_t smbmd_type;		/* memory type */
1264 	uint8_t smbmd_pad;		/* padding */
1265 	uint32_t smbmd_flags;		/* flags (see below) */
1266 	uint32_t smbmd_speed;		/* speed in MT/s */
1267 	const char *smbmd_dloc;		/* physical device locator string */
1268 	const char *smbmd_bloc;		/* physical bank locator string */
1269 	uint8_t smbmd_rank;		/* rank */
1270 	uint16_t smbmd_clkspeed;	/* configured clock speed */
1271 	uint16_t smbmd_minvolt;		/* minimum voltage */
1272 	uint16_t smbmd_maxvolt;		/* maximum voltage */
1273 	uint16_t smbmd_confvolt;	/* configured voltage */
1274 	uint8_t smbmd_memtech;		/* memory technology */
1275 	uint32_t smbmd_opcap_flags;	/* operating mode capability */
1276 	const char *smbmd_firmware_rev;	/* firmware rev */
1277 	uint16_t smbmd_modmfg_id;	/* JEDEC module mfg id */
1278 	uint16_t smbmd_modprod_id;	/* JEDEC module product id */
1279 	uint16_t smbmd_cntrlmfg_id;	/* JEDEC controller mfg id */
1280 	uint16_t smbmd_cntrlprod_id;	/* JEDEC controller prod id */
1281 	uint64_t smbmd_nvsize;		/* non-volatile size in bytes */
1282 	uint64_t smbmd_volatile_size;	/* volatile size in bytes */
1283 	uint64_t smbmd_cache_size;	/* cache size in bytes */
1284 	uint64_t smbmd_logical_size;	/* logical size in bytes */
1285 	uint64_t smbmd_extspeed;	/* extended device speed */
1286 	uint64_t smbmd_extclkspeed;	/* extended configured speed */
1287 } smbios_memdevice_t;
1288 
1289 #define	SMB_MDFF_OTHER		0x01	/* other */
1290 #define	SMB_MDFF_UNKNOWN	0x02	/* unknown */
1291 #define	SMB_MDFF_SIMM		0x03	/* SIMM */
1292 #define	SMB_MDFF_SIP		0x04	/* SIP */
1293 #define	SMB_MDFF_CHIP		0x05	/* chip */
1294 #define	SMB_MDFF_DIP		0x06	/* DIP */
1295 #define	SMB_MDFF_ZIP		0x07	/* ZIP */
1296 #define	SMB_MDFF_PROP		0x08	/* proprietary card */
1297 #define	SMB_MDFF_DIMM		0x09	/* DIMM */
1298 #define	SMB_MDFF_TSOP		0x0A	/* TSOP */
1299 #define	SMB_MDFF_CHIPROW	0x0B	/* row of chips */
1300 #define	SMB_MDFF_RIMM		0x0C	/* RIMM */
1301 #define	SMB_MDFF_SODIMM		0x0D	/* SODIMM */
1302 #define	SMB_MDFF_SRIMM		0x0E	/* SRIMM */
1303 #define	SMB_MDFF_FBDIMM		0x0F	/* FBDIMM */
1304 #define	SMB_MDFF_DIE		0x10	/* die */
1305 
1306 #define	SMB_MDT_OTHER		0x01	/* other */
1307 #define	SMB_MDT_UNKNOWN		0x02	/* unknown */
1308 #define	SMB_MDT_DRAM		0x03	/* DRAM */
1309 #define	SMB_MDT_EDRAM		0x04	/* EDRAM */
1310 #define	SMB_MDT_VRAM		0x05	/* VRAM */
1311 #define	SMB_MDT_SRAM		0x06	/* SRAM */
1312 #define	SMB_MDT_RAM		0x07	/* RAM */
1313 #define	SMB_MDT_ROM		0x08	/* ROM */
1314 #define	SMB_MDT_FLASH		0x09	/* FLASH */
1315 #define	SMB_MDT_EEPROM		0x0A	/* EEPROM */
1316 #define	SMB_MDT_FEPROM		0x0B	/* FEPROM */
1317 #define	SMB_MDT_EPROM		0x0C	/* EPROM */
1318 #define	SMB_MDT_CDRAM		0x0D	/* CDRAM */
1319 #define	SMB_MDT_3DRAM		0x0E	/* 3DRAM */
1320 #define	SMB_MDT_SDRAM		0x0F	/* SDRAM */
1321 #define	SMB_MDT_SGRAM		0x10	/* SGRAM */
1322 #define	SMB_MDT_RDRAM		0x11	/* RDRAM */
1323 #define	SMB_MDT_DDR		0x12	/* DDR */
1324 #define	SMB_MDT_DDR2		0x13	/* DDR2 */
1325 #define	SMB_MDT_DDR2FBDIMM	0x14	/* DDR2 FBDIMM */
1326 #define	SMB_MDT_DDR3		0x18	/* DDR3 */
1327 #define	SMB_MDT_FBD2		0x19	/* FBD2 */
1328 #define	SMB_MDT_DDR4		0x1A	/* DDR4 */
1329 #define	SMB_MDT_LPDDR		0x1B	/* LPDDR */
1330 #define	SMB_MDT_LPDDR2		0x1C	/* LPDDR2 */
1331 #define	SMB_MDT_LPDDR3		0x1D	/* LPDDR3 */
1332 #define	SMB_MDT_LPDDR4		0x1E	/* LPDDR4 */
1333 #define	SMB_MDT_LOGNV		0x1F	/* Logical non-volatile device */
1334 #define	SMB_MDT_HBM		0x20	/* High Bandwidth Memory */
1335 #define	SMB_MDT_HBM2		0x21	/* High Bandwidth Memory 2 */
1336 #define	SMB_MDT_DDR5		0x22	/* DDR5 */
1337 #define	SMB_MDT_LPDDR5		0x23	/* LPDDR5 */
1338 
1339 #define	SMB_MDF_OTHER		0x0002	/* other */
1340 #define	SMB_MDF_UNKNOWN		0x0004	/* unknown */
1341 #define	SMB_MDF_FASTPG		0x0008	/* fast-paged */
1342 #define	SMB_MDF_STATIC		0x0010	/* static column */
1343 #define	SMB_MDF_PSTATIC		0x0020	/* pseudo-static */
1344 #define	SMB_MDF_RAMBUS		0x0040	/* RAMBUS */
1345 #define	SMB_MDF_SYNC		0x0080	/* synchronous */
1346 #define	SMB_MDF_CMOS		0x0100	/* CMOS */
1347 #define	SMB_MDF_EDO		0x0200	/* EDO */
1348 #define	SMB_MDF_WDRAM		0x0400	/* Window DRAM */
1349 #define	SMB_MDF_CDRAM		0x0800	/* Cache DRAM */
1350 #define	SMB_MDF_NV		0x1000	/* non-volatile */
1351 #define	SMB_MDF_REG		0x2000	/* Registered (Buffered) */
1352 #define	SMB_MDF_UNREG		0x4000	/* Unregistered (Unbuffered) */
1353 #define	SMB_MDF_LRDIMM		0x8000	/* LRDIMM */
1354 
1355 #define	SMB_MDR_SINGLE		0x01	/* single */
1356 #define	SMB_MDR_DUAL		0x02	/* dual */
1357 #define	SMB_MDR_QUAD		0x04	/* quad */
1358 #define	SMB_MDR_OCTAL		0x08	/* octal */
1359 
1360 #define	SMB_MTECH_OTHER		0x01	/* other */
1361 #define	SMB_MTECH_UNKNOWN	0x02	/* unknown */
1362 #define	SMB_MTECH_DRAM		0x03	/* DRAM */
1363 #define	SMB_MTECH_NVDIMM_N	0x04	/* NVDIMM-N */
1364 #define	SMB_MTECH_NVDIMM_F	0x05	/* NVDIMM-F */
1365 #define	SMB_MTECH_NVDIMM_P	0x06	/* NVDIMM-P */
1366 #define	SMB_MTECH_INTCPM	0x07	/* Intel Optane persistent memory */
1367 
1368 #define	SMB_MOMC_RESERVED	0x01	/* reserved */
1369 #define	SMB_MOMC_OTHER		0x02	/* other */
1370 #define	SMB_MOMC_UNKNOWN	0x04	/* unknown */
1371 #define	SMB_MOMC_VOLATILE	0x08	/* Volatile memory */
1372 #define	SMB_MOMC_BYTE_PM	0x10	/* Byte-accessible persistent memory */
1373 #define	SMB_MOMC_BLOCK_PM	0x20	/* Block-accessible persistent memory */
1374 
1375 /*
1376  * SMBIOS Memory Array Mapped Address.  See DSP0134 Section 7.20 for more
1377  * information.  We convert start/end addresses into addr/size for convenience.
1378  */
1379 typedef struct smbios_memarrmap {
1380 	id_t smbmam_array;		/* physical memory array handle */
1381 	uint32_t smbmam_width;		/* number of devices that form a row */
1382 	uint64_t smbmam_addr;		/* physical address of mapping */
1383 	uint64_t smbmam_size;		/* size in bytes of address range */
1384 } smbios_memarrmap_t;
1385 
1386 /*
1387  * SMBIOS Memory Device Mapped Address.  See DSP0134 Section 7.21 for more
1388  * information.  We convert start/end addresses into addr/size for convenience.
1389  */
1390 typedef struct smbios_memdevmap {
1391 	id_t smbmdm_device;		/* memory device handle */
1392 	id_t smbmdm_arrmap;		/* memory array mapped address handle */
1393 	uint64_t smbmdm_addr;		/* physical address of mapping */
1394 	uint64_t smbmdm_size;		/* size in bytes of address range */
1395 	uint8_t smbmdm_rpos;		/* partition row position */
1396 	uint8_t smbmdm_ipos;		/* interleave position */
1397 	uint8_t smbmdm_idepth;		/* interleave data depth */
1398 } smbios_memdevmap_t;
1399 
1400 /*
1401  * SMBIOS Builtin Pointing Device (SMB_TYPE_POINTDEV).  See DSP0134 Sectin 7.22
1402  * for more information.
1403  */
1404 typedef struct smbios_pointdev {
1405 	uint16_t smbpd_type;		/* device type */
1406 	uint16_t smbpd_iface;		/* device information */
1407 	uint8_t smbpd_nbuttons;		/* number of buttons */
1408 } smbios_pointdev_t;
1409 
1410 #define	SMB_PDT_OTHER		0x01	/* Other */
1411 #define	SMB_PDT_UNKNOWN		0x02	/* Unknown */
1412 #define	SMB_PDT_MOUSE		0x03	/* Mouse */
1413 #define	SMB_PDT_TRBALL		0x04	/* Track Ball */
1414 #define	SMB_PDT_TRPOINT		0x05	/* Track Point */
1415 #define	SMB_PDT_GLPOINT		0x06	/* Glide Point */
1416 #define	SMB_PDT_TOPAD		0x07	/* Touch Pad */
1417 #define	SMB_PDT_TOSCREEN	0x08	/* Touch Screen */
1418 #define	SMB_PDT_OPTSENSE	0x09	/* Optical Sensor */
1419 
1420 #define	SMB_PDI_OTHER		0x01	/* Other */
1421 #define	SMB_PDI_UNKNOWN		0x02	/* Unknown */
1422 #define	SMB_PDI_SERIAL		0x03	/* Serial */
1423 #define	SMB_PDI_PS2		0x04	/* PS/2 */
1424 #define	SMB_PDI_INFRARED	0x05	/* Infrared */
1425 #define	SMB_PDI_HPHIL		0x06	/* HP-HIL */
1426 #define	SMB_PDI_BUSM		0x07	/* Bus mouse */
1427 #define	SMB_PDI_ADB		0x08	/* ADB (Apple Desktop Bus) */
1428 #define	SMB_PDI_BUSM_DB9	0xA0	/* Bus mouse DB-9 */
1429 #define	SMB_PDI_BUSM_UDIN	0xA1	/* Bus mouse micro-DIN */
1430 #define	SMB_PDI_USB		0xA2	/* USB */
1431 #define	SMB_PDI_I2C		0xA3	/* I2C */
1432 #define	SMB_PDI_SPI		0xA4	/* SPI */
1433 
1434 /*
1435  * SMBIOS Portable Battery.  See DSP0134 Section 7.23 for more information.
1436  */
1437 typedef struct smbios_battery {
1438 	const char *smbb_date;		/* Manufacture date */
1439 	const char *smbb_serial;	/* Serial number */
1440 	uint8_t smbb_chem;		/* Device Chemistry */
1441 	uint32_t smbb_cap;		/* Design Capacity */
1442 	uint16_t smbb_volt;		/* Design Voltage */
1443 	const char *smbb_version;	/* Smart Battery version */
1444 	uint8_t smbb_err;		/* Maximum error */
1445 	uint16_t smbb_ssn;		/* SBDS serial number */
1446 	uint16_t smbb_syear;		/* SBDS manufacture year */
1447 	uint8_t smbb_smonth;		/* SBDS manufacture month */
1448 	uint8_t smbb_sday;		/* SBDS manufacture day */
1449 	const char *smbb_schem;		/* SBDS chemistry */
1450 	uint32_t smbb_oemdata;		/* OEM data */
1451 } smbios_battery_t;
1452 
1453 #define	SMB_BDC_OTHER		0x01	/* Other */
1454 #define	SMB_BDC_UNKNOWN		0x02	/* Unknown */
1455 #define	SMB_BDC_LEADACID	0x03	/* Lead Acid */
1456 #define	SMB_BDC_NICD		0x04	/* Nickel Cadmium */
1457 #define	SMB_BDC_NIMH		0x05	/* Nickel Metal hydride */
1458 #define	SMB_BDC_LIB		0x06	/* Lithium-ion */
1459 #define	SMB_BDC_ZINCAIR		0x07	/* Zinc air */
1460 #define	SMB_BDC_LIPO		0x08	/* Lithium Polymer */
1461 
1462 /*
1463  * SMBIOS Hardware Security Settings.  See DSP0134 Section 7.25 for more
1464  * information.  Only one such record will be present in the SMBIOS.
1465  */
1466 typedef struct smbios_hwsec {
1467 	uint8_t smbh_pwr_ps;		/* power-on password status */
1468 	uint8_t smbh_kbd_ps;		/* keyboard password status */
1469 	uint8_t smbh_adm_ps;		/* administrator password status */
1470 	uint8_t smbh_pan_ps;		/* front panel reset status */
1471 } smbios_hwsec_t;
1472 
1473 #define	SMB_HWSEC_PS_DISABLED	0x00	/* password disabled */
1474 #define	SMB_HWSEC_PS_ENABLED	0x01	/* password enabled */
1475 #define	SMB_HWSEC_PS_NOTIMPL	0x02	/* password not implemented */
1476 #define	SMB_HWSEC_PS_UNKNOWN	0x03	/* password status unknown */
1477 
1478 /*
1479  * This value is used to represent a probe that has an unknown value.
1480  */
1481 #define	SMB_PROBE_UNKNOWN_VALUE	0x8000
1482 
1483 /*
1484  * SMBIOS Voltage Probe.  See DSP0134 Section 7.27 for more information.
1485  * Please see the specification for the units of each value.
1486  */
1487 typedef struct smbios_vprobe {
1488 	const char *smbvp_description;	/* description information */
1489 	uint8_t smbvp_location;		/* probe location */
1490 	uint8_t smbvp_status;		/* probe status */
1491 	uint16_t smbvp_maxval;		/* maximum voltage */
1492 	uint16_t smbvp_minval;		/* minimum voltage */
1493 	uint16_t smbvp_resolution;	/* probe resolution */
1494 	uint16_t smbvp_tolerance;	/* probe tolerance */
1495 	uint16_t smbvp_accuracy;	/* probe accuracy */
1496 	uint32_t smbvp_oem;		/* vendor-specific data */
1497 	uint16_t smbvp_nominal;		/* nominal value */
1498 } smbios_vprobe_t;
1499 
1500 #define	SMB_VPROBE_S_OTHER	0x01	/* other */
1501 #define	SMB_VPROBE_S_UNKNOWN	0x02	/* unknown */
1502 #define	SMB_VPROBE_S_OK		0x03	/* OK */
1503 #define	SMB_VPROBE_S_NONCRIT	0x04	/* non-critical */
1504 #define	SMB_VPROBE_S_CRIT	0x05	/* critical */
1505 #define	SMB_VPROBE_S_NONRECOV	0x06	/* non-recoverable */
1506 
1507 #define	SMB_VPROBE_L_OTHER	0x01	/* other */
1508 #define	SMB_VPROBE_L_UNKNOWN	0x02	/* unknown */
1509 #define	SMB_VPROBE_L_PROC	0x03	/* processor */
1510 #define	SMB_VPROBE_L_DISK	0x04	/* disk */
1511 #define	SMB_VPROBE_L_PBAY	0x05	/* peripheral bay */
1512 #define	SMB_VPROBE_L_MGMT	0x06	/* system management module */
1513 #define	SMB_VPROBE_L_MOBO	0x07	/* motherboard */
1514 #define	SMB_VPROBE_L_MEMMOD	0x08	/* memory module */
1515 #define	SMB_VPROBE_L_PROCMOD	0x09	/* processor module */
1516 #define	SMB_VPROBE_L_POWER	0x0a	/* power unit */
1517 #define	SMB_VPROBE_L_AIC	0x0b	/* add-in card */
1518 
1519 /*
1520  * SMBIOS Cooling Device.  See DSP0134 Section 7.28 for more information.
1521  * Please see the specification for the units of each value.
1522  */
1523 typedef struct smbios_cooldev {
1524 	id_t smbcd_tprobe;		/* temperature probe handle */
1525 	uint8_t smbcd_type;		/* cooling device type */
1526 	uint8_t smbcd_status;		/* status */
1527 	uint8_t smbcd_group;		/* group ID */
1528 	uint32_t smbcd_oem;		/* vendor-specific data */
1529 	uint16_t smbcd_nominal;		/* nominal speed */
1530 	const char *smbcd_descr;	/* device description */
1531 } smbios_cooldev_t;
1532 
1533 #define	SMB_COOLDEV_S_OTHER	0x01	/* other */
1534 #define	SMB_COOLDEV_S_UNKNOWN	0x02	/* unknown */
1535 #define	SMB_COOLDEV_S_OK	0x03	/* OK */
1536 #define	SMB_COOLDEV_S_NONCRIT	0x04	/* non-critical */
1537 #define	SMB_COOLDEV_S_CRIT	0x05	/* critical */
1538 #define	SMB_COOLDEV_S_NONRECOV	0x06	/* non-recoverable */
1539 
1540 #define	SMB_COOLDEV_T_OTHER	0x01	/* other */
1541 #define	SMB_COOLDEV_T_UNKNOWN	0x02	/* unknown */
1542 #define	SMB_COOLDEV_T_FAN	0x03	/* fan */
1543 #define	SMB_COOLDEV_T_BLOWER	0x04	/* centrifugal blower */
1544 #define	SMB_COOLDEV_T_CHIPFAN	0x05	/* chip fan */
1545 #define	SMB_COOLDEV_T_CABFAN	0x06	/* cabinet fan */
1546 #define	SMB_COOLDEV_T_PSFAN	0x07	/* power supply fan */
1547 #define	SMB_COOLDEV_T_HEATPIPE	0x08	/* head pipe */
1548 #define	SMB_COOLDEV_T_IREFRIG	0x09	/* integrated refrigeration */
1549 #define	SMB_COOLDEV_T_ACTCOOL	0x10	/* active cooling */
1550 #define	SMB_COOLDEV_T_PASSCOOL	0x11	/* passive cooling */
1551 
1552 /*
1553  * SMBIOS Temperature Probe.  See DSP0134 Section 7.29 for more information.
1554  * Please see the specification for the units of each value.
1555  */
1556 typedef struct smbios_tprobe {
1557 	const char *smbtp_description;	/* description information */
1558 	uint8_t smbtp_location;		/* probe location */
1559 	uint8_t smbtp_status;		/* probe status */
1560 	uint16_t smbtp_maxval;		/* maximum temperature */
1561 	uint16_t smbtp_minval;		/* minimum temperature */
1562 	uint16_t smbtp_resolution;	/* probe resolution */
1563 	uint16_t smbtp_tolerance;	/* probe tolerance */
1564 	uint16_t smbtp_accuracy;	/* probe accuracy */
1565 	uint32_t smbtp_oem;		/* vendor-specific data */
1566 	uint16_t smbtp_nominal;		/* nominal value */
1567 } smbios_tprobe_t;
1568 
1569 #define	SMB_TPROBE_S_OTHER	0x01	/* other */
1570 #define	SMB_TPROBE_S_UNKNOWN	0x02	/* unknown */
1571 #define	SMB_TPROBE_S_OK		0x03	/* OK */
1572 #define	SMB_TPROBE_S_NONCRIT	0x04	/* non-critical */
1573 #define	SMB_TPROBE_S_CRIT	0x05	/* critical */
1574 #define	SMB_TPROBE_S_NONRECOV	0x06	/* non-recoverable */
1575 
1576 #define	SMB_TPROBE_L_OTHER	0x01	/* other */
1577 #define	SMB_TPROBE_L_UNKNOWN	0x02	/* unknown */
1578 #define	SMB_TPROBE_L_PROC	0x03	/* processor */
1579 #define	SMB_TPROBE_L_DISK	0x04	/* disk */
1580 #define	SMB_TPROBE_L_PBAY	0x05	/* peripheral bay */
1581 #define	SMB_TPROBE_L_MGMT	0x06	/* system management module */
1582 #define	SMB_TPROBE_L_MOBO	0x07	/* motherboard */
1583 #define	SMB_TPROBE_L_MEMMOD	0x08	/* memory module */
1584 #define	SMB_TPROBE_L_PROCMOD	0x09	/* processor module */
1585 #define	SMB_TPROBE_L_POWER	0x0a	/* power unit */
1586 #define	SMB_TPROBE_L_AIC	0x0b	/* add-in card */
1587 #define	SMB_TPROBE_L_FPBOARD	0x0c	/* front panel board */
1588 #define	SMB_TPROBE_L_BPBOARD	0x0d	/* rear panel board */
1589 #define	SMB_TPROBE_L_PSBOARD	0x0e	/* power system board */
1590 #define	SMB_TPROBE_L_DBPANE	0x0f	/* drive back plane */
1591 
1592 /*
1593  * SMBIOS Current Probe.  See DSP0134 Section 7.30 for more information.
1594  * Please see the specification for the units of each value.
1595  */
1596 typedef struct smbios_iprobe {
1597 	const char *smbip_description;	/* description information */
1598 	uint8_t smbip_location;		/* probe location */
1599 	uint8_t smbip_status;		/* probe status */
1600 	uint16_t smbip_maxval;		/* maximum current */
1601 	uint16_t smbip_minval;		/* minimum current */
1602 	uint16_t smbip_resolution;	/* probe resolution */
1603 	uint16_t smbip_tolerance;	/* probe tolerance */
1604 	uint16_t smbip_accuracy;	/* probe accuracy */
1605 	uint32_t smbip_oem;		/* vendor-specific data */
1606 	uint16_t smbip_nominal;		/* nominal value */
1607 } smbios_iprobe_t;
1608 
1609 #define	SMB_IPROBE_S_OTHER	0x01	/* other */
1610 #define	SMB_IPROBE_S_UNKNOWN	0x02	/* unknown */
1611 #define	SMB_IPROBE_S_OK		0x03	/* OK */
1612 #define	SMB_IPROBE_S_NONCRIT	0x04	/* non-critical */
1613 #define	SMB_IPROBE_S_CRIT	0x05	/* critical */
1614 #define	SMB_IPROBE_S_NONRECOV	0x06	/* non-recoverable */
1615 
1616 #define	SMB_IPROBE_L_OTHER	0x01	/* other */
1617 #define	SMB_IPROBE_L_UNKNOWN	0x02	/* unknown */
1618 #define	SMB_IPROBE_L_PROC	0x03	/* processor */
1619 #define	SMB_IPROBE_L_DISK	0x04	/* disk */
1620 #define	SMB_IPROBE_L_PBAY	0x05	/* peripheral bay */
1621 #define	SMB_IPROBE_L_MGMT	0x06	/* system management module */
1622 #define	SMB_IPROBE_L_MOBO	0x07	/* motherboard */
1623 #define	SMB_IPROBE_L_MEMMOD	0x08	/* memory module */
1624 #define	SMB_IPROBE_L_PROCMOD	0x09	/* processor module */
1625 #define	SMB_IPROBE_L_POWER	0x0a	/* power unit */
1626 #define	SMB_IPROBE_L_AIC	0x0b	/* add-in card */
1627 
1628 /*
1629  * SMBIOS System Boot Information.  See DSP0134 Section 7.33 for more
1630  * information.  The contents of the data varies by type and is undocumented
1631  * from the perspective of DSP0134 -- it seems to be left as vendor-specific.
1632  * The (D) annotation next to SMB_BOOT_* below indicates possible data payload.
1633  */
1634 typedef struct smbios_boot {
1635 	uint8_t smbt_status;		/* boot status code (see below) */
1636 	const void *smbt_data;		/* data buffer specific to status */
1637 	size_t smbt_size;		/* size of smbt_data buffer in bytes */
1638 } smbios_boot_t;
1639 
1640 #define	SMB_BOOT_NORMAL		0	/* no errors detected */
1641 #define	SMB_BOOT_NOMEDIA	1	/* no bootable media */
1642 #define	SMB_BOOT_OSFAIL		2	/* normal o/s failed to load */
1643 #define	SMB_BOOT_FWHWFAIL	3	/* firmware-detected hardware failure */
1644 #define	SMB_BOOT_OSHWFAIL	4	/* o/s-detected hardware failure */
1645 #define	SMB_BOOT_USERREQ	5	/* user-requested boot (keystroke) */
1646 #define	SMB_BOOT_SECURITY	6	/* system security violation */
1647 #define	SMB_BOOT_PREVREQ	7	/* previously requested image (D) */
1648 #define	SMB_BOOT_WATCHDOG	8	/* watchdog initiated reboot */
1649 #define	SMB_BOOT_RESV_LO	9	/* low end of reserved range */
1650 #define	SMB_BOOT_RESV_HI	127	/* high end of reserved range */
1651 #define	SMB_BOOT_OEM_LO		128	/* low end of OEM-specific range */
1652 #define	SMB_BOOT_OEM_HI		191	/* high end of OEM-specific range */
1653 #define	SMB_BOOT_PROD_LO	192	/* low end of product-specific range */
1654 #define	SMB_BOOT_PROD_HI	255	/* high end of product-specific range */
1655 
1656 /*
1657  * SMBIOS IPMI Device Information.  See DSP0134 Section 7.39 and also
1658  * Appendix C1 of the IPMI specification for more information on this record.
1659  */
1660 typedef struct smbios_ipmi {
1661 	uint_t smbip_type;		/* BMC interface type */
1662 	smbios_version_t smbip_vers;	/* BMC's IPMI specification version */
1663 	uint32_t smbip_i2c;		/* BMC I2C bus slave address */
1664 	uint32_t smbip_bus;		/* bus ID of NV storage device, or -1 */
1665 	uint64_t smbip_addr;		/* BMC base address */
1666 	uint32_t smbip_flags;		/* flags (see below) */
1667 	uint16_t smbip_intr;		/* interrupt number (or zero if none) */
1668 	uint16_t smbip_regspacing;	/* i/o space register spacing (bytes) */
1669 } smbios_ipmi_t;
1670 
1671 #define	SMB_IPMI_T_UNKNOWN	0x00	/* unknown */
1672 #define	SMB_IPMI_T_KCS		0x01	/* KCS: Keyboard Controller Style */
1673 #define	SMB_IPMI_T_SMIC		0x02	/* SMIC: Server Mgmt Interface Chip */
1674 #define	SMB_IPMI_T_BT		0x03	/* BT: Block Transfer */
1675 #define	SMB_IPMI_T_SSIF		0x04	/* SSIF: SMBus System Interface */
1676 
1677 #define	SMB_IPMI_F_IOADDR	0x01	/* base address is in i/o space */
1678 #define	SMB_IPMI_F_INTRSPEC	0x02	/* intr information is specified */
1679 #define	SMB_IPMI_F_INTRHIGH	0x04	/* intr active high (else low) */
1680 #define	SMB_IPMI_F_INTREDGE	0x08	/* intr is edge triggered (else lvl) */
1681 
1682 /*
1683  * SMBIOS System Power Supply Information.  See DSP0134 7.40 for more
1684  * information.
1685  */
1686 typedef struct smbios_powersup {
1687 	uint32_t smbps_group;		/* group ID */
1688 	uint64_t smbps_maxout;		/* max output in milliwatts */
1689 	uint32_t smbps_flags;		/* see below */
1690 	uint8_t smbps_ivrs;		/* input voltage range switching type */
1691 	uint8_t smbps_status;		/* PSU status */
1692 	uint8_t smbps_pstype;		/* PSU type */
1693 	id_t smbps_vprobe;		/* voltage probe handle */
1694 	id_t smbps_cooldev;		/* cooling device handle */
1695 	id_t smbps_iprobe;		/* current probe handle */
1696 } smbios_powersup_t;
1697 
1698 /* smbpfs_flags */
1699 #define	SMB_POWERSUP_F_HOT	0x01	/* PSU is hot-replaceable */
1700 #define	SMB_POWERSUP_F_PRESENT	0x02	/* PSU is present */
1701 #define	SMB_POWERSUP_F_UNPLUG	0x04	/* PSU is unplugged from outlet */
1702 
1703 /* Values for smbps_ivrs */
1704 #define	SMB_POWERSUP_I_OTHER	0x01	/* other */
1705 #define	SMB_POWERSUP_I_UNKNOWN	0x02	/* unknown */
1706 #define	SMB_POWERSUP_I_MANUAL	0x03	/* manual */
1707 #define	SMB_POWERSUP_I_AUTO	0x04	/* auto-switch */
1708 #define	SMB_POWERSUP_I_WIDE	0x05	/* wide range */
1709 #define	SMB_POWERSUP_I_NA	0x06	/* not applicable */
1710 
1711 #define	SMB_POWERSUP_S_OTHER	0x01	/* other */
1712 #define	SMB_POWERSUP_S_UNKNOWN	0x02	/* unknown */
1713 #define	SMB_POWERSUP_S_OK	0x03	/* OK */
1714 #define	SMB_POWERSUP_S_NONCRIT	0x04	/* non-critical */
1715 #define	SMB_POWERSUP_S_CRIT	0x05	/* critical; PSU failed */
1716 
1717 #define	SMB_POWERSUP_T_OTHER	0x01	/* other */
1718 #define	SMB_POWERSUP_T_UNKNOWN	0x02	/* unknown */
1719 #define	SMB_POWERSUP_T_LINEAR	0x03	/* linear */
1720 #define	SMB_POWERSUP_T_SWITCH	0x04	/* switching */
1721 #define	SMB_POWERSUP_T_BAT	0x05	/* battery */
1722 #define	SMB_POWERSUP_T_UPS	0x06	/* UPS */
1723 #define	SMB_POWERSUP_T_CONV	0x07	/* converter */
1724 #define	SMB_POWERSUP_T_REGL	0x08	/* regulator */
1725 
1726 /*
1727  * SMBIOS Onboard Devices Extended Information.  See DSP0134 Section 7.42
1728  * for more information.
1729  */
1730 typedef struct smbios_obdev_ext {
1731 	const char *smboe_name;		/* reference designation */
1732 	uint8_t smboe_dtype;		/* device type */
1733 	uint8_t smboe_dti;		/* device type instance */
1734 	uint16_t smboe_sg;		/* segment group number */
1735 	uint8_t smboe_bus;		/* bus number */
1736 	uint8_t smboe_df;		/* device/function number */
1737 } smbios_obdev_ext_t;
1738 
1739 #define	SMB_OBET_OTHER		0x01	/* Other */
1740 #define	SMB_OBET_UNKNOWN	0x02	/* Unknown */
1741 #define	SMB_OBET_VIDEO		0x03	/* video */
1742 #define	SMB_OBET_SCSI		0x04	/* SCSI */
1743 #define	SMB_OBET_ETHERNET	0x05	/* Ethernet */
1744 #define	SMB_OBET_TOKEN		0x06	/* Token Ring */
1745 #define	SMB_OBET_SOUND		0x07	/* Sound */
1746 #define	SMB_OBET_PATA		0x08	/* PATA */
1747 #define	SMB_OBET_SATA		0x09	/* SATA */
1748 #define	SMB_OBET_SAS		0x0A	/* SAS */
1749 #define	SMB_OBET_WLAN		0x0B	/* Wireless LAN */
1750 #define	SMB_OBET_BT		0x0C	/* Bluetooth */
1751 #define	SMB_OBET_WWAN		0x0D	/* WWAN */
1752 #define	SMB_OBET_EMMC		0x0E	/* eMMC */
1753 #define	SMB_OBET_NVME		0x0F	/* NVMe */
1754 #define	SMB_OBET_UFS		0x10	/* UFS */
1755 
1756 /*
1757  * SMBIOS Processor Additional Information (Type 44). See section 7.45 for more
1758  * information.
1759  */
1760 typedef struct smbios_processor_info {
1761 	id_t smbpi_processor;		/* processor handle */
1762 	uint32_t smbpi_ptype;		/* processor type */
1763 } smbios_processor_info_t;
1764 
1765 /* BEGIN CSTYLED */
1766 #define	SMB_PROCINFO_T_RESERVED	0x00	/* reserved */
1767 #define	SMB_PROCINFO_T_IA32	0x01	/* IA32 (x86) */
1768 #define	SMB_PROCINFO_T_AMD64	0x02	/* X64 (x86-64, Intel64, AMD64, EMT64) */
1769 #define	SMB_PROCINFO_T_IA	0x03	/* Intel Itanium architecture */
1770 #define	SMB_PROCINFO_T_AARCH32	0x04	/* 32-bit ARM (aarch32) */
1771 #define	SMB_PROCINFO_T_AARCH64	0x05	/* 64-bit ARM (aarch64) */
1772 #define	SMB_PROCINFO_T_RV32	0x06	/* 32-bit RISC-V (RV32) */
1773 #define	SMB_PROCINFO_T_RV64	0x07	/* 64-bit RISC-V (RV64) */
1774 #define	SMB_PROCINFO_T_RV128	0x08	/* 128-bit RISC-V (RV128) */
1775 /* END CSTYLED */
1776 
1777 typedef struct smbios_processor_info_riscv {
1778 	uint8_t smbpirv_hartid[16];	/* HART ID */
1779 	uint8_t smbpirv_vendid[16];	/* Vendor ID */
1780 	uint8_t smbpirv_archid[16];	/* Architecture ID */
1781 	uint8_t smbpirv_machid[16];	/* Machine ID */
1782 	uint8_t smbpirv_metdi[16];	/* Machine exception delegation */
1783 	uint8_t smbpirv_mitdi[16];	/* Machine interrupt delegation */
1784 	uint64_t smbpirv_isa;		/* Supported ISA */
1785 	uint32_t smbpirv_privlvl;	/* Privilege Level */
1786 	uint8_t smbpirv_boothart;	/* Indicates if boot processor */
1787 	uint8_t smbpirv_xlen;		/* Default register width */
1788 	uint8_t smbpirv_mxlen;		/* Machine register width */
1789 	uint8_t smbpirv_sxlen;		/* Supervisor register width */
1790 	uint8_t smbpirv_uxlen;		/* User register width */
1791 } smbios_processor_info_riscv_t;
1792 
1793 /*
1794  * RISC-V Supported Privilege Levels
1795  */
1796 #define	SMB_RV_PRIV_M	(1 << 0)	/* Machine Mode */
1797 #define	SMB_RV_PRIV_S	(1 << 2)	/* Supervisor Mode */
1798 #define	SMB_RV_PRIV_U	(1 << 3)	/* User Mode */
1799 #define	SMB_RV_PRIV_DBG	(1 << 7)	/* Debug Mode */
1800 
1801 /*
1802  * Values used to define the various XLEN Values.
1803  */
1804 #define	SMB_RV_WIDTH_UNSUP	0x00	/* Unsupported */
1805 #define	SMB_RV_WIDTH_32B	0x01	/* 32-bit */
1806 #define	SMB_RV_WIDTH_64B	0x02	/* 64-bit */
1807 #define	SMB_RV_WIDTH_128B	0x03	/* 128-bit */
1808 
1809 /*
1810  * RISC-V ISA extensions
1811  */
1812 /* BEGIN CSTYLED */
1813 #define	SMB_RV_ISA_A	(1 << 0)	/* Atomic */
1814 #define	SMB_RV_ISA_B	(1 << 1)	/* Reserved */
1815 #define	SMB_RV_ISA_C	(1 << 2)	/* Compressed */
1816 #define	SMB_RV_ISA_D	(1 << 3)	/* Double-precision floating-point */
1817 #define	SMB_RV_ISA_E	(1 << 4)	/* RV32E base */
1818 #define	SMB_RV_ISA_F	(1 << 5)	/* Single-precision floating-point */
1819 #define	SMB_RV_ISA_G	(1 << 6)	/* Additional standard extensions present */
1820 #define	SMB_RV_ISA_H	(1 << 7)	/* Hypervisor */
1821 #define	SMB_RV_ISA_I	(1 << 8)	/* Integer base ISA */
1822 #define	SMB_RV_ISA_J	(1 << 9)	/* Reserved */
1823 #define	SMB_RV_ISA_K	(1 << 10)	/* Reserved */
1824 #define	SMB_RV_ISA_L	(1 << 11)	/* Reserved */
1825 #define	SMB_RV_ISA_M	(1 << 12)	/* Integer Multiply/Divide */
1826 #define	SMB_RV_ISA_N	(1 << 13)	/* User-level interrupts */
1827 #define	SMB_RV_ISA_O	(1 << 14)	/* Reserved */
1828 #define	SMB_RV_ISA_P	(1 << 15)	/* Reserved */
1829 #define	SMB_RV_ISA_Q	(1 << 16)	/* Quad-precision floating-point */
1830 #define	SMB_RV_ISA_R	(1 << 17)	/* Reserved */
1831 #define	SMB_RV_ISA_S	(1 << 18)	/* Supervisor mode */
1832 #define	SMB_RV_ISA_T	(1 << 19)	/* Reserved */
1833 #define	SMB_RV_ISA_U	(1 << 20)	/* User mode */
1834 #define	SMB_RV_ISA_V	(1 << 21)	/* Reserved */
1835 #define	SMB_RV_ISA_W	(1 << 22)	/* Reserved */
1836 #define	SMB_RV_ISA_X	(1 << 23)	/* Non-standard extensions */
1837 #define	SMB_RV_ISA_Y	(1 << 24)	/* Reserved */
1838 #define	SMB_RV_ISA_Z	(1 << 25)	/* Reserved */
1839 /* END CSTYLED */
1840 
1841 /*
1842  * SMBIOS Firmware Inventory Information (Type 45).
1843  */
1844 typedef struct smbios_fwinfo {
1845 	const char *smbfw_name;		/* Firmware component name */
1846 	const char *smbfw_id;		/* Firmware ID */
1847 	const char *smbfw_reldate;	/* Release date */
1848 	const char *smbfw_lsv;		/* Lowest supported version */
1849 	uint64_t smbfw_imgsz;		/* Image size */
1850 	uint16_t smbfw_chars;		/* Characteristics */
1851 	uint16_t smbfw_state;		/* State */
1852 	uint16_t smbfw_ncomps;		/* Number of associated components */
1853 	uint8_t smbfw_vers_fmt;		/* Firmware version format */
1854 	uint8_t smbfw_id_fmt;		/* Firmware ID format */
1855 } smbios_fwinfo_t;
1856 
1857 typedef struct smbios_fwinfo_comp {
1858 	id_t smbfwe_id;			/* Contained element ID */
1859 } smbios_fwinfo_comp_t;
1860 
1861 /*
1862  * Firmware version format constants.
1863  */
1864 #define	SMB_FWV_FF		0x00	/* free-form */
1865 #define	SMB_FWV_MM		0x01	/* major.minor */
1866 #define	SMB_FWV_HEX32		0x02	/* 32-bit hex */
1867 #define	SMB_FWV_HEX64		0x03	/* 64-bit hex */
1868 
1869 /*
1870  * Firmware ID format constants.
1871  */
1872 #define	SMB_FWI_FF		0x00	/* free-form */
1873 #define	SMB_FWI_UEFI		0x01	/* UEFI GUID */
1874 
1875 /*
1876  * Firmware characteristic bitfields.
1877  */
1878 #define	SMB_FWC_UPDATE		0x01	/* updatable */
1879 #define	SMB_FWC_WP		0x02	/* write-protect */
1880 
1881 /*
1882  * Firmware state constants.
1883  */
1884 #define	SMB_FWS_OTHER		0x01	/* other */
1885 #define	SMB_FWS_UNKNOWN		0x02	/* unknown */
1886 #define	SMB_FWS_DISABLED	0x03	/* disabled */
1887 #define	SMB_FWS_ENABLED		0x04	/* enabled */
1888 #define	SMB_FWS_ABSENT		0x05	/* absent */
1889 #define	SMB_FWS_STB_OFFLINE	0x06	/* standby offline */
1890 #define	SMB_FWS_STB_SPARE	0x07	/* standby spare */
1891 #define	SMB_FWS_UA_OFFLINE	0x08	/* unavailable offline */
1892 
1893 /*
1894  * SMBIOS String Property (Type 46). See section 7.47 for more information.
1895  */
1896 typedef struct smbios_strprop {
1897 	uint32_t smbsp_prop_id;		/* property ID */
1898 	const char *smbsp_prop_val;	/* property Value */
1899 	id_t smbsp_parent;		/* parent handle */
1900 } smbios_strprop_t;
1901 
1902 /*
1903  * String Property IDs
1904  */
1905 #define	SMB_STRP_RESERVED	0x00		/* reserved */
1906 #define	SMB_STRP_UEFI_DEVPATH	0x01		/* UEFI device path */
1907 
1908 /*
1909  * SMBIOS OEM-specific (Type 132) Processor Extended Information.
1910  */
1911 typedef struct smbios_processor_ext {
1912 	uint16_t smbpe_processor;	/* extending processor handle */
1913 	uint8_t smbpe_fru;		/* FRU indicator */
1914 	uint8_t smbpe_n;		/* number of APIC IDs */
1915 	uint16_t *smbpe_apicid;		/* strand Inital APIC IDs */
1916 } smbios_processor_ext_t;
1917 
1918 /*
1919  * SMBIOS OEM-specific (Type 136) Port Extended Information.
1920  */
1921 typedef struct smbios_port_ext {
1922 	uint16_t smbporte_chassis;	/* chassis handle */
1923 	uint16_t smbporte_port;		/* port connector handle */
1924 	uint8_t smbporte_dtype;		/* device type */
1925 	uint16_t smbporte_devhdl;	/* device handle */
1926 	uint8_t smbporte_phy;		/* PHY number */
1927 } smbios_port_ext_t;
1928 
1929 /*
1930  * SMBIOS OEM-specific (Type 138) PCI-Express RC/RP Information.
1931  */
1932 typedef struct smbios_pciexrc {
1933 	uint16_t smbpcie_bb;		/* base board handle */
1934 	uint16_t smbpcie_bdf;		/* Bus/Dev/Funct (PCI) */
1935 } smbios_pciexrc_t;
1936 
1937 /*
1938  * SMBIOS OEM-specific (Type 144) Memory Array Extended Information.
1939  */
1940 typedef struct smbios_memarray_ext {
1941 	uint16_t smbmae_ma;		/* memory array handle */
1942 	uint16_t smbmae_comp;		/* component parent handle */
1943 	uint16_t smbmae_bdf;		/* Bus/Dev/Funct (PCI) */
1944 } smbios_memarray_ext_t;
1945 
1946 /*
1947  * SMBIOS OEM-specific (Type 145) Memory Device Extended Information.
1948  */
1949 typedef struct smbios_memdevice_ext {
1950 	uint16_t smbmdeve_md;		/* memory device handle */
1951 	uint8_t smbmdeve_drch;		/* DRAM channel */
1952 	uint8_t smbmdeve_ncs;		/* number of chip selects */
1953 	uint8_t *smbmdeve_cs;		/* array of chip select numbers */
1954 } smbios_memdevice_ext_t;
1955 
1956 /*
1957  * SMBIOS Interfaces.  An SMBIOS image can be opened by either providing a file
1958  * pathname, device pathname, file descriptor, or raw memory buffer.  Once an
1959  * image is opened the functions below can be used to iterate over the various
1960  * structures and convert the underlying data representation into the simpler
1961  * data structures described earlier in this header file.  The SMB_VERSION
1962  * constant specified when opening an image indicates the version of the ABI
1963  * the caller expects and the DMTF SMBIOS version the client can understand.
1964  * The library will then map older or newer data structures to that as needed.
1965  */
1966 
1967 #define	SMB_VERSION_23	0x0203		/* SMBIOS encoding for DMTF spec 2.3 */
1968 #define	SMB_VERSION_24	0x0204		/* SMBIOS encoding for DMTF spec 2.4 */
1969 #define	SMB_VERSION_25	0x0205		/* SMBIOS encoding for DMTF spec 2.5 */
1970 #define	SMB_VERSION_26	0x0206		/* SMBIOS encoding for DMTF spec 2.6 */
1971 #define	SMB_VERSION_27	0x0207		/* SMBIOS encoding for DMTF spec 2.7 */
1972 #define	SMB_VERSION_28	0x0208		/* SMBIOS encoding for DMTF spec 2.8 */
1973 #define	SMB_VERSION_30	0x0300		/* SMBIOS encoding for DMTF spec 3.0 */
1974 #define	SMB_VERSION_31	0x0301		/* SMBIOS encoding for DMTF spec 3.1 */
1975 #define	SMB_VERSION_32	0x0302		/* SMBIOS encoding for DMTF spec 3.2 */
1976 #define	SMB_VERSION_33	0x0303		/* SMBIOS encoding for DMTF spec 3.3 */
1977 #define	SMB_VERSION_34	0x0304		/* SMBIOS encoding for DMTF spec 3.4 */
1978 #define	SMB_VERSION_35	0x0305		/* SMBIOS encoding for DMTF spec 3.5 */
1979 #define	SMB_VERSION	SMB_VERSION_35	/* SMBIOS latest version definitions */
1980 
1981 #define	SMB_O_NOCKSUM	0x1		/* do not verify header checksums */
1982 #define	SMB_O_NOVERS	0x2		/* do not verify header versions */
1983 #define	SMB_O_ZIDS	0x4		/* strip out identification numbers */
1984 #define	SMB_O_MASK	0x7		/* mask of valid smbios_*open flags */
1985 
1986 #define	SMB_ID_NOTSUP	0xFFFE		/* structure is not supported by BIOS */
1987 #define	SMB_ID_NONE	0xFFFF		/* structure is a null reference */
1988 
1989 #define	SMB_ERR		(-1)		/* id_t value indicating error */
1990 
1991 typedef struct smbios_hdl smbios_hdl_t;
1992 
1993 typedef struct smbios_struct {
1994 	id_t smbstr_id;			/* structure ID handle */
1995 	uint_t smbstr_type;		/* structure type */
1996 	const void *smbstr_data;	/* structure data */
1997 	size_t smbstr_size;		/* structure size */
1998 } smbios_struct_t;
1999 
2000 typedef int smbios_struct_f(smbios_hdl_t *,
2001     const smbios_struct_t *, void *);
2002 
2003 extern smbios_hdl_t *smbios_open(const char *, int, int, int *);
2004 extern smbios_hdl_t *smbios_fdopen(int, int, int, int *);
2005 extern smbios_hdl_t *smbios_bufopen(const smbios_entry_t *,
2006     const void *, size_t, int, int, int *);
2007 
2008 extern const void *smbios_buf(smbios_hdl_t *);
2009 extern size_t smbios_buflen(smbios_hdl_t *);
2010 
2011 extern void smbios_checksum(smbios_hdl_t *, smbios_entry_t *);
2012 extern int smbios_write(smbios_hdl_t *, int);
2013 extern void smbios_close(smbios_hdl_t *);
2014 
2015 extern boolean_t smbios_truncated(smbios_hdl_t *);
2016 extern int smbios_errno(smbios_hdl_t *);
2017 extern const char *smbios_errmsg(int);
2018 
2019 extern int smbios_lookup_id(smbios_hdl_t *, id_t, smbios_struct_t *);
2020 extern int smbios_lookup_type(smbios_hdl_t *, uint_t, smbios_struct_t *);
2021 extern int smbios_iter(smbios_hdl_t *, smbios_struct_f *, void *);
2022 
2023 extern smbios_entry_point_t smbios_info_smbios(smbios_hdl_t *,
2024     smbios_entry_t *);
2025 extern void smbios_info_smbios_version(smbios_hdl_t *, smbios_version_t *);
2026 extern int smbios_info_common(smbios_hdl_t *, id_t, smbios_info_t *);
2027 extern int smbios_info_contains(smbios_hdl_t *, id_t, uint_t, id_t *);
2028 extern id_t smbios_info_bios(smbios_hdl_t *, smbios_bios_t *);
2029 extern id_t smbios_info_system(smbios_hdl_t *, smbios_system_t *);
2030 extern int smbios_info_bboard(smbios_hdl_t *, id_t, smbios_bboard_t *);
2031 extern int smbios_info_chassis(smbios_hdl_t *, id_t, smbios_chassis_t *);
2032 extern int smbios_info_chassis_elts(smbios_hdl_t *, id_t, uint_t *,
2033     smbios_chassis_entry_t **);
2034 extern void smbios_info_chassis_elts_free(smbios_hdl_t *, uint_t,
2035     smbios_chassis_entry_t *);
2036 extern int smbios_info_processor(smbios_hdl_t *, id_t, smbios_processor_t *);
2037 extern int smbios_info_extprocessor(smbios_hdl_t *, id_t,
2038     smbios_processor_ext_t *);
2039 extern int smbios_info_cache(smbios_hdl_t *, id_t, smbios_cache_t *);
2040 extern int smbios_info_pointdev(smbios_hdl_t *, id_t, smbios_pointdev_t *);
2041 extern int smbios_info_battery(smbios_hdl_t *, id_t, smbios_battery_t *);
2042 extern int smbios_info_port(smbios_hdl_t *, id_t, smbios_port_t *);
2043 extern int smbios_info_extport(smbios_hdl_t *, id_t, smbios_port_ext_t *);
2044 extern int smbios_info_slot(smbios_hdl_t *, id_t, smbios_slot_t *);
2045 extern int smbios_info_slot_peers(smbios_hdl_t *, id_t, uint_t *,
2046     smbios_slot_peer_t **);
2047 extern void smbios_info_slot_peers_free(smbios_hdl_t *, uint_t,
2048     smbios_slot_peer_t *);
2049 extern int smbios_info_obdevs(smbios_hdl_t *, id_t, int, smbios_obdev_t *);
2050 extern int smbios_info_obdevs_ext(smbios_hdl_t *, id_t, smbios_obdev_ext_t *);
2051 extern int smbios_info_strtab(smbios_hdl_t *, id_t, int, const char *[]);
2052 extern id_t smbios_info_lang(smbios_hdl_t *, smbios_lang_t *);
2053 extern id_t smbios_info_eventlog(smbios_hdl_t *, smbios_evlog_t *);
2054 extern int smbios_info_memarray(smbios_hdl_t *, id_t, smbios_memarray_t *);
2055 extern int smbios_info_extmemarray(smbios_hdl_t *, id_t,
2056     smbios_memarray_ext_t *);
2057 extern int smbios_info_memarrmap(smbios_hdl_t *, id_t, smbios_memarrmap_t *);
2058 extern int smbios_info_memdevice(smbios_hdl_t *, id_t, smbios_memdevice_t *);
2059 extern int smbios_info_extmemdevice(smbios_hdl_t *, id_t,
2060     smbios_memdevice_ext_t *);
2061 extern int smbios_info_memdevmap(smbios_hdl_t *, id_t, smbios_memdevmap_t *);
2062 extern id_t smbios_info_hwsec(smbios_hdl_t *, smbios_hwsec_t *);
2063 extern int smbios_info_vprobe(smbios_hdl_t *, id_t, smbios_vprobe_t *);
2064 extern int smbios_info_cooldev(smbios_hdl_t *, id_t, smbios_cooldev_t *);
2065 extern int smbios_info_tprobe(smbios_hdl_t *, id_t, smbios_tprobe_t *);
2066 extern int smbios_info_iprobe(smbios_hdl_t *, id_t, smbios_iprobe_t *);
2067 extern id_t smbios_info_boot(smbios_hdl_t *, smbios_boot_t *);
2068 extern id_t smbios_info_ipmi(smbios_hdl_t *, smbios_ipmi_t *);
2069 extern int smbios_info_powersup(smbios_hdl_t *, id_t, smbios_powersup_t *);
2070 extern int smbios_info_pciexrc(smbios_hdl_t *, id_t, smbios_pciexrc_t *);
2071 extern int smbios_info_processor_info(smbios_hdl_t *, id_t,
2072     smbios_processor_info_t *);
2073 extern int smbios_info_processor_riscv(smbios_hdl_t *, id_t,
2074     smbios_processor_info_riscv_t *);
2075 extern int smbios_info_strprop(smbios_hdl_t *, id_t, smbios_strprop_t *);
2076 extern int smbios_info_fwinfo(smbios_hdl_t *, id_t, smbios_fwinfo_t *);
2077 extern int smbios_info_fwinfo_comps(smbios_hdl_t *, id_t, uint_t *,
2078     smbios_fwinfo_comp_t **);
2079 extern void smbios_info_fwinfo_comps_free(smbios_hdl_t *, uint_t,
2080     smbios_fwinfo_comp_t *);
2081 
2082 extern const char *smbios_psn(smbios_hdl_t *);
2083 extern const char *smbios_csn(smbios_hdl_t *);
2084 
2085 #ifndef _KERNEL
2086 /*
2087  * The smbios_*_desc() and smbios_*_name() interfaces can be used for utilities
2088  * such as smbios(8) that wish to decode SMBIOS fields for humans.  The _desc
2089  * functions return the comment string next to the #defines listed above, and
2090  * the _name functions return the appropriate #define identifier itself.
2091  */
2092 extern const char *smbios_battery_chem_desc(uint_t);
2093 
2094 extern const char *smbios_bboard_flag_desc(uint_t);
2095 extern const char *smbios_bboard_flag_name(uint_t);
2096 extern const char *smbios_bboard_type_desc(uint_t);
2097 
2098 extern const char *smbios_bios_flag_desc(uint64_t);
2099 extern const char *smbios_bios_flag_name(uint64_t);
2100 
2101 extern const char *smbios_bios_xb1_desc(uint_t);
2102 extern const char *smbios_bios_xb1_name(uint_t);
2103 extern const char *smbios_bios_xb2_desc(uint_t);
2104 extern const char *smbios_bios_xb2_name(uint_t);
2105 
2106 extern const char *smbios_boot_desc(uint_t);
2107 
2108 extern const char *smbios_cache_assoc_desc(uint_t);
2109 extern const char *smbios_cache_ctype_desc(uint_t);
2110 extern const char *smbios_cache_ctype_name(uint_t);
2111 extern const char *smbios_cache_ecc_desc(uint_t);
2112 extern const char *smbios_cache_flag_desc(uint_t);
2113 extern const char *smbios_cache_flag_name(uint_t);
2114 extern const char *smbios_cache_loc_desc(uint_t);
2115 extern const char *smbios_cache_logical_desc(uint_t);
2116 extern const char *smbios_cache_mode_desc(uint_t);
2117 
2118 extern const char *smbios_chassis_state_desc(uint_t);
2119 extern const char *smbios_chassis_type_desc(uint_t);
2120 
2121 extern const char *smbios_evlog_flag_desc(uint_t);
2122 extern const char *smbios_evlog_flag_name(uint_t);
2123 extern const char *smbios_evlog_format_desc(uint_t);
2124 extern const char *smbios_evlog_method_desc(uint_t);
2125 
2126 extern const char *smbios_fwinfo_ch_name(uint_t);
2127 extern const char *smbios_fwinfo_ch_desc(uint_t);
2128 extern const char *smbios_fwinfo_id_desc(uint_t);
2129 extern const char *smbios_fwinfo_state_desc(uint_t);
2130 extern const char *smbios_fwinfo_vers_desc(uint_t);
2131 
2132 extern const char *smbios_vprobe_loc_desc(uint_t);
2133 extern const char *smbios_vprobe_status_desc(uint_t);
2134 
2135 extern const char *smbios_cooldev_status_desc(uint_t);
2136 extern const char *smbios_cooldev_type_desc(uint_t);
2137 
2138 extern const char *smbios_tprobe_loc_desc(uint_t);
2139 extern const char *smbios_tprobe_status_desc(uint_t);
2140 
2141 extern const char *smbios_iprobe_loc_desc(uint_t);
2142 extern const char *smbios_iprobe_status_desc(uint_t);
2143 
2144 extern const char *smbios_ipmi_flag_name(uint_t);
2145 extern const char *smbios_ipmi_flag_desc(uint_t);
2146 extern const char *smbios_ipmi_type_desc(uint_t);
2147 
2148 extern const char *smbios_powersup_flag_name(uint_t);
2149 extern const char *smbios_powersup_flag_desc(uint_t);
2150 extern const char *smbios_powersup_input_desc(uint_t);
2151 extern const char *smbios_powersup_status_desc(uint_t);
2152 extern const char *smbios_powersup_type_desc(uint_t);
2153 
2154 extern const char *smbios_hwsec_desc(uint_t);
2155 
2156 extern const char *smbios_memarray_loc_desc(uint_t);
2157 extern const char *smbios_memarray_use_desc(uint_t);
2158 extern const char *smbios_memarray_ecc_desc(uint_t);
2159 
2160 extern const char *smbios_memdevice_form_desc(uint_t);
2161 extern const char *smbios_memdevice_type_desc(uint_t);
2162 extern const char *smbios_memdevice_flag_name(uint_t);
2163 extern const char *smbios_memdevice_flag_desc(uint_t);
2164 extern const char *smbios_memdevice_rank_desc(uint_t);
2165 extern const char *smbios_memdevice_memtech_desc(uint_t);
2166 extern const char *smbios_memdevice_op_capab_name(uint_t);
2167 extern const char *smbios_memdevice_op_capab_desc(uint_t);
2168 
2169 extern const char *smbios_onboard_type_desc(uint_t);
2170 extern const char *smbios_onboard_ext_type_desc(uint_t);
2171 
2172 extern const char *smbios_pointdev_iface_desc(uint_t);
2173 extern const char *smbios_pointdev_type_desc(uint_t);
2174 
2175 extern const char *smbios_port_conn_desc(uint_t);
2176 extern const char *smbios_port_type_desc(uint_t);
2177 
2178 extern const char *smbios_processor_family_desc(uint_t);
2179 extern const char *smbios_processor_status_desc(uint_t);
2180 extern const char *smbios_processor_type_desc(uint_t);
2181 extern const char *smbios_processor_upgrade_desc(uint_t);
2182 extern const char *smbios_processor_core_flag_name(uint_t);
2183 extern const char *smbios_processor_core_flag_desc(uint_t);
2184 
2185 extern const char *smbios_processor_info_type_desc(uint_t);
2186 extern const char *smbios_riscv_isa_desc(uint64_t);
2187 extern const char *smbios_riscv_isa_name(uint64_t);
2188 extern const char *smbios_riscv_priv_desc(uint_t);
2189 extern const char *smbios_riscv_priv_name(uint_t);
2190 extern const char *smbios_riscv_width_desc(uint_t);
2191 
2192 extern const char *smbios_slot_type_desc(uint_t);
2193 extern const char *smbios_slot_width_desc(uint_t);
2194 extern const char *smbios_slot_usage_desc(uint_t);
2195 extern const char *smbios_slot_length_desc(uint_t);
2196 extern const char *smbios_slot_ch1_desc(uint_t);
2197 extern const char *smbios_slot_ch1_name(uint_t);
2198 extern const char *smbios_slot_ch2_desc(uint_t);
2199 extern const char *smbios_slot_ch2_name(uint_t);
2200 extern const char *smbios_slot_height_desc(uint_t);
2201 
2202 extern const char *smbios_strprop_id_desc(uint_t);
2203 
2204 extern const char *smbios_type_desc(uint_t);
2205 extern const char *smbios_type_name(uint_t);
2206 
2207 extern const char *smbios_system_wakeup_desc(uint_t);
2208 #endif /* !_KERNEL */
2209 
2210 #ifdef _KERNEL
2211 /*
2212  * For SMBIOS clients within the kernel itself, ksmbios is used to refer to
2213  * the kernel's current snapshot of the SMBIOS, if one exists, and the
2214  * ksmbios_flags tunable is the set of flags for use with smbios_open().
2215  */
2216 extern smbios_hdl_t *ksmbios;
2217 extern int ksmbios_flags;
2218 #endif /* _KERNEL */
2219 
2220 #ifdef	__cplusplus
2221 }
2222 #endif
2223 
2224 #endif	/* _SYS_SMBIOS_H */
2225