1*ac88567aSHyon Kim /* 2*ac88567aSHyon Kim * CDDL HEADER START 3*ac88567aSHyon Kim * 4*ac88567aSHyon Kim * The contents of this file are subject to the terms of the 5*ac88567aSHyon Kim * Common Development and Distribution License (the "License"). 6*ac88567aSHyon Kim * You may not use this file except in compliance with the License. 7*ac88567aSHyon Kim * 8*ac88567aSHyon Kim * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*ac88567aSHyon Kim * or http://www.opensolaris.org/os/licensing. 10*ac88567aSHyon Kim * See the License for the specific language governing permissions 11*ac88567aSHyon Kim * and limitations under the License. 12*ac88567aSHyon Kim * 13*ac88567aSHyon Kim * When distributing Covered Code, include this CDDL HEADER in each 14*ac88567aSHyon Kim * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*ac88567aSHyon Kim * If applicable, add the following below this CDDL HEADER, with the 16*ac88567aSHyon Kim * fields enclosed by brackets "[]" replaced with your own identifying 17*ac88567aSHyon Kim * information: Portions Copyright [yyyy] [name of copyright owner] 18*ac88567aSHyon Kim * 19*ac88567aSHyon Kim * CDDL HEADER END 20*ac88567aSHyon Kim */ 21*ac88567aSHyon Kim 22*ac88567aSHyon Kim /* 23*ac88567aSHyon Kim * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 24*ac88567aSHyon Kim */ 25*ac88567aSHyon Kim 26*ac88567aSHyon Kim #ifndef _SYS_SCSI_GENERIC_SFF_FRAMES_H 27*ac88567aSHyon Kim #define _SYS_SCSI_GENERIC_SFF_FRAMES_H 28*ac88567aSHyon Kim 29*ac88567aSHyon Kim #ifdef __cplusplus 30*ac88567aSHyon Kim extern "C" { 31*ac88567aSHyon Kim #endif 32*ac88567aSHyon Kim 33*ac88567aSHyon Kim #include <sys/sysmacros.h> 34*ac88567aSHyon Kim 35*ac88567aSHyon Kim /* 36*ac88567aSHyon Kim * The definitions of SMP frame formats defined by SFF-8485. 37*ac88567aSHyon Kim * These are NOT compatible with the generic SAS-1 and/or SAS-2 SMP frame 38*ac88567aSHyon Kim * formats, but the function numbers and result codes are defined by SAS-2. 39*ac88567aSHyon Kim */ 40*ac88567aSHyon Kim 41*ac88567aSHyon Kim #pragma pack(1) 42*ac88567aSHyon Kim 43*ac88567aSHyon Kim typedef struct sff_request_frame { 44*ac88567aSHyon Kim uint8_t srf_frame_type; 45*ac88567aSHyon Kim uint8_t srf_function; 46*ac88567aSHyon Kim uint8_t srf_data[1]; 47*ac88567aSHyon Kim } sff_request_frame_t; 48*ac88567aSHyon Kim 49*ac88567aSHyon Kim typedef struct sff_response_frame { 50*ac88567aSHyon Kim uint8_t srf_frame_type; 51*ac88567aSHyon Kim uint8_t srf_function; 52*ac88567aSHyon Kim uint8_t srf_result; 53*ac88567aSHyon Kim uint8_t _reserved1; 54*ac88567aSHyon Kim uint8_t srf_data[1]; 55*ac88567aSHyon Kim } sff_response_frame_t; 56*ac88567aSHyon Kim 57*ac88567aSHyon Kim /* 58*ac88567aSHyon Kim * SFF-8485 8.4.1 GPIO register overview 59*ac88567aSHyon Kim */ 60*ac88567aSHyon Kim typedef enum sff_gpio_reg_type { 61*ac88567aSHyon Kim SFF_GPIO_CFG = 0x00, 62*ac88567aSHyon Kim SFF_GPIO_RX = 0x01, 63*ac88567aSHyon Kim SFF_GPIO_RX_GP = 0x02, 64*ac88567aSHyon Kim SFF_GPIO_TX = 0x03, 65*ac88567aSHyon Kim SFF_GPIO_TX_GP = 0x04 66*ac88567aSHyon Kim } sff_gpio_reg_type_t; 67*ac88567aSHyon Kim 68*ac88567aSHyon Kim /* 69*ac88567aSHyon Kim * SFF-8485 8.4.2.1 GPIO configuration registers overview 70*ac88567aSHyon Kim */ 71*ac88567aSHyon Kim typedef enum sff_gpio_cfg_reg_index { 72*ac88567aSHyon Kim SFF_GPIO_CFG_0 = 0x00, 73*ac88567aSHyon Kim SFF_GPIO_CFG_1 = 0x01 74*ac88567aSHyon Kim } sff_gpio_cfg_reg_index_t; 75*ac88567aSHyon Kim 76*ac88567aSHyon Kim /* 77*ac88567aSHyon Kim * SFF-8485 8.4.2.2 GPIO_CFG[0] register 78*ac88567aSHyon Kim */ 79*ac88567aSHyon Kim typedef struct sff_gpio_cfg_reg_0 { 80*ac88567aSHyon Kim uint8_t _reserved1; 81*ac88567aSHyon Kim DECL_BITFIELD2( 82*ac88567aSHyon Kim sgcr0_version :4, 83*ac88567aSHyon Kim _reserved2 :4); 84*ac88567aSHyon Kim DECL_BITFIELD3( 85*ac88567aSHyon Kim sgcr0_gp_register_count :4, 86*ac88567aSHyon Kim sgcr0_cfg_register_count :3, 87*ac88567aSHyon Kim sgcr0_gpio_enable :1); 88*ac88567aSHyon Kim uint8_t sgcr0_supported_drive_count; 89*ac88567aSHyon Kim } sff_gpio_cfg_reg_0_t; 90*ac88567aSHyon Kim 91*ac88567aSHyon Kim /* 92*ac88567aSHyon Kim * SFF-8485 8.4.2.3 GPIO_CFG[1] register 93*ac88567aSHyon Kim */ 94*ac88567aSHyon Kim typedef struct sff_gpio_cfg_reg_1 { 95*ac88567aSHyon Kim uint8_t _reserved1; 96*ac88567aSHyon Kim DECL_BITFIELD2( 97*ac88567aSHyon Kim sgcr1_blink_gen_rate_a :4, 98*ac88567aSHyon Kim sgcr1_blink_gen_rate_b :4); 99*ac88567aSHyon Kim DECL_BITFIELD2( 100*ac88567aSHyon Kim sgcr1_max_activity_on :4, 101*ac88567aSHyon Kim sgcr1_force_activity_off :4); 102*ac88567aSHyon Kim DECL_BITFIELD2( 103*ac88567aSHyon Kim sgcr1_stretch_activity_on :4, 104*ac88567aSHyon Kim sgcr1_stretch_activity_off :4); 105*ac88567aSHyon Kim } sff_gpio_cfg_reg_1_t; 106*ac88567aSHyon Kim 107*ac88567aSHyon Kim /* 108*ac88567aSHyon Kim * SFF-8485 8.4.3 GPIO receive registers 109*ac88567aSHyon Kim */ 110*ac88567aSHyon Kim typedef struct sff_gpio_rx_reg { 111*ac88567aSHyon Kim DECL_BITFIELD2( 112*ac88567aSHyon Kim sgrr_drive_3_gpio_input :3, 113*ac88567aSHyon Kim _reserved1 :5); 114*ac88567aSHyon Kim DECL_BITFIELD2( 115*ac88567aSHyon Kim sgrr_drive_2_gpio_input :3, 116*ac88567aSHyon Kim _reserved1 :5); 117*ac88567aSHyon Kim DECL_BITFIELD2( 118*ac88567aSHyon Kim sgrr_drive_1_gpio_input :3, 119*ac88567aSHyon Kim _reserved1 :5); 120*ac88567aSHyon Kim DECL_BITFIELD2( 121*ac88567aSHyon Kim sgrr_drive_0_gpio_input :3, 122*ac88567aSHyon Kim _reserved1 :5); 123*ac88567aSHyon Kim } sff_gpio_rx_reg_t; 124*ac88567aSHyon Kim 125*ac88567aSHyon Kim /* 126*ac88567aSHyon Kim * SFF-8485 8.4.4 GPIO transmit registers 127*ac88567aSHyon Kim */ 128*ac88567aSHyon Kim typedef enum sff_drive_error { 129*ac88567aSHyon Kim SFF_DRIVE_ERR_DISABLE = 0x0, 130*ac88567aSHyon Kim SFF_DRIVE_ERR_ENABLE = 0x1, 131*ac88567aSHyon Kim SFF_DRIVE_ERR_BLINK_A_1_0 = 0x2, 132*ac88567aSHyon Kim SFF_DRIVE_ERR_BLINK_A_0_1 = 0x3, 133*ac88567aSHyon Kim SFF_DRIVE_ERR_ENABLE_4 = 0x4, 134*ac88567aSHyon Kim SFF_DRIVE_ERR_ENABLE_5 = 0x5, 135*ac88567aSHyon Kim SFF_DRIVE_ERR_BLINK_B_1_0 = 0x6, 136*ac88567aSHyon Kim SFF_DRIVE_ERR_BLINK_B_0_1 = 0x7 137*ac88567aSHyon Kim } sff_drive_error_t; 138*ac88567aSHyon Kim 139*ac88567aSHyon Kim typedef enum sff_drive_locate { 140*ac88567aSHyon Kim SFF_DRIVE_LOC_DISABLE = 0x0, 141*ac88567aSHyon Kim SFF_DRIVE_LOC_ENABLE = 0x1, 142*ac88567aSHyon Kim SFF_DRIVE_BLINK_A_1_0 = 0x2, 143*ac88567aSHyon Kim SFF_DRIVE_BLINK_A_0_1 = 0x3 144*ac88567aSHyon Kim } sff_drive_locate_t; 145*ac88567aSHyon Kim 146*ac88567aSHyon Kim typedef enum sff_drive_activity { 147*ac88567aSHyon Kim SFF_DRIVE_ACT_DISABLE = 0x0, 148*ac88567aSHyon Kim SFF_DRIVE_ACT_ENABLE = 0x1, 149*ac88567aSHyon Kim SFF_DRIVE_ACT_BLINK_A_1_0 = 0x2, 150*ac88567aSHyon Kim SFF_DRIVE_ACT_BLINK_A_0_1 = 0x3, 151*ac88567aSHyon Kim SFF_DRIVE_ACT_ENABLE_END = 0x4, 152*ac88567aSHyon Kim SFF_DRIVE_ACT_ENABLE_START = 0x5, 153*ac88567aSHyon Kim SFF_DRIVE_ACT_BLINK_B_1_0 = 0x6, 154*ac88567aSHyon Kim SFF_DRIVE_ACT_BLINK_B_0_1 = 0x7 155*ac88567aSHyon Kim } sff_drive_activity_t; 156*ac88567aSHyon Kim 157*ac88567aSHyon Kim typedef struct sff_gpio_tx_reg { 158*ac88567aSHyon Kim DECL_BITFIELD3( 159*ac88567aSHyon Kim sgtr_drive_3_error :3, /* sff_drive_error_t */ 160*ac88567aSHyon Kim sgtr_drive_3_locate :2, /* sff_drive_locate_t */ 161*ac88567aSHyon Kim sgtr_drive_3_activity :3); /* sff_drive_activity_t */ 162*ac88567aSHyon Kim DECL_BITFIELD3( 163*ac88567aSHyon Kim sgtr_drive_2_error :3, /* sff_drive_error_t */ 164*ac88567aSHyon Kim sgtr_drive_2_locate :2, /* sff_drive_locate_t */ 165*ac88567aSHyon Kim sgtr_drive_2_activity :3); /* sff_drive_activity_t */ 166*ac88567aSHyon Kim DECL_BITFIELD3( 167*ac88567aSHyon Kim sgtr_drive_1_error :3, /* sff_drive_error_t */ 168*ac88567aSHyon Kim sgtr_drive_1_locate :2, /* sff_drive_locate_t */ 169*ac88567aSHyon Kim sgtr_drive_1_activity :3); /* sff_drive_activity_t */ 170*ac88567aSHyon Kim DECL_BITFIELD3( 171*ac88567aSHyon Kim sgtr_drive_0_error :3, /* sff_drive_error_t */ 172*ac88567aSHyon Kim sgtr_drive_0_locate :2, /* sff_drive_locate_t */ 173*ac88567aSHyon Kim sgtr_drive_0_activity :3); /* sff_drive_activity_t */ 174*ac88567aSHyon Kim } sff_gpio_tx_reg_t; 175*ac88567aSHyon Kim 176*ac88567aSHyon Kim /* 177*ac88567aSHyon Kim * SFF-8485 8.4.5.1 GPIO general purpose receive registers overview 178*ac88567aSHyon Kim */ 179*ac88567aSHyon Kim typedef enum sff_gpio_rx_gp_reg_index { 180*ac88567aSHyon Kim SFF_GPIO_REG_RX_GP_CFG = 0x00, 181*ac88567aSHyon Kim SFF_GPIO_REG_RX_GP_1 = 0x01 /* ... */ 182*ac88567aSHyon Kim } sff_gpio_rx_gp_reg_index_t; 183*ac88567aSHyon Kim 184*ac88567aSHyon Kim /* 185*ac88567aSHyon Kim * SFF-8485 8.4.5.2 GPIO_RX_GP_CFG register 186*ac88567aSHyon Kim */ 187*ac88567aSHyon Kim typedef struct sff_gpio_rx_gp_cfg_reg { 188*ac88567aSHyon Kim uint8_t _reserved1[2]; 189*ac88567aSHyon Kim uint8_t sgrgcr_count; 190*ac88567aSHyon Kim uint8_t _reserved2; 191*ac88567aSHyon Kim } sff_gpio_rx_gp_cfg_reg_t; 192*ac88567aSHyon Kim 193*ac88567aSHyon Kim /* 194*ac88567aSHyon Kim * SFF-8485 8.4.5.3 GPIO_RX_GP[1..n] register 195*ac88567aSHyon Kim */ 196*ac88567aSHyon Kim typedef uint8_t sff_gpio_rx_gp_reg_t[4]; /* little-endian */ 197*ac88567aSHyon Kim 198*ac88567aSHyon Kim /* 199*ac88567aSHyon Kim * SFF-8485 8.4.6.1 GPIO general purpose transmit registers overview 200*ac88567aSHyon Kim */ 201*ac88567aSHyon Kim typedef enum sff_gpio_tx_gp_reg_index { 202*ac88567aSHyon Kim SFF_GPIO_REG_TX_GP_CFG = 0x00, 203*ac88567aSHyon Kim SFF_GPIO_REG_TX_GP_1 = 0x01 /* ... */ 204*ac88567aSHyon Kim } sff_gpio_tx_gp_reg_index_t; 205*ac88567aSHyon Kim 206*ac88567aSHyon Kim /* 207*ac88567aSHyon Kim * SFF-8485 8.4.6.2 GPIO_TX_GP_CFG register 208*ac88567aSHyon Kim */ 209*ac88567aSHyon Kim typedef struct sff_gpio_tx_cfg_reg { 210*ac88567aSHyon Kim uint8_t _reserved1[2]; 211*ac88567aSHyon Kim uint8_t sgtcr_count; 212*ac88567aSHyon Kim DECL_BITFIELD5( 213*ac88567aSHyon Kim sgtcr_sload_0 :1, 214*ac88567aSHyon Kim sgtcr_sload_1 :1, 215*ac88567aSHyon Kim sgtcr_sload_2 :1, 216*ac88567aSHyon Kim sgtcr_sload_3 :1, 217*ac88567aSHyon Kim _reserved2 :4); 218*ac88567aSHyon Kim } sff_gpio_tx_cfg_reg_t; 219*ac88567aSHyon Kim 220*ac88567aSHyon Kim /* 221*ac88567aSHyon Kim * SFF-8485 8.4.6.3 GPIO_TX_GP[1..n] registers 222*ac88567aSHyon Kim */ 223*ac88567aSHyon Kim typedef uint8_t sff_gpio_tx_gp_reg_t[4]; /* little-endian */ 224*ac88567aSHyon Kim 225*ac88567aSHyon Kim /* 226*ac88567aSHyon Kim * SFF-8485 8.2.2 READ GPIO REGISTER request 227*ac88567aSHyon Kim */ 228*ac88567aSHyon Kim typedef struct sff_read_gpio_req { 229*ac88567aSHyon Kim uint8_t srgr_register_type; 230*ac88567aSHyon Kim uint8_t srgr_register_index; 231*ac88567aSHyon Kim uint8_t srgr_register_count; 232*ac88567aSHyon Kim uint8_t _reserved1[3]; 233*ac88567aSHyon Kim } sff_read_gpio_req_t; 234*ac88567aSHyon Kim 235*ac88567aSHyon Kim typedef uint8_t sff_gpio_reg_t[4]; 236*ac88567aSHyon Kim 237*ac88567aSHyon Kim /* 238*ac88567aSHyon Kim * SFF-8485 8.2.2 READ GPIO REGISTER response 239*ac88567aSHyon Kim */ 240*ac88567aSHyon Kim typedef struct sff_read_gpio_resp { 241*ac88567aSHyon Kim sff_gpio_reg_t srgr_regs[1]; 242*ac88567aSHyon Kim } smp_response_frame_t; 243*ac88567aSHyon Kim 244*ac88567aSHyon Kim /* 245*ac88567aSHyon Kim * SFF-8485 8.2.3 WRITE GPIO REGISTER request (no additional response) 246*ac88567aSHyon Kim */ 247*ac88567aSHyon Kim typedef struct sff_write_gpio_req { 248*ac88567aSHyon Kim uint8_t swgr_register_type; 249*ac88567aSHyon Kim uint8_t swgr_register_index; 250*ac88567aSHyon Kim uint8_t swgr_register_count; 251*ac88567aSHyon Kim uint8_t _reserved1[3]; 252*ac88567aSHyon Kim sff_gpio_reg_t swgr_regs[1]; 253*ac88567aSHyon Kim } sff_write_gpio_req_t; 254*ac88567aSHyon Kim 255*ac88567aSHyon Kim #pragma pack() 256*ac88567aSHyon Kim 257*ac88567aSHyon Kim #ifdef __cplusplus 258*ac88567aSHyon Kim } 259*ac88567aSHyon Kim #endif 260*ac88567aSHyon Kim 261*ac88567aSHyon Kim #endif /* _SYS_SCSI_GENERIC_SFF_FRAMES_H */ 262