14c06356bSdh /* 24c06356bSdh * CDDL HEADER START 34c06356bSdh * 44c06356bSdh * The contents of this file are subject to the terms of the 54c06356bSdh * Common Development and Distribution License (the "License"). 64c06356bSdh * You may not use this file except in compliance with the License. 74c06356bSdh * 84c06356bSdh * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 94c06356bSdh * or http://www.opensolaris.org/os/licensing. 104c06356bSdh * See the License for the specific language governing permissions 114c06356bSdh * and limitations under the License. 124c06356bSdh * 134c06356bSdh * When distributing Covered Code, include this CDDL HEADER in each 144c06356bSdh * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 154c06356bSdh * If applicable, add the following below this CDDL HEADER, with the 164c06356bSdh * fields enclosed by brackets "[]" replaced with your own identifying 174c06356bSdh * information: Portions Copyright [yyyy] [name of copyright owner] 184c06356bSdh * 194c06356bSdh * CDDL HEADER END 204c06356bSdh * 214c06356bSdh * 22*c280a92bSDavid Hollister * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 234c06356bSdh * Use is subject to license terms. 244c06356bSdh */ 254c06356bSdh /* 264c06356bSdh * PMC 8x6G Message Passing Interface Definitions 274c06356bSdh */ 284c06356bSdh #ifndef _PMCS_MPI_H 294c06356bSdh #define _PMCS_MPI_H 304c06356bSdh #ifdef __cplusplus 314c06356bSdh extern "C" { 324c06356bSdh #endif 334c06356bSdh 344c06356bSdh #define PMCS_DWRD(x) (x << 2) 354c06356bSdh 364c06356bSdh /* 374c06356bSdh * MPI Configuration Table Offsets 384c06356bSdh */ 394c06356bSdh #define PMCS_MPI_AS PMCS_DWRD(0) /* ASCII Signature */ 404c06356bSdh #define PMCS_SIGNATURE 0x53434D50 414c06356bSdh 424c06356bSdh #define PMCS_MPI_IR PMCS_DWRD(1) /* Interface Revision */ 434c06356bSdh #define PMCS_MPI_REVISION1 1 444c06356bSdh 454c06356bSdh #define PMCS_MPI_FW PMCS_DWRD(2) /* Firmware Version */ 464c06356bSdh #define PMCS_FW_TYPE(hwp) (hwp->fw & 0xf) 474c06356bSdh #define PMCS_FW_TYPE_RELEASED 0 484c06356bSdh #define PMCS_FW_TYPE_DEVELOPMENT 1 494c06356bSdh #define PMCS_FW_TYPE_ALPHA 2 504c06356bSdh #define PMCS_FW_TYPE_BETA 3 514c06356bSdh #define PMCS_FW_VARIANT(hwp) ((hwp->fw >> 4) & 0xf) 524c06356bSdh #define PMCS_FW_MAJOR(hwp) ((hwp->fw >> 24) & 0xff) 534c06356bSdh #define PMCS_FW_MINOR(hwp) ((hwp->fw >> 16) & 0xff) 544c06356bSdh #define PMCS_FW_MICRO(hwp) ((hwp->fw >> 8) & 0xff) 554c06356bSdh #define PMCS_FW_REV(hwp) ((hwp->fw >> 8) & 0xffffff) 564c06356bSdh #define PMCS_FW_VERSION(maj, min, mic) ((maj << 16)|(min << 8)|mic) 574c06356bSdh 584c06356bSdh #define PMCS_MPI_MOIO PMCS_DWRD(3) /* Maximum # of outstandiong I/Os */ 594c06356bSdh #define PMCS_MPI_INFO0 PMCS_DWRD(4) /* Maximum S/G Elem, Max Dev Handle */ 604c06356bSdh #define PMCS_MSGL(x) (x & 0xffff) 614c06356bSdh #define PMCS_MD(x) ((x >> 16) & 0xffff) 624c06356bSdh 634c06356bSdh #define PMCS_MPI_INFO1 PMCS_DWRD(5) /* Info #0 */ 644c06356bSdh 654c06356bSdh #define PMCS_MNIQ(x) (x & 0xff) /* Max # of Inbound Queues */ 664c06356bSdh #define PMCS_MNOQ(x) ((x >> 8) & 0xff) /* Max # of Outbound Queues */ 674c06356bSdh #define PMCS_HPIQ(x) ((x >> 16) & 0x1) /* High Pri Queue Supported */ 684c06356bSdh #define PMCS_ICS(x) ((x >> 18) & 0x1) /* Interrupt Coalescing */ 694c06356bSdh #define PMCS_NPHY(x) ((x >> 19) & 0x3f) /* Numbers of PHYs */ 704c06356bSdh #define PMCS_SASREV(x) ((x >> 25) & 0x7) /* SAS Revision Specification */ 714c06356bSdh 724c06356bSdh #define PMCS_MPI_GSTO PMCS_DWRD(6) /* General Status Table Offset */ 734c06356bSdh #define PMCS_MPI_IQCTO PMCS_DWRD(7) /* Inbound Queue Config Table Offset */ 744c06356bSdh #define PMCS_MPI_OQCTO PMCS_DWRD(8) /* Outbound Queue Config Table Offset */ 754c06356bSdh 764c06356bSdh #define PMCS_MPI_INFO2 PMCS_DWRD(9) /* Info #1 */ 774c06356bSdh 784c06356bSdh #define IQ_NORMAL_PRI_DEPTH_SHIFT 0 794c06356bSdh #define IQ_NORMAL_PRI_DEPTH_MASK 0xff 804c06356bSdh #define IQ_HIPRI_PRI_DEPTH_SHIFT 8 814c06356bSdh #define IQ_HIPRI_PRI_DEPTH_MASK 0xff00 824c06356bSdh #define GENERAL_EVENT_OQ_SHIFT 16 834c06356bSdh #define GENERAL_EVENT_OQ_MASK 0xff0000 844c06356bSdh #define DEVICE_HANDLE_REMOVED_SHIFT 24 854c06356bSdh #define DEVICE_HANDLE_REMOVED_MASK 0xff000000ul 864c06356bSdh 874c06356bSdh #define PMCS_MPI_EVQS PMCS_DWRD(0xA) /* SAS Event Queues */ 884c06356bSdh #define PMCS_MPI_EVQSET(pwp, oq, phy) { \ 894c06356bSdh uint32_t woff = phy / 4; \ 904c06356bSdh uint32_t shf = (phy % 4) * 8; \ 914c06356bSdh uint32_t tmp = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_EVQS + (woff << 2)); \ 924c06356bSdh tmp &= ~(0xff << shf); \ 934c06356bSdh tmp |= ((oq & 0xff) << shf); \ 944c06356bSdh pmcs_wr_mpi_tbl(pwp, PMCS_MPI_EVQS + (woff << 2), tmp); \ 954c06356bSdh } 964c06356bSdh 974c06356bSdh #define PMCS_MPI_SNCQ PMCS_DWRD(0xC) /* Sata NCQ Notification Queues */ 984c06356bSdh #define PMCS_MPI_NCQSET(pwp, oq, phy) { \ 994c06356bSdh uint32_t woff = phy / 4; \ 1004c06356bSdh uint32_t shf = (phy % 4) * 8; \ 1014c06356bSdh uint32_t tmp = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_SNCQ + (woff << 2)); \ 1024c06356bSdh tmp &= ~(0xff << shf); \ 1034c06356bSdh tmp |= ((oq & 0xff) << shf); \ 1044c06356bSdh pmcs_wr_mpi_tbl(pwp, PMCS_MPI_SNCQ + (woff << 2), tmp); \ 1054c06356bSdh } 1064c06356bSdh 1074c06356bSdh /* 1084c06356bSdh * I_T Nexus Target Event Notification Queue 1094c06356bSdh */ 1104c06356bSdh #define PMCS_MPI_IT_NTENQ PMCS_DWRD(0xE) 1114c06356bSdh 1124c06356bSdh /* 1134c06356bSdh * SSP Target Event Notification Queue 1144c06356bSdh */ 1154c06356bSdh #define PMCS_MPI_SSP_TENQ PMCS_DWRD(0x10) 1164c06356bSdh 1174c06356bSdh /* 118*c280a92bSDavid Hollister * I/O Abort Delay 1194c06356bSdh */ 120*c280a92bSDavid Hollister #define PMCS_MPI_IOABTDLY PMCS_DWRD(0x12) 121*c280a92bSDavid Hollister 122*c280a92bSDavid Hollister /* 123*c280a92bSDavid Hollister * Customization Setting 124*c280a92bSDavid Hollister */ 125*c280a92bSDavid Hollister #define PMCS_MPI_CUSTSET PMCS_DWRD(0x13) 126*c280a92bSDavid Hollister 127*c280a92bSDavid Hollister #define PMCS_MPI_CUST_HW_RSC_BSY_ALT 0x1 /* Bit 0 */ 128*c280a92bSDavid Hollister #define PMCS_MPI_CUST_ABORT_ITNL 0x2 /* Bit 1 */ 1294c06356bSdh 1304c06356bSdh /* 1314c06356bSdh * This specifies a log buffer in host memory for the MSGU. 1324c06356bSdh */ 1334c06356bSdh #define PMCS_MPI_MELBAH PMCS_DWRD(0x14) /* MSGU Log Buffer high 32 bits */ 1344c06356bSdh #define PMCS_MPI_MELBAL PMCS_DWRD(0x15) /* MSGU Log Buffer low 32 bits */ 1354c06356bSdh #define PMCS_MPI_MELBS PMCS_DWRD(0x16) /* size in bytes of MSGU log buffer */ 1364c06356bSdh #define PMCS_MPI_MELSEV PMCS_DWRD(0x17) /* Log Severity */ 1374c06356bSdh 1384c06356bSdh /* 1394c06356bSdh * This specifies a log buffer in host memory for the IOP. 1404c06356bSdh */ 1414c06356bSdh #define PMCS_MPI_IELBAH PMCS_DWRD(0x18) /* IOP Log Buffer high 32 bits */ 1424c06356bSdh #define PMCS_MPI_IELBAL PMCS_DWRD(0x19) /* IOP Log Buffer low 32 bits */ 1434c06356bSdh #define PMCS_MPI_IELBS PMCS_DWRD(0x1A) /* size in bytes of IOP log buffer */ 1444c06356bSdh #define PMCS_MPI_IELSEV PMCS_DWRD(0x1B) /* Log Severity */ 1454c06356bSdh 1464c06356bSdh /* 1474c06356bSdh * Fatal Error Handling 1484c06356bSdh */ 1494c06356bSdh #define PMCS_MPI_FERR PMCS_DWRD(0x1C) 1504c06356bSdh #define PMCS_FERRIE 0x1 /* Fatal Err Interrupt Enable */ 151*c280a92bSDavid Hollister #define PMCS_PCAD64 0x2 /* PI/CI addresses are 64-bit */ 1524c06356bSdh #define PMCS_FERIV_MASK 0xff00 /* Fatal Err Interrupt Mask */ 1534c06356bSdh #define PMCS_FERIV_SHIFT 8 /* Fatal Err Interrupt Shift */ 1544c06356bSdh 1554c06356bSdh #define PMCS_MPI_IRAE 0x20000 /* Interrupt Reassertion Enable */ 1564c06356bSdh #define PMCS_MPI_IRAU 0x40000 /* Interrupt Reassertion Unit */ 1574c06356bSdh #define PMCS_MPI_IRAD_MASK 0xfff80000 /* Reassertion Delay Mask */ 1584c06356bSdh 1594c06356bSdh #define PMCS_FERDOMSGU PMCS_DWRD(0x1D) 1604c06356bSdh #define PMCS_FERDLMSGU PMCS_DWRD(0x1E) 1614c06356bSdh #define PMCS_FERDOIOP PMCS_DWRD(0x1F) 1624c06356bSdh #define PMCS_FERDLIOP PMCS_DWRD(0x20) 1634c06356bSdh 1644c06356bSdh /* 1654c06356bSdh * MPI GST Table Offsets 1664c06356bSdh */ 1674c06356bSdh 1684c06356bSdh #define PMCS_GST_BASE 0 1694c06356bSdh #define PMCS_GST_IQFRZ0 (PMCS_GST_BASE + PMCS_DWRD(1)) 1704c06356bSdh #define PMCS_GST_IQFRZ1 (PMCS_GST_BASE + PMCS_DWRD(2)) 1714c06356bSdh #define PMCS_GST_MSGU_TICK (PMCS_GST_BASE + PMCS_DWRD(3)) 1724c06356bSdh #define PMCS_GST_IOP_TICK (PMCS_GST_BASE + PMCS_DWRD(4)) 1734c06356bSdh #define PMCS_GST_PHY_INFO(x) (PMCS_GST_BASE + PMCS_DWRD(0x6) + PMCS_DWRD(x)) 1744c06356bSdh #define PMCS_GST_RERR_BASE (PMCS_GST_BASE + PMCS_DWRD(0x11)) 1754c06356bSdh #define PMCS_GST_RERR_INFO(x) (PMCS_GST_RERR_BASE + PMCS_DWRD(x)) 1764c06356bSdh 1774c06356bSdh #define PMCS_MPI_S(x) ((x) & 0x7) 1784c06356bSdh #define PMCS_QF(x) (((x) >> 3) & 0x1) 1794c06356bSdh #define PMCS_GSTLEN(x) (((x) >> 4) & 0x3fff) 1804c06356bSdh #define PMCS_HMI_ERR(x) (((x) >> 16) & 0xffff) 1814c06356bSdh 1824c06356bSdh #define PMCS_MPI_STATE_NIL 0 1834c06356bSdh #define PMCS_MPI_STATE_INIT 1 1844c06356bSdh #define PMCS_MPI_STATE_DEINIT 2 1854c06356bSdh #define PMCS_MPI_STATE_ERR 3 1864c06356bSdh 1874c06356bSdh /* 1884c06356bSdh * MPI Inbound Queue Configuration Table Offsets 1894c06356bSdh * 1904c06356bSdh * Each Inbound Queue configuration area consumes 8 DWORDS (32 bit words), 1914c06356bSdh * or 32 bytes. 1924c06356bSdh */ 1934c06356bSdh #define PMCS_IQC_PARMX(x) ((x) << 5) 1944c06356bSdh #define PMCS_IQBAHX(x) (((x) << 5) + 4) 1954c06356bSdh #define PMCS_IQBALX(x) (((x) << 5) + 8) 1964c06356bSdh #define PMCS_IQCIBAHX(x) (((x) << 5) + 12) 1974c06356bSdh #define PMCS_IQCIBALX(x) (((x) << 5) + 16) 1984c06356bSdh #define PMCS_IQPIBARX(x) (((x) << 5) + 20) 1994c06356bSdh #define PMCS_IQPIOFFX(x) (((x) << 5) + 24) 2004c06356bSdh #define PMCS_IQDX(x) ((x) & 0xffff) 2014c06356bSdh #define PMCS_IQESX(x) (((x) >> 16) & 0x3fff) 2024c06356bSdh #define PMCS_IQPX(x) (((x) >> 30) & 0x3) 2034c06356bSdh 2044c06356bSdh /* 2054c06356bSdh * MPI Outbound Queue Configuration Table Offsets 2064c06356bSdh * 2074c06356bSdh * Each Outbound Queue configuration area consumes 9 DWORDS (32 bit words), 2084c06356bSdh * or 36 bytes. 2094c06356bSdh */ 2104c06356bSdh #define PMCS_OQC_PARMX(x) (x * 36) 2114c06356bSdh #define PMCS_OQBAHX(x) ((x * 36) + 4) 2124c06356bSdh #define PMCS_OQBALX(x) ((x * 36) + 8) 2134c06356bSdh #define PMCS_OQPIBAHX(x) ((x * 36) + 12) 2144c06356bSdh #define PMCS_OQPIBALX(x) ((x * 36) + 16) 2154c06356bSdh #define PMCS_OQCIBARX(x) ((x * 36) + 20) 2164c06356bSdh #define PMCS_OQCIOFFX(x) ((x * 36) + 24) 2174c06356bSdh #define PMCS_OQIPARM(x) ((x * 36) + 28) 2184c06356bSdh #define PMCS_OQDICX(x) ((x * 36) + 32) 2194c06356bSdh 2204c06356bSdh #define PMCS_OQDX(x) ((x) & 0xffff) 2214c06356bSdh #define PMCS_OQESX(x) (((x) >> 16) & 0x3fff) 2224c06356bSdh #define PMCS_OQICT(x) ((x) & 0xffff) 2234c06356bSdh #define PMCS_OQICC(x) (((x) >> 16) & 0xff) 2244c06356bSdh #define PMCS_OQIV(x) (((x) >> 24) & 0xff) 2254c06356bSdh 2264c06356bSdh #define OQIEX (1 << 30) 2274c06356bSdh 2284c06356bSdh #ifdef __cplusplus 2294c06356bSdh } 2304c06356bSdh #endif 2314c06356bSdh #endif /* _PMCS_MPI_H */ 232