1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * This file is the principle header file for the PMCS driver 27 */ 28 #ifndef _PMCS_H 29 #define _PMCS_H 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 #include <sys/cpuvar.h> 36 #include <sys/ddi.h> 37 #include <sys/sunddi.h> 38 #include <sys/modctl.h> 39 #include <sys/pci.h> 40 #include <sys/pcie.h> 41 #include <sys/isa_defs.h> 42 #include <sys/sunmdi.h> 43 #include <sys/mdi_impldefs.h> 44 #include <sys/scsi/scsi.h> 45 #include <sys/scsi/impl/scsi_reset_notify.h> 46 #include <sys/scsi/impl/scsi_sas.h> 47 #include <sys/scsi/impl/smp_transport.h> 48 #include <sys/scsi/generic/sas.h> 49 #include <sys/scsi/generic/smp_frames.h> 50 #include <sys/atomic.h> 51 #include <sys/byteorder.h> 52 #include <sys/sysmacros.h> 53 #include <sys/bitmap.h> 54 #include <sys/queue.h> 55 #include <sys/sdt.h> 56 #include <sys/ddifm.h> 57 #include <sys/fm/protocol.h> 58 #include <sys/fm/util.h> 59 #include <sys/fm/io/ddi.h> 60 #include <sys/scsi/impl/spc3_types.h> 61 62 typedef struct pmcs_hw pmcs_hw_t; 63 typedef struct pmcs_iport pmcs_iport_t; 64 typedef struct pmcs_phy pmcs_phy_t; 65 typedef struct lsas_cmd lsas_cmd_t; 66 typedef struct lsas_result lsas_result_t; 67 typedef struct lsata_cmd lsata_cmd_t; 68 typedef struct lsata_result lsata_result_t; 69 typedef struct pmcwork pmcwork_t; 70 typedef struct pmcs_cmd pmcs_cmd_t; 71 typedef struct pmcs_xscsi pmcs_xscsi_t; 72 typedef struct pmcs_lun pmcs_lun_t; 73 typedef struct pmcs_chunk pmcs_chunk_t; 74 75 #include <sys/scsi/adapters/pmcs/pmcs_param.h> 76 #include <sys/scsi/adapters/pmcs/pmcs_reg.h> 77 #include <sys/scsi/adapters/pmcs/pmcs_mpi.h> 78 #include <sys/scsi/adapters/pmcs/pmcs_iomb.h> 79 #include <sys/scsi/adapters/pmcs/pmcs_sgl.h> 80 81 #include <sys/scsi/adapters/pmcs/ata.h> 82 #include <sys/scsi/adapters/pmcs/pmcs_def.h> 83 #include <sys/scsi/adapters/pmcs/pmcs_proto.h> 84 #include <sys/scsi/adapters/pmcs/pmcs_scsa.h> 85 #include <sys/scsi/adapters/pmcs/pmcs_smhba.h> 86 87 #define PMCS_MAX_UA_SIZE 32 88 89 struct pmcs_xscsi { 90 uint32_t 91 ca : 1, /* SATA specific */ 92 ncq : 1, /* SATA specific */ 93 pio : 1, /* SATA specific */ 94 special_needed : 1, /* SATA specific */ 95 special_running : 1, /* SATA specific */ 96 reset_success : 1, /* last reset ok */ 97 reset_wait : 1, /* wait for reset */ 98 resetting : 1, /* now resetting */ 99 recover_wait : 1, /* wait for recovery */ 100 recovering : 1, /* now recovering */ 101 event_recovery : 1, /* event recovery */ 102 draining : 1, 103 new : 1, 104 assigned : 1, 105 dev_gone : 1, 106 phy_addressable : 1, /* Direct attach SATA */ 107 dev_state : 4; 108 uint16_t maxdepth; 109 uint16_t qdepth; 110 uint16_t actv_cnt; /* Pkts ON CHIP */ 111 uint16_t actv_pkts; /* Pkts in driver */ 112 uint16_t target_num; 113 /* statlock protects both target stats and the special queue (sq) */ 114 kmutex_t statlock; 115 int32_t ref_count; 116 dev_info_t *dip; /* Solaris device dip */ 117 pmcs_phy_t *phy; 118 STAILQ_HEAD(wqh, pmcs_cmd) wq; 119 pmcs_cmd_t *wq_recovery_tail; /* See below */ 120 kmutex_t wqlock; 121 STAILQ_HEAD(aqh, pmcs_cmd) aq; 122 kmutex_t aqlock; 123 STAILQ_HEAD(sqh, pmcs_cmd) sq; /* SATA specific */ 124 uint32_t tagmap; /* SATA specific */ 125 pmcs_hw_t *pwp; 126 ddi_soft_state_bystr *lun_sstate; 127 uint64_t capacity; /* SATA specific */ 128 char unit_address[PMCS_MAX_UA_SIZE]; 129 kcondvar_t reset_cv; 130 kcondvar_t abort_cv; 131 char *ua; 132 pmcs_dtype_t dtype; 133 list_t lun_list; /* list of LUNs */ 134 struct smp_device *smpd; /* Ptr to smp_device */ 135 }; 136 137 /* 138 * wq_recovery_tail in the pmcs_xscsi structure is a pointer to a command in 139 * the wait queue (wq). That pointer is the last command in the wait queue 140 * that needs to be reissued after device state recovery is complete. Commands 141 * that need to be retried are reinserted into the wq after wq_recovery_tail 142 * to maintain the order in which the commands were originally submitted. 143 */ 144 145 #define PMCS_INVALID_TARGET_NUM (uint16_t)-1 146 147 #define PMCS_TGT_WAIT_QUEUE 0x01 148 #define PMCS_TGT_ACTIVE_QUEUE 0x02 149 #define PMCS_TGT_SPECIAL_QUEUE 0x04 150 #define PMCS_TGT_ALL_QUEUES 0xff 151 152 /* 153 * LUN representation. Just a LUN (number) and pointer to the target 154 * structure (pmcs_xscsi). 155 */ 156 157 struct pmcs_lun { 158 list_node_t lun_list_next; 159 pmcs_xscsi_t *target; 160 struct scsi_device *sd; 161 uint64_t lun_num; /* lun64 */ 162 scsi_lun_t scsi_lun; /* Wire format */ 163 char unit_address[PMCS_MAX_UA_SIZE]; 164 }; 165 166 /* 167 * Interrupt coalescing values 168 */ 169 #define PMCS_MAX_IO_COMPS_PER_INTR 12 170 #define PMCS_MAX_IO_COMPS_HIWAT_SHIFT 6 171 #define PMCS_MAX_IO_COMPS_LOWAT_SHIFT 10 172 #define PMCS_QUANTUM_TIME_USECS (1000000 / 10) /* 1/10th sec. */ 173 #define PMCS_MAX_COAL_TIMER 0x200 /* Don't set > than this */ 174 #define PMCS_MAX_CQ_THREADS 4 175 #define PMCS_COAL_TIMER_GRAN 2 /* Go up/down by 2 usecs */ 176 #define PMCS_INTR_THRESHOLD(x) ((x) * 6 / 10) 177 178 /* 179 * This structure is used to maintain state with regard to I/O interrupt 180 * coalescing. 181 */ 182 183 typedef struct pmcs_io_intr_coal_s { 184 hrtime_t nsecs_between_intrs; 185 hrtime_t last_io_comp; 186 clock_t quantum; 187 uint32_t num_io_completions; 188 uint32_t num_intrs; 189 uint32_t max_io_completions; 190 uint32_t intr_latency; 191 uint32_t intr_threshold; 192 uint16_t intr_coal_timer; 193 boolean_t timer_on; 194 boolean_t stop_thread; 195 boolean_t int_cleared; 196 } pmcs_io_intr_coal_t; 197 198 typedef struct pmcs_cq_thr_info_s { 199 kthread_t *cq_thread; 200 kmutex_t cq_thr_lock; 201 kcondvar_t cq_cv; 202 pmcs_hw_t *cq_pwp; 203 } pmcs_cq_thr_info_t; 204 205 typedef struct pmcs_cq_info_s { 206 uint32_t cq_threads; 207 uint32_t cq_next_disp_thr; 208 boolean_t cq_stop; 209 pmcs_cq_thr_info_t *cq_thr_info; 210 } pmcs_cq_info_t; 211 212 typedef struct pmcs_iocomp_cb_s { 213 pmcwork_t *pwrk; 214 char iomb[PMCS_QENTRY_SIZE << 1]; 215 struct pmcs_iocomp_cb_s *next; 216 } pmcs_iocomp_cb_t; 217 218 typedef struct pmcs_iqp_trace_s { 219 char *head; 220 char *curpos; 221 uint32_t size_left; 222 } pmcs_iqp_trace_t; 223 224 /* 225 * Used by string-based softstate as hint to possible size. 226 */ 227 228 #define PMCS_TGT_SSTATE_SZ 64 229 #define PMCS_LUN_SSTATE_SZ 4 230 231 /* 232 * HBA iport node softstate 233 */ 234 #define PMCS_IPORT_INVALID_PORT_ID 0xf 235 236 struct pmcs_iport { 237 kmutex_t lock; /* iport lock */ 238 list_node_t list_node; /* list node for pwp->iports list_t */ 239 kmutex_t refcnt_lock; /* refcnt lock */ 240 kcondvar_t refcnt_cv; /* refcnt cv */ 241 int refcnt; /* refcnt for this iport */ 242 dev_info_t *dip; /* iport dip */ 243 pmcs_hw_t *pwp; /* back pointer to HBA state */ 244 pmcs_phy_t *pptr; /* pointer to this port's primary phy */ 245 enum { /* unit address state in the phymap */ 246 UA_INACTIVE, 247 UA_PEND_ACTIVATE, 248 UA_ACTIVE, 249 UA_PEND_DEACTIVATE 250 } ua_state; 251 char *ua; /* unit address (phy mask) */ 252 int portid; /* portid */ 253 int report_skip; /* skip or report during discovery */ 254 list_t phys; /* list of phys on this port */ 255 int nphy; /* number of phys in this port */ 256 scsi_hba_tgtmap_t *iss_tgtmap; /* tgtmap */ 257 ddi_soft_state_bystr *tgt_sstate; /* tgt softstate */ 258 /* SMP serialization */ 259 kmutex_t smp_lock; 260 kcondvar_t smp_cv; 261 boolean_t smp_active; 262 kthread_t *smp_active_thread; 263 }; 264 265 struct pmcs_chunk { 266 pmcs_chunk_t *next; 267 ddi_acc_handle_t acc_handle; 268 ddi_dma_handle_t dma_handle; 269 uint8_t *addrp; 270 uint64_t dma_addr; 271 }; 272 273 /* 274 * HBA node (i.e. non-iport) softstate 275 */ 276 struct pmcs_hw { 277 /* 278 * Identity 279 */ 280 dev_info_t *dip; 281 282 /* 283 * 16 possible initiator PHY WWNs 284 */ 285 uint64_t sas_wwns[PMCS_MAX_PORTS]; 286 287 /* 288 * Card State 289 */ 290 enum pwpstate { 291 STATE_NIL, 292 STATE_PROBING, 293 STATE_RUNNING, 294 STATE_UNPROBING, 295 STATE_IN_RESET, 296 STATE_DEAD 297 } state; 298 299 /* 300 * Last reason for a soft reset 301 */ 302 enum pwp_last_reset_reason { 303 PMCS_LAST_RST_UNINIT, 304 PMCS_LAST_RST_ATTACH, 305 PMCS_LAST_RST_FW_UPGRADE, 306 PMCS_LAST_RST_FATAL_ERROR, 307 PMCS_LAST_RST_STALL, 308 PMCS_LAST_RST_QUIESCE, 309 PMCS_LAST_RST_DETACH 310 } last_reset_reason; 311 312 uint32_t 313 fw_disable_update : 1, 314 fw_force_update : 1, 315 blocked : 1, 316 stuck : 1, 317 locks_initted : 1, 318 mpi_table_setup : 1, 319 hba_attached : 1, 320 iports_attached : 1, 321 suspended : 1, 322 separate_ports : 1, 323 fwlog : 4, 324 phymode : 3, 325 physpeed : 3, 326 resource_limited : 1, 327 configuring : 1, 328 ds_err_recovering : 1, 329 quiesced : 1; 330 331 /* 332 * This HBA instance's iportmap and list of iport states. 333 * Note: iports_lock protects iports, iports_attached, and 334 * num_iports on the HBA softstate. 335 */ 336 krwlock_t iports_lock; 337 scsi_hba_iportmap_t *hss_iportmap; 338 list_t iports; 339 int num_iports; 340 341 sas_phymap_t *hss_phymap; 342 int phymap_active; 343 344 /* 345 * Locks 346 */ 347 kmutex_t lock; 348 kmutex_t dma_lock; 349 kmutex_t axil_lock; 350 kcondvar_t drain_cv; 351 352 /* 353 * FMA Capabilities 354 */ 355 int fm_capabilities; 356 357 /* 358 * Register Access Handles 359 */ 360 ddi_device_acc_attr_t dev_acc_attr; 361 ddi_device_acc_attr_t reg_acc_attr; 362 ddi_acc_handle_t pci_acc_handle; 363 ddi_acc_handle_t msg_acc_handle; 364 ddi_acc_handle_t top_acc_handle; 365 ddi_acc_handle_t mpi_acc_handle; 366 ddi_acc_handle_t gsm_acc_handle; 367 ddi_acc_handle_t iqp_acchdls[PMCS_MAX_IQ]; 368 ddi_acc_handle_t oqp_acchdls[PMCS_MAX_IQ]; 369 ddi_acc_handle_t cip_acchdls; 370 ddi_acc_handle_t fwlog_acchdl; 371 ddi_acc_handle_t regdump_acchdl; 372 373 /* 374 * DMA Handles 375 */ 376 ddi_dma_attr_t iqp_dma_attr; 377 ddi_dma_attr_t oqp_dma_attr; 378 ddi_dma_attr_t cip_dma_attr; 379 ddi_dma_attr_t fwlog_dma_attr; 380 ddi_dma_attr_t regdump_dma_attr; 381 ddi_dma_handle_t iqp_handles[PMCS_MAX_IQ]; 382 ddi_dma_handle_t oqp_handles[PMCS_MAX_OQ]; 383 ddi_dma_handle_t cip_handles; 384 ddi_dma_handle_t fwlog_hndl; 385 ddi_dma_handle_t regdump_hndl; 386 387 /* 388 * Register Pointers 389 */ 390 uint32_t *msg_regs; /* message unit registers */ 391 uint32_t *top_regs; /* top unit registers */ 392 uint32_t *mpi_regs; /* message passing unit registers */ 393 uint32_t *gsm_regs; /* GSM registers */ 394 395 /* 396 * Message Passing and other offsets. 397 * 398 * mpi_offset is the offset within the fourth register set (mpi_regs) 399 * that contains the base of the MPI structures. Since this is actually 400 * set by the card firmware, it can change from startup to startup. 401 * 402 * The other offsets (gst, iqc, oqc) are for similar tables in 403 * MPI space, typically only accessed during setup. 404 */ 405 uint32_t mpi_offset; 406 uint32_t mpi_gst_offset; 407 uint32_t mpi_iqc_offset; 408 uint32_t mpi_oqc_offset; 409 410 /* 411 * Inbound and outbound queue depth 412 */ 413 uint32_t ioq_depth; 414 415 /* 416 * Kernel addresses and offsets for Inbound Queue Producer Indices 417 * 418 * See comments in pmcs_iomb.h about Inbound Queues. Since it 419 * is relatively expensive to go across the PCIe bus to read or 420 * write inside the card, we maintain shadow copies in kernel 421 * memory and update the card as needed. 422 */ 423 uint32_t shadow_iqpi[PMCS_MAX_IQ]; 424 uint32_t last_iqci[PMCS_MAX_IQ]; 425 uint32_t iqpi_offset[PMCS_MAX_IQ]; 426 uint32_t *iqp[PMCS_MAX_IQ]; 427 kmutex_t iqp_lock[PMCS_NIQ]; 428 429 pmcs_iqp_trace_t *iqpt; 430 431 /* 432 * Kernel addresses and offsets for Outbound Queue Consumer Indices 433 */ 434 uint32_t *oqp[PMCS_MAX_OQ]; 435 uint32_t oqci_offset[PMCS_MAX_OQ]; 436 437 /* 438 * Driver's copy of the outbound queue indices 439 */ 440 441 uint32_t oqci[PMCS_NOQ]; 442 uint32_t oqpi[PMCS_NOQ]; 443 444 /* 445 * DMA addresses for both Inbound and Outbound queues. 446 */ 447 uint64_t oqaddr[PMCS_MAX_OQ]; 448 uint64_t iqaddr[PMCS_MAX_IQ]; 449 450 /* 451 * Producer/Queue Host Memory Pointers and scratch areas, 452 * as well as DMA scatter/gather chunk areas. 453 * 454 * See discussion in pmcs_def.h about how this is laid out. 455 */ 456 uint8_t *cip; 457 uint64_t ciaddr; 458 459 /* 460 * Scratch area pointer and DMA addrress for SATA and SMP operations. 461 */ 462 void *scratch; 463 uint64_t scratch_dma; 464 volatile uint8_t scratch_locked; /* Scratch area ownership */ 465 466 /* 467 * Firmware log pointer 468 */ 469 uint32_t *fwlogp; 470 uint64_t fwaddr; 471 472 /* 473 * Internal register dump region and flash chunk DMA info 474 */ 475 476 caddr_t regdumpp; 477 uint32_t *flash_chunkp; 478 uint64_t flash_chunk_addr; 479 480 /* 481 * Copies of the last read MSGU and IOP heartbeats. 482 */ 483 uint32_t last_msgu_tick; 484 uint32_t last_iop_tick; 485 486 /* 487 * Card information, some determined during MPI setup 488 */ 489 uint32_t fw; /* firmware version */ 490 uint8_t max_iq; /* maximum inbound queues this card */ 491 uint8_t max_oq; /* "" outbound "" */ 492 uint8_t nphy; /* number of phys this card */ 493 uint8_t chiprev; /* chip revision */ 494 uint16_t max_cmd; /* max number of commands supported */ 495 uint16_t max_dev; /* max number of devices supported */ 496 uint16_t last_wq_dev; /* last dev whose wq was serviced */ 497 498 /* 499 * Counter for the number of times watchdog fires. We can use this 500 * to throttle events which fire off of the watchdog, such as the 501 * forward progress detection routine. 502 */ 503 uint8_t watchdog_count; 504 505 /* 506 * Interrupt Setup stuff. 507 * 508 * int_type defines the kind of interrupt we're using with this card. 509 * oqvec defines the relationship between an Outbound Queue Number and 510 * a MSI-X vector. 511 */ 512 enum { 513 PMCS_INT_NONE, 514 PMCS_INT_TIMER, 515 PMCS_INT_MSI, 516 PMCS_INT_MSIX, 517 PMCS_INT_FIXED 518 } int_type; 519 uint8_t oqvec[PMCS_NOQ]; 520 521 /* 522 * Interrupt handle table and size 523 */ 524 ddi_intr_handle_t *ih_table; 525 size_t ih_table_size; 526 527 timeout_id_t wdhandle; 528 uint32_t intr_mask; 529 int intr_cnt; 530 int intr_cap; 531 uint32_t odb_auto_clear; 532 533 /* 534 * DMA S/G chunk list 535 */ 536 int nchunks; 537 pmcs_chunk_t *dma_chunklist; 538 539 /* 540 * Front of the DMA S/G chunk freelist 541 */ 542 pmcs_dmachunk_t *dma_freelist; 543 544 /* 545 * PHY and Discovery Related Stuff 546 * 547 * The PMC chip can have up to 16 local phys. We build a level-first 548 * traversal tree of phys starting with the physical phys on the 549 * chip itself (i.e., treating the chip as if it were an expander). 550 * 551 * Our discovery process goes through a level and discovers what 552 * each entity is (and it's phy number within that expander's 553 * address space). It then configures each non-empty item (SAS, 554 * SATA/STP, EXPANDER). For expanders, it then performs 555 * discover on that expander itself via REPORT GENERAL and 556 * DISCOVERY SMP commands, attaching the discovered entities 557 * to the next level. Then we step down a level and continue 558 * (and so on). 559 * 560 * The PMC chip maintains an I_T_NEXUS notion based upon our 561 * registering each new device found (getting back a device handle). 562 * 563 * Like with the number of physical PHYS being a maximum of 16, 564 * there are a maximum number of PORTS also being 16. Some 565 * events apply to PORTS entirely, so we track PORTS as well. 566 */ 567 pmcs_phy_t *root_phys; /* HBA PHYs (level 0) */ 568 pmcs_phy_t *ports[PMCS_MAX_PORTS]; 569 kmutex_t dead_phylist_lock; /* Protects dead_phys */ 570 pmcs_phy_t *dead_phys; /* PHYs waiting to be freed */ 571 572 kmem_cache_t *phy_cache; 573 574 /* 575 * Discovery-related items. 576 * config_lock: Protects config_changed and should never be held 577 * outside of getting or setting the value of config_changed. 578 * config_changed: Boolean indicating whether discovery needs to 579 * be restarted. 580 * configuring: 1 = discovery is running, 0 = discovery not running. 581 * NOTE: configuring is now in the bitfield above. 582 * 583 * config_restart_time is set by the tgtmap_[de]activate callbacks each 584 * time we decide we want SCSA to retry enumeration on some device. 585 * The watchdog timer will not fire discovery unless it has reached 586 * config_restart_time and config_restart is TRUE. This ensures that 587 * we don't ask SCSA to retry enumerating devices while it is still 588 * running. 589 */ 590 kmutex_t config_lock; 591 volatile boolean_t config_changed; 592 boolean_t config_restart; 593 clock_t config_restart_time; 594 595 /* 596 * Work Related Stuff 597 * 598 * Each command given to the PMC chip has an associated work structure. 599 * See the discussion in pmcs_def.h about work structures. 600 */ 601 pmcwork_t *work; /* pool of work structures */ 602 STAILQ_HEAD(wfh, pmcwork) wf; /* current freelist */ 603 STAILQ_HEAD(pfh, pmcwork) pf; /* current pending freelist */ 604 uint16_t wserno; /* rolling serial number */ 605 kmutex_t wfree_lock; /* freelist/actvlist/wserno lock */ 606 kmutex_t pfree_lock; /* freelist/actvlist/wserno lock */ 607 608 /* 609 * Solaris/SCSA items. 610 */ 611 scsi_hba_tran_t *tran; 612 smp_hba_tran_t *smp_tran; 613 struct scsi_reset_notify_entry *reset_notify_listf; 614 615 /* 616 * Thread Level stuff. 617 * 618 * A number of tasks are done off worker thread taskq. 619 */ 620 ddi_taskq_t *tq; /* For the worker thread */ 621 volatile ulong_t work_flags; 622 623 /* 624 * Solaris target representation. 625 * targets = array of pointers to xscsi structures 626 * allocated by ssoftstate. 627 */ 628 pmcs_xscsi_t **targets; 629 630 STAILQ_HEAD(dqh, pmcs_cmd) dq; /* dead commands */ 631 STAILQ_HEAD(cqh, pmcs_cmd) cq; /* completed commands */ 632 kmutex_t cq_lock; 633 kmem_cache_t *iocomp_cb_cache; 634 pmcs_iocomp_cb_t *iocomp_cb_head; 635 pmcs_iocomp_cb_t *iocomp_cb_tail; 636 637 uint16_t debug_mask; 638 uint16_t phyid_block_mask; 639 uint16_t phys_started; 640 uint32_t hipri_queue; 641 uint32_t mpibar; 642 uint32_t intr_pri; 643 644 pmcs_io_intr_coal_t io_intr_coal; 645 pmcs_cq_info_t cq_info; 646 kmutex_t ict_lock; 647 kcondvar_t ict_cv; 648 kthread_t *ict_thread; 649 650 #ifdef DEBUG 651 kmutex_t dbglock; 652 uint32_t ltags[256]; 653 uint32_t ftags[256]; 654 hrtime_t ltime[256]; 655 hrtime_t ftime[256]; 656 uint16_t ftag_lines[256]; 657 uint8_t lti; /* last tag index */ 658 uint8_t fti; /* first tag index */ 659 #endif 660 }; 661 662 extern void *pmcs_softc_state; 663 extern void *pmcs_iport_softstate; 664 665 /* 666 * Some miscellaneous, oft used strings 667 */ 668 extern const char pmcs_nowrk[]; 669 extern const char pmcs_nomsg[]; 670 extern const char pmcs_timeo[]; 671 672 #ifdef __cplusplus 673 } 674 #endif 675 #endif /* _PMCS_H */ 676