18d483882Smlf /* 28d483882Smlf * CDDL HEADER START 38d483882Smlf * 48d483882Smlf * The contents of this file are subject to the terms of the 58d483882Smlf * Common Development and Distribution License (the "License"). 68d483882Smlf * You may not use this file except in compliance with the License. 78d483882Smlf * 88d483882Smlf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 98d483882Smlf * or http://www.opensolaris.org/os/licensing. 108d483882Smlf * See the License for the specific language governing permissions 118d483882Smlf * and limitations under the License. 128d483882Smlf * 138d483882Smlf * When distributing Covered Code, include this CDDL HEADER in each 148d483882Smlf * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 158d483882Smlf * If applicable, add the following below this CDDL HEADER, with the 168d483882Smlf * fields enclosed by brackets "[]" replaced with your own identifying 178d483882Smlf * information: Portions Copyright [yyyy] [name of copyright owner] 188d483882Smlf * 198d483882Smlf * CDDL HEADER END 208d483882Smlf */ 218d483882Smlf 228d483882Smlf /* 237798b2a0SMartin Faltesek * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. 248d483882Smlf */ 258d483882Smlf 268d483882Smlf #ifndef _NV_SATA_H 278d483882Smlf #define _NV_SATA_H 288d483882Smlf 298d483882Smlf 308d483882Smlf #ifdef __cplusplus 318d483882Smlf extern "C" { 328d483882Smlf #endif 338d483882Smlf 343f318a28SAlan Perry 353f318a28SAlan Perry /* 363f318a28SAlan Perry * SGPIO Support 373f318a28SAlan Perry * Enable SGPIO support only on x86/x64, because it is implemented using 383f318a28SAlan Perry * functions that are only available on x86/x64. 393f318a28SAlan Perry */ 403f318a28SAlan Perry 418d483882Smlf #define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports 428d483882Smlf 438d483882Smlf typedef struct nv_port nv_port_t; 448d483882Smlf 453f318a28SAlan Perry #ifdef SGPIO_SUPPORT 463f318a28SAlan Perry typedef struct nv_sgp_cmn nv_sgp_cmn_t; 473f318a28SAlan Perry #endif 483f318a28SAlan Perry 497798b2a0SMartin Faltesek /* 507798b2a0SMartin Faltesek * sizes of strings to allocate 517798b2a0SMartin Faltesek */ 527798b2a0SMartin Faltesek #define NV_STR_LEN 10 537798b2a0SMartin Faltesek #define NV_LOGBUF_LEN 512 547798b2a0SMartin Faltesek #define NV_REASON_LEN 30 557798b2a0SMartin Faltesek 56a78a9fafSMartin Faltesek 578d483882Smlf typedef struct nv_ctl { 588d483882Smlf /* 598d483882Smlf * Each of these are specific to the chipset in use. 608d483882Smlf */ 618d483882Smlf uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2); 628d483882Smlf void (*nvc_reg_init)(struct nv_ctl *nvc, 638d483882Smlf ddi_acc_handle_t pci_conf_handle); 648d483882Smlf 658d483882Smlf dev_info_t *nvc_dip; /* devinfo pointer of controller */ 668d483882Smlf 678d483882Smlf struct nv_port *nvc_port; /* array of pointers to port struct */ 688d483882Smlf 698d483882Smlf /* 708d483882Smlf * handle and base address to register space. 718d483882Smlf * 728d483882Smlf * 0: port 0 task file 738d483882Smlf * 1: port 0 status 748d483882Smlf * 2: port 1 task file 758d483882Smlf * 3: port 1 status 768d483882Smlf * 4: bus master for both ports 778d483882Smlf * 5: extended registers for SATA features 788d483882Smlf */ 798d483882Smlf ddi_acc_handle_t nvc_bar_hdl[6]; 808d483882Smlf uchar_t *nvc_bar_addr[6]; 818d483882Smlf 828d483882Smlf /* 838d483882Smlf * sata registers in bar 5 which are shared on all devices 848d483882Smlf * on the channel. 858d483882Smlf */ 865b439bedSPraveen Kumar Dasaraju Rama uint32_t *nvc_mcp5x_ctl; 875b439bedSPraveen Kumar Dasaraju Rama uint32_t *nvc_mcp5x_ncq; /* NCQ status control bits */ 888d483882Smlf 898d483882Smlf kmutex_t nvc_mutex; /* ctrl level lock */ 908d483882Smlf 918d483882Smlf ddi_intr_handle_t *nvc_htable; /* For array of interrupts */ 928d483882Smlf int nvc_intr_type; /* What type of interrupt */ 938d483882Smlf int nvc_intr_cnt; /* # of intrs count returned */ 948d483882Smlf size_t nvc_intr_size; /* Size of intr array to */ 958d483882Smlf uint_t nvc_intr_pri; /* Interrupt priority */ 968d483882Smlf int nvc_intr_cap; /* Interrupt capabilities */ 975b439bedSPraveen Kumar Dasaraju Rama uint8_t *nvc_ck804_int_status; /* interrupt status ck804 */ 988d483882Smlf 998d483882Smlf sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */ 1008d483882Smlf 1018d483882Smlf /* 1028d483882Smlf * enable/disable interrupts, controller specific 1038d483882Smlf */ 1048d483882Smlf void (*nvc_set_intr)(nv_port_t *nvp, int flag); 1058d483882Smlf int nvc_state; /* state flags of ctrl see below */ 106*57454abeSAlbert Lee uint16_t nvc_devid; /* PCI devid of device */ 1078d483882Smlf uint8_t nvc_revid; /* PCI revid of device */ 10874202013SGuoli Shu boolean_t dma_40bit; /* 40bit DMA support */ 109*57454abeSAlbert Lee boolean_t nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */ 1103f318a28SAlan Perry 1113f318a28SAlan Perry #ifdef SGPIO_SUPPORT 1123f318a28SAlan Perry uint8_t nvc_ctlr_num; /* controller number within the part */ 1133f318a28SAlan Perry uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */ 114a150bf85SAlan Perry volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */ 1153f318a28SAlan Perry nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */ 1163f318a28SAlan Perry #endif 1178d483882Smlf } nv_ctl_t; 1188d483882Smlf 1198d483882Smlf 1208d483882Smlf struct nv_port { 1218d483882Smlf 1228d483882Smlf struct nv_ctl *nvp_ctlp; /* back pointer to controller */ 1238d483882Smlf 1247798b2a0SMartin Faltesek uint8_t nvp_port_num; /* port number, ie 0 or 1 */ 1258d483882Smlf 1268d483882Smlf uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */ 1278d483882Smlf uint32_t nvp_signature; /* sig acquired from task file regs */ 1288d483882Smlf uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */ 1298d483882Smlf uchar_t *nvp_bm_addr; /* base addr for bus master for port */ 1308d483882Smlf uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */ 1318d483882Smlf 1328d483882Smlf ddi_acc_handle_t nvp_cmd_hdl; 1338d483882Smlf uchar_t *nvp_data; /* data register */ 1348d483882Smlf uchar_t *nvp_error; /* error register (read) */ 1358d483882Smlf uchar_t *nvp_feature; /* features (write) */ 1368d483882Smlf uchar_t *nvp_count; /* sector count */ 1378d483882Smlf uchar_t *nvp_sect; /* sector number */ 1388d483882Smlf uchar_t *nvp_lcyl; /* cylinder low byte */ 1398d483882Smlf uchar_t *nvp_hcyl; /* cylinder high byte */ 1408d483882Smlf uchar_t *nvp_drvhd; /* drive/head register */ 1418d483882Smlf uchar_t *nvp_status; /* status/command register */ 1428d483882Smlf uchar_t *nvp_cmd; /* status/command register */ 1438d483882Smlf 1448d483882Smlf ddi_acc_handle_t nvp_ctl_hdl; 1458d483882Smlf uchar_t *nvp_altstatus; /* alternate status (read) */ 1468d483882Smlf uchar_t *nvp_devctl; /* device control (write) */ 1478d483882Smlf 1488d483882Smlf ddi_acc_handle_t nvp_bm_hdl; 1498d483882Smlf uchar_t *nvp_bmisx; 1508d483882Smlf uint32_t *nvp_bmidtpx; 1518d483882Smlf uchar_t *nvp_bmicx; 1528d483882Smlf 1538d483882Smlf ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */ 1548d483882Smlf caddr_t *nvp_sg_addr; /* virtual addr of prd table */ 1558d483882Smlf uint32_t *nvp_sg_paddr; /* physical address of prd table */ 1568d483882Smlf ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */ 1578d483882Smlf 1588d483882Smlf uint32_t *nvp_sstatus; 1598d483882Smlf uint32_t *nvp_serror; 1608d483882Smlf uint32_t *nvp_sctrl; 1618d483882Smlf uint32_t *nvp_sactive; 1628d483882Smlf 1638d483882Smlf kmutex_t nvp_mutex; /* main per port mutex */ 164a78a9fafSMartin Faltesek kcondvar_t nvp_sync_cv; /* handshake btwn ISR and start thrd */ 165a78a9fafSMartin Faltesek kcondvar_t nvp_reset_cv; /* when reset is synchronous */ 1668d483882Smlf 1678d483882Smlf /* 1688d483882Smlf * nvp_slot is a pointer to an array of nv_slot 1698d483882Smlf */ 1708d483882Smlf struct nv_slot *nvp_slot; 1718d483882Smlf uint32_t nvp_sactive_cache; /* cache of SACTIVE */ 1728d483882Smlf uint8_t nvp_queue_depth; 1738d483882Smlf 1748d483882Smlf /* 1758d483882Smlf * NCQ flow control. During NCQ operation, no other commands 1768d483882Smlf * allowed. The following are used to enforce this. 1778d483882Smlf */ 1788d483882Smlf int nvp_ncq_run; 1798d483882Smlf int nvp_non_ncq_run; 1807798b2a0SMartin Faltesek int nvp_seq; 1818d483882Smlf 1828d483882Smlf timeout_id_t nvp_timeout_id; 1838d483882Smlf 184a78a9fafSMartin Faltesek clock_t nvp_reset_time; /* time of last reset */ 185a78a9fafSMartin Faltesek clock_t nvp_link_event_time; /* time of last plug event */ 186a78a9fafSMartin Faltesek int nvp_reset_retry_count; 187a78a9fafSMartin Faltesek clock_t nvp_wait_sig; /* wait before rechecking sig */ 1888d483882Smlf 1898d483882Smlf int nvp_state; /* state of port. flags defined below */ 1908d483882Smlf 1915b439bedSPraveen Kumar Dasaraju Rama uint16_t *nvp_mcp5x_int_status; 1925b439bedSPraveen Kumar Dasaraju Rama uint16_t *nvp_mcp5x_int_ctl; 1933f318a28SAlan Perry 1943f318a28SAlan Perry #ifdef SGPIO_SUPPORT 1953f318a28SAlan Perry uint8_t nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */ 1963f318a28SAlan Perry #endif 197a78a9fafSMartin Faltesek clock_t nvp_timeout_duration; 198a78a9fafSMartin Faltesek 199a78a9fafSMartin Faltesek 200a78a9fafSMartin Faltesek /* 201a78a9fafSMartin Faltesek * debug and statistical information 202a78a9fafSMartin Faltesek */ 203a78a9fafSMartin Faltesek clock_t nvp_rem_time; 204a78a9fafSMartin Faltesek clock_t nvp_add_time; 205a78a9fafSMartin Faltesek clock_t nvp_trans_link_time; 206a78a9fafSMartin Faltesek int nvp_trans_link_count; 207a9d5ae2eSPawel Wojcik 208a9d5ae2eSPawel Wojcik uint8_t nvp_last_cmd; 209a9d5ae2eSPawel Wojcik uint8_t nvp_previous_cmd; 210a9d5ae2eSPawel Wojcik int nvp_reset_count; 2117798b2a0SMartin Faltesek char nvp_first_reset_reason[NV_REASON_LEN]; 2127798b2a0SMartin Faltesek char nvp_reset_reason[NV_REASON_LEN]; 213a9d5ae2eSPawel Wojcik clock_t intr_duration; /* max length of port intr (ticks) */ 214a9d5ae2eSPawel Wojcik clock_t intr_start_time; 215a9d5ae2eSPawel Wojcik int intr_loop_cnt; 2168d483882Smlf }; 2178d483882Smlf 2188d483882Smlf 2198d483882Smlf typedef struct nv_device_table { 2208d483882Smlf ushort_t vendor_id; /* vendor id */ 2218d483882Smlf ushort_t device_id; /* device id */ 2225b439bedSPraveen Kumar Dasaraju Rama ushort_t type; /* chipset type, ck804 or mcp51/mcp55 */ 2238d483882Smlf } nv_device_table_t; 2248d483882Smlf 2258d483882Smlf 2268d483882Smlf typedef struct nv_slot { 2278d483882Smlf caddr_t nvslot_v_addr; /* I/O buffer address */ 2288d483882Smlf size_t nvslot_byte_count; /* # bytes left to read/write */ 2298d483882Smlf sata_pkt_t *nvslot_spkt; 230b5fc475bSap uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN]; 2318d483882Smlf clock_t nvslot_stime; 2328d483882Smlf int (*nvslot_start)(nv_port_t *nvp, int queue); 2338d483882Smlf void (*nvslot_intr)(nv_port_t *nvp, 2348d483882Smlf struct nv_slot *nv_slotp); 2358d483882Smlf uint32_t nvslot_flags; 2368d483882Smlf } nv_slot_t; 2378d483882Smlf 2388d483882Smlf 2393f318a28SAlan Perry #ifdef SGPIO_SUPPORT 2403f318a28SAlan Perry struct nv_sgp_cmn { 2413f318a28SAlan Perry uint8_t nvs_in_use; /* bit-field of active ctlrs */ 2423f318a28SAlan Perry uint8_t nvs_connected; /* port connected bit-field flag */ 2433f318a28SAlan Perry uint8_t nvs_activity; /* port usage bit-field flag */ 244a150bf85SAlan Perry int nvs_cbp; /* SGPIO Control Block Pointer */ 2453f318a28SAlan Perry int nvs_taskq_delay; /* rest time for activity LED taskq */ 2463f318a28SAlan Perry kmutex_t nvs_slock; /* lock for shared data */ 2473f318a28SAlan Perry kmutex_t nvs_tlock; /* lock for taskq */ 2483f318a28SAlan Perry kcondvar_t nvs_cv; /* condition variable for taskq wait */ 2493f318a28SAlan Perry ddi_taskq_t *nvs_taskq; /* activity LED taskq */ 2503f318a28SAlan Perry }; 251a150bf85SAlan Perry 252a150bf85SAlan Perry struct nv_sgp_cbp2cmn { 253a150bf85SAlan Perry uint32_t c2cm_cbp; /* ctlr block ptr from pci cfg space */ 254a150bf85SAlan Perry nv_sgp_cmn_t *c2cm_cmn; /* point to common space */ 255a150bf85SAlan Perry }; 2563f318a28SAlan Perry #endif 2573f318a28SAlan Perry 2583f318a28SAlan Perry 2598d483882Smlf /* 2608d483882Smlf * nvslot_flags 2618d483882Smlf */ 2628d483882Smlf #define NVSLOT_COMPLETE 0x01 263b5fc475bSap #define NVSLOT_NCQ 0x02 /* NCQ is active */ 264b5fc475bSap #define NVSLOT_RQSENSE 0x04 /* processing request sense */ 2658d483882Smlf 2668d483882Smlf /* 2678d483882Smlf * state values for nv_attach 2688d483882Smlf */ 2698d483882Smlf #define ATTACH_PROGRESS_NONE (1 << 0) 2708d483882Smlf #define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1) 2718d483882Smlf #define ATTACH_PROGRESS_PCI_HANDLE (1 << 2) 2728d483882Smlf #define ATTACH_PROGRESS_BARS (1 << 3) 2738d483882Smlf #define ATTACH_PROGRESS_INTR_ADDED (1 << 4) 2748d483882Smlf #define ATTACH_PROGRESS_MUTEX_INIT (1 << 5) 2758d483882Smlf #define ATTACH_PROGRESS_CTL_SETUP (1 << 6) 2768d483882Smlf #define ATTACH_PROGRESS_TRAN_SETUP (1 << 7) 2778d483882Smlf #define ATTACH_PROGRESS_COUNT (1 << 8) 2788d483882Smlf #define ATTACH_PROGRESS_CONF_HANDLE (1 << 9) 2798d483882Smlf #define ATTACH_PROGRESS_SATA_MODULE (1 << 10) 2808d483882Smlf 2818d483882Smlf #ifdef DEBUG 2828d483882Smlf 2838d483882Smlf #define NV_DEBUG 1 2848d483882Smlf 2858d483882Smlf #endif /* DEBUG */ 2868d483882Smlf 2878d483882Smlf 2888d483882Smlf /* 2898d483882Smlf * nv_debug_flags 2908d483882Smlf */ 2917798b2a0SMartin Faltesek #define NVDBG_ALWAYS 0x00001 2927798b2a0SMartin Faltesek #define NVDBG_INIT 0x00002 2937798b2a0SMartin Faltesek #define NVDBG_ENTRY 0x00004 2947798b2a0SMartin Faltesek #define NVDBG_DELIVER 0x00008 2957798b2a0SMartin Faltesek #define NVDBG_EVENT 0x00010 2967798b2a0SMartin Faltesek #define NVDBG_SYNC 0x00020 2977798b2a0SMartin Faltesek #define NVDBG_PKTCOMP 0x00040 2987798b2a0SMartin Faltesek #define NVDBG_TIMEOUT 0x00080 2997798b2a0SMartin Faltesek #define NVDBG_INFO 0x00100 3007798b2a0SMartin Faltesek #define NVDBG_VERBOSE 0x00200 3017798b2a0SMartin Faltesek #define NVDBG_INTR 0x00400 3027798b2a0SMartin Faltesek #define NVDBG_ERRS 0x00800 3037798b2a0SMartin Faltesek #define NVDBG_COOKIES 0x01000 3047798b2a0SMartin Faltesek #define NVDBG_HOT 0x02000 3057798b2a0SMartin Faltesek #define NVDBG_RESET 0x04000 3067798b2a0SMartin Faltesek #define NVDBG_ATAPI 0x08000 3077798b2a0SMartin Faltesek 3087798b2a0SMartin Faltesek #define NVLOG(flag, nvc, nvp, fmt, args ...) \ 3097798b2a0SMartin Faltesek if (nv_debug_flags & (flag)) { \ 3107798b2a0SMartin Faltesek nv_log(nvc, nvp, fmt, ## args); \ 3117798b2a0SMartin Faltesek } 3128d483882Smlf 3138d483882Smlf 3148d483882Smlf #define NV_SUCCESS 0 3158d483882Smlf #define NV_FAILURE -1 3168d483882Smlf 3178d483882Smlf /* 3188d483882Smlf * indicates whether nv_wait functions can sleep or not. 3198d483882Smlf */ 3208d483882Smlf #define NV_SLEEP 1 3218d483882Smlf #define NV_NOSLEEP 2 3228d483882Smlf 323a78a9fafSMartin Faltesek 3248d483882Smlf /* 3258d483882Smlf * port offsets from base address ioaddr1 3268d483882Smlf */ 3278d483882Smlf #define NV_DATA 0x00 /* data register */ 3288d483882Smlf #define NV_ERROR 0x01 /* error register (read) */ 3298d483882Smlf #define NV_FEATURE 0x01 /* features (write) */ 3308d483882Smlf #define NV_COUNT 0x02 /* sector count */ 3318d483882Smlf #define NV_SECT 0x03 /* sector number */ 3328d483882Smlf #define NV_LCYL 0x04 /* cylinder low byte */ 3338d483882Smlf #define NV_HCYL 0x05 /* cylinder high byte */ 3348d483882Smlf #define NV_DRVHD 0x06 /* drive/head register */ 3358d483882Smlf #define NV_STATUS 0x07 /* status/command register */ 3368d483882Smlf #define NV_CMD 0x07 /* status/command register */ 3378d483882Smlf 3388d483882Smlf /* 3398d483882Smlf * port offsets from base address ioaddr2 3408d483882Smlf */ 3418d483882Smlf #define NV_ALTSTATUS 0x02 /* alternate status (read) */ 3428d483882Smlf #define NV_DEVCTL 0x02 /* device control (write) */ 3438d483882Smlf 3448d483882Smlf /* 3458d483882Smlf * device control register 3468d483882Smlf */ 3478d483882Smlf #define ATDC_NIEN 0x02 /* disable interrupts */ 3488d483882Smlf #define ATDC_SRST 0x04 /* controller reset */ 3498d483882Smlf #define ATDC_D3 0x08 /* mysterious bit */ 3508d483882Smlf #define ATDC_HOB 0x80 /* high order byte to read 48-bit values */ 3518d483882Smlf 352a9d5ae2eSPawel Wojcik /* 353a9d5ae2eSPawel Wojcik * MCP5x NCQ and INTR control registers 354a9d5ae2eSPawel Wojcik */ 3555b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_CTL 0x400 /* queuing control */ 3565b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_STATUS 0x440 /* status bits for interrupt */ 3575b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_CTL 0x444 /* enable bits for interrupt */ 3585b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_NCQ 0x448 /* NCQ status and ctrl bits */ 3598d483882Smlf 3608d483882Smlf /* 3618d483882Smlf * if either of these bits are set, when using NCQ, if no other commands are 3628d483882Smlf * active while a new command is started, DMA engine can be programmed ahead 3638d483882Smlf * of time to save extra interrupt. Presumably pre-programming is discarded 3648d483882Smlf * if a subsequent command ends up finishing first. 3658d483882Smlf */ 3668d483882Smlf #define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7) 3678d483882Smlf #define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23) 3688d483882Smlf 3698d483882Smlf /* 3708d483882Smlf * bit definitions to indicate which NCQ command requires 3718d483882Smlf * DMA setup. 3728d483882Smlf */ 3738d483882Smlf #define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2 3748d483882Smlf #define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18 3758d483882Smlf #define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f 3768d483882Smlf 3778d483882Smlf 3788d483882Smlf /* 3795b439bedSPraveen Kumar Dasaraju Rama * Bits for NV_MCP5X_INT_CTL and NV_MCP5X_INT_STATUS 3808d483882Smlf */ 3815b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_SNOTIFY 0x200 /* snotification set */ 3825b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_SERROR 0x100 /* serror set */ 3835b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_DMA_SETUP 0x80 /* DMA to be programmed */ 3845b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_DH_REGFIS 0x40 /* REGFIS received */ 3855b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_SDB_FIS 0x20 /* SDB FIS */ 3865b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_TX_BACKOUT 0x10 /* TX backout */ 3875b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_REM 0x08 /* device removed */ 3885b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_ADD 0x04 /* device added */ 3895b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_PM 0x02 /* power changed */ 3905b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_COMPLETE 0x01 /* device interrupt */ 3918d483882Smlf 3928d483882Smlf /* 3938d483882Smlf * Bits above that are not used for now. 3948d483882Smlf */ 3955b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_IGNORE (MCP5X_INT_DMA_SETUP|MCP5X_INT_DH_REGFIS|\ 3965b439bedSPraveen Kumar Dasaraju Rama MCP5X_INT_SDB_FIS|MCP5X_INT_TX_BACKOUT|MCP5X_INT_PM|\ 3975b439bedSPraveen Kumar Dasaraju Rama MCP5X_INT_SNOTIFY|MCP5X_INT_SERROR) 3988d483882Smlf 3998d483882Smlf /* 4008d483882Smlf * Bits for MCP_SATA_AE_CTL 4018d483882Smlf */ 4028d483882Smlf #define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */ 4038d483882Smlf #define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */ 4048d483882Smlf 405a78a9fafSMartin Faltesek #define NV_DELAY_NSEC(wait_ns) \ 406a78a9fafSMartin Faltesek { \ 407a78a9fafSMartin Faltesek hrtime_t start, end; \ 408a78a9fafSMartin Faltesek start = end = gethrtime(); \ 409a78a9fafSMartin Faltesek while ((end - start) < wait_ns) \ 410a78a9fafSMartin Faltesek end = gethrtime(); \ 4118d483882Smlf } 4128d483882Smlf 4138d483882Smlf /* 414a78a9fafSMartin Faltesek * signature in task file registers after device reset 4158d483882Smlf */ 416a78a9fafSMartin Faltesek #define NV_DISK_SIG 0x00000101 417a78a9fafSMartin Faltesek #define NV_ATAPI_SIG 0xeb140101 418a78a9fafSMartin Faltesek #define NV_PM_SIG 0x96690101 419a78a9fafSMartin Faltesek #define NV_NO_SIG 0x00000000 4208d483882Smlf 4218d483882Smlf /* 4225b439bedSPraveen Kumar Dasaraju Rama * These bar5 offsets are common to mcp51/mcp55/ck804 and thus 4238d483882Smlf * prefixed with NV. 4248d483882Smlf */ 4258d483882Smlf #define NV_SSTATUS 0x00 4268d483882Smlf #define NV_SERROR 0x04 4278d483882Smlf #define NV_SCTRL 0x08 4288d483882Smlf #define NV_SACTIVE 0x0c 4298d483882Smlf #define NV_SNOTIFICATION 0x10 4308d483882Smlf 4318d483882Smlf #define CH0_SREG_OFFSET 0x0 4328d483882Smlf #define CH1_SREG_OFFSET 0x40 4338d483882Smlf 4348d483882Smlf 4358d483882Smlf /* 4368d483882Smlf * The following config space offsets are needed to enable 4375b439bedSPraveen Kumar Dasaraju Rama * bar 5 register access in ck804/mcp51/mcp55 4388d483882Smlf */ 4398d483882Smlf #define NV_SATA_CFG_20 0x50 4408d483882Smlf #define NV_BAR5_SPACE_EN 0x04 4418d483882Smlf #define NV_40BIT_PRD 0x20 4428d483882Smlf 443f8a5505bSMartin Faltesek #define NV_SATA_CFG_23 0x60 444f8a5505bSMartin Faltesek 4458d483882Smlf /* 4465b439bedSPraveen Kumar Dasaraju Rama * ck804 interrupt status register 4478d483882Smlf */ 4488d483882Smlf 4498d483882Smlf /* 4508d483882Smlf * offsets to bar 5 registers 4518d483882Smlf */ 4525b439bedSPraveen Kumar Dasaraju Rama #define CK804_SATA_INT_STATUS 0x440 4535b439bedSPraveen Kumar Dasaraju Rama #define CK804_SATA_INT_EN 0x441 4548d483882Smlf 4558d483882Smlf 4568d483882Smlf /* 4578d483882Smlf * bit fields for int status and int enable 4588d483882Smlf * registers 4598d483882Smlf */ 4605b439bedSPraveen Kumar Dasaraju Rama #define CK804_INT_PDEV_INT 0x01 /* completion interrupt */ 4615b439bedSPraveen Kumar Dasaraju Rama #define CK804_INT_PDEV_PM 0x02 /* power change */ 4625b439bedSPraveen Kumar Dasaraju Rama #define CK804_INT_PDEV_ADD 0x04 /* hot plug */ 4635b439bedSPraveen Kumar Dasaraju Rama #define CK804_INT_PDEV_REM 0x08 /* hot remove */ 4645b439bedSPraveen Kumar Dasaraju Rama #define CK804_INT_PDEV_HOT CK804_INT_PDEV_ADD|CK804_INT_PDEV_REM 4658d483882Smlf 4665b439bedSPraveen Kumar Dasaraju Rama #define CK804_INT_SDEV_INT 0x10 /* completion interrupt */ 4675b439bedSPraveen Kumar Dasaraju Rama #define CK804_INT_SDEV_PM 0x20 /* power change */ 4685b439bedSPraveen Kumar Dasaraju Rama #define CK804_INT_SDEV_ADD 0x40 /* hot plug */ 4695b439bedSPraveen Kumar Dasaraju Rama #define CK804_INT_SDEV_REM 0x80 /* hot remove */ 4705b439bedSPraveen Kumar Dasaraju Rama #define CK804_INT_SDEV_HOT CK804_INT_SDEV_ADD|CK804_INT_SDEV_REM 4718d483882Smlf 4725b439bedSPraveen Kumar Dasaraju Rama #define CK804_INT_PDEV_ALL CK804_INT_PDEV_INT|CK804_INT_PDEV_HOT|\ 4735b439bedSPraveen Kumar Dasaraju Rama CK804_INT_PDEV_PM 4745b439bedSPraveen Kumar Dasaraju Rama #define CK804_INT_SDEV_ALL CK804_INT_SDEV_INT|CK804_INT_SDEV_HOT|\ 4755b439bedSPraveen Kumar Dasaraju Rama CK804_INT_SDEV_PM 4768d483882Smlf 4778d483882Smlf /* 4788d483882Smlf * config space offset 42 4798d483882Smlf */ 4808d483882Smlf #define NV_SATA_CFG_42 0xac 4818d483882Smlf 4828d483882Smlf /* 4838d483882Smlf * bit in CFG_42 which delays hotplug interrupt until 4848d483882Smlf * PHY ready 4858d483882Smlf */ 4865b439bedSPraveen Kumar Dasaraju Rama #define CK804_CFG_DELAY_HOTPLUG_INTR (0x1 << 12) 4878d483882Smlf 4888d483882Smlf 4898d483882Smlf /* 4908d483882Smlf * bar 5 offsets for SATA registers in ck804 4918d483882Smlf */ 4925b439bedSPraveen Kumar Dasaraju Rama #define CK804_CH1_SSTATUS 0x00 4935b439bedSPraveen Kumar Dasaraju Rama #define CK804_CH1_SERROR 0x04 4945b439bedSPraveen Kumar Dasaraju Rama #define CK804_CH1_SCTRL 0x08 4955b439bedSPraveen Kumar Dasaraju Rama #define CK804_CH1_SACTIVE 0x0c 4965b439bedSPraveen Kumar Dasaraju Rama #define CK804_CH1_SNOTIFICATION 0x10 4978d483882Smlf 4985b439bedSPraveen Kumar Dasaraju Rama #define CK804_CH2_SSTATUS 0x40 4995b439bedSPraveen Kumar Dasaraju Rama #define CK804_CH2_SERROR 0x44 5005b439bedSPraveen Kumar Dasaraju Rama #define CK804_CH2_SCTRL 0x48 5015b439bedSPraveen Kumar Dasaraju Rama #define CK804_CH2_SACTIVE 0x4c 5025b439bedSPraveen Kumar Dasaraju Rama #define CK804_CH2_SNOTIFICATION 0x50 5038d483882Smlf 5048d483882Smlf 5058d483882Smlf /* 5065b439bedSPraveen Kumar Dasaraju Rama * bar 5 offsets for ADMACTL settings for both ck804/mcp51/mcp/55 5078d483882Smlf */ 5088d483882Smlf #define NV_ADMACTL_X 0x4C0 5098d483882Smlf #define NV_ADMACTL_Y 0x5C0 5108d483882Smlf 5118d483882Smlf /* 5128d483882Smlf * Bits for NV_ADMACTL_X and NV_ADMACTL_Y 5138d483882Smlf */ 5148d483882Smlf #define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */ 5158d483882Smlf #define NV_CH_RST 0x04 /* reset channel */ 5168d483882Smlf 5178d483882Smlf 5188d483882Smlf /* 5195b439bedSPraveen Kumar Dasaraju Rama * bar 5 offset for ADMASTAT regs for ck804 5208d483882Smlf */ 5215b439bedSPraveen Kumar Dasaraju Rama #define CK804_ADMASTAT_X 0x4C4 5225b439bedSPraveen Kumar Dasaraju Rama #define CK804_ADMASTAT_Y 0x5C4 5238d483882Smlf 5248d483882Smlf /* 5255b439bedSPraveen Kumar Dasaraju Rama * Bits for CK804_ADMASTAT_X and CK804_ADMASTAT_Y 5268d483882Smlf */ 5275b439bedSPraveen Kumar Dasaraju Rama #define CK804_HPIRQ 0x4 5288d483882Smlf #define MCP05_HUIRQ 0x2 5298d483882Smlf 5308d483882Smlf 5318d483882Smlf /* 5328d483882Smlf * bar 4 offset to bus master command registers 5338d483882Smlf */ 5348d483882Smlf #define BMICX_REG 0 5358d483882Smlf 5368d483882Smlf /* 5378d483882Smlf * bit definitions for BMICX_REG 5388d483882Smlf */ 5398d483882Smlf #define BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 5408d483882Smlf /* 1=Start (Enable) */ 5418d483882Smlf /* 0=Start (Disable) */ 5428d483882Smlf 5438d483882Smlf /* 5448d483882Smlf * NOTE: "read" and "write" are the actions of the DMA engine 5458d483882Smlf * on the PCI bus, not the SATA bus. Therefore for a ATA READ 5468d483882Smlf * command, program the DMA engine to "write to memory" mode 5478d483882Smlf * (and vice versa). 5488d483882Smlf */ 5498d483882Smlf #define BMICX_RWCON 0x08 /* Read/Write Control */ 5508d483882Smlf #define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 5518d483882Smlf #define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 5528d483882Smlf 5538d483882Smlf /* 5548d483882Smlf * BMICX bits to preserve during updates 5558d483882Smlf */ 5568d483882Smlf #define BMICX_MASK (~(BMICX_SSBM | BMICX_RWCON)) 5578d483882Smlf 5588d483882Smlf /* 5598d483882Smlf * bar 4 offset to bus master status register 5608d483882Smlf */ 5618d483882Smlf #define BMISX_REG 2 5628d483882Smlf 5638d483882Smlf /* 5648d483882Smlf * bit fields for bus master status register 5658d483882Smlf */ 5668d483882Smlf #define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 5678d483882Smlf #define BMISX_IDERR 0x02 /* IDE DMA Error */ 5688d483882Smlf #define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 5698d483882Smlf 5708d483882Smlf /* 5718d483882Smlf * bus master status register bits to preserve 5728d483882Smlf */ 5738d483882Smlf #define BMISX_MASK 0xf8 5748d483882Smlf 5758d483882Smlf /* 5768d483882Smlf * bar4 offset to bus master PRD descriptor table 5778d483882Smlf */ 5788d483882Smlf #define BMIDTPX_REG 4 5798d483882Smlf 5808d483882Smlf 5818d483882Smlf /* 5828d483882Smlf * structure for a single entry in the PRD table 5838d483882Smlf * (physical region descriptor table) 5848d483882Smlf */ 5858d483882Smlf typedef struct prde { 5868d483882Smlf uint32_t p_address; /* physical address */ 5878d483882Smlf uint32_t p_count; /* byte count, EOT in high order bit */ 5888d483882Smlf } prde_t; 5898d483882Smlf 5908d483882Smlf 5918d483882Smlf #define PRDE_EOT ((uint_t)0x80000000) 5928d483882Smlf 593a78a9fafSMartin Faltesek #define NV_DMA_NSEGS 257 /* at least 1MB (4KB/pg * 256) + 1 if misaligned */ 5948d483882Smlf 5958d483882Smlf /* 5968d483882Smlf * ck804 and mcp55 both have 2 ports per controller 5978d483882Smlf */ 598a78a9fafSMartin Faltesek #define NV_NUM_PORTS 2 5998d483882Smlf 6008d483882Smlf /* 6018d483882Smlf * Number of slots to allocate in data nv_sata structures to handle 6028d483882Smlf * multiple commands at once. This does not reflect the capability of 6038d483882Smlf * the drive or the hardware, and in many cases will not match. 6048d483882Smlf * 1 or 32 slots are allocated, so in cases where the driver has NCQ 6058d483882Smlf * enabled but the drive doesn't support it, or supports fewer than 6068d483882Smlf * 32 slots, here may be an over allocation of memory. 6078d483882Smlf */ 6088d483882Smlf #ifdef NCQ 6098d483882Smlf #define NV_QUEUE_SLOTS 32 6108d483882Smlf #else 6118d483882Smlf #define NV_QUEUE_SLOTS 1 6128d483882Smlf #endif 6138d483882Smlf 614a9d5ae2eSPawel Wojcik #define NV_BM_64K_BOUNDARY 0x10000ull 615a9d5ae2eSPawel Wojcik 616a9d5ae2eSPawel Wojcik #define NV_MAX_INTR_PER_DEV 20 /* Empirical value */ 617a9d5ae2eSPawel Wojcik 6188d483882Smlf /* 619a9d5ae2eSPawel Wojcik * 1 second (in microseconds) 6208d483882Smlf */ 621a9d5ae2eSPawel Wojcik #define NV_ONE_SEC 1000000 6228d483882Smlf 623a9d5ae2eSPawel Wojcik /* 624a9d5ae2eSPawel Wojcik * 1 millisecond (in microseconds) 625a9d5ae2eSPawel Wojcik */ 626a9d5ae2eSPawel Wojcik #define NV_ONE_MSEC 1000 6278d483882Smlf 628a78a9fafSMartin Faltesek /* 629a78a9fafSMartin Faltesek * initial wait before checking for signature, in microseconds 630a78a9fafSMartin Faltesek */ 631a78a9fafSMartin Faltesek #define NV_WAIT_SIG 2500 632a78a9fafSMartin Faltesek 633a78a9fafSMartin Faltesek 6348d483882Smlf /* 635a9d5ae2eSPawel Wojcik * Length of port reset (microseconds) - SControl bit 0 set to 1 6368d483882Smlf */ 637a9d5ae2eSPawel Wojcik #define NV_RESET_LENGTH 1000 6388d483882Smlf 639a78a9fafSMartin Faltesek /* 640a78a9fafSMartin Faltesek * the maximum number of comresets to issue while 641a78a9fafSMartin Faltesek * performing link reset in nv_reset() 642a78a9fafSMartin Faltesek */ 643a78a9fafSMartin Faltesek #define NV_COMRESET_ATTEMPTS 3 6448d483882Smlf 6458d483882Smlf /* 646a78a9fafSMartin Faltesek * amount of time to wait for a signature in reset, in ms, before 647a78a9fafSMartin Faltesek * issuing another reset 6488d483882Smlf */ 649a78a9fafSMartin Faltesek #define NV_RETRY_RESET_SIG 5000 6508d483882Smlf 6518d483882Smlf /* 652a78a9fafSMartin Faltesek * the maximum number of resets to issue to gather signature 653a78a9fafSMartin Faltesek * before giving up 654a78a9fafSMartin Faltesek */ 655a78a9fafSMartin Faltesek #define NV_MAX_RESET_RETRY 8 656a78a9fafSMartin Faltesek 657a78a9fafSMartin Faltesek /* 658a78a9fafSMartin Faltesek * amount of time (us) to wait after receiving a link event 659a78a9fafSMartin Faltesek * before acting on it. This is because of flakey hardware 660a78a9fafSMartin Faltesek * sometimes issues the wrong, multiple, or out of order link 661a78a9fafSMartin Faltesek * events. 6628d483882Smlf */ 663a78a9fafSMartin Faltesek #define NV_LINK_EVENT_SETTLE 500000 6648d483882Smlf 665a9d5ae2eSPawel Wojcik /* 666a78a9fafSMartin Faltesek * The amount of time (ms) a link can be missing 667a78a9fafSMartin Faltesek * before declaring it removed. 668a9d5ae2eSPawel Wojcik */ 669a78a9fafSMartin Faltesek #define NV_LINK_EVENT_DOWN 200 6708d483882Smlf 6718d483882Smlf /* 6728d483882Smlf * nvp_state flags 6738d483882Smlf */ 674a78a9fafSMartin Faltesek #define NV_DEACTIVATED 0x001 675a78a9fafSMartin Faltesek #define NV_ABORTING 0x002 676a78a9fafSMartin Faltesek #define NV_FAILED 0x004 677a78a9fafSMartin Faltesek #define NV_RESET 0x008 678a78a9fafSMartin Faltesek #define NV_RESTORE 0x010 679a78a9fafSMartin Faltesek #define NV_LINK_EVENT 0x020 680a78a9fafSMartin Faltesek #define NV_ATTACH 0x040 681a78a9fafSMartin Faltesek #define NV_HOTPLUG 0x080 682a78a9fafSMartin Faltesek 683a78a9fafSMartin Faltesek 684a78a9fafSMartin Faltesek /* 685a78a9fafSMartin Faltesek * flags for nv_report_link_event() 686a78a9fafSMartin Faltesek */ 687a78a9fafSMartin Faltesek #define NV_ADD_DEV 0 688a78a9fafSMartin Faltesek #define NV_REM_DEV 1 6898d483882Smlf 6908d483882Smlf /* 6918d483882Smlf * nvc_state flags 6928d483882Smlf */ 6938d483882Smlf #define NV_CTRL_SUSPEND 0x1 6948d483882Smlf 6958d483882Smlf 6968d483882Smlf /* 6975b439bedSPraveen Kumar Dasaraju Rama * flags for ck804_set_intr/mcp5x_set_intr 6988d483882Smlf */ 6998d483882Smlf #define NV_INTR_DISABLE 0x1 7008d483882Smlf #define NV_INTR_ENABLE 0x2 7018d483882Smlf #define NV_INTR_CLEAR_ALL 0x4 70219397407SSherry Moore #define NV_INTR_DISABLE_NON_BLOCKING 0x8 7038d483882Smlf 7048d483882Smlf 7058d483882Smlf #define NV_BYTES_PER_SEC 512 7068d483882Smlf 7078d483882Smlf #define NV_WAIT_REG_CHECK 10 /* 10 microseconds */ 7088d483882Smlf #define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */ 7098d483882Smlf #define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */ 7105b439bedSPraveen Kumar Dasaraju Rama #define MCP5X_INT_CLEAR 0xffff /* clear all interrupts */ 7118d483882Smlf 7128d483882Smlf /* 7138d483882Smlf * definition labels for the BAR registers 7148d483882Smlf */ 7158d483882Smlf #define NV_BAR_0 0 /* chan 0 task file regs */ 7168d483882Smlf #define NV_BAR_1 1 /* chan 0 status reg */ 7178d483882Smlf #define NV_BAR_2 2 /* chan 1 task file regs */ 7188d483882Smlf #define NV_BAR_3 3 /* chan 1 status reg */ 7198d483882Smlf #define NV_BAR_4 4 /* bus master regs */ 7208d483882Smlf #define NV_BAR_5 5 /* extra regs mostly SATA related */ 7218d483882Smlf 7228d483882Smlf /* 7238d483882Smlf * transform seconds to microseconds 7248d483882Smlf */ 7258d483882Smlf #define NV_SEC2USEC(x) x * MICROSEC 7268d483882Smlf 7278d483882Smlf 7288d483882Smlf /* 7298d483882Smlf * ck804 maps in task file regs into bar 5. These are 7308d483882Smlf * only used to identify ck804, therefore only this reg is 7318d483882Smlf * listed here. 7328d483882Smlf */ 7338d483882Smlf #define NV_BAR5_TRAN_LEN_CH_X 0x518 7348d483882Smlf 7358d483882Smlf /* 7368d483882Smlf * if after this many iterations through the interrupt 7378d483882Smlf * processing loop, declare the interrupt wedged and 7388d483882Smlf * disable. 7398d483882Smlf */ 7408d483882Smlf #define NV_MAX_INTR_LOOP 10 7418d483882Smlf 7428d483882Smlf /* 7438d483882Smlf * flag values for nv_copy_regs_out 7448d483882Smlf */ 7458d483882Smlf #define NV_COPY_COMPLETE 0x01 /* normal command completion */ 7468d483882Smlf #define NV_COPY_ERROR 0x02 /* error, did not complete ok */ 7478d483882Smlf #define NV_COPY_SSREGS 0x04 /* SS port registers */ 7488d483882Smlf 7493f318a28SAlan Perry #ifdef SGPIO_SUPPORT 750a150bf85SAlan Perry #define NV_MAX_CBPS 16 /* Maximum # of Control Block */ 751a150bf85SAlan Perry /* Pointers. Corresponds to */ 752a150bf85SAlan Perry /* each MCP55 and IO55 */ 7533f318a28SAlan Perry #define SGPIO_LOOP_WAIT_USECS 62500 /* 1/16 second (in usecs) */ 7543f318a28SAlan Perry #define SGPIO_TQ_NAME_LEN 32 7553f318a28SAlan Perry 7563f318a28SAlan Perry /* 7573f318a28SAlan Perry * The drive number format is ccp (binary). 7583f318a28SAlan Perry * cc is the controller number (0-based number) 7593f318a28SAlan Perry * p is the port number (0 or 1) 7603f318a28SAlan Perry */ 7613f318a28SAlan Perry #define SGP_DRV_TO_PORT(d) ((d) & 1) 7623f318a28SAlan Perry #define SGP_DRV_TO_CTLR(d) ((d) >> 1) 7633f318a28SAlan Perry #define SGP_CTLR_PORT_TO_DRV(c, p) (((c) << 1) | ((p) & 1)) 7643f318a28SAlan Perry #endif 7658d483882Smlf 7668d483882Smlf #ifdef __cplusplus 7678d483882Smlf } 7688d483882Smlf #endif 7698d483882Smlf 7708d483882Smlf #endif /* _NV_SATA_H */ 771