xref: /illumos-gate/usr/src/uts/common/sys/pci.h (revision 7687d0d8)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  * Copyright 2019, Joyent, Inc.
25  */
26 
27 #ifndef	_SYS_PCI_H
28 #define	_SYS_PCI_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 /*
35  * PCI Configuration Header offsets
36  */
37 #define	PCI_CONF_VENID		0x0	/* vendor id, 2 bytes */
38 #define	PCI_CONF_DEVID		0x2	/* device id, 2 bytes */
39 #define	PCI_CONF_COMM		0x4	/* command register, 2 bytes */
40 #define	PCI_CONF_STAT		0x6	/* status register, 2 bytes */
41 #define	PCI_CONF_REVID		0x8	/* revision id, 1 byte */
42 #define	PCI_CONF_PROGCLASS	0x9	/* programming class code, 1 byte */
43 #define	PCI_CONF_SUBCLASS	0xA	/* sub-class code, 1 byte */
44 #define	PCI_CONF_BASCLASS	0xB	/* basic class code, 1 byte */
45 #define	PCI_CONF_CACHE_LINESZ	0xC	/* cache line size, 1 byte */
46 #define	PCI_CONF_LATENCY_TIMER	0xD	/* latency timer, 1 byte */
47 #define	PCI_CONF_HEADER		0xE	/* header type, 1 byte */
48 #define	PCI_CONF_BIST		0xF	/* builtin self test, 1 byte */
49 
50 /*
51  * Header type 0 offsets
52  */
53 #define	PCI_CONF_BASE0		0x10	/* base register 0, 4 bytes */
54 #define	PCI_CONF_BASE1		0x14	/* base register 1, 4 bytes */
55 #define	PCI_CONF_BASE2		0x18	/* base register 2, 4 bytes */
56 #define	PCI_CONF_BASE3		0x1c	/* base register 3, 4 bytes */
57 #define	PCI_CONF_BASE4		0x20	/* base register 4, 4 bytes */
58 #define	PCI_CONF_BASE5		0x24	/* base register 5, 4 bytes */
59 #define	PCI_CONF_CIS		0x28	/* Cardbus CIS Pointer */
60 #define	PCI_CONF_SUBVENID	0x2c	/* Subsystem Vendor ID */
61 #define	PCI_CONF_SUBSYSID	0x2e	/* Subsystem ID */
62 #define	PCI_CONF_ROM		0x30	/* ROM base register, 4 bytes */
63 #define	PCI_CONF_CAP_PTR	0x34	/* capabilities pointer, 1 byte */
64 #define	PCI_CONF_ILINE		0x3c	/* interrupt line, 1 byte */
65 #define	PCI_CONF_IPIN		0x3d	/* interrupt pin, 1 byte */
66 #define	PCI_CONF_MIN_G		0x3e	/* minimum grant, 1 byte */
67 #define	PCI_CONF_MAX_L		0x3f	/* maximum grant, 1 byte */
68 
69 /*
70  * PCI to PCI bridge configuration space header format
71  */
72 #define	PCI_BCNF_PRIBUS		0x18	/* primary bus number */
73 #define	PCI_BCNF_SECBUS		0x19	/* secondary bus number */
74 #define	PCI_BCNF_SUBBUS		0x1a	/* subordinate bus number */
75 #define	PCI_BCNF_LATENCY_TIMER	0x1b
76 #define	PCI_BCNF_IO_BASE_LOW	0x1c
77 #define	PCI_BCNF_IO_LIMIT_LOW	0x1d
78 #define	PCI_BCNF_SEC_STATUS	0x1e
79 #define	PCI_BCNF_MEM_BASE	0x20
80 #define	PCI_BCNF_MEM_LIMIT	0x22
81 #define	PCI_BCNF_PF_BASE_LOW	0x24
82 #define	PCI_BCNF_PF_LIMIT_LOW	0x26
83 #define	PCI_BCNF_PF_BASE_HIGH	0x28
84 #define	PCI_BCNF_PF_LIMIT_HIGH	0x2c
85 #define	PCI_BCNF_IO_BASE_HI	0x30
86 #define	PCI_BCNF_IO_LIMIT_HI	0x32
87 #define	PCI_BCNF_CAP_PTR	0x34
88 #define	PCI_BCNF_ROM		0x38
89 #define	PCI_BCNF_ILINE		0x3c
90 #define	PCI_BCNF_IPIN		0x3d
91 #define	PCI_BCNF_BCNTRL		0x3e
92 
93 #define	PCI_BCNF_BASE_NUM	0x2
94 
95 /*
96  * PCI to PCI bridge control register (0x3e) format
97  */
98 #define	PCI_BCNF_BCNTRL_PARITY_ENABLE	0x1
99 #define	PCI_BCNF_BCNTRL_SERR_ENABLE	0x2
100 #define	PCI_BCNF_BCNTRL_ISA_ENABLE	0x4
101 #define	PCI_BCNF_BCNTRL_VGA_ENABLE	0x8
102 #define	PCI_BCNF_BCNTRL_MAST_AB_MODE	0x20
103 #define	PCI_BCNF_BCNTRL_DTO_STAT	0x400
104 
105 #define	PCI_BCNF_BCNTRL_RESET		0x0040
106 #define	PCI_BCNF_BCNTRL_B2B_ENAB	0x0080
107 
108 #define	PCI_BCNF_IO_MASK	0xf0
109 #define	PCI_BCNF_IO_SHIFT	8
110 #define	PCI_BCNF_MEM_MASK	0xfff0
111 #define	PCI_BCNF_MEM_SHIFT	16
112 #define	PCI_BCNF_ADDR_MASK	0x000f
113 
114 #define	PCI_BCNF_IO_32BIT	0x01
115 #define	PCI_BCNF_PF_MEM_64BIT	0x01
116 
117 /*
118  * Header type 2 (Cardbus) offsets
119  */
120 #define	PCI_CBUS_SOCK_REG	0x10	/* Cardbus socket regs, 4 bytes */
121 #define	PCI_CBUS_CAP_PTR	0x14	/* Capability ptr, 1 byte */
122 #define	PCI_CBUS_RESERVED1	0x15	/* Reserved, 1 byte */
123 #define	PCI_CBUS_SEC_STATUS	0x16	/* Secondary status, 2 bytes */
124 #define	PCI_CBUS_PCI_BUS_NO	0x18	/* PCI bus number, 1 byte */
125 #define	PCI_CBUS_CBUS_NO	0x19	/* Cardbus bus number, 1 byte */
126 #define	PCI_CBUS_SUB_BUS_NO	0x1a	/* Subordinate bus number, 1 byte */
127 #define	PCI_CBUS_LATENCY_TIMER	0x1b	/* Cardbus latency timer, 1 byte */
128 #define	PCI_CBUS_MEM_BASE0	0x1c	/* Memory base reg 0, 4 bytes */
129 #define	PCI_CBUS_MEM_LIMIT0	0x20	/* Memory limit reg 0, 4 bytes */
130 #define	PCI_CBUS_MEM_BASE1	0x24	/* Memory base reg 1, 4 bytes */
131 #define	PCI_CBUS_MEM_LIMIT1	0x28	/* Memory limit reg 1, 4 bytes */
132 #define	PCI_CBUS_IO_BASE0	0x2c	/* IO base reg 0, 4 bytes */
133 #define	PCI_CBUS_IO_LIMIT0	0x30	/* IO limit reg 0, 4 bytes */
134 #define	PCI_CBUS_IO_BASE1	0x34	/* IO base reg 1, 4 bytes */
135 #define	PCI_CBUS_IO_LIMIT1	0x38	/* IO limit reg 1, 4 bytes */
136 #define	PCI_CBUS_ILINE		0x3c	/* interrupt line, 1 byte */
137 #define	PCI_CBUS_IPIN		0x3d	/* interrupt pin, 1 byte */
138 #define	PCI_CBUS_BRIDGE_CTRL	0x3e	/* Bridge control, 2 bytes */
139 #define	PCI_CBUS_SUBVENID	0x40	/* Subsystem Vendor ID, 2 bytes */
140 #define	PCI_CBUS_SUBSYSID	0x42	/* Subsystem ID, 2 bytes */
141 #define	PCI_CBUS_LEG_MODE_ADDR	0x44	/* PCCard 16bit IF legacy mode addr */
142 
143 #define	PCI_CBUS_BASE_NUM	0x1	/* number of base registers */
144 
145 /*
146  * PCI command register bits
147  */
148 #define	PCI_COMM_IO		0x1	/* I/O access enable */
149 #define	PCI_COMM_MAE		0x2	/* memory access enable */
150 #define	PCI_COMM_ME		0x4	/* master enable */
151 #define	PCI_COMM_SPEC_CYC	0x8
152 #define	PCI_COMM_MEMWR_INVAL	0x10
153 #define	PCI_COMM_PALETTE_SNOOP	0x20
154 #define	PCI_COMM_PARITY_DETECT	0x40
155 #define	PCI_COMM_WAIT_CYC_ENAB	0x80
156 #define	PCI_COMM_SERR_ENABLE	0x100
157 #define	PCI_COMM_BACK2BACK_ENAB	0x200
158 #define	PCI_COMM_INTX_DISABLE	0x400	/* INTx emulation disable */
159 
160 /*
161  * PCI Interrupt pin value
162  */
163 #define	PCI_INTA	1
164 #define	PCI_INTB	2
165 #define	PCI_INTC	3
166 #define	PCI_INTD	4
167 
168 /*
169  * PCI status register bits
170  */
171 #define	PCI_STAT_READY		0x1	/* Immediate Readiness */
172 #define	PCI_STAT_INTR		0x8	/* Interrupt state */
173 #define	PCI_STAT_CAP		0x10	/* Implements Capabilities */
174 #define	PCI_STAT_66MHZ		0x20	/* 66 MHz capable */
175 #define	PCI_STAT_UDF		0x40	/* UDF supported */
176 #define	PCI_STAT_FBBC		0x80	/* Fast Back-to-Back Capable */
177 #define	PCI_STAT_S_PERROR	0x100	/* Data Parity Reported */
178 #define	PCI_STAT_DEVSELT	0x600	/* Device select timing */
179 #define	PCI_STAT_S_TARG_AB	0x800	/* Signaled Target Abort */
180 #define	PCI_STAT_R_TARG_AB	0x1000	/* Received Target Abort */
181 #define	PCI_STAT_R_MAST_AB	0x2000	/* Received Master Abort */
182 #define	PCI_STAT_S_SYSERR	0x4000	/* Signaled System Error */
183 #define	PCI_STAT_PERROR		0x8000	/* Detected Parity Error */
184 
185 /*
186  * DEVSEL timing values
187  */
188 #define	PCI_STAT_DEVSELT_FAST	0x0000
189 #define	PCI_STAT_DEVSELT_MEDIUM	0x0200
190 #define	PCI_STAT_DEVSELT_SLOW	0x0400
191 
192 /*
193  * BIST values
194  */
195 #define	PCI_BIST_SUPPORTED	0x80
196 #define	PCI_BIST_GO		0x40
197 #define	PCI_BIST_RESULT_M	0x0f
198 #define	PCI_BIST_RESULT_OK	0x00
199 
200 /*
201  * PCI class codes
202  */
203 #define	PCI_CLASS_NONE		0x0	/* class code for pre-2.0 devices */
204 #define	PCI_CLASS_MASS		0x1	/* Mass storage Controller class */
205 #define	PCI_CLASS_NET		0x2	/* Network Controller class */
206 #define	PCI_CLASS_DISPLAY	0x3	/* Display Controller class */
207 #define	PCI_CLASS_MM		0x4	/* Multimedia Controller class */
208 #define	PCI_CLASS_MEM		0x5	/* Memory Controller class */
209 #define	PCI_CLASS_BRIDGE	0x6	/* Bridge Controller class */
210 #define	PCI_CLASS_COMM		0x7	/* Communications Controller class */
211 #define	PCI_CLASS_PERIPH	0x8	/* Peripheral Controller class */
212 #define	PCI_CLASS_INPUT		0x9	/* Input Device class */
213 #define	PCI_CLASS_DOCK		0xa	/* Docking Station class */
214 #define	PCI_CLASS_PROCESSOR	0xb	/* Processor class */
215 #define	PCI_CLASS_SERIALBUS	0xc	/* Serial Bus class */
216 #define	PCI_CLASS_WIRELESS	0xd	/* Wireless Controller class */
217 #define	PCI_CLASS_INTIO		0xe	/* Intelligent IO Controller class */
218 #define	PCI_CLASS_SATELLITE	0xf	/* Satellite Communication class */
219 #define	PCI_CLASS_CRYPT		0x10	/* Encrytion/Decryption class */
220 #define	PCI_CLASS_SIGNAL	0x11	/* Signal Processing class */
221 
222 /*
223  * PCI Sub-class codes - base class 0x0 (no new devices should use this code).
224  */
225 #define	PCI_NONE_NOTVGA		0x0	/* All devices except VGA compatible */
226 #define	PCI_NONE_VGA		0x1	/* VGA compatible */
227 
228 /*
229  * PCI Sub-class codes - base class 0x1 (mass storage controllers)
230  */
231 #define	PCI_MASS_SCSI		0x0	/* SCSI bus Controller */
232 #define	PCI_MASS_IDE		0x1	/* IDE Controller */
233 #define	PCI_MASS_FD		0x2	/* Floppy disk Controller */
234 #define	PCI_MASS_IPI		0x3	/* IPI bus Controller */
235 #define	PCI_MASS_RAID		0x4	/* RAID Controller */
236 #define	PCI_MASS_ATA		0x5	/* ATA Controller */
237 #define	PCI_MASS_SATA		0x6	/* Serial ATA */
238 #define	PCI_MASS_SAS		0x7	/* Serial Attached SCSI (SAS) Cntrlr */
239 #define	PCI_MASS_NVME		0x8	/* Non-Volatile memory controller */
240 #define	PCI_MASS_OTHER		0x80	/* Other Mass Storage Controller */
241 
242 /*
243  * programming interface for IDE (subclass 1)
244  */
245 #define	PCI_IDE_IF_NATIVE_PRI	0x1	/* primary channel is native */
246 #define	PCI_IDE_IF_PROG_PRI	0x2	/* primary can operate in either mode */
247 #define	PCI_IDE_IF_NATIVE_SEC	0x4	/* secondary channel is native */
248 #define	PCI_IDE_IF_PROG_SEC	0x8	/* sec. can operate in either mode */
249 #define	PCI_IDE_IF_MASK		0xf	/* programming interface mask */
250 
251 
252 /*
253  * programming interface for ATA (subclass 5)
254  */
255 #define	PCI_ATA_IF_SINGLE_DMA	0x20	/* ATA controller with single DMA */
256 #define	PCI_ATA_IF_CHAINED_DMA	0x30	/* ATA controller with chained DMA */
257 
258 /*
259  * programming interface for ATA (subclass 6) for SATA
260  */
261 #define	PCI_SATA_VS_INTERFACE	0x0	/* SATA Ctlr Vendor Specific Intfc */
262 #define	PCI_SATA_AHCI_INTERFACE	0x1	/* SATA Ctlr AHCI 1.0 Interface */
263 #define	PCI_SATA_SSB_INTERFACE	0x2	/* Serial Storage Bus Interface */
264 
265 /*
266  * programming interface for ATA (subclass 7) for SAS
267  */
268 #define	PCI_SAS_CONTROLLER	0x0	/* SAS Controller */
269 #define	PCI_SAS_BUS_INTERFACE	0x1	/* Serial Storage Bus Interface */
270 
271 /*
272  * PCI Sub-class codes - base class 0x2 (Network controllers)
273  */
274 #define	PCI_NET_ENET		0x0	/* Ethernet Controller */
275 #define	PCI_NET_TOKEN		0x1	/* Token Ring Controller */
276 #define	PCI_NET_FDDI		0x2	/* FDDI Controller */
277 #define	PCI_NET_ATM		0x3	/* ATM Controller */
278 #define	PCI_NET_ISDN		0x4	/* ISDN Controller */
279 #define	PCI_NET_WFIP		0x5	/* WorldFip Controller */
280 #define	PCI_NET_PICMG		0x6	/* PICMG 2.14 Multi Computing */
281 #define	PCI_NET_OTHER		0x80	/* Other Network Controller */
282 
283 /*
284  * PCI Sub-class codes - base class 03 (display controllers)
285  */
286 #define	PCI_DISPLAY_VGA		0x0	/* VGA device */
287 #define	PCI_DISPLAY_XGA		0x1	/* XGA device */
288 #define	PCI_DISPLAY_3D		0x2	/* 3D controller */
289 #define	PCI_DISPLAY_OTHER	0x80	/* Other Display Device */
290 
291 /*
292  * programming interface for display for display class (subclass 0) VGA ctrlrs
293  */
294 #define	PCI_DISPLAY_IF_VGA	0x0	/* VGA compatible */
295 #define	PCI_DISPLAY_IF_8514	0x1	/* 8514 compatible */
296 
297 /*
298  * PCI Sub-class codes - base class 0x4 (multi-media devices)
299  */
300 #define	PCI_MM_VIDEO		0x0	/* Video device */
301 #define	PCI_MM_AUDIO		0x1	/* Audio device */
302 #define	PCI_MM_TELEPHONY	0x2	/* Computer Telephony device */
303 #define	PCI_MM_MIXED_MODE	0x3	/* Mixed Mode device */
304 #define	PCI_MM_OTHER		0x80	/* Other Multimedia Device */
305 
306 /*
307  * PCI Sub-class codes - base class 0x5 (memory controllers)
308  */
309 #define	PCI_MEM_RAM		0x0	/* RAM device */
310 #define	PCI_MEM_FLASH		0x1	/* FLASH device */
311 #define	PCI_MEM_OTHER		0x80	/* Other Memory Controller */
312 
313 /*
314  * PCI Sub-class codes - base class 0x6 (Bridge devices)
315  */
316 #define	PCI_BRIDGE_HOST		0x0	/* Host/PCI Bridge */
317 #define	PCI_BRIDGE_ISA		0x1	/* PCI/ISA Bridge */
318 #define	PCI_BRIDGE_EISA		0x2	/* PCI/EISA Bridge */
319 #define	PCI_BRIDGE_MC		0x3	/* PCI/MC Bridge */
320 #define	PCI_BRIDGE_PCI		0x4	/* PCI/PCI Bridge */
321 #define	PCI_BRIDGE_PCMCIA	0x5	/* PCI/PCMCIA Bridge */
322 #define	PCI_BRIDGE_NUBUS	0x6	/* PCI/NUBUS Bridge */
323 #define	PCI_BRIDGE_CARDBUS	0x7	/* PCI/CARDBUS Bridge */
324 #define	PCI_BRIDGE_RACE		0x8	/* RACE-way Bridge */
325 #define	PCI_BRIDGE_STPCI	0x9	/* Semi-transparent PCI/PCI Bridge */
326 #define	PCI_BRIDGE_IB		0xA	/* InfiniBand/PCI host Bridge */
327 #define	PCI_BRIDGE_AS		0xB	/* AS/PCI host Bridge */
328 #define	PCI_BRIDGE_OTHER	0x80	/* PCI/Other Bridge Device */
329 
330 /*
331  * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge
332  */
333 #define	PCI_BRIDGE_PCI_IF_PCI2PCI	0x0	/* PCI-PCI bridge */
334 #define	PCI_BRIDGE_PCI_IF_SUBDECODE	0x1	/* Subtractive Decode */
335 						/* PCI/PCI bridge */
336 
337 /*
338  * programming interface for Bridges class 0x6 (subclass 08) RACEway bridge
339  */
340 #define	PCI_BRIDGE_RACE_IF_TRANSPARENT	0x0	/* Transport mode */
341 #define	PCI_BRIDGE_RACE_IF_ENDPOINT	0x1	/* Endpoint mode */
342 
343 /*
344  * programming interface for Bridges class 0x6 (subclass 09)
345  * Semi-transparent PCI-to-PCI bridge
346  */
347 #define	PCI_BRIDGE_STPCI_IF_PRIMARY	0x40	/* primary PCI side bus */
348 						/* facing system processor */
349 #define	PCI_BRIDGE_STPCI_IF_SECONDARY	0x80	/* secondary PCI side bus */
350 						/* facing system processor */
351 
352 /*
353  * programming interface for Bridges class 0x6 (subclass 0B) AS bridge
354  */
355 #define	PCI_BRIDGE_AS_CUSTOM_INTFC	0x0	/* Custom interface */
356 #define	PCI_BRIDGE_AS_PORTAL_INTFC	0x1	/* ASI-SIG Portal Interface */
357 
358 /*
359  * PCI Sub-class codes - base class 0x7 (communication devices)
360  */
361 #define	PCI_COMM_GENERIC_XT	0x0	/* XT Compatible Serial Controller */
362 #define	PCI_COMM_PARALLEL	0x1	/* Parallel Port Controller */
363 #define	PCI_COMM_MSC		0x2	/* Multiport Serial Controller */
364 #define	PCI_COMM_MODEM		0x3	/* Modem Controller */
365 #define	PCI_COMM_GPIB		0x4	/* GPIB Controller */
366 #define	PCI_COMM_SMARTCARD	0x5	/* Smart Card Controller */
367 #define	PCI_COMM_OTHER		0x80	/* Other Communications Controller */
368 
369 /*
370  * Programming interfaces for class 0x7 / subclass 0x0 (Serial)
371  */
372 #define	PCI_COMM_SERIAL_IF_GENERIC	0x0	/* Generic XT-compat serial */
373 #define	PCI_COMM_SERIAL_IF_16450	0x1	/* 16450-compat serial ctrlr */
374 #define	PCI_COMM_SERIAL_IF_16550	0x2	/* 16550-compat serial ctrlr */
375 #define	PCI_COMM_SERIAL_IF_16650	0x3	/* 16650-compat serial ctrlr */
376 #define	PCI_COMM_SERIAL_IF_16750	0x4	/* 16750-compat serial ctrlr */
377 #define	PCI_COMM_SERIAL_IF_16850	0x5	/* 16850-compat serial ctrlr */
378 #define	PCI_COMM_SERIAL_IF_16950	0x6	/* 16950-compat serial ctrlr */
379 
380 /*
381  * Programming interfaces for class 0x7 / subclass 0x1 (Parallel)
382  */
383 #define	PCI_COMM_PARALLEL_IF_GENERIC	0x0	/* Generic Parallel port */
384 #define	PCI_COMM_PARALLEL_IF_BIDIRECT	0x1	/* Bi-directional Parallel */
385 #define	PCI_COMM_PARALLEL_IF_ECP	0x2	/* ECP 1.X Parallel port */
386 #define	PCI_COMM_PARALLEL_IF_1284	0x3	/* IEEE 1284 Parallel port */
387 #define	PCI_COMM_PARALLEL_IF_1284_TARG	0xFE	/* IEEE 1284 target device */
388 
389 /*
390  * Programming interfaces for class 0x7 / subclass 0x3 (Modem)
391  */
392 #define	PCI_COMM_MODEM_IF_GENERIC	0x0	/* Generic Modem */
393 #define	PCI_COMM_MODEM_IF_HAYES_16450	0x1	/* Hayes 16450-compat Modem */
394 #define	PCI_COMM_MODEM_IF_HAYES_16550	0x2	/* Hayes 16550-compat Modem */
395 #define	PCI_COMM_MODEM_IF_HAYES_16650	0x3	/* Hayes 16650-compat Modem */
396 #define	PCI_COMM_MODEM_IF_HAYES_16750	0x4	/* Hayes 16750-compat Modem */
397 
398 /*
399  * PCI Sub-class codes - base class 0x8
400  */
401 #define	PCI_PERIPH_PIC		0x0	/* Generic PIC */
402 #define	PCI_PERIPH_DMA		0x1	/* Generic DMA Controller */
403 #define	PCI_PERIPH_TIMER	0x2	/* Generic System Timer Controller */
404 #define	PCI_PERIPH_RTC		0x3	/* Generic RTC Controller */
405 #define	PCI_PERIPH_HPC		0x4	/* Generic PCI Hot-Plug Controller */
406 #define	PCI_PERIPH_SD_HC	0x5	/* SD Host Controller */
407 #define	PCI_PERIPH_IOMMU	0x6	/* IOMMU */
408 #define	PCI_PERIPH_OTHER	0x80	/* Other System Peripheral */
409 
410 /*
411  * Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller)
412  */
413 #define	PCI_PERIPH_PIC_IF_GENERIC	0x0	/* Generic 8259 APIC */
414 #define	PCI_PERIPH_PIC_IF_ISA		0x1	/* ISA PIC */
415 #define	PCI_PERIPH_PIC_IF_EISA		0x2	/* EISA PIC */
416 #define	PCI_PERIPH_PIC_IF_IO_APIC	0x10	/* I/O APIC interrupt ctrlr */
417 #define	PCI_PERIPH_PIC_IF_IOX_APIC	0x20	/* I/O(x) APIC intr ctrlr */
418 
419 /*
420  * Programming interfaces for class 0x8 / subclass 0x1 (DMA controller)
421  */
422 #define	PCI_PERIPH_DMA_IF_GENERIC	0x0	/* Generic 8237 DMA ctrlr */
423 #define	PCI_PERIPH_DMA_IF_ISA		0x1	/* ISA DMA ctrlr */
424 #define	PCI_PERIPH_DMA_IF_EISA		0x2	/* EISA DMA ctrlr */
425 
426 /*
427  * Programming interfaces for class 0x8 / subclass 0x2 (timer)
428  */
429 #define	PCI_PERIPH_TIMER_IF_GENERIC	0x0	/* Generic 8254 system timer */
430 #define	PCI_PERIPH_TIMER_IF_ISA		0x1	/* ISA system timers */
431 #define	PCI_PERIPH_TIMER_IF_EISA	0x2	/* EISA system timers (two) */
432 #define	PCI_PERIPH_TIMER_IF_HPET	0x3	/* High Perf Event timer */
433 
434 /*
435  * Programming interfaces for class 0x8 / subclass 0x3 (realtime clock)
436  */
437 #define	PCI_PERIPH_RTC_IF_GENERIC	0x0	/* Generic RTC controller */
438 #define	PCI_PERIPH_RTC_IF_ISA		0x1	/* ISA RTC controller */
439 
440 /*
441  * PCI Sub-class codes - base class 0x9
442  */
443 #define	PCI_INPUT_KEYBOARD	0x0	/* Keyboard Controller */
444 #define	PCI_INPUT_DIGITIZ	0x1	/* Digitizer (Pen) */
445 #define	PCI_INPUT_MOUSE		0x2	/* Mouse Controller */
446 #define	PCI_INPUT_SCANNER	0x3	/* Scanner Controller */
447 #define	PCI_INPUT_GAMEPORT	0x4	/* Gameport Controller */
448 #define	PCI_INPUT_OTHER		0x80	/* Other Input Controller */
449 
450 /*
451  * Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller)
452  */
453 #define	PCI_INPUT_GAMEPORT_IF_GENERIC	0x00	/* Generic controller */
454 #define	PCI_INPUT_GAMEPORT_IF_LEGACY	0x10	/* Legacy controller */
455 
456 /*
457  * PCI Sub-class codes - base class 0xA
458  */
459 #define	PCI_DOCK_GENERIC	0x00	/* Generic Docking Station */
460 #define	PCI_DOCK_OTHER		0x80	/* Other Type of Docking Station */
461 
462 /*
463  * PCI Sub-class codes - base class 0xB
464  */
465 #define	PCI_PROCESSOR_386	0x0	/* 386 */
466 #define	PCI_PROCESSOR_486	0x1	/* 486 */
467 #define	PCI_PROCESSOR_PENT	0x2	/* Pentium */
468 #define	PCI_PROCESSOR_ALPHA	0x10	/* Alpha */
469 #define	PCI_PROCESSOR_POWERPC	0x20	/* PowerPC */
470 #define	PCI_PROCESSOR_MIPS	0x30	/* MIPS */
471 #define	PCI_PROCESSOR_COPROC	0x40	/* Co-processor */
472 #define	PCI_PROCESSOR_OTHER	0x80	/* Other processors */
473 
474 /*
475  * PCI Sub-class codes - base class 0xC (Serial Controllers)
476  */
477 #define	PCI_SERIAL_FIRE		0x0	/* FireWire (IEEE 1394) */
478 #define	PCI_SERIAL_ACCESS	0x1	/* ACCESS.bus */
479 #define	PCI_SERIAL_SSA		0x2	/* SSA */
480 #define	PCI_SERIAL_USB		0x3	/* Universal Serial Bus */
481 #define	PCI_SERIAL_FIBRE	0x4	/* Fibre Channel */
482 #define	PCI_SERIAL_SMBUS	0x5	/* System Management Bus */
483 #define	PCI_SERIAL_IB		0x6	/* InfiniBand */
484 #define	PCI_SERIAL_IPMI		0x7	/* IPMI */
485 #define	PCI_SERIAL_SERCOS	0x8	/* SERCOS Interface Std (IEC 61491) */
486 #define	PCI_SERIAL_CANBUS	0x9	/* CANbus */
487 #define	PCI_SERIAL_OTHER	0x80	/* Other Serial Bus Controllers */
488 
489 /*
490  * Programming interfaces for class 0xC / subclass 0x0 (Firewire)
491  */
492 #define	PCI_SERIAL_FIRE_WIRE		0x00	/* IEEE 1394 (Firewire) */
493 #define	PCI_SERIAL_FIRE_1394_HCI	0x10	/* 1394 OpenHCI Host Cntrlr */
494 
495 /*
496  * Programming interfaces for class 0xC / subclass 0x3 (USB controller)
497  */
498 #define	PCI_SERIAL_USB_IF_UHCI		0x00	/* UHCI Compliant */
499 #define	PCI_SERIAL_USB_IF_OHCI		0x10	/* OHCI Compliant */
500 #define	PCI_SERIAL_USB_IF_EHCI		0x20	/* EHCI Compliant */
501 #define	PCI_SERIAL_USB_IF_GENERIC	0x80	/* no specific HCD */
502 #define	PCI_SERIAL_USB_IF_DEVICE	0xFE	/* not a HCD */
503 
504 /*
505  * Programming interfaces for class 0xC / subclass 0x7 (IPMI controller)
506  */
507 #define	PCI_SERIAL_IPMI_IF_SMIC		0x0	/* SMIC Interface */
508 #define	PCI_SERIAL_IPMI_IF_KBD		0x1	/* Keyboard Ctrl Style Intfc */
509 #define	PCI_SERIAL_IPMI_IF_BTI		0x2	/* Block Transfer Interface */
510 
511 /*
512  * PCI Sub-class codes - base class 0xD (Wireless controllers)
513  */
514 #define	PCI_WIRELESS_IRDA		0x0	/* iRDA Compatible Controller */
515 #define	PCI_WIRELESS_IR			0x1	/* Consumer IR Controller */
516 #define	PCI_WIRELESS_RF			0x10	/* RF Controller */
517 #define	PCI_WIRELESS_BLUETOOTH		0x11	/* Bluetooth Controller */
518 #define	PCI_WIRELESS_BROADBAND		0x12	/* Broadband Controller */
519 #define	PCI_WIRELESS_80211A		0x20	/* Ethernet 802.11a 5 GHz */
520 #define	PCI_WIRELESS_80211B		0x21	/* Ethernet 802.11b 2.4 GHz */
521 #define	PCI_WIRELESS_OTHER		0x80	/* Other Wireless Controllers */
522 
523 /*
524  * Programming interfaces for class 0xD / subclass 0x1 (Consumer IR controller)
525  */
526 #define	PCI_WIRELESS_IR_CONSUMER	0x00	/* Consumer IR Controller */
527 #define	PCI_WIRELESS_IR_UWB_RC		0x10	/* UWB Radio Controller */
528 
529 /*
530  * PCI Sub-class codes - base class 0xE (Intelligent I/O controllers)
531  */
532 #define	PCI_INTIO_MSG_FIFO		0x0	/* Message FIFO at off 40h */
533 #define	PCI_INTIO_I20			0x1	/* I20 Arch Spec 1.0 */
534 
535 /*
536  * PCI Sub-class codes - base class 0xF (Satellite Communication controllers)
537  */
538 #define	PCI_SATELLITE_COMM_TV		0x01	/* TV */
539 #define	PCI_SATELLITE_COMM_AUDIO	0x02	/* Audio */
540 #define	PCI_SATELLITE_COMM_VOICE	0x03	/* Voice */
541 #define	PCI_SATELLITE_COMM_DATA		0x04	/* DATA */
542 #define	PCI_SATELLITE_COMM_OTHER	0x80	/* Other Satelite Comm Cntrlr */
543 
544 /*
545  * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers)
546  */
547 #define	PCI_CRYPT_NETWORK		0x00	/* Network and Computing */
548 #define	PCI_CRYPT_ENTERTAINMENT		0x10	/* Entertainment en/decrypt */
549 #define	PCI_CRYPT_OTHER			0x80	/* Other en/decryption ctrlrs */
550 
551 /*
552  * PCI Sub-class codes - base class 0x11 (Signal Processing controllers)
553  */
554 #define	PCI_SIGNAL_DPIO			0x00	/* DPIO modules */
555 #define	PCI_SIGNAL_PERF_COUNTERS	0x01	/* Performance counters */
556 #define	PCI_SIGNAL_COMM_SYNC		0x10	/* Comm. synchronization plus */
557 						/* time and freq test ctrlr */
558 #define	PCI_SIGNAL_MANAGEMENT		0x20	/* Management card */
559 #define	PCI_SIGNAL_OTHER		0x80	/* DSP/DAP controller */
560 
561 /* PCI header decode */
562 #define	PCI_HEADER_MULTI	0x80	/* multi-function device */
563 #define	PCI_HEADER_ZERO		0x00	/* type zero PCI header */
564 #define	PCI_HEADER_ONE		0x01	/* type one PCI header */
565 #define	PCI_HEADER_TWO		0x02	/* type two PCI header */
566 #define	PCI_HEADER_PPB		PCI_HEADER_ONE  /* type one PCI to PCI Bridge */
567 #define	PCI_HEADER_CARDBUS	PCI_HEADER_TWO	/* type one PCI header */
568 
569 #define	PCI_HEADER_TYPE_M	0x7f  /* type mask for header */
570 
571 /*
572  * Base register bit definitions.
573  */
574 #define	PCI_BASE_SPACE_M    0x1  /* memory space indicator */
575 #define	PCI_BASE_SPACE_IO   0x1   /* IO space */
576 #define	PCI_BASE_SPACE_MEM  0x0   /* memory space */
577 
578 #define	PCI_BASE_TYPE_MEM   0x0   /* 32-bit memory address */
579 #define	PCI_BASE_TYPE_LOW   0x2   /* less than 1Mb address */
580 #define	PCI_BASE_TYPE_ALL   0x4   /* 64-bit memory address */
581 #define	PCI_BASE_TYPE_RES   0x6   /* reserved */
582 
583 #define	PCI_BASE_TYPE_M		0x00000006  /* type indicator mask */
584 #define	PCI_BASE_PREF_M		0x00000008  /* prefetch mask */
585 #define	PCI_BASE_M_ADDR_M	0xfffffff0  /* memory address mask */
586 #define	PCI_BASE_M_ADDR64_M	0xfffffffffffffff0ULL /* 64bit mem addr mask */
587 #define	PCI_BASE_IO_ADDR_M	0xfffffffe  /* I/O address mask */
588 
589 #define	PCI_BASE_ROM_ADDR_M	0xfffff800  /* ROM address mask */
590 #define	PCI_BASE_ROM_ENABLE	0x00000001  /* ROM decoder enable */
591 
592 /*
593  * Capabilities linked list entry offsets
594  */
595 #define	PCI_CAP_ID		0x0	/* capability identifier, 1 byte */
596 #define	PCI_CAP_NEXT_PTR	0x1	/* next entry pointer, 1 byte */
597 #define	PCI_CAP_ID_REGS_OFF	0x2	/* cap id register offset */
598 #define	PCI_CAP_MAX_PTR		0x30	/* maximum number of cap pointers */
599 #define	PCI_CAP_PTR_OFF		0x40	/* minimum cap pointer offset */
600 #define	PCI_CAP_PTR_MASK	0xFC	/* mask for capability pointer */
601 
602 /*
603  * Capability identifier values
604  */
605 #define	PCI_CAP_ID_PM		0x1	/* power management entry */
606 #define	PCI_CAP_ID_AGP		0x2	/* AGP supported */
607 #define	PCI_CAP_ID_VPD		0x3	/* VPD supported */
608 #define	PCI_CAP_ID_SLOT_ID	0x4	/* Slot Identification supported */
609 #define	PCI_CAP_ID_MSI		0x5	/* MSI supported */
610 #define	PCI_CAP_ID_cPCI_HS	0x6	/* CompactPCI Host Swap supported */
611 #define	PCI_CAP_ID_PCIX		0x7	/* PCI-X supported */
612 #define	PCI_CAP_ID_HT		0x8	/* HyperTransport supported */
613 #define	PCI_CAP_ID_VS		0x9	/* Vendor Specific */
614 #define	PCI_CAP_ID_DEBUG_PORT	0xA	/* Debug Port supported */
615 #define	PCI_CAP_ID_cPCI_CRC	0xB	/* CompactPCI central resource ctrl */
616 #define	PCI_CAP_ID_PCI_HOTPLUG	0xC	/* PCI Hot Plug (SHPC) supported */
617 #define	PCI_CAP_ID_P2P_SUBSYS	0xD	/* PCI bridge Sub-system ID */
618 #define	PCI_CAP_ID_AGP_8X	0xE	/* AGP 8X supported */
619 #define	PCI_CAP_ID_SECURE_DEV	0xF	/* Secure Device supported */
620 #define	PCI_CAP_ID_PCI_E	0x10	/* PCI Express supported */
621 #define	PCI_CAP_ID_MSI_X	0x11	/* MSI-X supported */
622 #define	PCI_CAP_ID_SATA		0x12	/* SATA Data/Index Config supported */
623 #define	PCI_CAP_ID_FLR		0x13	/* Function Level Reset supported */
624 #define	PCI_CAP_ID_EA		0x14	/* Enhanced Allocation */
625 #define	PCI_CAP_ID_FPB		0x15	/* Flattening Portal Bridge */
626 
627 /*
628  * Capability next entry pointer values
629  */
630 #define	PCI_CAP_NEXT_PTR_NULL	0x0	/* no more entries in the list */
631 
632 /*
633  * PCI power management (PM) capability entry offsets
634  */
635 #define	PCI_PMCAP		0x2	/* PM capabilities, 2 bytes */
636 #define	PCI_PMCSR		0x4	/* PM control/status reg, 2 bytes */
637 #define	PCI_PMCSR_BSE		0x6	/* PCI-PCI bridge extensions, 1 byte */
638 #define	PCI_PMDATA		0x7	/* PM data, 1 byte */
639 
640 /*
641  * PM capabilities values - 2 bytes
642  */
643 #define	PCI_PMCAP_VER_1_0	0x1	/* PCI PM spec 1.0 */
644 #define	PCI_PMCAP_VER_1_1	0x2	/* PCI PM spec 1.1 */
645 #define	PCI_PMCAP_VER_MASK	0x7	/* version mask */
646 #define	PCI_PMCAP_PME_CLOCK	0x8	/* needs PCI clock for PME */
647 #define	PCI_PMCAP_DSI		0x20	/* needs device specific init */
648 #define	PCI_PMCAP_AUX_CUR_SELF	0x0	/* 0 aux current - self powered */
649 #define	PCI_PMCAP_AUX_CUR_55mA	0x40	/* 55 mA aux current */
650 #define	PCI_PMCAP_AUX_CUR_100mA	0x80	/* 100 mA aux current */
651 #define	PCI_PMCAP_AUX_CUR_160mA	0xc0	/* 160 mA aux current */
652 #define	PCI_PMCAP_AUX_CUR_220mA	0x100	/* 220 mA aux current */
653 #define	PCI_PMCAP_AUX_CUR_270mA	0x140	/* 270 mA aux current */
654 #define	PCI_PMCAP_AUX_CUR_320mA	0x180	/* 320 mA aux current */
655 #define	PCI_PMCAP_AUX_CUR_375mA	0x1c0	/* 375 mA aux current */
656 #define	PCI_PMCAP_AUX_CUR_MASK	0x1c0	/* 3.3Vaux aux current needs */
657 #define	PCI_PMCAP_D1		0x200	/* D1 state supported */
658 #define	PCI_PMCAP_D2		0x400	/* D2 state supported */
659 #define	PCI_PMCAP_D0_PME	0x800	/* PME from D0 */
660 #define	PCI_PMCAP_D1_PME	0x1000	/* PME from D1 */
661 #define	PCI_PMCAP_D2_PME	0x2000	/* PME from D2 */
662 #define	PCI_PMCAP_D3HOT_PME	0x4000	/* PME from D3hot */
663 #define	PCI_PMCAP_D3COLD_PME	0x8000	/* PME from D3cold */
664 #define	PCI_PMCAP_PME_MASK	0xf800	/* PME support mask */
665 
666 /*
667  * PM control/status values - 2 bytes
668  */
669 #define	PCI_PMCSR_D0			0x0	/* power state D0 */
670 #define	PCI_PMCSR_D1			0x1	/* power state D1 */
671 #define	PCI_PMCSR_D2			0x2	/* power state D2 */
672 #define	PCI_PMCSR_D3HOT			0x3	/* power state D3hot */
673 #define	PCI_PMCSR_STATE_MASK		0x3	/* power state mask */
674 #define	PCI_PMCSR_PME_EN		0x100	/* enable PME assertion */
675 #define	PCI_PMCSR_DSEL_D0_PWR_C		0x0	/* D0 power consumed */
676 #define	PCI_PMCSR_DSEL_D1_PWR_C		0x200	/* D1 power consumed */
677 #define	PCI_PMCSR_DSEL_D2_PWR_C		0x400	/* D2 power consumed */
678 #define	PCI_PMCSR_DSEL_D3_PWR_C		0x600	/* D3 power consumed */
679 #define	PCI_PMCSR_DSEL_D0_PWR_D		0x800	/* D0 power dissipated */
680 #define	PCI_PMCSR_DSEL_D1_PWR_D		0xa00	/* D1 power dissipated */
681 #define	PCI_PMCSR_DSEL_D2_PWR_D		0xc00	/* D2 power dissipated */
682 #define	PCI_PMCSR_DSEL_D3_PWR_D		0xe00	/* D3 power dissipated */
683 #define	PCI_PMCSR_DSEL_COM_C		0x1000	/* common power consumption */
684 #define	PCI_PMCSR_DSEL_MASK		0x1e00	/* data select mask */
685 #define	PCI_PMCSR_DSCL_UNKNOWN		0x0	/* data scale unknown */
686 #define	PCI_PMCSR_DSCL_1_BY_10		0x2000	/* data scale 0.1x */
687 #define	PCI_PMCSR_DSCL_1_BY_100		0x4000	/* data scale 0.01x */
688 #define	PCI_PMCSR_DSCL_1_BY_1000	0x6000	/* data scale 0.001x */
689 #define	PCI_PMCSR_DSCL_MASK		0x6000	/* data scale mask */
690 #define	PCI_PMCSR_PME_STAT		0x8000	/* PME status */
691 
692 /*
693  * PM PMCSR PCI to PCI bridge support extension values - 1 byte
694  */
695 #define	PCI_PMCSR_BSE_B2_B3	0x40	/* bridge D3hot -> secondary B2 */
696 #define	PCI_PMCSR_BSE_BPCC_EN	0x80	/* bus power/clock control enabled */
697 
698 /*
699  * PCI-X capability related definitions
700  */
701 #define	PCI_PCIX_COMMAND	0x2	/* Command register offset */
702 #define	PCI_PCIX_STATUS		0x4	/* Status register offset */
703 #define	PCI_PCIX_ECC_STATUS	0x8	/* ECC Status register offset */
704 #define	PCI_PCIX_ECC_FST_AD	0xC	/* ECC First address register offset */
705 #define	PCI_PCIX_ECC_SEC_AD	0x10	/* ECC Second address register offset */
706 #define	PCI_PCIX_ECC_ATTR	0x14	/* ECC Attribute register offset */
707 
708 /*
709  * PCI-X bridge capability related definitions
710  */
711 #define	PCI_PCIX_SEC_STATUS		0x2	/* Secondary Status offset */
712 #define	PCI_PCIX_SEC_STATUS_SCD		0x4	/* Split Completion Discarded */
713 #define	PCI_PCIX_SEC_STATUS_USC		0x8	/* Unexpected Split Complete */
714 #define	PCI_PCIX_SEC_STATUS_SCO		0x10	/* Split Completion Overrun */
715 #define	PCI_PCIX_SEC_STATUS_SRD		0x20	/* Split Completion Delayed */
716 #define	PCI_PCIX_SEC_STATUS_ERR_MASK	0x3C
717 
718 #define	PCI_PCIX_BDG_STATUS		0x4	/* Bridge Status offset */
719 #define	PCI_PCIX_BDG_STATUS_USC		0x80000
720 #define	PCI_PCIX_BDG_STATUS_SCO		0x100000
721 #define	PCI_PCIX_BDG_STATUS_SRD		0x200000
722 #define	PCI_PCIX_BDG_STATUS_ERR_MASK	0x380000
723 
724 #define	PCI_PCIX_UP_SPL_CTL	0x8	/* Upstream split ctrl reg offset */
725 #define	PCI_PCIX_DOWN_SPL_CTL	0xC	/* Downstream split ctrl reg offset */
726 #define	PCI_PCIX_BDG_ECC_STATUS	0x10	/* ECC Status register offset */
727 #define	PCI_PCIX_BDG_ECC_FST_AD	0x14	/* ECC First address register offset */
728 #define	PCI_PCIX_BDG_ECC_SEC_AD	0x18	/* ECC Second address register offset */
729 #define	PCI_PCIX_BDG_ECC_ATTR	0x1C	/* ECC Attribute register offset */
730 
731 /*
732  * PCIX capabilities values
733  */
734 #define	PCI_PCIX_VER_MASK	0x3000	/* Bits 12 and 13 */
735 #define	PCI_PCIX_VER_0		0x0000	/* PCIX cap list item version 0 */
736 #define	PCI_PCIX_VER_1		0x1000	/* PCIX cap list item version 1 */
737 #define	PCI_PCIX_VER_2		0x2000	/* PCIX cap list item version 2 */
738 
739 #define	PCI_PCIX_SPL_DSCD	0x40000 /* Split Completion Discarded */
740 #define	PCI_PCIX_UNEX_SPL	0x80000	/* Unexpected Split Completion */
741 #define	PCI_PCIX_RX_SPL_MSG	0x20000000 /* Recieved Spl Comp Error Message */
742 
743 #define	PCI_PCIX_ECC_SEL	0x1	/* Secondary ECC register select */
744 #define	PCI_PCIX_ECC_EP		0x2	/* Error Present on other side */
745 #define	PCI_PCIX_ECC_S_CE	0x4	/* Addl Correctable ECC Error */
746 #define	PCI_PCIX_ECC_S_UE	0x8	/* Addl Uncorrectable ECC Error */
747 #define	PCI_PCIX_ECC_PHASE	0x70	/* ECC Error Phase */
748 #define	PCI_PCIX_ECC_CORR	0x80	/* ECC Error Corrected */
749 #define	PCI_PCIX_ECC_SYN	0xff00	/* ECC Error Syndrome */
750 #define	PCI_PCIX_ECC_FST_CMD	0xf0000	 /* ECC Error First Command */
751 #define	PCI_PCIX_ECC_SEC_CMD	0xf00000 /* ECC Error Second Command */
752 #define	PCI_PCIX_ECC_UP_ATTR	0xf000000 /* ECC Error Upper Attributes */
753 
754 /*
755  * PCIX ECC Phase Values
756  */
757 #define	PCI_PCIX_ECC_PHASE_NOERR	0x0
758 #define	PCI_PCIX_ECC_PHASE_FADDR	0x1
759 #define	PCI_PCIX_ECC_PHASE_SADDR	0x2
760 #define	PCI_PCIX_ECC_PHASE_ATTR		0x3
761 #define	PCI_PCIX_ECC_PHASE_DATA32	0x4
762 #define	PCI_PCIX_ECC_PHASE_DATA64	0x5
763 
764 /*
765  * PCI-X Command Encoding
766  */
767 #define	PCI_PCIX_CMD_INTR		0x0
768 #define	PCI_PCIX_CMD_SPEC		0x1
769 #define	PCI_PCIX_CMD_IORD		0x2
770 #define	PCI_PCIX_CMD_IOWR		0x3
771 #define	PCI_PCIX_CMD_DEVID		0x5
772 #define	PCI_PCIX_CMD_MEMRD_DW		0x6
773 #define	PCI_PCIX_CMD_MEMWR		0x7
774 #define	PCI_PCIX_CMD_MEMRD_BL		0x8
775 #define	PCI_PCIX_CMD_MEMWR_BL		0x9
776 #define	PCI_PCIX_CMD_CFRD		0xA
777 #define	PCI_PCIX_CMD_CFWR		0xB
778 #define	PCI_PCIX_CMD_SPL		0xC
779 #define	PCI_PCIX_CMD_DADR		0xD
780 #define	PCI_PCIX_CMD_MEMRDBL		0xE
781 #define	PCI_PCIX_CMD_MEMWRBL		0xF
782 
783 #if defined(_BIT_FIELDS_LTOH)
784 typedef struct pcix_attr {
785 	uint32_t	lbc	:8,
786 			rid	:16,
787 			tag	:5,
788 			ro	:1,
789 			ns	:1,
790 			r	:1;
791 } pcix_attr_t;
792 #elif defined(_BIT_FIELDS_HTOL)
793 typedef struct pcix_attr {
794 	uint32_t	r	:1,
795 			ns	:1,
796 			ro	:1,
797 			tag	:5,
798 			rid	:16,
799 			lbc	:8;
800 } pcix_attr_t;
801 #else
802 #error "bit field not defined"
803 #endif
804 
805 #define	PCI_PCIX_BSS_SPL_DSCD	0x4	/* Secondary split comp discarded */
806 #define	PCI_PCIX_BSS_UNEX_SPL	0x8	/* Secondary unexpected split comp */
807 #define	PCI_PCIX_BSS_SPL_OR	0x10	/* Secondary split comp overrun */
808 #define	PCI_PCIX_BSS_SPL_DLY	0x20	/* Secondary split comp delayed */
809 
810 /*
811  * PCI Hotplug capability entry offsets
812  *
813  * SHPC based PCI hotplug controller registers accessed via the DWORD
814  * select and DATA registers in PCI configuration space relative to the
815  * PCI HP capibility pointer.
816  */
817 #define	PCI_HP_DWORD_SELECT_OFF		0x2
818 #define	PCI_HP_DWORD_DATA_OFF		0x4
819 
820 #define	PCI_HP_BASE_OFFSET_REG		0x00
821 #define	PCI_HP_SLOTS_AVAIL_I_REG	0x01
822 #define	PCI_HP_SLOTS_AVAIL_II_REG	0x02
823 #define	PCI_HP_SLOT_CONFIGURATION_REG	0x03
824 #define	PCI_HP_PROF_IF_SBCR_REG		0x04
825 #define	PCI_HP_COMMAND_STATUS_REG	0x05
826 #define	PCI_HP_IRQ_LOCATOR_REG		0x06
827 #define	PCI_HP_SERR_LOCATOR_REG		0x07
828 #define	PCI_HP_CTRL_SERR_INT_REG	0x08
829 #define	PCI_HP_LOGICAL_SLOT_REGS	0x09
830 #define	PCI_HP_VENDOR_SPECIFIC		0x28
831 
832 /* Definitions used with the PCI_HP_SLOTS_AVAIL_I_REG register */
833 #define	PCI_HP_AVAIL_33MHZ_CONV_SPEED_SHIFT	0
834 #define	PCI_HP_AVAIL_66MHZ_PCIX_SPEED_SHIFT	8
835 #define	PCI_HP_AVAIL_100MHZ_PCIX_SPEED_SHIFT	16
836 #define	PCI_HP_AVAIL_133MHZ_PCIX_SPEED_SHIFT	24
837 #define	PCI_HP_AVAIL_SPEED_MASK			0x1F
838 
839 /* Definitions used with the PCI_HP_SLOTS_AVAIL_II_REG register */
840 #define	PCI_HP_AVAIL_66MHZ_CONV_SPEED_SHIFT	0
841 
842 /* Register bits used with the PCI_HP_PROF_IF_SBCR_REG register */
843 #define	PCI_HP_SBCR_33MHZ_CONV_SPEED		0x0
844 #define	PCI_HP_SBCR_66MHZ_CONV_SPEED		0x1
845 #define	PCI_HP_SBCR_66MHZ_PCIX_SPEED		0x2
846 #define	PCI_HP_SBCR_100MHZ_PCIX_SPEED		0x3
847 #define	PCI_HP_SBCR_133MHZ_PCIX_SPEED		0x4
848 #define	PCI_HP_SBCR_SPEED_MASK			0x7
849 
850 /* Register bits used with the PCI_HP_COMMAND_STATUS_REG register */
851 #define	PCI_HP_COMM_STS_ERR_INVALID_SPEED	0x80000
852 #define	PCI_HP_COMM_STS_ERR_INVALID_COMMAND	0x40000
853 #define	PCI_HP_COMM_STS_ERR_MRL_OPEN		0x20000
854 #define	PCI_HP_COMM_STS_ERR_MASK		0xe0000
855 #define	PCI_HP_COMM_STS_CTRL_BUSY		0x10000
856 #define	PCI_HP_COMM_STS_SET_SPEED		0x40
857 
858 /* Register bits used with the PCI_HP_CTRL_SERR_INT_REG register */
859 #define	PCI_HP_SERR_INT_GLOBAL_IRQ_MASK		0x1
860 #define	PCI_HP_SERR_INT_GLOBAL_SERR_MASK	0x2
861 #define	PCI_HP_SERR_INT_CMD_COMPLETE_MASK	0x4
862 #define	PCI_HP_SERR_INT_ARBITER_SERR_MASK	0x8
863 #define	PCI_HP_SERR_INT_CMD_COMPLETE_IRQ	0x10000
864 #define	PCI_HP_SERR_INT_ARBITER_IRQ		0x20000
865 #define	PCI_HP_SERR_INT_MASK_ALL		0xf
866 
867 /* Register bits used with the PCI_HP_LOGICAL_SLOT_REGS register */
868 #define	PCI_HP_SLOT_POWER_ONLY			0x1
869 #define	PCI_HP_SLOT_ENABLED			0x2
870 #define	PCI_HP_SLOT_DISABLED			0x3
871 #define	PCI_HP_SLOT_STATE_MASK			0x3
872 #define	PCI_HP_SLOT_MRL_STATE_MASK		0x100
873 #define	PCI_HP_SLOT_66MHZ_CONV_CAPABLE		0x200
874 #define	PCI_HP_SLOT_CARD_EMPTY_MASK		0xc00
875 #define	PCI_HP_SLOT_66MHZ_PCIX_CAPABLE		0x1000
876 #define	PCI_HP_SLOT_100MHZ_PCIX_CAPABLE		0x2000
877 #define	PCI_HP_SLOT_133MHZ_PCIX_CAPABLE		0x3000
878 #define	PCI_HP_SLOT_PCIX_CAPABLE_MASK		0x3000
879 #define	PCI_HP_SLOT_PCIX_CAPABLE_SHIFT		12
880 #define	PCI_HP_SLOT_PRESENCE_DETECTED		0x10000
881 #define	PCI_HP_SLOT_ISO_PWR_DETECTED		0x20000
882 #define	PCI_HP_SLOT_ATTN_DETECTED		0x40000
883 #define	PCI_HP_SLOT_MRL_DETECTED		0x80000
884 #define	PCI_HP_SLOT_POWER_DETECTED		0x100000
885 #define	PCI_HP_SLOT_PRESENCE_MASK		0x1000000
886 #define	PCI_HP_SLOT_ISO_PWR_MASK		0x2000000
887 #define	PCI_HP_SLOT_ATTN_MASK			0x4000000
888 #define	PCI_HP_SLOT_MRL_MASK			0x8000000
889 #define	PCI_HP_SLOT_POWER_MASK			0x10000000
890 #define	PCI_HP_SLOT_MRL_SERR_MASK		0x20000000
891 #define	PCI_HP_SLOT_POWER_SERR_MASK		0x40000000
892 #define	PCI_HP_SLOT_MASK_ALL			0x5f000000
893 
894 /* Register bits used with the PCI_HP_IRQ_LOCATOR_REG register */
895 #define	PCI_HP_IRQ_CMD_COMPLETE			0x1
896 #define	PCI_HP_IRQ_SLOT_N_PENDING		0x2
897 
898 /* Register bits used with the PCI_HP_SERR_LOCATOR_REG register */
899 #define	PCI_HP_IRQ_SERR_ARBITER_PENDING		0x1
900 #define	PCI_HP_IRQ_SERR_SLOT_N_PENDING		0x2
901 
902 /* Register bits used with the PCI_HP_SLOT_CONFIGURATION_REG register */
903 #define	PCI_HP_SLOT_CONFIG_MRL_SENSOR		0x40000000
904 #define	PCI_HP_SLOT_CONFIG_ATTN_BUTTON		0x80000000
905 #define	PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_SHIFT	16
906 #define	PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_MASK	0x3FF
907 
908 /*
909  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
910  */
911 #define	PCI_MSI_CTRL		0x02	/* MSI control register, 2 bytes */
912 #define	PCI_MSI_ADDR_OFFSET	0x04	/* MSI 32-bit msg address, 4 bytes */
913 #define	PCI_MSI_32BIT_DATA	0x08	/* MSI 32-bit msg data, 2 bytes */
914 #define	PCI_MSI_32BIT_EXTDATA	0x0A	/* MSI 32-bit msg ext data, 2 bytes */
915 #define	PCI_MSI_32BIT_MASK	0x0C	/* MSI 32-bit mask bits, 4 bytes */
916 #define	PCI_MSI_32BIT_PENDING	0x10	/* MSI 32-bit pending bits, 4 bytes */
917 
918 /*
919  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
920  */
921 #define	PCI_MSI_64BIT_ADDR	0x08	/* MSI 64-bit upper address, 4 bytes */
922 #define	PCI_MSI_64BIT_DATA	0x0C	/* MSI 64-bit msg data, 2 bytes */
923 #define	PCI_MSI_64BIT_EXTDATA	0x0E	/* MSI 64-bit msg ext data, 2 bytes */
924 #define	PCI_MSI_64BIT_MASKBITS	0x10	/* MSI 64-bit mask bits, 4 bytes */
925 #define	PCI_MSI_64BIT_PENDING	0x14	/* MSI 64-bit pending bits, 4 bytes */
926 
927 /*
928  * PCI Message Signalled Interrupts (MSI) capability masks and shifts
929  */
930 #define	PCI_MSI_ENABLE_BIT	0x0001	/* MSI enable mask in MSI ctrl reg */
931 #define	PCI_MSI_MMC_MASK	0x000E	/* MMC mask in MSI ctrl reg */
932 #define	PCI_MSI_MMC_SHIFT	0x1	/* Shift for MMC bits */
933 #define	PCI_MSI_MME_MASK	0x0070	/* MME mask in MSI ctrl reg */
934 #define	PCI_MSI_MME_SHIFT	0x4	/* Shift for MME bits */
935 #define	PCI_MSI_64BIT_MASK	0x0080	/* 64bit support mask in MSI ctrl reg */
936 #define	PCI_MSI_PVM_MASK	0x0100	/* PVM support mask in MSI ctrl reg */
937 #define	PCI_MSI_EMD_MASK	0x0200	/* EMD Capable Mask */
938 #define	PCI_MSI_EMD_ENABLE	0x0400	/* EMD Enable bit */
939 
940 /*
941  * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets
942  */
943 #define	PCI_MSIX_CTRL		0x02	/* MSI-X control register, 2 bytes */
944 #define	PCI_MSIX_TBL_OFFSET	0x04	/* MSI-X table offset, 4 bytes */
945 #define	PCI_MSIX_TBL_BIR_MASK	0x0007	/* MSI-X table BIR mask */
946 #define	PCI_MSIX_PBA_OFFSET	0x08	/* MSI-X pending bit array, 4 bytes */
947 #define	PCI_MSIX_PBA_BIR_MASK	0x0007	/* MSI-X PBA BIR mask */
948 
949 #define	PCI_MSIX_TBL_SIZE_MASK	0x07FF	/* table size mask in MSI-X ctrl reg */
950 #define	PCI_MSIX_FUNCTION_MASK	0x4000	/* function mask in MSI-X ctrl reg */
951 #define	PCI_MSIX_ENABLE_BIT	0x8000	/* MSI-X enable mask in MSI-X ctl reg */
952 
953 #define	PCI_MSIX_LOWER_ADDR_OFFSET	0	/* MSI-X lower addr offset */
954 #define	PCI_MSIX_UPPER_ADDR_OFFSET	4	/* MSI-X upper addr offset */
955 #define	PCI_MSIX_DATA_OFFSET		8	/* MSI-X data offset */
956 #define	PCI_MSIX_VECTOR_CTRL_OFFSET	12	/* MSI-X vector ctrl offset */
957 #define	PCI_MSIX_VECTOR_SIZE		16	/* MSI-X size of each vector */
958 
959 /*
960  * PCI Message Signalled Interrupts: other interesting constants
961  */
962 #define	PCI_MSI_MAX_INTRS	32	/* maximum MSI interrupts supported */
963 #define	PCI_MSIX_MAX_INTRS	2048	/* maximum MSI-X interrupts supported */
964 
965 /*
966  * PCI Slot Id Capabilities, 2 bytes
967  */
968 /* Byte 1: Expansion Slot Register (ESR), Byte 2: Chassis Number Register */
969 #define	PCI_CAPSLOT_ESR_NSLOTS_MASK	0x1F	/* Number of slots mask */
970 #define	PCI_CAPSLOT_ESR_FIC		0x20	/* First In Chassis bit */
971 #define	PCI_CAPSLOT_ESR_FIC_MASK	0x01	/* First In Chassis mask */
972 #define	PCI_CAPSLOT_ESR_FIC_SHIFT	5	/* First In Chassis shift */
973 #define	PCI_CAPSLOT_FIC(esr_reg)	((esr_reg) & PCI_CAPSLOT_ESR_FIC)
974 #define	PCI_CAPSLOT_NSLOTS(esr_reg)	((esr_reg) & \
975 						PCI_CAPSLOT_ESR_NSLOTS_MASK)
976 
977 /*
978  * HyperTransport Capabilities; each HT cap uses the same PCI cap id of
979  * PCI_CAP_ID_HT.  The header's upper 16-bits (command reg) contains an HT
980  * cap type reg at bits [15:11].  For Slave/Pri Interface and Host/Sec
981  * Interface types, only bits [15:13] are used.
982  */
983 #define	PCI_HTCAP_TYPE_MASK		0xF800
984 #define	PCI_HTCAP_TYPE_SLHOST_MASK	0xE000	/* SLPRI and HOSTSEC types */
985 #define	PCI_HTCAP_TYPE_SHIFT		11
986 
987 #define	PCI_HTCAP_SLPRI_ID		0x00
988 #define	PCI_HTCAP_HOSTSEC_ID		0x04
989 #define	PCI_HTCAP_SWITCH_ID		0x08
990 #define	PCI_HTCAP_INTCONF_ID		0x10
991 #define	PCI_HTCAP_REVID_ID		0x11
992 #define	PCI_HTCAP_UNITID_CLUMP_ID	0x12
993 #define	PCI_HTCAP_ECFG_ID		0x13
994 #define	PCI_HTCAP_ADDRMAP_ID		0x14
995 #define	PCI_HTCAP_MSIMAP_ID		0x15
996 #define	PCI_HTCAP_DIRROUTE_ID		0x16
997 #define	PCI_HTCAP_VCSET_ID		0x17
998 #define	PCI_HTCAP_RETRYMODE_ID		0x18
999 #define	PCI_HTCAP_X86ENC_ID		0x19
1000 #define	PCI_HTCAP_GEN3_ID		0x1A
1001 #define	PCI_HTCAP_FUNCEXT_ID		0x1B
1002 #define	PCI_HTCAP_PM_ID			0x1C
1003 
1004 #define	PCI_HTCAP_SLPRI_TYPE		/* 0x0000 */	\
1005 	(PCI_HTCAP_SLPRI_ID	<< PCI_HTCAP_TYPE_SHIFT)
1006 
1007 #define	PCI_HTCAP_HOSTSEC_TYPE		/* 0x2000 */	\
1008 	(PCI_HTCAP_HOSTSEC_ID	<< PCI_HTCAP_TYPE_SHIFT)
1009 
1010 #define	PCI_HTCAP_SWITCH_TYPE		/* 0x4000 */	\
1011 	(PCI_HTCAP_SWITCH_ID	<< PCI_HTCAP_TYPE_SHIFT)
1012 
1013 #define	PCI_HTCAP_INTCONF_TYPE		/* 0x8000 */	\
1014 	(PCI_HTCAP_INTCONF_ID	<< PCI_HTCAP_TYPE_SHIFT)
1015 
1016 #define	PCI_HTCAP_REVID_TYPE		/* 0x8800 */	\
1017 	(PCI_HTCAP_REVID_ID	<< PCI_HTCAP_TYPE_SHIFT)
1018 
1019 #define	PCI_HTCAP_UNITID_CLUMP_TYPE	/* 0x9000 */	\
1020 	(PCI_HTCAP_UNITID_CLUMP_ID	<< PCI_HTCAP_TYPE_SHIFT)
1021 
1022 #define	PCI_HTCAP_ECFG_TYPE		/* 0x9800 */	\
1023 	(PCI_HTCAP_ECFG_ID	<< PCI_HTCAP_TYPE_SHIFT)
1024 
1025 #define	PCI_HTCAP_ADDRMAP_TYPE		/* 0xA000 */	\
1026 	(PCI_HTCAP_ADDRMAP_ID	<< PCI_HTCAP_TYPE_SHIFT)
1027 
1028 #define	PCI_HTCAP_MSIMAP_TYPE		/* 0xA800 */	\
1029 	(PCI_HTCAP_MSIMAP_ID	<< PCI_HTCAP_TYPE_SHIFT)
1030 
1031 #define	PCI_HTCAP_DIRROUTE_TYPE		/* 0xB000 */	\
1032 	(PCI_HTCAP_DIRROUTE_ID	<< PCI_HTCAP_TYPE_SHIFT)
1033 
1034 #define	PCI_HTCAP_VCSET_TYPE		/* 0xB800 */	\
1035 	(PCI_HTCAP_VCSET_ID	<< PCI_HTCAP_TYPE_SHIFT)
1036 
1037 #define	PCI_HTCAP_RETRYMODE_TYPE	/* 0xC000 */	\
1038 	(PCI_HTCAP_RETRYMODE_ID	<< PCI_HTCAP_TYPE_SHIFT)
1039 
1040 #define	PCI_HTCAP_X86ENC_TYPE		/* 0xC800 */	\
1041 	(PCI_HTCAP_X86ENC_ID	<< PCI_HTCAP_TYPE_SHIFT)
1042 
1043 #define	PCI_HTCAP_GEN3_TYPE		/* 0xD000 */	\
1044 	(PCI_HTCAP_GEN3_ID	<< PCI_HTCAP_TYPE_SHIFT)
1045 
1046 #define	PCI_HTCAP_FUNCEXT_TYPE		/* 0xD800 */	\
1047 	(PCI_HTCAP_FUNCEXT_ID	<< PCI_HTCAP_TYPE_SHIFT)
1048 
1049 #define	PCI_HTCAP_PM_TYPE		/* 0xE000 */	\
1050 	(PCI_HTCAP_PM_ID	<< PCI_HTCAP_TYPE_SHIFT)
1051 
1052 #define	PCI_HTCAP_MSIMAP_ENABLE			0x0001
1053 #define	PCI_HTCAP_MSIMAP_ENABLE_MASK		0x0001
1054 
1055 #define	PCI_HTCAP_ADDRMAP_MAPTYPE_MASK		0x600
1056 #define	PCI_HTCAP_ADDRMAP_MAPTYPE_SHIFT		9
1057 #define	PCI_HTCAP_ADDRMAP_NUMMAP_MASK		0xF
1058 #define	PCI_HTCAP_ADDRMAP_40BIT_ID		0x0
1059 #define	PCI_HTCAP_ADDRMAP_64BIT_ID		0x1
1060 
1061 #define	PCI_HTCAP_FUNCEXT_LEN_MASK		0xFF
1062 
1063 
1064 /*
1065  * other interesting PCI constants
1066  */
1067 #define	PCI_BASE_NUM	6	/* num of base regs in configuration header */
1068 #define	PCI_BAR_SZ_32	4	/* size of 32 bit base addr reg in bytes */
1069 #define	PCI_BAR_SZ_64	8	/* size of 64 bit base addr reg in bytes */
1070 #define	PCI_BASE_SIZE	4	/* size of base reg in bytes */
1071 #define	PCI_CONF_HDR_SIZE	256	/* configuration header size */
1072 #define	PCI_MAX_BUS_NUM		256		/* Maximum PCI buses allowed */
1073 #define	PCI_MAX_DEVICES		32		/* Max PCI devices allowed */
1074 #define	PCI_MAX_FUNCTIONS	8		/* Max PCI functions allowed */
1075 #define	PCI_MAX_CHILDREN	PCI_MAX_DEVICES * PCI_MAX_FUNCTIONS
1076 #define	PCI_CLK_33MHZ	(33 * 1000 * 1000)	/* 33MHz clock speed */
1077 #define	PCI_CLK_66MHZ	(66 * 1000 * 1000)	/* 66MHz clock speed */
1078 #define	PCI_CLK_133MHZ	(133 * 1000 * 1000)	/* 133MHz clock speed */
1079 
1080 /*
1081  * pci bus range definition
1082  */
1083 typedef struct pci_bus_range {
1084 	uint32_t lo;
1085 	uint32_t hi;
1086 } pci_bus_range_t;
1087 
1088 /*
1089  * The following typedef is used to represent an entry in the "ranges"
1090  * property of a pci hostbridge device node.
1091  */
1092 typedef struct pci_ranges {
1093 	uint32_t child_high;
1094 	uint32_t child_mid;
1095 	uint32_t child_low;
1096 	uint32_t parent_high;
1097 	uint32_t parent_low;
1098 	uint32_t size_high;
1099 	uint32_t size_low;
1100 } pci_ranges_t;
1101 
1102 /*
1103  * The following typedef is used to represent an entry in the "ranges"
1104  * property of a pci-pci bridge device node.
1105  */
1106 typedef struct {
1107 	uint32_t child_high;
1108 	uint32_t child_mid;
1109 	uint32_t child_low;
1110 	uint32_t parent_high;
1111 	uint32_t parent_mid;
1112 	uint32_t parent_low;
1113 	uint32_t size_high;
1114 	uint32_t size_low;
1115 } ppb_ranges_t;
1116 
1117 /*
1118  * This structure represents one entry of the 1275 "reg" property and
1119  * "assigned-addresses" property for a PCI node.  For the "reg" property, it
1120  * may be one of an arbitrary length array for devices with multiple address
1121  * windows.  For the "assigned-addresses" property, it denotes an assigned
1122  * physical address on the PCI bus.  It may be one entry of the six entries
1123  * for devices with multiple base registers.
1124  *
1125  * The physical address format is:
1126  *
1127  *             Bit#:  33222222 22221111 11111100 00000000
1128  *                    10987654 32109876 54321098 76543210
1129  *
1130  * pci_phys_hi cell:  npt000ss bbbbbbbb dddddfff rrrrrrrr
1131  * pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
1132  * pci_phys_low cell: llllllll llllllll llllllll llllllll
1133  *
1134  * n          is 0 if the address is relocatable, 1 otherwise
1135  * p          is 1 if the addressable region is "prefetchable", 0 otherwise
1136  * t          is 1 if the address is aliased (for non-relocatable I/O), below
1137  *	      1MB (for mem), or below 64 KB (for relocatable I/O).
1138  * ss         is the type code, denoting which address space
1139  * bbbbbbbb   is the 8-bit bus number
1140  * ddddd      is the 5-bit device number
1141  * fff        is the 3-bit function number
1142  * rrrrrrrr   is the 8-bit register number
1143  *	      should be zero for non-relocatable, when ss is 01, or 10
1144  * hh...hhh   is the 32-bit unsigned number
1145  * ll...lll   is the 32-bit unsigned number
1146  *
1147  * The physical size format is:
1148  *
1149  * pci_size_hi cell:  hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
1150  * pci_size_low cell: llllllll llllllll llllllll llllllll
1151  *
1152  * hh...hhh   is the 32-bit unsigned number
1153  * ll...lll   is the 32-bit unsigned number
1154  */
1155 struct pci_phys_spec {
1156 	uint_t pci_phys_hi;		/* child's address, hi word */
1157 	uint_t pci_phys_mid;		/* child's address, middle word */
1158 	uint_t pci_phys_low;		/* child's address, low word */
1159 	uint_t pci_size_hi;		/* high word of size field */
1160 	uint_t pci_size_low;		/* low word of size field */
1161 };
1162 
1163 typedef struct pci_phys_spec pci_regspec_t;
1164 
1165 /*
1166  * PCI masks for pci_phy_hi of PCI 1275 address cell.
1167  */
1168 #define	PCI_REG_REG_M		0xff		/* register mask */
1169 #define	PCI_REG_FUNC_M		0x700		/* function mask */
1170 #define	PCI_REG_DEV_M		0xf800		/* device mask */
1171 #define	PCI_REG_BUS_M		0xff0000	/* bus number mask */
1172 #define	PCI_REG_ADDR_M		0x3000000	/* address space mask */
1173 #define	PCI_REG_ALIAS_M		0x20000000	/* aliased bit mask */
1174 #define	PCI_REG_PF_M		0x40000000	/* prefetch bit mask */
1175 #define	PCI_REG_REL_M		0x80000000	/* relocation bit mask */
1176 #define	PCI_REG_BDFR_M		0xffffff	/* bus, dev, func, reg mask */
1177 #define	PCI_REG_EXTREG_M	0xF0000000	/* extended config bits mask */
1178 
1179 #define	PCI_REG_FUNC_SHIFT	8		/* Offset of function bits */
1180 #define	PCI_REG_DEV_SHIFT	11		/* Offset of device bits */
1181 #define	PCI_REG_BUS_SHIFT	16		/* Offset of bus bits */
1182 #define	PCI_REG_ADDR_SHIFT	24		/* Offset of address bits */
1183 #define	PCI_REG_EXTREG_SHIFT	28		/* Offset of ext. config bits */
1184 
1185 #define	PCI_REG_REG_G(x)	((x) & PCI_REG_REG_M)
1186 #define	PCI_REG_FUNC_G(x)	(((x) & PCI_REG_FUNC_M) >> PCI_REG_FUNC_SHIFT)
1187 #define	PCI_REG_DEV_G(x)	(((x) & PCI_REG_DEV_M) >> PCI_REG_DEV_SHIFT)
1188 #define	PCI_REG_BUS_G(x)	(((x) & PCI_REG_BUS_M) >> PCI_REG_BUS_SHIFT)
1189 #define	PCI_REG_ADDR_G(x)	(((x) & PCI_REG_ADDR_M) >> PCI_REG_ADDR_SHIFT)
1190 #define	PCI_REG_BDFR_G(x)	((x) & PCI_REG_BDFR_M)
1191 
1192 /*
1193  * PCI bit encodings of pci_phys_hi of PCI 1275 address cell.
1194  */
1195 #define	PCI_ADDR_MASK		PCI_REG_ADDR_M
1196 #define	PCI_ADDR_CONFIG		0x00000000	/* configuration address */
1197 #define	PCI_ADDR_IO		0x01000000	/* I/O address */
1198 #define	PCI_ADDR_MEM32		0x02000000	/* 32-bit memory address */
1199 #define	PCI_ADDR_MEM64		0x03000000	/* 64-bit memory address */
1200 #define	PCI_ALIAS_B		PCI_REG_ALIAS_M	/* aliased bit */
1201 #define	PCI_PREFETCH_B		PCI_REG_PF_M	/* prefetch bit */
1202 #define	PCI_RELOCAT_B		PCI_REG_REL_M	/* non-relocatable bit */
1203 #define	PCI_CONF_ADDR_MASK	0x00ffffff	/* mask for config address */
1204 
1205 #define	PCI_HARDDEC_8514 2	/* number of reg entries for 8514 hard-decode */
1206 #define	PCI_HARDDEC_VGA	3	/* number of reg entries for VGA hard-decode */
1207 #define	PCI_HARDDEC_IDE	4	/* number of reg entries for IDE hard-decode */
1208 #define	PCI_HARDDEC_IDE_PRI 2	/* number of reg entries for IDE primary */
1209 #define	PCI_HARDDEC_IDE_SEC 2	/* number of reg entries for IDE secondary */
1210 
1211 /*
1212  * PCI Expansion ROM Header Format
1213  */
1214 #define	PCI_ROM_SIGNATURE		0x0	/* ROM Signature 0xaa55 */
1215 #define	PCI_ROM_ARCH_UNIQUE_START	0x2	/* Start of processor unique */
1216 #define	PCI_ROM_PCI_DATA_STRUCT_PTR	0x18	/* Ptr to PCI Data Structure */
1217 
1218 /*
1219  * PCI Data Structure
1220  *
1221  * The PCI Data Structure is located within the first 64KB
1222  * of the ROM image and must be DWORD aligned.
1223  */
1224 #define	PCI_PDS_SIGNATURE	0x0	/* Signature, the string 'PCIR' */
1225 #define	PCI_PDS_VENDOR_ID	0x4	/* Vendor Identification */
1226 #define	PCI_PDS_DEVICE_ID	0x6	/* Device Identification */
1227 #define	PCI_PDS_VPD_PTR		0x8	/* Pointer to Vital Product Data */
1228 #define	PCI_PDS_PDS_LENGTH	0xa	/* PCI Data Structure Length */
1229 #define	PCI_PDS_PDS_REVISION	0xc	/* PCI Data Structure Revision */
1230 #define	PCI_PDS_CLASS_CODE	0xd	/* Class Code */
1231 #define	PCI_PDS_IMAGE_LENGTH	0x10	/* Image Length in 512 byte units */
1232 #define	PCI_PDS_CODE_REVISON	0x12	/* Revision Level of Code/Data */
1233 #define	PCI_PDS_CODE_TYPE	0x14	/* Code Type */
1234 #define	PCI_PDS_INDICATOR	0x15	/* Indicates if image is last in ROM */
1235 
1236 #define	PCI_PDS_CODE_TYPE_PCAT		0x0	/* Intel x86/PC-AT Type */
1237 #define	PCI_PDS_CODE_TYPE_OPEN_FW	0x1	/* Open Firmware */
1238 
1239 /*
1240  * we recognize the non transparent bridge child nodes with the
1241  * following property. This is specific to an implementation only.
1242  * This property is specific to AP nodes only.
1243  */
1244 #define	PCI_DEV_CONF_MAP_PROP	"pci-parent-indirect"
1245 
1246 /*
1247  * If a bridge device provides its own config space access services,
1248  * and supports a hotplug/hotswap bus below at any level, then
1249  * the following property must be defined for the node either by
1250  * the driver or the OBP.
1251  */
1252 #define	PCI_BUS_CONF_MAP_PROP	"pci-conf-indirect"
1253 
1254 /*
1255  * PCI returns all 1s for an invalid read.
1256  */
1257 #define	PCI_EINVAL8	0xff
1258 #define	PCI_EINVAL16	0xffff
1259 #define	PCI_EINVAL32	0xffffffff
1260 
1261 #ifdef	__cplusplus
1262 }
1263 #endif
1264 
1265 #endif	/* _SYS_PCI_H */
1266