144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 2244961713Sgirish * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #ifndef _SYS_NXGE_NXGE_ZCP_HW_H 2744961713Sgirish #define _SYS_NXGE_NXGE_ZCP_HW_H 2844961713Sgirish 2944961713Sgirish #ifdef __cplusplus 3044961713Sgirish extern "C" { 3144961713Sgirish #endif 3244961713Sgirish 3344961713Sgirish #include <nxge_defs.h> 3444961713Sgirish 3544961713Sgirish /* 3644961713Sgirish * Neptune Zerocopy Hardware definitions 3744961713Sgirish * Updated to reflect PRM-0.8. 3844961713Sgirish */ 3944961713Sgirish 4044961713Sgirish #define ZCP_CONFIG_REG (FZC_ZCP + 0x00000) 4144961713Sgirish #define ZCP_INT_STAT_REG (FZC_ZCP + 0x00008) 4244961713Sgirish #define ZCP_INT_STAT_TEST_REG (FZC_ZCP + 0x00108) 4344961713Sgirish #define ZCP_INT_MASK_REG (FZC_ZCP + 0x00010) 4444961713Sgirish 4544961713Sgirish #define ZCP_BAM4_RE_CTL_REG (FZC_ZCP + 0x00018) 4644961713Sgirish #define ZCP_BAM8_RE_CTL_REG (FZC_ZCP + 0x00020) 4744961713Sgirish #define ZCP_BAM16_RE_CTL_REG (FZC_ZCP + 0x00028) 4844961713Sgirish #define ZCP_BAM32_RE_CTL_REG (FZC_ZCP + 0x00030) 4944961713Sgirish 5044961713Sgirish #define ZCP_DST4_RE_CTL_REG (FZC_ZCP + 0x00038) 5144961713Sgirish #define ZCP_DST8_RE_CTL_REG (FZC_ZCP + 0x00040) 5244961713Sgirish #define ZCP_DST16_RE_CTL_REG (FZC_ZCP + 0x00048) 5344961713Sgirish #define ZCP_DST32_RE_CTL_REG (FZC_ZCP + 0x00050) 5444961713Sgirish 5544961713Sgirish #define ZCP_RAM_DATA_REG (FZC_ZCP + 0x00058) 5644961713Sgirish #define ZCP_RAM_DATA0_REG (FZC_ZCP + 0x00058) 5744961713Sgirish #define ZCP_RAM_DATA1_REG (FZC_ZCP + 0x00060) 5844961713Sgirish #define ZCP_RAM_DATA2_REG (FZC_ZCP + 0x00068) 5944961713Sgirish #define ZCP_RAM_DATA3_REG (FZC_ZCP + 0x00070) 6044961713Sgirish #define ZCP_RAM_DATA4_REG (FZC_ZCP + 0x00078) 6144961713Sgirish #define ZCP_RAM_BE_REG (FZC_ZCP + 0x00080) 6244961713Sgirish #define ZCP_RAM_ACC_REG (FZC_ZCP + 0x00088) 6344961713Sgirish 6444961713Sgirish #define ZCP_TRAINING_VECTOR_REG (FZC_ZCP + 0x000C0) 6544961713Sgirish #define ZCP_STATE_MACHINE_REG (FZC_ZCP + 0x000C8) 6644961713Sgirish #define ZCP_CHK_BIT_DATA_REG (FZC_ZCP + 0x00090) 6744961713Sgirish #define ZCP_RESET_CFIFO_REG (FZC_ZCP + 0x00098) 6844961713Sgirish #define ZCP_RESET_CFIFO_MASK 0x0F 6944961713Sgirish 7044961713Sgirish #define ZCP_CFIFIO_RESET_WAIT 10 7144961713Sgirish #define ZCP_P0_P1_CFIFO_DEPTH 2048 7244961713Sgirish #define ZCP_P2_P3_CFIFO_DEPTH 1024 7344961713Sgirish #define ZCP_NIU_CFIFO_DEPTH 1024 7444961713Sgirish 7544961713Sgirish typedef union _zcp_reset_cfifo { 7644961713Sgirish uint64_t value; 7744961713Sgirish struct { 7844961713Sgirish #if defined(_BIG_ENDIAN) 7944961713Sgirish uint32_t hdw; 8044961713Sgirish #endif 8144961713Sgirish struct { 8244961713Sgirish #if defined(_BIT_FIELDS_HTOL) 8344961713Sgirish uint32_t rsrvd:28; 8444961713Sgirish uint32_t reset_cfifo3:1; 8544961713Sgirish uint32_t reset_cfifo2:1; 8644961713Sgirish uint32_t reset_cfifo1:1; 8744961713Sgirish uint32_t reset_cfifo0:1; 8844961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 8944961713Sgirish uint32_t reset_cfifo0:1; 9044961713Sgirish uint32_t reset_cfifo1:1; 9144961713Sgirish uint32_t reset_cfifo2:1; 9244961713Sgirish uint32_t reset_cfifo3:1; 9344961713Sgirish uint32_t rsrvd:28; 9444961713Sgirish #endif 9544961713Sgirish } ldw; 9644961713Sgirish #if !defined(_BIG_ENDIAN) 9744961713Sgirish uint32_t hdw; 9844961713Sgirish #endif 9944961713Sgirish } bits; 10044961713Sgirish } zcp_reset_cfifo_t, *p_zcp_reset_cfifo_t; 10144961713Sgirish 10244961713Sgirish #define ZCP_CFIFO_ECC_PORT0_REG (FZC_ZCP + 0x000A0) 10344961713Sgirish #define ZCP_CFIFO_ECC_PORT1_REG (FZC_ZCP + 0x000A8) 10444961713Sgirish #define ZCP_CFIFO_ECC_PORT2_REG (FZC_ZCP + 0x000B0) 10544961713Sgirish #define ZCP_CFIFO_ECC_PORT3_REG (FZC_ZCP + 0x000B8) 10644961713Sgirish 10744961713Sgirish /* NOTE: Same as RX_LOG_PAGE_HDL */ 10844961713Sgirish #define ZCP_PAGE_HDL_REG (FZC_DMC + 0x20038) 10944961713Sgirish 11044961713Sgirish /* Data Structures */ 11144961713Sgirish 11244961713Sgirish typedef union zcp_config_reg_u { 11344961713Sgirish uint64_t value; 11444961713Sgirish struct { 11544961713Sgirish #if defined(_BIG_ENDIAN) 11644961713Sgirish uint32_t hdw; 11744961713Sgirish #endif 11844961713Sgirish struct { 11944961713Sgirish #if defined(_BIT_FIELDS_HTOL) 12044961713Sgirish uint32_t rsvd:7; 12144961713Sgirish uint32_t mode_32_bit:1; 12244961713Sgirish uint32_t debug_sel:8; 12344961713Sgirish uint32_t rdma_th:11; 12444961713Sgirish uint32_t ecc_chk_dis:1; 12544961713Sgirish uint32_t par_chk_dis:1; 12644961713Sgirish uint32_t dis_buf_rn:1; 12744961713Sgirish uint32_t dis_buf_rq_if:1; 12844961713Sgirish uint32_t zc_enable:1; 12944961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 13044961713Sgirish uint32_t zc_enable:1; 13144961713Sgirish uint32_t dis_buf_rq_if:1; 13244961713Sgirish uint32_t dis_buf_rn:1; 13344961713Sgirish uint32_t par_chk_dis:1; 13444961713Sgirish uint32_t ecc_chk_dis:1; 13544961713Sgirish uint32_t rdma_th:11; 13644961713Sgirish uint32_t debug_sel:8; 13744961713Sgirish uint32_t mode_32_bit:1; 13844961713Sgirish uint32_t rsvd:7; 13944961713Sgirish #endif 14044961713Sgirish } ldw; 14144961713Sgirish #if !defined(_BIG_ENDIAN) 14244961713Sgirish uint32_t hdw; 14344961713Sgirish #endif 14444961713Sgirish } bits; 14544961713Sgirish } zcp_config_reg_t, *zcp_config_reg_pt; 14644961713Sgirish 14744961713Sgirish #define ZCP_DEBUG_SEL_BITS 0xFF 14844961713Sgirish #define ZCP_DEBUG_SEL_SHIFT 16 14944961713Sgirish #define ZCP_DEBUG_SEL_MASK (ZCP_DEBUG_SEL_BITS << ZCP_DEBUG_SEL_SHIFT) 15044961713Sgirish #define RDMA_TH_BITS 0x7FF 15144961713Sgirish #define RDMA_TH_SHIFT 5 15244961713Sgirish #define RDMA_TH_MASK (RDMA_TH_BITS << RDMA_TH_SHIFT) 15344961713Sgirish #define ECC_CHK_DIS (1 << 4) 15444961713Sgirish #define PAR_CHK_DIS (1 << 3) 15544961713Sgirish #define DIS_BUFF_RN (1 << 2) 15644961713Sgirish #define DIS_BUFF_RQ_IF (1 << 1) 15744961713Sgirish #define ZC_ENABLE (1 << 0) 15844961713Sgirish 15944961713Sgirish typedef union zcp_int_stat_reg_u { 16044961713Sgirish uint64_t value; 16144961713Sgirish struct { 16244961713Sgirish #if defined(_BIG_ENDIAN) 16344961713Sgirish uint32_t hdw; 16444961713Sgirish #endif 16544961713Sgirish struct { 16644961713Sgirish #if defined(_BIT_FIELDS_HTOL) 16744961713Sgirish uint32_t rsvd:16; 16844961713Sgirish uint32_t rrfifo_urun:1; 16944961713Sgirish uint32_t rrfifo_orun:1; 17044961713Sgirish uint32_t rsvd1:1; 17144961713Sgirish uint32_t rspfifo_uc_err:1; 17244961713Sgirish uint32_t buf_overflow:1; 17344961713Sgirish uint32_t stat_tbl_perr:1; 17444961713Sgirish uint32_t dyn_tbl_perr:1; 17544961713Sgirish uint32_t buf_tbl_perr:1; 17644961713Sgirish uint32_t tt_tbl_perr:1; 17744961713Sgirish uint32_t rsp_tt_index_err:1; 17844961713Sgirish uint32_t slv_tt_index_err:1; 17944961713Sgirish uint32_t zcp_tt_index_err:1; 18044961713Sgirish uint32_t cfifo_ecc3:1; 18144961713Sgirish uint32_t cfifo_ecc2:1; 18244961713Sgirish uint32_t cfifo_ecc1:1; 18344961713Sgirish uint32_t cfifo_ecc0:1; 18444961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 18544961713Sgirish uint32_t cfifo_ecc0:1; 18644961713Sgirish uint32_t cfifo_ecc1:1; 18744961713Sgirish uint32_t cfifo_ecc2:1; 18844961713Sgirish uint32_t cfifo_ecc3:1; 18944961713Sgirish uint32_t zcp_tt_index_err:1; 19044961713Sgirish uint32_t slv_tt_index_err:1; 19144961713Sgirish uint32_t rsp_tt_index_err:1; 19244961713Sgirish uint32_t tt_tbl_perr:1; 19344961713Sgirish uint32_t buf_tbl_perr:1; 19444961713Sgirish uint32_t dyn_tbl_perr:1; 19544961713Sgirish uint32_t stat_tbl_perr:1; 19644961713Sgirish uint32_t buf_overflow:1; 19744961713Sgirish uint32_t rspfifo_uc_err:1; 19844961713Sgirish uint32_t rsvd1:1; 19944961713Sgirish uint32_t rrfifo_orun:1; 20044961713Sgirish uint32_t rrfifo_urun:1; 20144961713Sgirish uint32_t rsvd:16; 20244961713Sgirish #endif 20344961713Sgirish } ldw; 20444961713Sgirish #if !defined(_BIG_ENDIAN) 20544961713Sgirish uint32_t hdw; 20644961713Sgirish #endif 20744961713Sgirish } bits; 20844961713Sgirish } zcp_int_stat_reg_t, *zcp_int_stat_reg_pt, zcp_int_mask_reg_t, 20944961713Sgirish *zcp_int_mask_reg_pt; 21044961713Sgirish 21144961713Sgirish #define RRFIFO_UNDERRUN (1 << 15) 21244961713Sgirish #define RRFIFO_OVERRUN (1 << 14) 21344961713Sgirish #define RSPFIFO_UNCORR_ERR (1 << 12) 21444961713Sgirish #define BUFFER_OVERFLOW (1 << 11) 21544961713Sgirish #define STAT_TBL_PERR (1 << 10) 21644961713Sgirish #define BUF_DYN_TBL_PERR (1 << 9) 21744961713Sgirish #define BUF_TBL_PERR (1 << 8) 21844961713Sgirish #define TT_PROGRAM_ERR (1 << 7) 21944961713Sgirish #define RSP_TT_INDEX_ERR (1 << 6) 22044961713Sgirish #define SLV_TT_INDEX_ERR (1 << 5) 22144961713Sgirish #define ZCP_TT_INDEX_ERR (1 << 4) 22244961713Sgirish #define CFIFO_ECC3 (1 << 3) 22344961713Sgirish #define CFIFO_ECC0 (1 << 0) 22444961713Sgirish #define CFIFO_ECC2 (1 << 2) 22544961713Sgirish #define CFIFO_ECC1 (1 << 1) 22644961713Sgirish 22744961713Sgirish typedef union zcp_bam_region_reg_u { 22844961713Sgirish uint64_t value; 22944961713Sgirish struct { 23044961713Sgirish #if defined(_BIG_ENDIAN) 23144961713Sgirish uint32_t hdw; 23244961713Sgirish #endif 23344961713Sgirish struct { 23444961713Sgirish #if defined(_BIT_FIELDS_HTOL) 23544961713Sgirish uint32_t loj:1; 23644961713Sgirish uint32_t range_chk_en:1; 23744961713Sgirish uint32_t last_zcfid:10; 23844961713Sgirish uint32_t first_zcfid:10; 23944961713Sgirish uint32_t offset:10; 24044961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 24144961713Sgirish uint32_t offset:10; 24244961713Sgirish uint32_t first_zcfid:10; 24344961713Sgirish uint32_t last_zcfid:10; 24444961713Sgirish uint32_t range_chk_en:1; 24544961713Sgirish uint32_t loj:1; 24644961713Sgirish #endif 24744961713Sgirish } ldw; 24844961713Sgirish #if !defined(_BIG_ENDIAN) 24944961713Sgirish uint32_t hdw; 25044961713Sgirish #endif 25144961713Sgirish } bits; 25244961713Sgirish } zcp_bam_region_reg_t, *zcp_bam_region_reg_pt; 25344961713Sgirish 25444961713Sgirish typedef union zcp_dst_region_reg_u { 25544961713Sgirish uint64_t value; 25644961713Sgirish struct { 25744961713Sgirish #if defined(_BIG_ENDIAN) 25844961713Sgirish uint32_t hdw; 25944961713Sgirish #endif 26044961713Sgirish struct { 26144961713Sgirish #if defined(_BIT_FIELDS_HTOL) 26244961713Sgirish uint32_t rsvd:22; 26344961713Sgirish uint32_t ds_offset:10; 26444961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 26544961713Sgirish uint32_t rsvd:22; 26644961713Sgirish uint32_t ds_offset:10; 26744961713Sgirish #endif 26844961713Sgirish } ldw; 26944961713Sgirish #if !defined(_BIG_ENDIAN) 27044961713Sgirish uint32_t hdw; 27144961713Sgirish #endif 27244961713Sgirish } bits; 27344961713Sgirish } zcp_dst_region_reg_t, *zcp_dst_region_reg_pt; 27444961713Sgirish 27544961713Sgirish typedef enum tbuf_size_e { 27644961713Sgirish TBUF_4K = 0, 27744961713Sgirish TBUF_8K, 27844961713Sgirish TBUF_16K, 27944961713Sgirish TBUF_32K, 28044961713Sgirish TBUF_64K, 28144961713Sgirish TBUF_128K, 28244961713Sgirish TBUF_256K, 28344961713Sgirish TBUF_512K, 28444961713Sgirish TBUF_1M, 28544961713Sgirish TBUF_2M, 28644961713Sgirish TBUF_4M, 28744961713Sgirish TBUF_8M 28844961713Sgirish } tbuf_size_t; 28944961713Sgirish 29044961713Sgirish typedef enum tbuf_num_e { 29144961713Sgirish TBUF_NUM_4 = 0, 29244961713Sgirish TBUF_NUM_8, 29344961713Sgirish TBUF_NUM_16, 29444961713Sgirish TBUF_NUM_32 29544961713Sgirish } tbuf_num_t; 29644961713Sgirish 29744961713Sgirish typedef enum tmode_e { 29844961713Sgirish TMODE_BASIC = 0, 29944961713Sgirish TMODE_AUTO_UNMAP = 1, 30044961713Sgirish TMODE_AUTO_ADV = 3 30144961713Sgirish } tmode_t; 30244961713Sgirish 30344961713Sgirish typedef struct tte_sflow_attr_s { 30444961713Sgirish union { 30544961713Sgirish uint64_t value; 30644961713Sgirish struct { 30744961713Sgirish #if defined(_BIG_ENDIAN) 30844961713Sgirish uint32_t hdw; 30944961713Sgirish #endif 31044961713Sgirish struct { 31144961713Sgirish #if defined(_BIT_FIELDS_HTOL) 31244961713Sgirish uint32_t ulp_end:18; 31344961713Sgirish uint32_t num_buf:2; 31444961713Sgirish uint32_t buf_size:4; 31544961713Sgirish uint32_t rdc_tbl_offset:8; 31644961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 31744961713Sgirish uint32_t rdc_tbl_offset:8; 31844961713Sgirish uint32_t buf_size:4; 31944961713Sgirish uint32_t num_buf:2; 32044961713Sgirish uint32_t ulp_end:18; 32144961713Sgirish #endif 32244961713Sgirish } ldw; 32344961713Sgirish #if !defined(_BIG_ENDIAN) 32444961713Sgirish uint32_t hdw; 32544961713Sgirish #endif 32644961713Sgirish } bits; 32744961713Sgirish } qw0; 32844961713Sgirish 32944961713Sgirish union { 33044961713Sgirish uint64_t value; 33144961713Sgirish struct { 33244961713Sgirish #if defined(_BIG_ENDIAN) 33344961713Sgirish uint32_t hdw; 33444961713Sgirish #endif 33544961713Sgirish struct { 33644961713Sgirish #if defined(_BIT_FIELDS_HTOL) 33744961713Sgirish uint32_t ring_base:12; 33844961713Sgirish uint32_t skip:1; 33944961713Sgirish uint32_t rsvd:1; 34044961713Sgirish uint32_t tmode:2; 34144961713Sgirish uint32_t unmap_all_en:1; 34244961713Sgirish uint32_t ulp_end_en:1; 34344961713Sgirish uint32_t ulp_end:14; 34444961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 34544961713Sgirish uint32_t ulp_end:14; 34644961713Sgirish uint32_t ulp_end_en:1; 34744961713Sgirish uint32_t unmap_all_en:1; 34844961713Sgirish uint32_t tmode:2; 34944961713Sgirish uint32_t rsvd:1; 35044961713Sgirish uint32_t skip:1; 35144961713Sgirish uint32_t ring_base:12; 35244961713Sgirish #endif 35344961713Sgirish } ldw; 35444961713Sgirish #if !defined(_BIG_ENDIAN) 35544961713Sgirish uint32_t hdw; 35644961713Sgirish #endif 35744961713Sgirish } bits; 35844961713Sgirish } qw1; 35944961713Sgirish 36044961713Sgirish union { 36144961713Sgirish uint64_t value; 36244961713Sgirish struct { 36344961713Sgirish #if defined(_BIG_ENDIAN) 36444961713Sgirish uint32_t hdw; 36544961713Sgirish #endif 36644961713Sgirish struct { 36744961713Sgirish #if defined(_BIT_FIELDS_HTOL) 36844961713Sgirish uint32_t busy:1; 36944961713Sgirish uint32_t ring_size:4; 37044961713Sgirish uint32_t ring_base:27; 37144961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 37244961713Sgirish uint32_t ring_base:27; 37344961713Sgirish uint32_t ring_size:4; 37444961713Sgirish uint32_t busy:1; 37544961713Sgirish #endif 37644961713Sgirish } ldw; 37744961713Sgirish #if !defined(_BIG_ENDIAN) 37844961713Sgirish uint32_t hdw; 37944961713Sgirish #endif 38044961713Sgirish } bits; 38144961713Sgirish } qw2; 38244961713Sgirish 38344961713Sgirish union { 38444961713Sgirish uint64_t value; 38544961713Sgirish struct { 38644961713Sgirish #if defined(_BIG_ENDIAN) 38744961713Sgirish uint32_t hdw; 38844961713Sgirish #endif 38944961713Sgirish struct { 39044961713Sgirish #if defined(_BIT_FIELDS_HTOL) 39144961713Sgirish uint32_t rsvd:16; 39244961713Sgirish uint32_t toq:16; 39344961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 39444961713Sgirish uint32_t toq:16; 39544961713Sgirish uint32_t rsvd:16; 39644961713Sgirish #endif 39744961713Sgirish } ldw; 39844961713Sgirish #if !defined(_BIG_ENDIAN) 39944961713Sgirish uint32_t hdw; 40044961713Sgirish #endif 40144961713Sgirish } bits; 40244961713Sgirish } qw3; 40344961713Sgirish 40444961713Sgirish union { 40544961713Sgirish uint64_t value; 40644961713Sgirish struct { 40744961713Sgirish #if defined(_BIG_ENDIAN) 40844961713Sgirish uint32_t hdw; 40944961713Sgirish #endif 41044961713Sgirish struct { 41144961713Sgirish #if defined(_BIT_FIELDS_HTOL) 41244961713Sgirish uint32_t rsvd:28; 41344961713Sgirish uint32_t dat4:4; 41444961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 41544961713Sgirish uint32_t dat4:4; 41644961713Sgirish uint32_t rsvd:28; 41744961713Sgirish #endif 41844961713Sgirish } ldw; 41944961713Sgirish #if !defined(_BIG_ENDIAN) 42044961713Sgirish uint32_t hdw; 42144961713Sgirish #endif 42244961713Sgirish } bits; 42344961713Sgirish } qw4; 42444961713Sgirish 42544961713Sgirish } tte_sflow_attr_t, *tte_sflow_attr_pt; 42644961713Sgirish 42744961713Sgirish #define TTE_RDC_TBL_SFLOW_BITS_EN 0x0001 42844961713Sgirish #define TTE_BUF_SIZE_BITS_EN 0x0002 42944961713Sgirish #define TTE_NUM_BUF_BITS_EN 0x0002 43044961713Sgirish #define TTE_ULP_END_BITS_EN 0x003E 43144961713Sgirish #define TTE_ULP_END_EN_BITS_EN 0x0020 43244961713Sgirish #define TTE_UNMAP_ALL_BITS_EN 0x0020 43344961713Sgirish #define TTE_TMODE_BITS_EN 0x0040 43444961713Sgirish #define TTE_SKIP_BITS_EN 0x0040 43544961713Sgirish #define TTE_RING_BASE_ADDR_BITS_EN 0x0FC0 43644961713Sgirish #define TTE_RING_SIZE_BITS_EN 0x0800 43744961713Sgirish #define TTE_BUSY_BITS_EN 0x0800 43844961713Sgirish #define TTE_TOQ_BITS_EN 0x3000 43944961713Sgirish 44044961713Sgirish #define TTE_MAPPED_IN_BITS_EN 0x0000F 44144961713Sgirish #define TTE_ANCHOR_SEQ_BITS_EN 0x000F0 44244961713Sgirish #define TTE_ANCHOR_OFFSET_BITS_EN 0x00700 44344961713Sgirish #define TTE_ANCHOR_BUFFER_BITS_EN 0x00800 44444961713Sgirish #define TTE_ANCHOR_BUF_FLAG_BITS_EN 0x00800 44544961713Sgirish #define TTE_UNMAP_ON_LEFT_BITS_EN 0x00800 44644961713Sgirish #define TTE_ULP_END_REACHED_BITS_EN 0x00800 44744961713Sgirish #define TTE_ERR_STAT_BITS_EN 0x01000 44844961713Sgirish #define TTE_WR_PTR_BITS_EN 0x01000 44944961713Sgirish #define TTE_HOQ_BITS_EN 0x0E000 45044961713Sgirish #define TTE_PREFETCH_ON_BITS_EN 0x08000 45144961713Sgirish 45244961713Sgirish typedef enum tring_size_e { 45344961713Sgirish TRING_SIZE_8 = 0, 45444961713Sgirish TRING_SIZE_16, 45544961713Sgirish TRING_SIZE_32, 45644961713Sgirish TRING_SIZE_64, 45744961713Sgirish TRING_SIZE_128, 45844961713Sgirish TRING_SIZE_256, 45944961713Sgirish TRING_SIZE_512, 46044961713Sgirish TRING_SIZE_1K, 46144961713Sgirish TRING_SIZE_2K, 46244961713Sgirish TRING_SIZE_4K, 46344961713Sgirish TRING_SIZE_8K, 46444961713Sgirish TRING_SIZE_16K, 46544961713Sgirish TRING_SIZE_32K 46644961713Sgirish } tring_size_t; 46744961713Sgirish 46844961713Sgirish typedef struct tte_dflow_attr_s { 46944961713Sgirish union { 47044961713Sgirish uint64_t value; 47144961713Sgirish struct { 47244961713Sgirish #if defined(_BIG_ENDIAN) 47344961713Sgirish uint32_t hdw; 47444961713Sgirish #endif 47544961713Sgirish struct { 47644961713Sgirish #if defined(_BIT_FIELDS_HTOL) 47744961713Sgirish uint32_t mapped_in; 47844961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 47944961713Sgirish uint32_t mapped_in; 48044961713Sgirish #endif 48144961713Sgirish } ldw; 48244961713Sgirish #if !defined(_BIG_ENDIAN) 48344961713Sgirish uint32_t hdw; 48444961713Sgirish #endif 48544961713Sgirish } bits; 48644961713Sgirish } qw0; 48744961713Sgirish 48844961713Sgirish union { 48944961713Sgirish uint64_t value; 49044961713Sgirish struct { 49144961713Sgirish #if defined(_BIG_ENDIAN) 49244961713Sgirish uint32_t hdw; 49344961713Sgirish #endif 49444961713Sgirish struct { 49544961713Sgirish #if defined(_BIT_FIELDS_HTOL) 49644961713Sgirish uint32_t anchor_seq; 49744961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 49844961713Sgirish uint32_t anchor_seq; 49944961713Sgirish #endif 50044961713Sgirish } ldw; 50144961713Sgirish #if !defined(_BIG_ENDIAN) 50244961713Sgirish uint32_t hdw; 50344961713Sgirish #endif 50444961713Sgirish } bits; 50544961713Sgirish } qw1; 50644961713Sgirish 50744961713Sgirish union { 50844961713Sgirish uint64_t value; 50944961713Sgirish struct { 51044961713Sgirish #if defined(_BIG_ENDIAN) 51144961713Sgirish uint32_t hdw; 51244961713Sgirish #endif 51344961713Sgirish struct { 51444961713Sgirish #if defined(_BIT_FIELDS_HTOL) 51544961713Sgirish uint32_t ulp_end_reached; 51644961713Sgirish uint32_t unmap_on_left; 51744961713Sgirish uint32_t anchor_buf_flag; 51844961713Sgirish uint32_t anchor_buf:5; 51944961713Sgirish uint32_t anchor_offset:24; 52044961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 52144961713Sgirish uint32_t anchor_offset:24; 52244961713Sgirish uint32_t anchor_buf:5; 52344961713Sgirish uint32_t anchor_buf_flag; 52444961713Sgirish uint32_t unmap_on_left; 52544961713Sgirish uint32_t ulp_end_reached; 52644961713Sgirish #endif 52744961713Sgirish } ldw; 52844961713Sgirish #if !defined(_BIG_ENDIAN) 52944961713Sgirish uint32_t hdw; 53044961713Sgirish #endif 53144961713Sgirish } bits; 53244961713Sgirish } qw2; 53344961713Sgirish 53444961713Sgirish union { 53544961713Sgirish uint64_t value; 53644961713Sgirish struct { 53744961713Sgirish #if defined(_BIG_ENDIAN) 53844961713Sgirish uint32_t hdw; 53944961713Sgirish #endif 54044961713Sgirish struct { 54144961713Sgirish #if defined(_BIT_FIELDS_HTOL) 54244961713Sgirish uint32_t rsvd1:1; 54344961713Sgirish uint32_t prefetch_on:1; 54444961713Sgirish uint32_t hoq:16; 54544961713Sgirish uint32_t rsvd:6; 54644961713Sgirish uint32_t wr_ptr:6; 54744961713Sgirish uint32_t err_stat:2; 54844961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 54944961713Sgirish uint32_t err_stat:2; 55044961713Sgirish uint32_t wr_ptr:6; 55144961713Sgirish uint32_t rsvd:6; 55244961713Sgirish uint32_t hoq:16; 55344961713Sgirish uint32_t prefetch_on:1; 55444961713Sgirish uint32_t rsvd1:1; 55544961713Sgirish #endif 55644961713Sgirish } ldw; 55744961713Sgirish #if !defined(_BIG_ENDIAN) 55844961713Sgirish uint32_t hdw; 55944961713Sgirish #endif 56044961713Sgirish } bits; 56144961713Sgirish } qw3; 56244961713Sgirish 56344961713Sgirish union { 56444961713Sgirish uint64_t value; 56544961713Sgirish struct { 56644961713Sgirish #if defined(_BIG_ENDIAN) 56744961713Sgirish uint32_t hdw; 56844961713Sgirish #endif 56944961713Sgirish struct { 57044961713Sgirish #if defined(_BIT_FIELDS_HTOL) 57144961713Sgirish uint32_t rsvd:28; 57244961713Sgirish uint32_t dat4:4; 57344961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 57444961713Sgirish uint32_t dat4:4; 57544961713Sgirish uint32_t rsvd:28; 57644961713Sgirish #endif 57744961713Sgirish } ldw; 57844961713Sgirish #if !defined(_BIG_ENDIAN) 57944961713Sgirish uint32_t hdw; 58044961713Sgirish #endif 58144961713Sgirish } bits; 58244961713Sgirish } qw4; 58344961713Sgirish 58444961713Sgirish } tte_dflow_attr_t, *tte_dflow_attr_pt; 58544961713Sgirish 58644961713Sgirish #define MAX_BAM_BANKS 8 58744961713Sgirish 58844961713Sgirish typedef struct zcp_ram_unit_s { 58944961713Sgirish uint32_t w0; 59044961713Sgirish uint32_t w1; 59144961713Sgirish uint32_t w2; 59244961713Sgirish uint32_t w3; 59344961713Sgirish uint32_t w4; 59444961713Sgirish } zcp_ram_unit_t; 59544961713Sgirish 59644961713Sgirish typedef enum dmaw_type_e { 59744961713Sgirish DMAW_NO_CROSS_BUF = 0, 59844961713Sgirish DMAW_IP_CROSS_BUF_2, 59944961713Sgirish DMAW_IP_CROSS_BUF_3, 60044961713Sgirish DMAW_IP_CROSS_BUF_4 60144961713Sgirish } dmaw_type_t; 60244961713Sgirish 60344961713Sgirish typedef union zcp_ram_data_u { 60444961713Sgirish tte_sflow_attr_t sentry; 60544961713Sgirish tte_dflow_attr_t dentry; 60644961713Sgirish } zcp_ram_data_t, *zcp_ram_data_pt; 60744961713Sgirish 60844961713Sgirish typedef union zcp_ram_access_u { 60944961713Sgirish uint64_t value; 61044961713Sgirish struct { 61144961713Sgirish #if defined(_BIG_ENDIAN) 61244961713Sgirish uint32_t hdw; 61344961713Sgirish #endif 61444961713Sgirish struct { 61544961713Sgirish #if defined(_BIT_FIELDS_HTOL) 61644961713Sgirish uint32_t busy:1; 61744961713Sgirish uint32_t rdwr:1; 61844961713Sgirish uint32_t rsvd:1; 61944961713Sgirish uint32_t zcfid:12; 62044961713Sgirish uint32_t ram_sel:5; 62144961713Sgirish uint32_t cfifo:12; 62244961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 62344961713Sgirish uint32_t cfifo:12; 62444961713Sgirish uint32_t ram_sel:5; 62544961713Sgirish uint32_t zcfid:12; 62644961713Sgirish uint32_t rsvd:1; 62744961713Sgirish uint32_t rdwr:1; 62844961713Sgirish uint32_t busy:1; 62944961713Sgirish #endif 63044961713Sgirish } ldw; 63144961713Sgirish #if !defined(_BIG_ENDIAN) 63244961713Sgirish uint32_t hdw; 63344961713Sgirish #endif 63444961713Sgirish } bits; 63544961713Sgirish } zcp_ram_access_t, *zcp_ram_access_pt; 63644961713Sgirish 63744961713Sgirish #define ZCP_RAM_WR 0 63844961713Sgirish #define ZCP_RAM_RD 1 63944961713Sgirish #define ZCP_RAM_SEL_BAM0 0 64044961713Sgirish #define ZCP_RAM_SEL_BAM1 0x1 64144961713Sgirish #define ZCP_RAM_SEL_BAM2 0x2 64244961713Sgirish #define ZCP_RAM_SEL_BAM3 0x3 64344961713Sgirish #define ZCP_RAM_SEL_BAM4 0x4 64444961713Sgirish #define ZCP_RAM_SEL_BAM5 0x5 64544961713Sgirish #define ZCP_RAM_SEL_BAM6 0x6 64644961713Sgirish #define ZCP_RAM_SEL_BAM7 0x7 64744961713Sgirish #define ZCP_RAM_SEL_TT_STATIC 0x8 64844961713Sgirish #define ZCP_RAM_SEL_TT_DYNAMIC 0x9 64944961713Sgirish #define ZCP_RAM_SEL_CFIFO0 0x10 65044961713Sgirish #define ZCP_RAM_SEL_CFIFO1 0x11 65144961713Sgirish #define ZCP_RAM_SEL_CFIFO2 0x12 65244961713Sgirish #define ZCP_RAM_SEL_CFIFO3 0x13 65344961713Sgirish 65444961713Sgirish typedef union zcp_ram_benable_u { 65544961713Sgirish uint64_t value; 65644961713Sgirish struct { 65744961713Sgirish #if defined(_BIG_ENDIAN) 65844961713Sgirish uint32_t hdw; 65944961713Sgirish #endif 66044961713Sgirish struct { 66144961713Sgirish #if defined(_BIT_FIELDS_HTOL) 66244961713Sgirish uint32_t rsvd:15; 66344961713Sgirish uint32_t be:17; 66444961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 66544961713Sgirish uint32_t be:17; 66644961713Sgirish uint32_t rsvd:15; 66744961713Sgirish #endif 66844961713Sgirish } ldw; 66944961713Sgirish #if !defined(_BIG_ENDIAN) 67044961713Sgirish uint32_t hdw; 67144961713Sgirish #endif 67244961713Sgirish } bits; 67344961713Sgirish } zcp_ram_benable_t, *zcp_ram_benable_pt; 67444961713Sgirish 67544961713Sgirish typedef union zcp_training_vector_u { 67644961713Sgirish uint64_t value; 67744961713Sgirish struct { 67844961713Sgirish #if defined(_BIG_ENDIAN) 67944961713Sgirish uint32_t hdw; 68044961713Sgirish #endif 68144961713Sgirish struct { 68244961713Sgirish #if defined(_BIT_FIELDS_HTOL) 68344961713Sgirish uint32_t train_vec; 68444961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 68544961713Sgirish uint32_t train_vec; 68644961713Sgirish #endif 68744961713Sgirish } ldw; 68844961713Sgirish #if !defined(_BIG_ENDIAN) 68944961713Sgirish uint32_t hdw; 69044961713Sgirish #endif 69144961713Sgirish } bits; 69244961713Sgirish } zcp_training_vector_t, *zcp_training_vector_pt; 69344961713Sgirish 69444961713Sgirish typedef union zcp_state_machine_u { 69544961713Sgirish uint64_t value; 69644961713Sgirish struct { 69744961713Sgirish #if defined(_BIG_ENDIAN) 69844961713Sgirish uint32_t hdw; 69944961713Sgirish #endif 70044961713Sgirish struct { 70144961713Sgirish #if defined(_BIT_FIELDS_HTOL) 70244961713Sgirish uint32_t state; 70344961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 70444961713Sgirish uint32_t state; 70544961713Sgirish #endif 70644961713Sgirish } ldw; 70744961713Sgirish #if !defined(_BIG_ENDIAN) 70844961713Sgirish uint32_t hdw; 70944961713Sgirish #endif 71044961713Sgirish } bits; 71144961713Sgirish } zcp_state_machine_t, *zcp_state_machine_pt; 71244961713Sgirish 71344961713Sgirish typedef struct zcp_hdr_s { 71444961713Sgirish uint16_t zflowid; 71544961713Sgirish uint16_t tcp_hdr_len; 71644961713Sgirish uint16_t tcp_payld_len; 71744961713Sgirish uint16_t head_of_que; 71844961713Sgirish uint32_t first_b_offset; 71944961713Sgirish boolean_t reach_buf_end; 72044961713Sgirish dmaw_type_t dmaw_type; 72144961713Sgirish uint8_t win_buf_offset; 72244961713Sgirish } zcp_hdr_t; 72344961713Sgirish 72444961713Sgirish typedef union _zcp_ecc_ctrl { 72544961713Sgirish uint64_t value; 72644961713Sgirish 72744961713Sgirish struct { 72844961713Sgirish #if defined(_BIG_ENDIAN) 72944961713Sgirish uint32_t w1; 73044961713Sgirish #endif 73144961713Sgirish struct { 73244961713Sgirish #if defined(_BIT_FIELDS_HTOL) 73344961713Sgirish uint32_t dis_dbl : 1; 73444961713Sgirish uint32_t res3 : 13; 73544961713Sgirish uint32_t cor_dbl : 1; 73644961713Sgirish uint32_t cor_sng : 1; 73744961713Sgirish uint32_t res2 : 5; 73844961713Sgirish uint32_t cor_all : 1; 73944961713Sgirish uint32_t res1 : 7; 74044961713Sgirish uint32_t cor_lst : 1; 74144961713Sgirish uint32_t cor_snd : 1; 74244961713Sgirish uint32_t cor_fst : 1; 74344961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 74444961713Sgirish uint32_t cor_fst : 1; 74544961713Sgirish uint32_t cor_snd : 1; 74644961713Sgirish uint32_t cor_lst : 1; 74744961713Sgirish uint32_t res1 : 7; 74844961713Sgirish uint32_t cor_all : 1; 74944961713Sgirish uint32_t res2 : 5; 75044961713Sgirish uint32_t cor_sng : 1; 75144961713Sgirish uint32_t cor_dbl : 1; 75244961713Sgirish uint32_t res3 : 13; 75344961713Sgirish uint32_t dis_dbl : 1; 75444961713Sgirish #else 75544961713Sgirish #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined 75644961713Sgirish #endif 75744961713Sgirish } w0; 75844961713Sgirish 75944961713Sgirish #if !defined(_BIG_ENDIAN) 76044961713Sgirish uint32_t w1; 76144961713Sgirish #endif 76244961713Sgirish } bits; 76344961713Sgirish } zcp_ecc_ctrl_t; 76444961713Sgirish 76544961713Sgirish #ifdef __cplusplus 76644961713Sgirish } 76744961713Sgirish #endif 76844961713Sgirish 76944961713Sgirish #endif /* _SYS_NXGE_NXGE_ZCP_HW_H */ 770