144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
2144961713Sgirish /*
22678453a8Sspeer  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
2344961713Sgirish  * Use is subject to license terms.
2444961713Sgirish  */
2544961713Sgirish 
2644961713Sgirish #ifndef	_SYS_NXGE_NXGE_TXDMA_HW_H
2744961713Sgirish #define	_SYS_NXGE_NXGE_TXDMA_HW_H
2844961713Sgirish 
2944961713Sgirish #ifdef	__cplusplus
3044961713Sgirish extern "C" {
3144961713Sgirish #endif
3244961713Sgirish 
3344961713Sgirish #include <nxge_defs.h>
3444961713Sgirish #include <nxge_hw.h>
3544961713Sgirish 
3644961713Sgirish #if !defined(_BIG_ENDIAN)
3744961713Sgirish #define	SWAP(X)	(X)
3844961713Sgirish #else
3944961713Sgirish #define	SWAP(X)   \
4044961713Sgirish 	(((X >> 32) & 0x00000000ffffffff) | \
4144961713Sgirish 	((X << 32) & 0xffffffff00000000))
4244961713Sgirish #endif
4344961713Sgirish 
4444961713Sgirish /*
4544961713Sgirish  * Partitioning Suport: same as those defined for the RX
4644961713Sgirish  */
47678453a8Sspeer 
4844961713Sgirish /*
4944961713Sgirish  * TDC: Partitioning Support
5044961713Sgirish  *	(Each of the following registers is for each TDC)
5144961713Sgirish  */
5244961713Sgirish #define	TX_LOG_REG_SIZE			512
5344961713Sgirish #define	TX_LOG_DMA_OFFSET(channel)	(channel * TX_LOG_REG_SIZE)
5444961713Sgirish 
5544961713Sgirish #define	TX_LOG_PAGE_VLD_REG		(FZC_DMC + 0x40000)
5644961713Sgirish #define	TX_LOG_PAGE_MASK1_REG		(FZC_DMC + 0x40008)
5744961713Sgirish #define	TX_LOG_PAGE_VAL1_REG		(FZC_DMC + 0x40010)
5844961713Sgirish #define	TX_LOG_PAGE_MASK2_REG		(FZC_DMC + 0x40018)
5944961713Sgirish #define	TX_LOG_PAGE_VAL2_REG		(FZC_DMC + 0x40020)
6044961713Sgirish #define	TX_LOG_PAGE_RELO1_REG		(FZC_DMC + 0x40028)
6144961713Sgirish #define	TX_LOG_PAGE_RELO2_REG		(FZC_DMC + 0x40030)
6244961713Sgirish #define	TX_LOG_PAGE_HDL_REG		(FZC_DMC + 0x40038)
6344961713Sgirish 
6444961713Sgirish /* Transmit Addressing Mode: Set to 1 to select 32-bit addressing mode */
6544961713Sgirish #define	TX_ADDR_MD_REG			(FZC_DMC + 0x45000)
6644961713Sgirish 
6744961713Sgirish #define	TX_ADDR_MD_SHIFT	0			/* bits 0:0 */
6844961713Sgirish #define	TX_ADDR_MD_SET_32	0x0000000000000001ULL	/* 1 to select 32 bit */
6944961713Sgirish #define	TX_ADDR_MD_MASK		0x0000000000000001ULL
7044961713Sgirish 
7144961713Sgirish typedef union _tx_addr_md_t {
7244961713Sgirish 	uint64_t value;
7344961713Sgirish 	struct {
7444961713Sgirish #if defined(_BIG_ENDIAN)
7544961713Sgirish 		uint32_t hdw;
7644961713Sgirish #endif
7744961713Sgirish 		struct {
7844961713Sgirish #if defined(_BIT_FIELDS_HTOL)
7944961713Sgirish 			uint32_t res1_1:31;
8044961713Sgirish 			uint32_t mode32:1;
8144961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
8244961713Sgirish 			uint32_t mode32:1;
8344961713Sgirish 			uint32_t res1_1:31;
8444961713Sgirish #endif
8544961713Sgirish 		} ldw;
8644961713Sgirish #if !defined(_BIG_ENDIAN)
8744961713Sgirish 		uint32_t hdw;
8844961713Sgirish #endif
8944961713Sgirish 	} bits;
9044961713Sgirish } tx_addr_md_t, *p_tx_addr_md_t;
9144961713Sgirish 
9244961713Sgirish /* Transmit Packet Descriptor Structure */
9344961713Sgirish #define	TX_PKT_DESC_SAD_SHIFT		0		/* bits 43:0 */
9444961713Sgirish #define	TX_PKT_DESC_SAD_MASK		0x00000FFFFFFFFFFFULL
9544961713Sgirish #define	TX_PKT_DESC_TR_LEN_SHIFT	44		/* bits 56:44 */
9644961713Sgirish #define	TX_PKT_DESC_TR_LEN_MASK		0x01FFF00000000000ULL
9744961713Sgirish #define	TX_PKT_DESC_NUM_PTR_SHIFT	58		/* bits 61:58 */
9844961713Sgirish #define	TX_PKT_DESC_NUM_PTR_MASK	0x3C00000000000000ULL
9944961713Sgirish #define	TX_PKT_DESC_MARK_SHIFT		62		/* bit 62 */
10044961713Sgirish #define	TX_PKT_DESC_MARK		0x4000000000000000ULL
10144961713Sgirish #define	TX_PKT_DESC_MARK_MASK		0x4000000000000000ULL
10244961713Sgirish #define	TX_PKT_DESC_SOP_SHIFT		63		/* bit 63 */
10344961713Sgirish #define	TX_PKT_DESC_SOP			0x8000000000000000ULL
10444961713Sgirish #define	TX_PKT_DESC_SOP_MASK		0x8000000000000000ULL
10544961713Sgirish 
10644961713Sgirish typedef union _tx_desc_t {
10744961713Sgirish 	uint64_t value;
10844961713Sgirish 	struct {
10944961713Sgirish #if defined(_BIG_ENDIAN)
11044961713Sgirish 		struct {
11144961713Sgirish #if defined(_BIT_FIELDS_HTOL)
11244961713Sgirish 			uint32_t sop:1;
11344961713Sgirish 			uint32_t mark:1;
11444961713Sgirish 			uint32_t num_ptr:4;
11544961713Sgirish 			uint32_t res1:1;
11644961713Sgirish 			uint32_t tr_len:13;
11744961713Sgirish 			uint32_t sad:12;
11844961713Sgirish 
11944961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
12044961713Sgirish 			uint32_t sad:12;
12144961713Sgirish 			uint32_t tr_len:13;
12244961713Sgirish 			uint32_t res1:1;
12344961713Sgirish 			uint32_t num_ptr:4;
12444961713Sgirish 			uint32_t mark:1;
12544961713Sgirish 			uint32_t sop:1;
12644961713Sgirish 
12744961713Sgirish #endif
12844961713Sgirish 		} hdw;
12944961713Sgirish #endif
13044961713Sgirish 		struct {
13144961713Sgirish #if defined(_BIT_FIELDS_HTOL)
13244961713Sgirish 			uint32_t sad:32;
13344961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
13444961713Sgirish 			uint32_t sad:32;
13544961713Sgirish #endif
13644961713Sgirish 		} ldw;
13744961713Sgirish #if !defined(_BIG_ENDIAN)
13844961713Sgirish 		struct {
13944961713Sgirish 
14044961713Sgirish #if defined(_BIT_FIELDS_HTOL)
14144961713Sgirish 			uint32_t sop:1;
14244961713Sgirish 			uint32_t mark:1;
14344961713Sgirish 			uint32_t num_ptr:4;
14444961713Sgirish 			uint32_t res1:1;
14544961713Sgirish 			uint32_t tr_len:13;
14644961713Sgirish 			uint32_t sad:12;
14744961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
14844961713Sgirish 			uint32_t sad:12;
14944961713Sgirish 			uint32_t tr_len:13;
15044961713Sgirish 			uint32_t res1:1;
15144961713Sgirish 			uint32_t num_ptr:4;
15244961713Sgirish 			uint32_t mark:1;
15344961713Sgirish 			uint32_t sop:1;
15444961713Sgirish #endif
15544961713Sgirish 		} hdw;
15644961713Sgirish #endif
15744961713Sgirish 	} bits;
15844961713Sgirish } tx_desc_t, *p_tx_desc_t;
15944961713Sgirish 
16044961713Sgirish 
16144961713Sgirish /* Transmit Ring Configuration (24 Channels) */
16244961713Sgirish #define	TX_RNG_CFIG_REG			(DMC + 0x40000)
16344961713Sgirish #if OLD
16444961713Sgirish #define	TX_RING_HDH_REG			(DMC + 0x40008)
16544961713Sgirish #endif
16644961713Sgirish #define	TX_RING_HDL_REG			(DMC + 0x40010)
16744961713Sgirish #define	TX_RING_KICK_REG		(DMC + 0x40018)
16844961713Sgirish #define	TX_ENT_MSK_REG			(DMC + 0x40020)
16944961713Sgirish #define	TX_CS_REG			(DMC + 0x40028)
17044961713Sgirish #define	TXDMA_MBH_REG			(DMC + 0x40030)
17144961713Sgirish #define	TXDMA_MBL_REG			(DMC + 0x40038)
17244961713Sgirish #define	TX_DMA_PRE_ST_REG		(DMC + 0x40040)
17344961713Sgirish #define	TX_RNG_ERR_LOGH_REG		(DMC + 0x40048)
17444961713Sgirish #define	TX_RNG_ERR_LOGL_REG		(DMC + 0x40050)
17544961713Sgirish #define	TDMC_INTR_DBG_REG		(DMC + 0x40060)
17644961713Sgirish #define	TX_CS_DBG_REG			(DMC + 0x40068)
17744961713Sgirish 
17844961713Sgirish /* Transmit Ring Configuration */
17944961713Sgirish #define	TX_RNG_CFIG_STADDR_SHIFT	6			/* bits 18:6 */
18044961713Sgirish #define	TX_RNG_CFIG_STADDR_MASK		0x000000000007FFC0ULL
18144961713Sgirish #define	TX_RNG_CFIG_ADDR_MASK		0x00000FFFFFFFFFC0ULL
18244961713Sgirish #define	TX_RNG_CFIG_STADDR_BASE_SHIFT	19			/* bits 43:19 */
18344961713Sgirish #define	TX_RNG_CFIG_STADDR_BASE_MASK	0x00000FFFFFF80000ULL
18444961713Sgirish #define	TX_RNG_CFIG_LEN_SHIFT		48			/* bits 60:48 */
18544961713Sgirish #define	TX_RNG_CFIG_LEN_MASK		0xFFF8000000000000ULL
18644961713Sgirish 
18744961713Sgirish #define	TX_RNG_HEAD_TAIL_SHIFT		3
18844961713Sgirish #define	TX_RNG_HEAD_TAIL_WRAP_SHIFT	19
18944961713Sgirish 
19044961713Sgirish typedef union _tx_rng_cfig_t {
19144961713Sgirish 	uint64_t value;
19244961713Sgirish 	struct {
19344961713Sgirish #if defined(_BIG_ENDIAN)
19444961713Sgirish 		struct {
19544961713Sgirish #if defined(_BIT_FIELDS_HTOL)
19644961713Sgirish 			uint32_t res2:3;
19744961713Sgirish 			uint32_t len:13;
19844961713Sgirish 			uint32_t res1:4;
19944961713Sgirish 			uint32_t staddr_base:12;
20044961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
20144961713Sgirish 			uint32_t staddr_base:12;
20244961713Sgirish 			uint32_t res1:4;
20344961713Sgirish 			uint32_t len:13;
20444961713Sgirish 			uint32_t res2:3;
20544961713Sgirish #endif
20644961713Sgirish 		} hdw;
20744961713Sgirish #endif
20844961713Sgirish 		struct {
20944961713Sgirish #if defined(_BIT_FIELDS_HTOL)
21044961713Sgirish 			uint32_t staddr_base:13;
21144961713Sgirish 			uint32_t staddr:13;
21244961713Sgirish 			uint32_t res2:6;
21344961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
21444961713Sgirish 			uint32_t res2:6;
21544961713Sgirish 			uint32_t staddr:13;
21644961713Sgirish 			uint32_t staddr_base:13;
21744961713Sgirish #endif
21844961713Sgirish 		} ldw;
21944961713Sgirish #ifndef _BIG_ENDIAN
22044961713Sgirish 		struct {
22144961713Sgirish #if defined(_BIT_FIELDS_HTOL)
22244961713Sgirish 			uint32_t res2:3;
22344961713Sgirish 			uint32_t len:13;
22444961713Sgirish 			uint32_t res1:4;
22544961713Sgirish 			uint32_t staddr_base:12;
22644961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
22744961713Sgirish 			uint32_t staddr_base:12;
22844961713Sgirish 			uint32_t res1:4;
22944961713Sgirish 			uint32_t len:13;
23044961713Sgirish 			uint32_t res2:3;
23144961713Sgirish #endif
23244961713Sgirish 		} hdw;
23344961713Sgirish #endif
23444961713Sgirish 	} bits;
23544961713Sgirish } tx_rng_cfig_t, *p_tx_rng_cfig_t;
23644961713Sgirish 
23744961713Sgirish /* Transmit Ring Head Low */
23844961713Sgirish #define	TX_RING_HDL_SHIFT		3			/* bit 31:3 */
23944961713Sgirish #define	TX_RING_HDL_MASK		0x00000000FFFFFFF8ULL
24044961713Sgirish 
24144961713Sgirish typedef union _tx_ring_hdl_t {
24244961713Sgirish 	uint64_t value;
24344961713Sgirish 	struct {
24444961713Sgirish #if defined(_BIG_ENDIAN)
24544961713Sgirish 		uint32_t hdw;
24644961713Sgirish #endif
24744961713Sgirish 		struct {
24844961713Sgirish #if defined(_BIT_FIELDS_HTOL)
24944961713Sgirish 			uint32_t res0:12;
25044961713Sgirish 			uint32_t wrap:1;
25144961713Sgirish 			uint32_t head:16;
25244961713Sgirish 			uint32_t res2:3;
25344961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
25444961713Sgirish 			uint32_t res2:3;
25544961713Sgirish 			uint32_t head:16;
25644961713Sgirish 			uint32_t wrap:1;
25744961713Sgirish 			uint32_t res0:12;
25844961713Sgirish #endif
25944961713Sgirish 		} ldw;
26044961713Sgirish #ifndef _BIG_ENDIAN
26144961713Sgirish 		uint32_t hdw;
26244961713Sgirish #endif
26344961713Sgirish 	} bits;
26444961713Sgirish } tx_ring_hdl_t, *p_tx_ring_hdl_t;
26544961713Sgirish 
26644961713Sgirish /* Transmit Ring Kick */
26744961713Sgirish #define	TX_RING_KICK_TAIL_SHIFT		3			/* bit 43:3 */
26844961713Sgirish #define	TX_RING_KICK_TAIL_MASK		0x000000FFFFFFFFFF8ULL
26944961713Sgirish 
27044961713Sgirish typedef union _tx_ring_kick_t {
27144961713Sgirish 	uint64_t value;
27244961713Sgirish 	struct {
27344961713Sgirish #ifdef	_BIG_ENDIAN
27444961713Sgirish 		uint32_t hdw;
27544961713Sgirish #endif
27644961713Sgirish 		struct {
27744961713Sgirish #if defined(_BIT_FIELDS_HTOL)
27844961713Sgirish 			uint32_t res0:12;
27944961713Sgirish 			uint32_t wrap:1;
28044961713Sgirish 			uint32_t tail:16;
28144961713Sgirish 			uint32_t res2:3;
28244961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
28344961713Sgirish 			uint32_t res2:3;
28444961713Sgirish 			uint32_t tail:16;
28544961713Sgirish 			uint32_t wrap:1;
28644961713Sgirish 			uint32_t res0:12;
28744961713Sgirish #endif
28844961713Sgirish 		} ldw;
28944961713Sgirish #ifndef _BIG_ENDIAN
29044961713Sgirish 		uint32_t hdw;
29144961713Sgirish #endif
29244961713Sgirish 	} bits;
29344961713Sgirish } tx_ring_kick_t, *p_tx_ring_kick_t;
29444961713Sgirish 
29544961713Sgirish /* Transmit Event Mask (DMC + 0x40020) */
29644961713Sgirish #define	TX_ENT_MSK_PKT_PRT_ERR_SHIFT		0	/* bit 0: 0 to flag */
29744961713Sgirish #define	TX_ENT_MSK_PKT_PRT_ERR_MASK		0x0000000000000001ULL
29844961713Sgirish #define	TX_ENT_MSK_CONF_PART_ERR_SHIFT		1	/* bit 1: 0 to flag */
29944961713Sgirish #define	TX_ENT_MSK_CONF_PART_ERR_MASK		0x0000000000000002ULL
30044961713Sgirish #define	TX_ENT_MSK_NACK_PKT_RD_SHIFT		2	/* bit 2: 0 to flag */
30144961713Sgirish #define	TX_ENT_MSK_NACK_PKT_RD_MASK		0x0000000000000004ULL
30244961713Sgirish #define	TX_ENT_MSK_NACK_PREF_SHIFT		3	/* bit 3: 0 to flag */
30344961713Sgirish #define	TX_ENT_MSK_NACK_PREF_MASK		0x0000000000000008ULL
30444961713Sgirish #define	TX_ENT_MSK_PREF_BUF_ECC_ERR_SHIFT	4	/* bit 4: 0 to flag */
30544961713Sgirish #define	TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK	0x0000000000000010ULL
30644961713Sgirish #define	TX_ENT_MSK_TX_RING_OFLOW_SHIFT		5	/* bit 5: 0 to flag */
30744961713Sgirish #define	TX_ENT_MSK_TX_RING_OFLOW_MASK		0x0000000000000020ULL
30844961713Sgirish #define	TX_ENT_MSK_PKT_SIZE_ERR_SHIFT		6	/* bit 6: 0 to flag */
30944961713Sgirish #define	TX_ENT_MSK_PKT_SIZE_ERR_MASK		0x0000000000000040ULL
31044961713Sgirish #define	TX_ENT_MSK_MBOX_ERR_SHIFT		7	/* bit 7: 0 to flag */
31144961713Sgirish #define	TX_ENT_MSK_MBOX_ERR_MASK		0x0000000000000080ULL
31244961713Sgirish #define	TX_ENT_MSK_MK_SHIFT			15	/* bit 15: 0 to flag */
31344961713Sgirish #define	TX_ENT_MSK_MK_MASK			0x0000000000008000ULL
31444961713Sgirish #define	TX_ENT_MSK_MK_ALL		(TX_ENT_MSK_PKT_PRT_ERR_MASK | \
31544961713Sgirish 					TX_ENT_MSK_CONF_PART_ERR_MASK |	\
31644961713Sgirish 					TX_ENT_MSK_NACK_PKT_RD_MASK |	\
31744961713Sgirish 					TX_ENT_MSK_NACK_PREF_MASK |	\
31844961713Sgirish 					TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK | \
31944961713Sgirish 					TX_ENT_MSK_TX_RING_OFLOW_MASK |	\
32044961713Sgirish 					TX_ENT_MSK_PKT_SIZE_ERR_MASK | \
32144961713Sgirish 					TX_ENT_MSK_MBOX_ERR_MASK | \
32244961713Sgirish 					TX_ENT_MSK_MK_MASK)
32344961713Sgirish 
32444961713Sgirish 
32544961713Sgirish typedef union _tx_dma_ent_msk_t {
32644961713Sgirish 	uint64_t value;
32744961713Sgirish 	struct {
32844961713Sgirish #ifdef	_BIG_ENDIAN
32944961713Sgirish 		uint32_t hdw;
33044961713Sgirish #endif
33144961713Sgirish 		struct {
33244961713Sgirish #if defined(_BIT_FIELDS_HTOL)
33344961713Sgirish 			uint32_t res1_1:16;
33444961713Sgirish 			uint32_t mk:1;
33544961713Sgirish 			uint32_t res2:7;
33644961713Sgirish 			uint32_t mbox_err:1;
33744961713Sgirish 			uint32_t pkt_size_err:1;
33844961713Sgirish 			uint32_t tx_ring_oflow:1;
33944961713Sgirish 			uint32_t pref_buf_ecc_err:1;
34044961713Sgirish 			uint32_t nack_pref:1;
34144961713Sgirish 			uint32_t nack_pkt_rd:1;
34244961713Sgirish 			uint32_t conf_part_err:1;
34344961713Sgirish 			uint32_t pkt_prt_err:1;
34444961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
34544961713Sgirish 			uint32_t pkt_prt_err:1;
34644961713Sgirish 			uint32_t conf_part_err:1;
34744961713Sgirish 			uint32_t nack_pkt_rd:1;
34844961713Sgirish 			uint32_t nack_pref:1;
34944961713Sgirish 			uint32_t pref_buf_ecc_err:1;
35044961713Sgirish 			uint32_t tx_ring_oflow:1;
35144961713Sgirish 			uint32_t pkt_size_err:1;
35244961713Sgirish 			uint32_t mbox_err:1;
35344961713Sgirish 			uint32_t res2:7;
35444961713Sgirish 			uint32_t mk:1;
35544961713Sgirish 			uint32_t res1_1:16;
35644961713Sgirish #endif
35744961713Sgirish 		} ldw;
35844961713Sgirish #ifndef _BIG_ENDIAN
35944961713Sgirish 		uint32_t hdw;
36044961713Sgirish #endif
36144961713Sgirish 	} bits;
36244961713Sgirish } tx_dma_ent_msk_t, *p_tx_dma_ent_msk_t;
36344961713Sgirish 
36444961713Sgirish 
36544961713Sgirish /* Transmit Control and Status  (DMC + 0x40028) */
36644961713Sgirish #define	TX_CS_PKT_PRT_ERR_SHIFT			0	/* RO, bit 0 */
36744961713Sgirish #define	TX_CS_PKT_PRT_ERR_MASK			0x0000000000000001ULL
36844961713Sgirish #define	TX_CS_CONF_PART_ERR_SHIF		1	/* RO, bit 1 */
36944961713Sgirish #define	TX_CS_CONF_PART_ERR_MASK		0x0000000000000002ULL
37044961713Sgirish #define	TX_CS_NACK_PKT_RD_SHIFT			2	/* RO, bit 2 */
37144961713Sgirish #define	TX_CS_NACK_PKT_RD_MASK			0x0000000000000004ULL
37244961713Sgirish #define	TX_CS_PREF_SHIFT			3	/* RO, bit 3 */
37344961713Sgirish #define	TX_CS_PREF_MASK				0x0000000000000008ULL
37444961713Sgirish #define	TX_CS_PREF_BUF_PAR_ERR_SHIFT		4	/* RO, bit 4 */
37544961713Sgirish #define	TX_CS_PREF_BUF_PAR_ERR_MASK		0x0000000000000010ULL
37644961713Sgirish #define	TX_CS_RING_OFLOW_SHIFT			5	/* RO, bit 5 */
37744961713Sgirish #define	TX_CS_RING_OFLOW_MASK			0x0000000000000020ULL
37844961713Sgirish #define	TX_CS_PKT_SIZE_ERR_SHIFT		6	/* RW, bit 6 */
37944961713Sgirish #define	TX_CS_PKT_SIZE_ERR_MASK			0x0000000000000040ULL
38044961713Sgirish #define	TX_CS_MMK_SHIFT				14	/* RC, bit 14 */
38144961713Sgirish #define	TX_CS_MMK_MASK				0x0000000000004000ULL
38244961713Sgirish #define	TX_CS_MK_SHIFT				15	/* RCW1C, bit 15 */
38344961713Sgirish #define	TX_CS_MK_MASK				0x0000000000008000ULL
38444961713Sgirish #define	TX_CS_SNG_SHIFT				27	/* RO, bit 27 */
38544961713Sgirish #define	TX_CS_SNG_MASK				0x0000000008000000ULL
38644961713Sgirish #define	TX_CS_STOP_N_GO_SHIFT			28	/* RW, bit 28 */
38744961713Sgirish #define	TX_CS_STOP_N_GO_MASK			0x0000000010000000ULL
38844961713Sgirish #define	TX_CS_MB_SHIFT				29	/* RO, bit 29 */
38944961713Sgirish #define	TX_CS_MB_MASK				0x0000000020000000ULL
39044961713Sgirish #define	TX_CS_RST_STATE_SHIFT			30	/* Rw, bit 30 */
39144961713Sgirish #define	TX_CS_RST_STATE_MASK			0x0000000040000000ULL
39244961713Sgirish #define	TX_CS_RST_SHIFT				31	/* Rw, bit 31 */
39344961713Sgirish #define	TX_CS_RST_MASK				0x0000000080000000ULL
39444961713Sgirish #define	TX_CS_LASTMASK_SHIFT			32	/* RW, bit 43:32 */
39544961713Sgirish #define	TX_CS_LASTMARK_MASK			0x00000FFF00000000ULL
39644961713Sgirish #define	TX_CS_PKT_CNT_SHIFT			48	/* RW, bit 59:48 */
39744961713Sgirish #define	TX_CS_PKT_CNT_MASK			0x0FFF000000000000ULL
39844961713Sgirish 
39944961713Sgirish /* Trasnmit Control and Status */
40044961713Sgirish typedef union _tx_cs_t {
40144961713Sgirish 	uint64_t value;
40244961713Sgirish 	struct {
40344961713Sgirish #ifdef	_BIG_ENDIAN
40444961713Sgirish 		struct {
40544961713Sgirish #if defined(_BIT_FIELDS_HTOL)
40644961713Sgirish 			uint32_t res1:4;
40744961713Sgirish 			uint32_t pkt_cnt:12;
40844961713Sgirish 			uint32_t res2:4;
40944961713Sgirish 			uint32_t lastmark:12;
41044961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
41144961713Sgirish 			uint32_t lastmark:12;
41244961713Sgirish 			uint32_t res2:4;
41344961713Sgirish 			uint32_t pkt_cnt:12;
41444961713Sgirish 			uint32_t res1:4;
41544961713Sgirish #endif
41644961713Sgirish 		} hdw;
41744961713Sgirish 
41844961713Sgirish #endif
41944961713Sgirish 		struct {
42044961713Sgirish #if defined(_BIT_FIELDS_HTOL)
42144961713Sgirish 			uint32_t rst:1;
42244961713Sgirish 			uint32_t rst_state:1;
42344961713Sgirish 			uint32_t mb:1;
42444961713Sgirish 			uint32_t stop_n_go:1;
42544961713Sgirish 			uint32_t sng_state:1;
42644961713Sgirish 			uint32_t res1:11;
42744961713Sgirish 			uint32_t mk:1;
42844961713Sgirish 			uint32_t mmk:1;
42944961713Sgirish 			uint32_t res2:6;
43044961713Sgirish 			uint32_t mbox_err:1;
43144961713Sgirish 			uint32_t pkt_size_err:1;
43244961713Sgirish 			uint32_t tx_ring_oflow:1;
43344961713Sgirish 			uint32_t pref_buf_par_err:1;
43444961713Sgirish 			uint32_t nack_pref:1;
43544961713Sgirish 			uint32_t nack_pkt_rd:1;
43644961713Sgirish 			uint32_t conf_part_err:1;
43744961713Sgirish 			uint32_t pkt_prt_err:1;
43844961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
43944961713Sgirish 			uint32_t pkt_prt_err:1;
44044961713Sgirish 			uint32_t conf_part_err:1;
44144961713Sgirish 			uint32_t nack_pkt_rd:1;
44244961713Sgirish 			uint32_t nack_pref:1;
44344961713Sgirish 			uint32_t pref_buf_par_err:1;
44444961713Sgirish 			uint32_t tx_ring_oflow:1;
44544961713Sgirish 			uint32_t pkt_size_err:1;
44644961713Sgirish 			uint32_t mbox_err:1;
44744961713Sgirish 			uint32_t res2:6;
44844961713Sgirish 			uint32_t mmk:1;
44944961713Sgirish 			uint32_t mk:1;
45044961713Sgirish 			uint32_t res1:11;
45144961713Sgirish 			uint32_t sng_state:1;
45244961713Sgirish 			uint32_t stop_n_go:1;
45344961713Sgirish 			uint32_t mb:1;
45444961713Sgirish 			uint32_t rst_state:1;
45544961713Sgirish 			uint32_t rst:1;
45644961713Sgirish #endif
45744961713Sgirish 		} ldw;
45844961713Sgirish #ifndef _BIG_ENDIAN
45944961713Sgirish 		struct {
46044961713Sgirish #if defined(_BIT_FIELDS_HTOL)
46144961713Sgirish 			uint32_t res1:4;
46244961713Sgirish 			uint32_t pkt_cnt:12;
46344961713Sgirish 			uint32_t res2:4;
46444961713Sgirish 			uint32_t lastmark:12;
46544961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
46644961713Sgirish 			uint32_t lastmark:12;
46744961713Sgirish 			uint32_t res2:4;
46844961713Sgirish 			uint32_t pkt_cnt:12;
46944961713Sgirish 			uint32_t res1:4;
47044961713Sgirish #endif
47144961713Sgirish 	} hdw;
47244961713Sgirish 
47344961713Sgirish #endif
47444961713Sgirish 	} bits;
47544961713Sgirish } tx_cs_t, *p_tx_cs_t;
47644961713Sgirish 
47744961713Sgirish /* Trasnmit Mailbox High (DMC + 0x40030) */
47844961713Sgirish #define	TXDMA_MBH_SHIFT			0	/* bit 11:0 */
47944961713Sgirish #define	TXDMA_MBH_ADDR_SHIFT		32	/* bit 43:32 */
48044961713Sgirish #define	TXDMA_MBH_MASK			0x0000000000000FFFULL
48144961713Sgirish 
48244961713Sgirish typedef union _txdma_mbh_t {
48344961713Sgirish 	uint64_t value;
48444961713Sgirish 	struct {
48544961713Sgirish #ifdef	_BIG_ENDIAN
48644961713Sgirish 		uint32_t hdw;
48744961713Sgirish #endif
48844961713Sgirish 		struct {
48944961713Sgirish #if defined(_BIT_FIELDS_HTOL)
49044961713Sgirish 			uint32_t res1_1:20;
49144961713Sgirish 			uint32_t mbaddr:12;
49244961713Sgirish 
49344961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
49444961713Sgirish 			uint32_t mbaddr:12;
49544961713Sgirish 			uint32_t res1_1:20;
49644961713Sgirish #endif
49744961713Sgirish 		} ldw;
49844961713Sgirish #ifndef _BIG_ENDIAN
49944961713Sgirish 		uint32_t hdw;
50044961713Sgirish #endif
50144961713Sgirish 	} bits;
50244961713Sgirish } txdma_mbh_t, *p_txdma_mbh_t;
50344961713Sgirish 
50444961713Sgirish 
50544961713Sgirish /* Trasnmit Mailbox Low (DMC + 0x40038) */
50644961713Sgirish #define	TXDMA_MBL_SHIFT			6	/* bit 31:6 */
50744961713Sgirish #define	TXDMA_MBL_MASK			0x00000000FFFFFFC0ULL
50844961713Sgirish 
50944961713Sgirish typedef union _txdma_mbl_t {
51044961713Sgirish 	uint64_t value;
51144961713Sgirish 	struct {
51244961713Sgirish #ifdef	_BIG_ENDIAN
51344961713Sgirish 		uint32_t hdw;
51444961713Sgirish #endif
51544961713Sgirish 		struct {
51644961713Sgirish #if defined(_BIT_FIELDS_HTOL)
51744961713Sgirish 			uint32_t mbaddr:26;
51844961713Sgirish 			uint32_t res2:6;
51944961713Sgirish 
52044961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
52144961713Sgirish 			uint32_t res2:6;
52244961713Sgirish 			uint32_t mbaddr:26;
52344961713Sgirish #endif
52444961713Sgirish 		} ldw;
52544961713Sgirish #ifndef _BIG_ENDIAN
52644961713Sgirish 		uint32_t hdw;
52744961713Sgirish #endif
52844961713Sgirish 	} bits;
52944961713Sgirish } txdma_mbl_t, *p_txdma_mbl_t;
53044961713Sgirish 
53144961713Sgirish /* Trasnmit Prefetch State High (DMC + 0x40040) */
53244961713Sgirish #define	TX_DMA_PREF_ST_SHIFT		0	/* bit 5:0 */
53344961713Sgirish #define	TX_DMA_PREF_ST_MASK		0x000000000000003FULL
53444961713Sgirish 
53544961713Sgirish typedef union _tx_dma_pre_st_t {
53644961713Sgirish 	uint64_t value;
53744961713Sgirish 	struct {
53844961713Sgirish #ifdef	_BIG_ENDIAN
53944961713Sgirish 		uint32_t hdw;
54044961713Sgirish #endif
54144961713Sgirish 		struct {
54244961713Sgirish #if defined(_BIT_FIELDS_HTOL)
54344961713Sgirish 			uint32_t res1_1:13;
54444961713Sgirish 			uint32_t shadow_hd:19;
54544961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
54644961713Sgirish 			uint32_t shadow_hd:19;
54744961713Sgirish 			uint32_t res1_1:13;
54844961713Sgirish #endif
54944961713Sgirish 		} ldw;
55044961713Sgirish #ifndef _BIG_ENDIAN
55144961713Sgirish 		uint32_t hdw;
55244961713Sgirish #endif
55344961713Sgirish 	} bits;
55444961713Sgirish } tx_dma_pre_st_t, *p_tx_dma_pre_st_t;
55544961713Sgirish 
55644961713Sgirish /* Trasnmit Ring Error Log High (DMC + 0x40048) */
55744961713Sgirish #define	TX_RNG_ERR_LOGH_ERR_ADDR_SHIFT		0	/* RO bit 11:0 */
55844961713Sgirish #define	TX_RNG_ERR_LOGH_ERR_ADDR_MASK		0x0000000000000FFFULL
55944961713Sgirish #define	TX_RNG_ERR_LOGH_ADDR_SHIFT		32
56044961713Sgirish #define	TX_RNG_ERR_LOGH_ERRCODE_SHIFT		26	/* RO bit 29:26 */
56144961713Sgirish #define	TX_RNG_ERR_LOGH_ERRCODE_MASK		0x000000003C000000ULL
56244961713Sgirish #define	TX_RNG_ERR_LOGH_MERR_SHIFT		30	/* RO bit 30 */
56344961713Sgirish #define	TX_RNG_ERR_LOGH_MERR_MASK		0x0000000040000000ULL
56444961713Sgirish #define	TX_RNG_ERR_LOGH_ERR_SHIFT		31	/* RO bit 31 */
56544961713Sgirish #define	TX_RNG_ERR_LOGH_ERR_MASK		0x0000000080000000ULL
56644961713Sgirish 
56744961713Sgirish /* Transmit Ring Error codes */
56844961713Sgirish #define	TXDMA_RING_PKT_PRT_ERR			0
56944961713Sgirish #define	TXDMA_RING_CONF_PART_ERR		0x01
57044961713Sgirish #define	TXDMA_RING_NACK_PKT_ERR			0x02
57144961713Sgirish #define	TXDMA_RING_NACK_PREF_ERR		0x03
57244961713Sgirish #define	TXDMA_RING_PREF_BUF_PAR_ERR		0x04
57344961713Sgirish #define	TXDMA_RING_TX_RING_OFLOW_ERR		0x05
57444961713Sgirish #define	TXDMA_RING_PKT_SIZE_ERR			0x06
57544961713Sgirish 
57644961713Sgirish typedef union _tx_rng_err_logh_t {
57744961713Sgirish 	uint64_t value;
57844961713Sgirish 	struct {
57944961713Sgirish #ifdef	_BIG_ENDIAN
58044961713Sgirish 		uint32_t hdw;
58144961713Sgirish #endif
58244961713Sgirish 		struct {
58344961713Sgirish #if defined(_BIT_FIELDS_HTOL)
58444961713Sgirish 			uint32_t err:1;
58544961713Sgirish 			uint32_t merr:1;
58644961713Sgirish 			uint32_t errcode:4;
58744961713Sgirish 			uint32_t res2:14;
58844961713Sgirish 			uint32_t err_addr:12;
58944961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
59044961713Sgirish 			uint32_t err_addr:12;
59144961713Sgirish 			uint32_t res2:14;
59244961713Sgirish 			uint32_t errcode:4;
59344961713Sgirish 			uint32_t merr:1;
59444961713Sgirish 			uint32_t err:1;
59544961713Sgirish 
59644961713Sgirish #endif
59744961713Sgirish 		} ldw;
59844961713Sgirish #ifndef _BIG_ENDIAN
59944961713Sgirish 		uint32_t hdw;
60044961713Sgirish #endif
60144961713Sgirish 	} bits;
60244961713Sgirish } tx_rng_err_logh_t, *p_tx_rng_err_logh_t;
60344961713Sgirish 
60444961713Sgirish 
60544961713Sgirish /* Trasnmit Ring Error Log Log (DMC + 0x40050) */
60644961713Sgirish #define	TX_RNG_ERR_LOGL_ERR_ADDR_SHIFT		0	/* RO bit 31:0 */
60744961713Sgirish #define	TX_RNG_ERR_LOGL_ERR_ADDR_MASK		0x00000000FFFFFFFFULL
60844961713Sgirish 
60944961713Sgirish typedef union _tx_rng_err_logl_t {
61044961713Sgirish 	uint64_t value;
61144961713Sgirish 	struct {
61244961713Sgirish #ifdef	_BIG_ENDIAN
61344961713Sgirish 		uint32_t hdw;
61444961713Sgirish #endif
61544961713Sgirish 		struct {
61644961713Sgirish #if defined(_BIT_FIELDS_HTOL)
61744961713Sgirish 			uint32_t err_addr:32;
61844961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
61944961713Sgirish 			uint32_t err_addr:32;
62044961713Sgirish 
62144961713Sgirish #endif
62244961713Sgirish 		} ldw;
62344961713Sgirish #ifndef _BIG_ENDIAN
62444961713Sgirish 		uint32_t hdw;
62544961713Sgirish #endif
62644961713Sgirish 	} bits;
62744961713Sgirish } tx_rng_err_logl_t, *p_tx_rng_err_logl_t;
62844961713Sgirish 
62944961713Sgirish /*
63044961713Sgirish  * TDMC_INTR_RBG_REG (DMC + 0x40060)
63144961713Sgirish  */
63244961713Sgirish typedef union _tdmc_intr_dbg_t {
63344961713Sgirish 	uint64_t value;
63444961713Sgirish 	struct {
63544961713Sgirish #ifdef	_BIG_ENDIAN
63644961713Sgirish 		uint32_t hdw;
63744961713Sgirish #endif
63844961713Sgirish 		struct {
63944961713Sgirish #if defined(_BIT_FIELDS_HTOL)
64044961713Sgirish 			uint32_t res:16;
64144961713Sgirish 			uint32_t mk:1;
64244961713Sgirish 			uint32_t rsvd:7;
64344961713Sgirish 			uint32_t mbox_err:1;
64444961713Sgirish 			uint32_t pkt_size_err:1;
64544961713Sgirish 			uint32_t tx_ring_oflow:1;
64644961713Sgirish 			uint32_t pref_buf_par_err:1;
64744961713Sgirish 			uint32_t nack_pref:1;
64844961713Sgirish 			uint32_t nack_pkt_rd:1;
64944961713Sgirish 			uint32_t conf_part_err:1;
65044961713Sgirish 			uint32_t pkt_part_err:1;
65144961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
65244961713Sgirish 			uint32_t pkt_part_err:1;
65344961713Sgirish 			uint32_t conf_part_err:1;
65444961713Sgirish 			uint32_t nack_pkt_rd:1;
65544961713Sgirish 			uint32_t nack_pref:1;
65644961713Sgirish 			uint32_t pref_buf_par_err:1;
65744961713Sgirish 			uint32_t tx_ring_oflow:1;
65844961713Sgirish 			uint32_t pkt_size_err:1;
65944961713Sgirish 			uint32_t mbox_err:1;
66044961713Sgirish 			uint32_t rsvd:7;
66144961713Sgirish 			uint32_t mk:1;
66244961713Sgirish 			uint32_t res:16;
66344961713Sgirish #endif
66444961713Sgirish 		} ldw;
66544961713Sgirish #ifndef _BIG_ENDIAN
66644961713Sgirish 		uint32_t hdw;
66744961713Sgirish #endif
66844961713Sgirish 	} bits;
66944961713Sgirish } tdmc_intr_dbg_t, *p_tdmc_intr_dbg_t;
67044961713Sgirish 
67144961713Sgirish 
67244961713Sgirish /*
67344961713Sgirish  * TX_CS_DBG (DMC + 0x40068)
67444961713Sgirish  */
67544961713Sgirish typedef union _tx_cs_dbg_t {
67644961713Sgirish 	uint64_t value;
67744961713Sgirish 	struct {
67844961713Sgirish #ifdef	_BIG_ENDIAN
67944961713Sgirish 		struct {
68044961713Sgirish #if defined(_BIT_FIELDS_HTOL)
68144961713Sgirish 			uint32_t res1:4;
68244961713Sgirish 			uint32_t pkt_cnt:12;
68344961713Sgirish 			uint32_t res2:16;
68444961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
68544961713Sgirish 			uint32_t res2:16;
68644961713Sgirish 			uint32_t pkt_cnt:12;
68744961713Sgirish 			uint32_t res1:4;
68844961713Sgirish #endif
68944961713Sgirish 		} hdw;
69044961713Sgirish 
69144961713Sgirish #endif
69244961713Sgirish 		struct {
69344961713Sgirish #if defined(_BIT_FIELDS_HTOL)
69444961713Sgirish 			uint32_t rsvd:32;
69544961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
69644961713Sgirish 			uint32_t rsvd:32;
69744961713Sgirish 
69844961713Sgirish #endif
69944961713Sgirish 		} ldw;
70044961713Sgirish 
70144961713Sgirish #ifndef _BIG_ENDIAN
70244961713Sgirish 		struct {
70344961713Sgirish #if defined(_BIT_FIELDS_HTOL)
70444961713Sgirish 			uint32_t res1:4;
70544961713Sgirish 			uint32_t pkt_cnt:12;
70644961713Sgirish 			uint32_t res2:16;
70744961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
70844961713Sgirish 			uint32_t res2:16;
70944961713Sgirish 			uint32_t pkt_cnt:12;
71044961713Sgirish 			uint32_t res1:4;
71144961713Sgirish #endif
71244961713Sgirish 	} hdw;
71344961713Sgirish 
71444961713Sgirish #endif
71544961713Sgirish 	} bits;
71644961713Sgirish } tx_cs_dbg_t, *p_tx_cs_dbg_t;
71744961713Sgirish 
71844961713Sgirish #define	TXDMA_MAILBOX_BYTE_LENGTH		64
71944961713Sgirish #define	TXDMA_MAILBOX_UNUSED			24
72044961713Sgirish 
72144961713Sgirish typedef struct _txdma_mailbox_t {
72244961713Sgirish 	tx_cs_t			tx_cs;				/* 8 bytes */
72344961713Sgirish 	tx_dma_pre_st_t		tx_dma_pre_st;			/* 8 bytes */
72444961713Sgirish 	tx_ring_hdl_t		tx_ring_hdl;			/* 8 bytes */
72544961713Sgirish 	tx_ring_kick_t		tx_ring_kick;			/* 8 bytes */
72644961713Sgirish 	uint32_t		tx_rng_err_logh;		/* 4 bytes */
72744961713Sgirish 	uint32_t		tx_rng_err_logl;		/* 4 bytes */
72844961713Sgirish 	uint32_t		resv[TXDMA_MAILBOX_UNUSED];
72944961713Sgirish } txdma_mailbox_t, *p_txdma_mailbox_t;
73044961713Sgirish 
73144961713Sgirish #if OLD
73244961713Sgirish /* Transmit Ring Scheduler (per port) */
73344961713Sgirish #define	TX_DMA_MAP_OFFSET(port)		(port * 8 + TX_DMA_MAP_REG)
73444961713Sgirish #define	TX_DMA_MAP_PORT_OFFSET(port)	(port * 8)
73544961713Sgirish #define	TX_DMA_MAP_REG			(FZC_DMC + 0x50000)
73644961713Sgirish #define	TX_DMA_MAP0_REG			(FZC_DMC + 0x50000)
73744961713Sgirish #define	TX_DMA_MAP1_REG			(FZC_DMC + 0x50008)
73844961713Sgirish #define	TX_DMA_MAP2_REG			(FZC_DMC + 0x50010)
73944961713Sgirish #define	TX_DMA_MAP3_REG			(FZC_DMC + 0x50018)
74044961713Sgirish 
74144961713Sgirish #define	TX_DMA_MAP_SHIFT		0	/* RO bit 31:0 */
74244961713Sgirish #define	TX_DMA_MAPMASK			0x00000000FFFFFFFFULL
74344961713Sgirish 
74444961713Sgirish typedef union _tx_dma_map_t {
74544961713Sgirish 	uint64_t value;
74644961713Sgirish 	struct {
74744961713Sgirish #ifdef	_BIG_ENDIAN
74844961713Sgirish 		uint32_t hdw;
74944961713Sgirish #endif
75044961713Sgirish 		struct {
75144961713Sgirish #if defined(_BIT_FIELDS_HTOL)
75244961713Sgirish 			uint32_t bind:32;
75344961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
75444961713Sgirish 			uint32_t bind:32;
75544961713Sgirish 
75644961713Sgirish #endif
75744961713Sgirish 		} ldw;
75844961713Sgirish #ifndef _BIG_ENDIAN
75944961713Sgirish 		uint32_t hdw;
76044961713Sgirish #endif
76144961713Sgirish 	} bits;
76244961713Sgirish } tx_dma_map_t, *p_tx_dma_map_t;
76344961713Sgirish #endif
76444961713Sgirish 
76544961713Sgirish #if OLD
76644961713Sgirish /* Transmit Ring Scheduler: DRR Weight (32 Channels) */
76744961713Sgirish #define	DRR_WT_REG			(FZC_DMC + 0x51000)
76844961713Sgirish #define	DRR_WT_SHIFT			0	/* RO bit 19:0 */
76944961713Sgirish #define	DRR_WT_MASK			0x00000000000FFFFFULL
77044961713Sgirish 
77144961713Sgirish #define	TXDMA_DRR_RNG_USE_OFFSET(channel)	(channel * 16)
77244961713Sgirish 
77344961713Sgirish typedef union _drr_wt_t {
77444961713Sgirish 	uint64_t value;
77544961713Sgirish 	struct {
77644961713Sgirish #ifdef	_BIG_ENDIAN
77744961713Sgirish 		uint32_t hdw;
77844961713Sgirish #endif
77944961713Sgirish 		struct {
78044961713Sgirish #if defined(_BIT_FIELDS_HTOL)
78144961713Sgirish 			uint32_t res1_1:12;
78244961713Sgirish 			uint32_t wt:20;
78344961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
78444961713Sgirish 			uint32_t wt:20;
78544961713Sgirish 			uint32_t res1_1:12;
78644961713Sgirish #endif
78744961713Sgirish 		} ldw;
78844961713Sgirish #ifndef _BIG_ENDIAN
78944961713Sgirish 		uint32_t hdw;
79044961713Sgirish #endif
79144961713Sgirish 	} bits;
79244961713Sgirish } drr_wt_t, *p_drr_wt_t;
79344961713Sgirish #endif
79444961713Sgirish 
79544961713Sgirish #if OLD
79644961713Sgirish 
79744961713Sgirish /* Performance Monitoring (32 Channels) */
79844961713Sgirish #define	TXRNG_USE_REG			(FZC_DMC + 0x51008)
79944961713Sgirish #define	TXRNG_USE_CNT_SHIFT		0	/* RO bit 26:0 */
80044961713Sgirish #define	TXRNG_USE_CNT_MASK		0x0000000007FFFFFFULL
80144961713Sgirish #define	TXRNG_USE_OFLOW_SHIFT		0	/* RO bit 27 */
80244961713Sgirish #define	TXRNG_USE_OFLOW_MASK		0x0000000008000000ULL
80344961713Sgirish 
80444961713Sgirish typedef union _txrng_use_t {
80544961713Sgirish 	uint64_t value;
80644961713Sgirish 	struct {
80744961713Sgirish #ifdef	_BIG_ENDIAN
80844961713Sgirish 		uint32_t hdw;
80944961713Sgirish #endif
81044961713Sgirish 		struct {
81144961713Sgirish #if defined(_BIT_FIELDS_HTOL)
81244961713Sgirish 			uint32_t res1_1:4;
81344961713Sgirish 			uint32_t oflow:1;
81444961713Sgirish 			uint32_t cnt:27;
81544961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
81644961713Sgirish 			uint32_t cnt:27;
81744961713Sgirish 			uint32_t oflow:1;
81844961713Sgirish 			uint32_t res1_1:4;
81944961713Sgirish 
82044961713Sgirish #endif
82144961713Sgirish 		} ldw;
82244961713Sgirish #ifndef _BIG_ENDIAN
82344961713Sgirish 		uint32_t hdw;
82444961713Sgirish #endif
82544961713Sgirish 	} bits;
82644961713Sgirish } txrng_use_t, *p_txrng_use_t;
82744961713Sgirish 
82844961713Sgirish #endif
82944961713Sgirish 
83044961713Sgirish /*
83144961713Sgirish  * Internal Transmit Packet Format (16 bytes)
83244961713Sgirish  */
83344961713Sgirish #define	TX_PKT_HEADER_SIZE			16
83444961713Sgirish #define	TX_MAX_GATHER_POINTERS			15
83544961713Sgirish #define	TX_GATHER_POINTERS_THRESHOLD		8
83644961713Sgirish /*
83744961713Sgirish  * There is bugs in the hardware
83844961713Sgirish  * and max sfter len is changed from 4096 to 4076.
83944961713Sgirish  *
84044961713Sgirish  * Jumbo from 9500 to 9216
84144961713Sgirish  */
84244961713Sgirish #define	TX_MAX_TRANSFER_LENGTH			4076
84344961713Sgirish #define	TX_JUMBO_MTU				9216
84444961713Sgirish 
84544961713Sgirish #define	TX_PKT_HEADER_PAD_SHIFT			0	/* bit 2:0 */
84644961713Sgirish #define	TX_PKT_HEADER_PAD_MASK			0x0000000000000007ULL
84744961713Sgirish #define	TX_PKT_HEADER_TOT_XFER_LEN_SHIFT	16	/* bit 16:29 */
84844961713Sgirish #define	TX_PKT_HEADER_TOT_XFER_LEN_MASK		0x000000000000FFF8ULL
84944961713Sgirish #define	TX_PKT_HEADER_L4STUFF_SHIFT		32	/* bit 37:32 */
85044961713Sgirish #define	TX_PKT_HEADER_L4STUFF_MASK		0x0000003F00000000ULL
85144961713Sgirish #define	TX_PKT_HEADER_L4START_SHIFT		40	/* bit 45:40 */
85244961713Sgirish #define	TX_PKT_HEADER_L4START_MASK		0x00003F0000000000ULL
85344961713Sgirish #define	TX_PKT_HEADER_L3START_SHIFT		48	/* bit 45:40 */
85444961713Sgirish #define	TX_PKT_HEADER_IHL_SHIFT			52	/* bit 52 */
85544961713Sgirish #define	TX_PKT_HEADER_VLAN__SHIFT		56	/* bit 56 */
85644961713Sgirish #define	TX_PKT_HEADER_TCP_UDP_CRC32C_SHIFT	57	/* bit 57 */
85744961713Sgirish #define	TX_PKT_HEADER_LLC_SHIFT			57	/* bit 57 */
85844961713Sgirish #define	TX_PKT_HEADER_TCP_UDP_CRC32C_SET	0x0200000000000000ULL
85944961713Sgirish #define	TX_PKT_HEADER_TCP_UDP_CRC32C_MASK	0x0200000000000000ULL
86044961713Sgirish #define	TX_PKT_HEADER_L4_PROTO_OP_SHIFT		2	/* bit 59:58 */
86144961713Sgirish #define	TX_PKT_HEADER_L4_PROTO_OP_MASK		0x0C00000000000000ULL
86244961713Sgirish #define	TX_PKT_HEADER_V4_HDR_CS_SHIFT		60	/* bit 60 */
86344961713Sgirish #define	TX_PKT_HEADER_V4_HDR_CS_SET		0x1000000000000000ULL
86444961713Sgirish #define	TX_PKT_HEADER_V4_HDR_CS_MASK		0x1000000000000000ULL
86544961713Sgirish #define	TX_PKT_HEADER_IP_VER_SHIFT		61	/* bit 61 */
86644961713Sgirish #define	TX_PKT_HEADER_IP_VER_MASK		0x2000000000000000ULL
86744961713Sgirish #define	TX_PKT_HEADER_PKT_TYPE_SHIFT		62	/* bit 62 */
86844961713Sgirish #define	TX_PKT_HEADER_PKT_TYPE_MASK		0x4000000000000000ULL
86944961713Sgirish 
87044961713Sgirish /* L4 Prototol Operations */
87144961713Sgirish #define	TX_PKT_L4_PROTO_OP_NOP			0x00
87244961713Sgirish #define	TX_PKT_L4_PROTO_OP_FULL_L4_CSUM		0x01
87344961713Sgirish #define	TX_PKT_L4_PROTO_OP_L4_PAYLOAD_CSUM	0x02
87444961713Sgirish #define	TX_PKT_L4_PROTO_OP_SCTP_CRC32		0x04
87544961713Sgirish 
87644961713Sgirish /* Transmit Packet Types */
87744961713Sgirish #define	TX_PKT_PKT_TYPE_NOP			0x00
87844961713Sgirish #define	TX_PKT_PKT_TYPE_TCP			0x01
87944961713Sgirish #define	TX_PKT_PKT_TYPE_UDP			0x02
88044961713Sgirish #define	TX_PKT_PKT_TYPE_SCTP			0x03
88144961713Sgirish 
882*b4d05839Sml #define	TX_CKSUM_EN_PKT_TYPE_TCP	(1ull << TX_PKT_HEADER_PKT_TYPE_SHIFT)
883*b4d05839Sml #define	TX_CKSUM_EN_PKT_TYPE_UDP	(2ull << TX_PKT_HEADER_PKT_TYPE_SHIFT)
884*b4d05839Sml #define	TX_CKSUM_EN_PKT_TYPE_NOOP	(0ull << TX_PKT_HEADER_PKT_TYPE_SHIFT)
885*b4d05839Sml 
88644961713Sgirish typedef union _tx_pkt_header_t {
88744961713Sgirish 	uint64_t value;
88844961713Sgirish 	struct {
88944961713Sgirish 		struct {
89044961713Sgirish #if defined(_BIT_FIELDS_HTOL)
89144961713Sgirish 			uint32_t pad:3;
89244961713Sgirish 			uint32_t resv2:13;
89344961713Sgirish 			uint32_t tot_xfer_len:14;
89444961713Sgirish 			uint32_t resv1:2;
89544961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
89644961713Sgirish 			uint32_t pad:3;
89744961713Sgirish 			uint32_t resv2:13;
89844961713Sgirish 			uint32_t tot_xfer_len:14;
89944961713Sgirish 			uint32_t resv1:2;
90044961713Sgirish #endif
90144961713Sgirish 		} ldw;
90244961713Sgirish 		struct {
90344961713Sgirish #if defined(_BIT_FIELDS_HTOL)
90444961713Sgirish 			uint32_t l4stuff:6;
90544961713Sgirish 			uint32_t resv3:2;
90644961713Sgirish 			uint32_t l4start:6;
90744961713Sgirish 			uint32_t resv2:2;
90844961713Sgirish 			uint32_t l3start:4;
90944961713Sgirish 			uint32_t ihl:4;
91044961713Sgirish 			uint32_t vlan:1;
91144961713Sgirish 			uint32_t llc:1;
91244961713Sgirish 			uint32_t res1:3;
91344961713Sgirish 			uint32_t ip_ver:1;
91444961713Sgirish 			uint32_t cksum_en_pkt_type:2;
91544961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
91644961713Sgirish 			uint32_t l4stuff:6;
91744961713Sgirish 			uint32_t resv3:2;
91844961713Sgirish 			uint32_t l4start:6;
91944961713Sgirish 			uint32_t resv2:2;
92044961713Sgirish 			uint32_t l3start:4;
92144961713Sgirish 			uint32_t ihl:4;
92244961713Sgirish 			uint32_t vlan:1;
92344961713Sgirish 			uint32_t llc:1;
92444961713Sgirish 			uint32_t res1:3;
92544961713Sgirish 			uint32_t ip_ver:1;
92644961713Sgirish 			uint32_t cksum_en_pkt_type:2;
92744961713Sgirish #endif
92844961713Sgirish 		} hdw;
92944961713Sgirish 	} bits;
93044961713Sgirish } tx_pkt_header_t, *p_tx_pkt_header_t;
93144961713Sgirish 
93244961713Sgirish typedef struct _tx_pkt_hdr_all_t {
93344961713Sgirish 	tx_pkt_header_t		pkthdr;
93444961713Sgirish 	uint64_t		reserved;
93544961713Sgirish } tx_pkt_hdr_all_t, *p_tx_pkt_hdr_all_t;
93644961713Sgirish 
93744961713Sgirish /* Debug only registers */
93844961713Sgirish #define	TDMC_INJ_PAR_ERR_REG		(FZC_DMC + 0x45040)
93944961713Sgirish #define	TDMC_INJ_PAR_ERR_MASK		0x0000000000FFFFFFULL
94044961713Sgirish #define	TDMC_INJ_PAR_ERR_MASK_N2	0x000000000000FFFFULL
94144961713Sgirish 
94244961713Sgirish typedef union _tdmc_inj_par_err_t {
94344961713Sgirish 	uint64_t value;
94444961713Sgirish 	struct {
94544961713Sgirish #ifdef	_BIG_ENDIAN
94644961713Sgirish 		uint32_t hdw;
94744961713Sgirish #endif
94844961713Sgirish 		struct {
94944961713Sgirish #if defined(_BIT_FIELDS_HTOL)
95044961713Sgirish 			uint32_t rsvc:8;
95144961713Sgirish 			uint32_t inject_parity_error:24;
95244961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
95344961713Sgirish 			uint32_t inject_parity_error:24;
95444961713Sgirish 			uint32_t rsvc:8;
95544961713Sgirish #endif
95644961713Sgirish 		} ldw;
95744961713Sgirish #ifndef _BIG_ENDIAN
95844961713Sgirish 		uint32_t hdw;
95944961713Sgirish #endif
96044961713Sgirish 	} bits;
96144961713Sgirish } tdmc_inj_par_err_t, *p_tdmc_inj_par_err_t;
96244961713Sgirish 
96344961713Sgirish typedef union _tdmc_inj_par_err_n2_t {
96444961713Sgirish 	uint64_t value;
96544961713Sgirish 	struct {
96644961713Sgirish #ifdef	_BIG_ENDIAN
96744961713Sgirish 		uint32_t hdw;
96844961713Sgirish #endif
96944961713Sgirish 		struct {
97044961713Sgirish #if defined(_BIT_FIELDS_HTOL)
97144961713Sgirish 			uint32_t rsvc:16;
97244961713Sgirish 			uint32_t inject_parity_error:16;
97344961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
97444961713Sgirish 			uint32_t inject_parity_error:16;
97544961713Sgirish 			uint32_t rsvc:16;
97644961713Sgirish #endif
97744961713Sgirish 		} ldw;
97844961713Sgirish #ifndef _BIG_ENDIAN
97944961713Sgirish 		uint32_t hdw;
98044961713Sgirish #endif
98144961713Sgirish 	} bits;
98244961713Sgirish } tdmc_inj_par_err_n2_t, *p_tdmc_inj_par_err_n2_t;
98344961713Sgirish 
98444961713Sgirish #define	TDMC_DBG_SEL_REG		(FZC_DMC + 0x45080)
98544961713Sgirish #define	TDMC_DBG_SEL_MASK		0x000000000000003FULL
98644961713Sgirish 
98744961713Sgirish typedef union _tdmc_dbg_sel_t {
98844961713Sgirish 	uint64_t value;
98944961713Sgirish 	struct {
99044961713Sgirish #ifdef	_BIG_ENDIAN
99144961713Sgirish 		uint32_t hdw;
99244961713Sgirish #endif
99344961713Sgirish 		struct {
99444961713Sgirish #if defined(_BIT_FIELDS_HTOL)
99544961713Sgirish 			uint32_t rsvc:26;
99644961713Sgirish 			uint32_t dbg_sel:6;
99744961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
99844961713Sgirish 			uint32_t dbg_sel:6;
99944961713Sgirish 			uint32_t rsvc:26;
100044961713Sgirish #endif
100144961713Sgirish 		} ldw;
100244961713Sgirish #ifndef _BIG_ENDIAN
100344961713Sgirish 		uint32_t hdw;
100444961713Sgirish #endif
100544961713Sgirish 	} bits;
100644961713Sgirish } tdmc_dbg_sel_t, *p_tdmc_dbg_sel_t;
100744961713Sgirish 
100844961713Sgirish #define	TDMC_TRAINING_REG		(FZC_DMC + 0x45088)
100944961713Sgirish #define	TDMC_TRAINING_MASK		0x00000000FFFFFFFFULL
101044961713Sgirish 
101144961713Sgirish typedef union _tdmc_training_t {
101244961713Sgirish 	uint64_t value;
101344961713Sgirish 	struct {
101444961713Sgirish #ifdef	_BIG_ENDIAN
101544961713Sgirish 		uint32_t hdw;
101644961713Sgirish #endif
101744961713Sgirish 		struct {
101844961713Sgirish #if defined(_BIT_FIELDS_HTOL)
101944961713Sgirish 			uint32_t vec:32;
102044961713Sgirish #elif defined(_BIT_FIELDS_LTOH)
102144961713Sgirish 			uint32_t vec:6;
102244961713Sgirish #endif
102344961713Sgirish 		} ldw;
102444961713Sgirish #ifndef _BIG_ENDIAN
102544961713Sgirish 		uint32_t hdw;
102644961713Sgirish #endif
102744961713Sgirish 	} bits;
102844961713Sgirish } tdmc_training_t, *p_tdmc_training_t;
102944961713Sgirish 
103044961713Sgirish #ifdef	__cplusplus
103144961713Sgirish }
103244961713Sgirish #endif
103344961713Sgirish 
103444961713Sgirish #endif	/* _SYS_NXGE_NXGE_TXDMA_HW_H */
1035