1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_NXGE_NXGE_RXDMA_H
27 #define	_SYS_NXGE_NXGE_RXDMA_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 #include <sys/nxge/nxge_rxdma_hw.h>
36 #include <npi_rxdma.h>
37 
38 #define	RXDMA_CK_DIV_DEFAULT		7500 	/* 25 usec */
39 /*
40  * Hardware RDC designer: 8 cache lines during Atlas bringup.
41  */
42 #define	RXDMA_RED_LESS_BYTES		(8 * 64) /* 8 cache line */
43 #define	RXDMA_RED_LESS_ENTRIES		(RXDMA_RED_LESS_BYTES/8)
44 #define	RXDMA_RED_WINDOW_DEFAULT	0
45 #define	RXDMA_RED_THRES_DEFAULT		0
46 
47 #define	RXDMA_RCR_PTHRES_DEFAULT	0x20
48 #define	RXDMA_RCR_TO_DEFAULT		0x8
49 
50 /*
51  * hardware workarounds: kick 16 (was 8 before)
52  */
53 #define	NXGE_RXDMA_POST_BATCH		16
54 
55 #define	RXBUF_START_ADDR(a, index, bsize)	((a & (index * bsize))
56 #define	RXBUF_OFFSET_FROM_START(a, start)	(start - a)
57 #define	RXBUF_64B_ALIGNED		64
58 
59 #define	NXGE_RXBUF_EXTRA		34
60 /*
61  * Receive buffer thresholds and buffer types
62  */
63 #define	NXGE_RX_BCOPY_SCALE	8	/* use 1/8 as lowest granularity */
64 typedef enum  {
65 	NXGE_RX_COPY_ALL = 0,		/* do bcopy on every packet	 */
66 	NXGE_RX_COPY_1,			/* bcopy on 1/8 of buffer posted */
67 	NXGE_RX_COPY_2,			/* bcopy on 2/8 of buffer posted */
68 	NXGE_RX_COPY_3,			/* bcopy on 3/8 of buffer posted */
69 	NXGE_RX_COPY_4,			/* bcopy on 4/8 of buffer posted */
70 	NXGE_RX_COPY_5,			/* bcopy on 5/8 of buffer posted */
71 	NXGE_RX_COPY_6,			/* bcopy on 6/8 of buffer posted */
72 	NXGE_RX_COPY_7,			/* bcopy on 7/8 of buffer posted */
73 	NXGE_RX_COPY_NONE		/* don't do bcopy at all	 */
74 } nxge_rxbuf_threshold_t;
75 
76 typedef enum  {
77 	NXGE_RBR_TYPE0 = RCR_PKTBUFSZ_0,  /* bcopy buffer size 0 (small) */
78 	NXGE_RBR_TYPE1 = RCR_PKTBUFSZ_1,  /* bcopy buffer size 1 (medium) */
79 	NXGE_RBR_TYPE2 = RCR_PKTBUFSZ_2	  /* bcopy buffer size 2 (large) */
80 } nxge_rxbuf_type_t;
81 
82 typedef	struct _rdc_errlog {
83 	rdmc_par_err_log_t	pre_par;
84 	rdmc_par_err_log_t	sha_par;
85 	uint8_t			compl_err_type;
86 } rdc_errlog_t;
87 
88 /*
89  * Receive  Statistics.
90  */
91 typedef struct _nxge_rx_ring_stats_t {
92 	uint64_t	ipackets;
93 	uint64_t	ibytes;
94 	uint32_t	ierrors;
95 	uint32_t	multircv;
96 	uint32_t	brdcstrcv;
97 	uint32_t	norcvbuf;
98 
99 	uint32_t	rx_inits;
100 	uint32_t	rx_jumbo_pkts;
101 	uint32_t	rx_multi_pkts;
102 	uint32_t	rx_mtu_pkts;
103 	uint32_t	rx_no_buf;
104 
105 	/*
106 	 * Receive buffer management statistics.
107 	 */
108 	uint32_t	rx_new_pages;
109 	uint32_t	rx_new_mtu_pgs;
110 	uint32_t	rx_new_nxt_pgs;
111 	uint32_t	rx_reused_pgs;
112 	uint32_t	rx_mtu_drops;
113 	uint32_t	rx_nxt_drops;
114 
115 	/*
116 	 * Error event stats.
117 	 */
118 	uint32_t	rx_rbr_tmout;
119 	uint32_t	l2_err;
120 	uint32_t	l4_cksum_err;
121 	uint32_t	fflp_soft_err;
122 	uint32_t	zcp_soft_err;
123 	uint32_t	rcr_unknown_err;
124 	uint32_t	dcf_err;
125 	uint32_t 	rbr_tmout;
126 	uint32_t 	rsp_cnt_err;
127 	uint32_t 	byte_en_err;
128 	uint32_t 	byte_en_bus;
129 	uint32_t 	rsp_dat_err;
130 	uint32_t 	rcr_ack_err;
131 	uint32_t 	dc_fifo_err;
132 	uint32_t 	rcr_sha_par;
133 	uint32_t 	rbr_pre_par;
134 	uint32_t 	port_drop_pkt;
135 	uint32_t 	wred_drop;
136 	uint32_t 	rbr_pre_empty;
137 	uint32_t 	rcr_shadow_full;
138 	uint32_t 	config_err;
139 	uint32_t 	rcrincon;
140 	uint32_t 	rcrfull;
141 	uint32_t 	rbr_empty;
142 	uint32_t 	rbrfull;
143 	uint32_t 	rbrlogpage;
144 	uint32_t 	cfiglogpage;
145 	uint32_t 	rcrto;
146 	uint32_t 	rcrthres;
147 	uint32_t 	mex;
148 	rdc_errlog_t	errlog;
149 } nxge_rx_ring_stats_t, *p_nxge_rx_ring_stats_t;
150 
151 typedef struct _nxge_rdc_sys_stats {
152 	uint32_t	pre_par;
153 	uint32_t	sha_par;
154 	uint32_t	id_mismatch;
155 	uint32_t	ipp_eop_err;
156 	uint32_t	zcp_eop_err;
157 } nxge_rdc_sys_stats_t, *p_nxge_rdc_sys_stats_t;
158 
159 /*
160  * Software reserved buffer offset
161  */
162 typedef struct _nxge_rxbuf_off_hdr_t {
163 	uint32_t		index;
164 } nxge_rxbuf_off_hdr_t, *p_nxge_rxbuf_off_hdr_t;
165 
166 /*
167  * Definitions for each receive buffer block.
168  */
169 typedef struct _nxge_rbb_t {
170 	nxge_os_dma_common_t	dma_buf_info;
171 	uint8_t			rbr_page_num;
172 	uint32_t		block_size;
173 	uint16_t		dma_channel;
174 	uint32_t		bytes_received;
175 	uint32_t		ref_cnt;
176 	uint_t			pkt_buf_size;
177 	uint_t			max_pkt_bufs;
178 	uint32_t		cur_usage_cnt;
179 } nxge_rbb_t, *p_nxge_rbb_t;
180 
181 
182 typedef struct _rx_tx_param_t {
183 	nxge_logical_page_t logical_pages[NXGE_MAX_LOGICAL_PAGES];
184 } rx_tx_param_t, *p_rx_tx_param_t;
185 
186 typedef struct _rx_tx_params {
187 	struct _tx_param_t 	*tx_param_p;
188 } rx_tx_params_t, *p_rx_tx_params_t;
189 
190 
191 typedef struct _rx_msg_t {
192 	nxge_os_dma_common_t	buf_dma;
193 	nxge_os_mutex_t 	lock;
194 	struct _nxge_t		*nxgep;
195 	struct _rx_rbr_ring_t	*rx_rbr_p;
196 	boolean_t 		spare_in_use;
197 	boolean_t 		free;
198 	uint32_t 		ref_cnt;
199 #ifdef RXBUFF_USE_SEPARATE_UP_CNTR
200 	uint32_t 		pass_up_cnt;
201 	boolean_t 		release;
202 #endif
203 	nxge_os_frtn_t 		freeb;
204 	size_t 			bytes_arrived;
205 	size_t 			bytes_expected;
206 	size_t 			block_size;
207 	uint32_t		block_index;
208 	uint32_t 		pkt_buf_size;
209 	uint32_t 		pkt_buf_size_code;
210 	uint32_t 		max_pkt_bufs;
211 	uint32_t		cur_usage_cnt;
212 	uint32_t		max_usage_cnt;
213 	uchar_t			*buffer;
214 	uint32_t 		pri;
215 	uint32_t 		shifted_addr;
216 	boolean_t		use_buf_pool;
217 	p_mblk_t 		rx_mblk_p;
218 	boolean_t		rx_use_bcopy;
219 } rx_msg_t, *p_rx_msg_t;
220 
221 typedef struct _rx_dma_handle_t {
222 	nxge_os_dma_handle_t	dma_handle;	/* DMA handle	*/
223 	nxge_os_acc_handle_t	acc_handle;	/* DMA memory handle */
224 	npi_handle_t		npi_handle;
225 } rx_dma_handle_t, *p_rx_dma_handle_t;
226 
227 #define	RXCOMP_HIST_ELEMENTS 100000
228 
229 typedef struct _nxge_rxcomphist_t {
230 	uint_t 			comp_cnt;
231 	uint64_t 		rx_comp_entry;
232 } nxge_rxcomphist_t, *p_nxge_rxcomphist_t;
233 
234 /* Receive Completion Ring */
235 typedef struct _rx_rcr_ring_t {
236 	nxge_os_dma_common_t	rcr_desc;
237 	uint8_t			rcr_page_num;
238 	uint8_t			rcr_buf_page_num;
239 
240 	struct _nxge_t		*nxgep;
241 
242 	p_nxge_rx_ring_stats_t	rdc_stats;
243 
244 	rcrcfig_a_t		rcr_cfga;
245 	rcrcfig_b_t		rcr_cfgb;
246 	boolean_t		cfg_set;
247 
248 	nxge_os_mutex_t 	lock;
249 	uint16_t		index;
250 	uint16_t		rdc;
251 	uint16_t		rdc_grp_id;
252 	uint16_t		ldg_group_id;
253 	boolean_t		full_hdr_flag;	 /* 1: 18 bytes header */
254 	uint16_t		sw_priv_hdr_len; /* 0 - 192 bytes (SW) */
255 	uint32_t 		comp_size;	 /* # of RCR entries */
256 	uint64_t		rcr_addr;
257 	uint_t 			comp_wrap_mask;
258 	uint_t 			comp_rd_index;
259 	uint_t 			comp_wt_index;
260 
261 	p_rcr_entry_t		rcr_desc_first_p;
262 	p_rcr_entry_t		rcr_desc_first_pp;
263 	p_rcr_entry_t		rcr_desc_last_p;
264 	p_rcr_entry_t		rcr_desc_last_pp;
265 
266 	p_rcr_entry_t		rcr_desc_rd_head_p;	/* software next read */
267 	p_rcr_entry_t		rcr_desc_rd_head_pp;
268 
269 	p_rcr_entry_t		rcr_desc_wt_tail_p;	/* hardware write */
270 	p_rcr_entry_t		rcr_desc_wt_tail_pp;
271 
272 	uint64_t		rcr_tail_pp;
273 	uint64_t		rcr_head_pp;
274 	struct _rx_rbr_ring_t	*rx_rbr_p;
275 	uint32_t		intr_timeout;
276 	uint32_t		intr_threshold;
277 	uint64_t		max_receive_pkts;
278 	p_mblk_t		rx_first_mp;
279 	mac_resource_handle_t	rcr_mac_handle;
280 	uint32_t		rcvd_pkt_bytes; /* Received bytes of a packet */
281 } rx_rcr_ring_t, *p_rx_rcr_ring_t;
282 
283 
284 
285 /* Buffer index information */
286 typedef struct _rxbuf_index_info_t {
287 	uint32_t buf_index;
288 	uint32_t start_index;
289 	uint32_t buf_size;
290 	uint64_t dvma_addr;
291 	uint64_t kaddr;
292 } rxbuf_index_info_t, *p_rxbuf_index_info_t;
293 
294 /* Buffer index information */
295 
296 typedef struct _rxring_info_t {
297 	uint32_t hint[3];
298 	uint32_t block_size_mask;
299 	uint16_t max_iterations;
300 	rxbuf_index_info_t buffer[NXGE_DMA_BLOCK];
301 } rxring_info_t, *p_rxring_info_t;
302 
303 
304 /* Receive Buffer Block Ring */
305 typedef struct _rx_rbr_ring_t {
306 	nxge_os_dma_common_t	rbr_desc;
307 	p_rx_msg_t 		*rx_msg_ring;
308 	p_nxge_dma_common_t 	*dma_bufp;
309 	rbr_cfig_a_t		rbr_cfga;
310 	rbr_cfig_b_t		rbr_cfgb;
311 	rbr_kick_t		rbr_kick;
312 	log_page_vld_t		page_valid;
313 	log_page_mask_t		page_mask_1;
314 	log_page_mask_t		page_mask_2;
315 	log_page_value_t	page_value_1;
316 	log_page_value_t	page_value_2;
317 	log_page_relo_t		page_reloc_1;
318 	log_page_relo_t		page_reloc_2;
319 	log_page_hdl_t		page_hdl;
320 
321 	boolean_t		cfg_set;
322 
323 	nxge_os_mutex_t		lock;
324 	nxge_os_mutex_t		post_lock;
325 	uint16_t		index;
326 	struct _nxge_t		*nxgep;
327 	uint16_t		rdc;
328 	uint16_t		rdc_grp_id;
329 	uint_t 			rbr_max_size;
330 	uint64_t		rbr_addr;
331 	uint_t 			rbr_wrap_mask;
332 	uint_t 			rbb_max;
333 	uint_t 			rbb_added;
334 	uint_t			block_size;
335 	uint_t			num_blocks;
336 	uint_t			tnblocks;
337 	uint_t			pkt_buf_size0;
338 	uint_t			pkt_buf_size0_bytes;
339 	uint_t			npi_pkt_buf_size0;
340 	uint_t			pkt_buf_size1;
341 	uint_t			pkt_buf_size1_bytes;
342 	uint_t			npi_pkt_buf_size1;
343 	uint_t			pkt_buf_size2;
344 	uint_t			pkt_buf_size2_bytes;
345 	uint_t			npi_pkt_buf_size2;
346 
347 	uint64_t		rbr_head_pp;
348 	uint64_t		rbr_tail_pp;
349 	uint32_t		*rbr_desc_vp;
350 
351 	p_rx_rcr_ring_t		rx_rcr_p;
352 
353 	rx_dma_ent_msk_t	rx_dma_ent_mask;
354 
355 	rbr_hdh_t		rbr_head;
356 	rbr_hdl_t		rbr_tail;
357 	uint_t 			rbr_wr_index;
358 	uint_t 			rbr_rd_index;
359 	uint_t 			rbr_hw_head_index;
360 	uint64_t 		rbr_hw_head_ptr;
361 
362 	/* may not be needed */
363 	p_nxge_rbb_t		rbb_p;
364 
365 	rxring_info_t  *ring_info;
366 #ifdef RX_USE_RECLAIM_POST
367 	uint32_t hw_freed;
368 	uint32_t sw_freed;
369 	uint32_t msg_rd_index;
370 	uint32_t msg_cnt;
371 #endif
372 #if	defined(sun4v) && defined(NIU_LP_WORKAROUND)
373 	uint64_t		hv_rx_buf_base_ioaddr_pp;
374 	uint64_t		hv_rx_buf_ioaddr_size;
375 	uint64_t		hv_rx_cntl_base_ioaddr_pp;
376 	uint64_t		hv_rx_cntl_ioaddr_size;
377 	boolean_t		hv_set;
378 #endif
379 	uint_t 			rbr_consumed;
380 	uint_t 			rbr_threshold_hi;
381 	uint_t 			rbr_threshold_lo;
382 	nxge_rxbuf_type_t	rbr_bufsize_type;
383 	boolean_t		rbr_use_bcopy;
384 } rx_rbr_ring_t, *p_rx_rbr_ring_t;
385 
386 /* Receive Mailbox */
387 typedef struct _rx_mbox_t {
388 	nxge_os_dma_common_t	rx_mbox;
389 	rxdma_cfig1_t		rx_cfg1;
390 	rxdma_cfig2_t		rx_cfg2;
391 	uint64_t		mbox_addr;
392 	boolean_t		cfg_set;
393 
394 	nxge_os_mutex_t 	lock;
395 	uint16_t		index;
396 	struct _nxge_t		*nxgep;
397 	uint16_t		rdc;
398 } rx_mbox_t, *p_rx_mbox_t;
399 
400 
401 typedef struct _rx_rbr_rings_t {
402 	p_rx_rbr_ring_t 	*rbr_rings;
403 	uint32_t			ndmas;
404 	boolean_t		rxbuf_allocated;
405 } rx_rbr_rings_t, *p_rx_rbr_rings_t;
406 
407 typedef struct _rx_rcr_rings_t {
408 	p_rx_rcr_ring_t 	*rcr_rings;
409 	uint32_t			ndmas;
410 	boolean_t		cntl_buf_allocated;
411 } rx_rcr_rings_t, *p_rx_rcr_rings_t;
412 
413 typedef struct _rx_mbox_areas_t {
414 	p_rx_mbox_t 		*rxmbox_areas;
415 	uint32_t			ndmas;
416 	boolean_t		mbox_allocated;
417 } rx_mbox_areas_t, *p_rx_mbox_areas_t;
418 
419 /*
420  * Global register definitions per chip and they are initialized
421  * using the function zero control registers.
422  * .
423  */
424 
425 typedef struct _rxdma_globals {
426 	boolean_t		mode32;
427 	uint16_t		rxdma_ck_div_cnt;
428 	uint16_t		rxdma_red_ran_init;
429 	uint32_t		rxdma_eing_timeout;
430 } rxdma_globals_t, *p_rxdma_globals;
431 
432 
433 /*
434  * Receive DMA Prototypes.
435  */
436 nxge_status_t nxge_init_rxdma_channel_rcrflush(p_nxge_t, uint8_t);
437 nxge_status_t nxge_init_rxdma_channels(p_nxge_t);
438 void nxge_uninit_rxdma_channels(p_nxge_t);
439 nxge_status_t nxge_reset_rxdma_channel(p_nxge_t, uint16_t);
440 nxge_status_t nxge_init_rxdma_channel_cntl_stat(p_nxge_t,
441 	uint16_t, p_rx_dma_ctl_stat_t);
442 nxge_status_t nxge_enable_rxdma_channel(p_nxge_t,
443 	uint16_t, p_rx_rbr_ring_t, p_rx_rcr_ring_t,
444 	p_rx_mbox_t);
445 nxge_status_t nxge_init_rxdma_channel_event_mask(p_nxge_t,
446 		uint16_t, p_rx_dma_ent_msk_t);
447 
448 nxge_status_t nxge_rxdma_hw_mode(p_nxge_t, boolean_t);
449 void nxge_hw_start_rx(p_nxge_t);
450 void nxge_fixup_rxdma_rings(p_nxge_t);
451 nxge_status_t nxge_dump_rxdma_channel(p_nxge_t, uint8_t);
452 
453 void nxge_rxdma_fix_channel(p_nxge_t, uint16_t);
454 void nxge_rxdma_fixup_channel(p_nxge_t, uint16_t, int);
455 int nxge_rxdma_get_ring_index(p_nxge_t, uint16_t);
456 
457 void nxge_rxdma_regs_dump_channels(p_nxge_t);
458 nxge_status_t nxge_rxdma_handle_sys_errors(p_nxge_t);
459 void nxge_rxdma_inject_err(p_nxge_t, uint32_t, uint8_t);
460 
461 
462 #ifdef	__cplusplus
463 }
464 #endif
465 
466 #endif	/* _SYS_NXGE_NXGE_RXDMA_H */
467