144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22a3c5bd6dSspeer * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #ifndef _SYS_NXGE_NXGE_RXDMA_H 2744961713Sgirish #define _SYS_NXGE_NXGE_RXDMA_H 2844961713Sgirish 2944961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 3044961713Sgirish 3144961713Sgirish #ifdef __cplusplus 3244961713Sgirish extern "C" { 3344961713Sgirish #endif 3444961713Sgirish 3544961713Sgirish #include <sys/nxge/nxge_rxdma_hw.h> 3644961713Sgirish #include <npi_rxdma.h> 3744961713Sgirish 3844961713Sgirish #define RXDMA_CK_DIV_DEFAULT 7500 /* 25 usec */ 3944961713Sgirish /* 4044961713Sgirish * Hardware RDC designer: 8 cache lines during Atlas bringup. 4144961713Sgirish */ 4244961713Sgirish #define RXDMA_RED_LESS_BYTES (8 * 64) /* 8 cache line */ 4344961713Sgirish #define RXDMA_RED_LESS_ENTRIES (RXDMA_RED_LESS_BYTES/8) 4444961713Sgirish #define RXDMA_RED_WINDOW_DEFAULT 0 4544961713Sgirish #define RXDMA_RED_THRES_DEFAULT 0 4644961713Sgirish 4744961713Sgirish #define RXDMA_RCR_PTHRES_DEFAULT 0x20 4844961713Sgirish #define RXDMA_RCR_TO_DEFAULT 0x8 4944961713Sgirish 5044961713Sgirish /* 5144961713Sgirish * hardware workarounds: kick 16 (was 8 before) 5244961713Sgirish */ 5344961713Sgirish #define NXGE_RXDMA_POST_BATCH 16 5444961713Sgirish 5544961713Sgirish #define RXBUF_START_ADDR(a, index, bsize) ((a & (index * bsize)) 5644961713Sgirish #define RXBUF_OFFSET_FROM_START(a, start) (start - a) 5744961713Sgirish #define RXBUF_64B_ALIGNED 64 5844961713Sgirish 5944961713Sgirish #define NXGE_RXBUF_EXTRA 34 6044961713Sgirish /* 6144961713Sgirish * Receive buffer thresholds and buffer types 6244961713Sgirish */ 6344961713Sgirish #define NXGE_RX_BCOPY_SCALE 8 /* use 1/8 as lowest granularity */ 6444961713Sgirish typedef enum { 6544961713Sgirish NXGE_RX_COPY_ALL = 0, /* do bcopy on every packet */ 6644961713Sgirish NXGE_RX_COPY_1, /* bcopy on 1/8 of buffer posted */ 6744961713Sgirish NXGE_RX_COPY_2, /* bcopy on 2/8 of buffer posted */ 6844961713Sgirish NXGE_RX_COPY_3, /* bcopy on 3/8 of buffer posted */ 6944961713Sgirish NXGE_RX_COPY_4, /* bcopy on 4/8 of buffer posted */ 7044961713Sgirish NXGE_RX_COPY_5, /* bcopy on 5/8 of buffer posted */ 7144961713Sgirish NXGE_RX_COPY_6, /* bcopy on 6/8 of buffer posted */ 7244961713Sgirish NXGE_RX_COPY_7, /* bcopy on 7/8 of buffer posted */ 7344961713Sgirish NXGE_RX_COPY_NONE /* don't do bcopy at all */ 7444961713Sgirish } nxge_rxbuf_threshold_t; 7544961713Sgirish 7644961713Sgirish typedef enum { 7744961713Sgirish NXGE_RBR_TYPE0 = RCR_PKTBUFSZ_0, /* bcopy buffer size 0 (small) */ 7844961713Sgirish NXGE_RBR_TYPE1 = RCR_PKTBUFSZ_1, /* bcopy buffer size 1 (medium) */ 7944961713Sgirish NXGE_RBR_TYPE2 = RCR_PKTBUFSZ_2 /* bcopy buffer size 2 (large) */ 8044961713Sgirish } nxge_rxbuf_type_t; 8144961713Sgirish 8244961713Sgirish typedef struct _rdc_errlog { 8344961713Sgirish rdmc_par_err_log_t pre_par; 8444961713Sgirish rdmc_par_err_log_t sha_par; 8544961713Sgirish uint8_t compl_err_type; 8644961713Sgirish } rdc_errlog_t; 8744961713Sgirish 8844961713Sgirish /* 8944961713Sgirish * Receive Statistics. 9044961713Sgirish */ 9144961713Sgirish typedef struct _nxge_rx_ring_stats_t { 9244961713Sgirish uint64_t ipackets; 9344961713Sgirish uint64_t ibytes; 9444961713Sgirish uint32_t ierrors; 9544961713Sgirish uint32_t multircv; 9644961713Sgirish uint32_t brdcstrcv; 9744961713Sgirish uint32_t norcvbuf; 9844961713Sgirish 9944961713Sgirish uint32_t rx_inits; 10044961713Sgirish uint32_t rx_jumbo_pkts; 10144961713Sgirish uint32_t rx_multi_pkts; 10244961713Sgirish uint32_t rx_mtu_pkts; 10344961713Sgirish uint32_t rx_no_buf; 10444961713Sgirish 10544961713Sgirish /* 10644961713Sgirish * Receive buffer management statistics. 10744961713Sgirish */ 10844961713Sgirish uint32_t rx_new_pages; 10944961713Sgirish uint32_t rx_new_mtu_pgs; 11044961713Sgirish uint32_t rx_new_nxt_pgs; 11144961713Sgirish uint32_t rx_reused_pgs; 11244961713Sgirish uint32_t rx_mtu_drops; 11344961713Sgirish uint32_t rx_nxt_drops; 11444961713Sgirish 11544961713Sgirish /* 11644961713Sgirish * Error event stats. 11744961713Sgirish */ 11844961713Sgirish uint32_t rx_rbr_tmout; 11944961713Sgirish uint32_t l2_err; 12044961713Sgirish uint32_t l4_cksum_err; 12144961713Sgirish uint32_t fflp_soft_err; 12244961713Sgirish uint32_t zcp_soft_err; 123*53f3d8ecSyc uint32_t rcr_unknown_err; 12444961713Sgirish uint32_t dcf_err; 12544961713Sgirish uint32_t rbr_tmout; 12644961713Sgirish uint32_t rsp_cnt_err; 12744961713Sgirish uint32_t byte_en_err; 12844961713Sgirish uint32_t byte_en_bus; 12944961713Sgirish uint32_t rsp_dat_err; 13044961713Sgirish uint32_t rcr_ack_err; 13144961713Sgirish uint32_t dc_fifo_err; 13244961713Sgirish uint32_t rcr_sha_par; 13344961713Sgirish uint32_t rbr_pre_par; 13444961713Sgirish uint32_t port_drop_pkt; 13544961713Sgirish uint32_t wred_drop; 13644961713Sgirish uint32_t rbr_pre_empty; 13744961713Sgirish uint32_t rcr_shadow_full; 13844961713Sgirish uint32_t config_err; 13944961713Sgirish uint32_t rcrincon; 14044961713Sgirish uint32_t rcrfull; 14144961713Sgirish uint32_t rbr_empty; 14244961713Sgirish uint32_t rbrfull; 14344961713Sgirish uint32_t rbrlogpage; 14444961713Sgirish uint32_t cfiglogpage; 14544961713Sgirish uint32_t rcrto; 14644961713Sgirish uint32_t rcrthres; 14744961713Sgirish uint32_t mex; 14844961713Sgirish rdc_errlog_t errlog; 14944961713Sgirish } nxge_rx_ring_stats_t, *p_nxge_rx_ring_stats_t; 15044961713Sgirish 15144961713Sgirish typedef struct _nxge_rdc_sys_stats { 15244961713Sgirish uint32_t pre_par; 15344961713Sgirish uint32_t sha_par; 15444961713Sgirish uint32_t id_mismatch; 15544961713Sgirish uint32_t ipp_eop_err; 15644961713Sgirish uint32_t zcp_eop_err; 15744961713Sgirish } nxge_rdc_sys_stats_t, *p_nxge_rdc_sys_stats_t; 15844961713Sgirish 15944961713Sgirish /* 16044961713Sgirish * Software reserved buffer offset 16144961713Sgirish */ 16244961713Sgirish typedef struct _nxge_rxbuf_off_hdr_t { 16344961713Sgirish uint32_t index; 16444961713Sgirish } nxge_rxbuf_off_hdr_t, *p_nxge_rxbuf_off_hdr_t; 16544961713Sgirish 16644961713Sgirish /* 16744961713Sgirish * Definitions for each receive buffer block. 16844961713Sgirish */ 16944961713Sgirish typedef struct _nxge_rbb_t { 17044961713Sgirish nxge_os_dma_common_t dma_buf_info; 17144961713Sgirish uint8_t rbr_page_num; 17244961713Sgirish uint32_t block_size; 17344961713Sgirish uint16_t dma_channel; 17444961713Sgirish uint32_t bytes_received; 17544961713Sgirish uint32_t ref_cnt; 17644961713Sgirish uint_t pkt_buf_size; 17744961713Sgirish uint_t max_pkt_bufs; 17844961713Sgirish uint32_t cur_usage_cnt; 17944961713Sgirish } nxge_rbb_t, *p_nxge_rbb_t; 18044961713Sgirish 18144961713Sgirish 18244961713Sgirish typedef struct _rx_tx_param_t { 18344961713Sgirish nxge_logical_page_t logical_pages[NXGE_MAX_LOGICAL_PAGES]; 18444961713Sgirish } rx_tx_param_t, *p_rx_tx_param_t; 18544961713Sgirish 18644961713Sgirish typedef struct _rx_tx_params { 18744961713Sgirish struct _tx_param_t *tx_param_p; 18844961713Sgirish } rx_tx_params_t, *p_rx_tx_params_t; 18944961713Sgirish 19044961713Sgirish 19144961713Sgirish typedef struct _rx_msg_t { 19244961713Sgirish nxge_os_dma_common_t buf_dma; 19344961713Sgirish nxge_os_mutex_t lock; 19444961713Sgirish struct _nxge_t *nxgep; 19544961713Sgirish struct _rx_rbr_ring_t *rx_rbr_p; 19644961713Sgirish boolean_t spare_in_use; 19744961713Sgirish boolean_t free; 19844961713Sgirish uint32_t ref_cnt; 19944961713Sgirish #ifdef RXBUFF_USE_SEPARATE_UP_CNTR 20044961713Sgirish uint32_t pass_up_cnt; 20144961713Sgirish boolean_t release; 20244961713Sgirish #endif 20344961713Sgirish nxge_os_frtn_t freeb; 20444961713Sgirish size_t bytes_arrived; 20544961713Sgirish size_t bytes_expected; 20644961713Sgirish size_t block_size; 20744961713Sgirish uint32_t block_index; 20844961713Sgirish uint32_t pkt_buf_size; 20944961713Sgirish uint32_t pkt_buf_size_code; 21044961713Sgirish uint32_t max_pkt_bufs; 21144961713Sgirish uint32_t cur_usage_cnt; 21244961713Sgirish uint32_t max_usage_cnt; 21344961713Sgirish uchar_t *buffer; 21444961713Sgirish uint32_t pri; 21544961713Sgirish uint32_t shifted_addr; 21644961713Sgirish boolean_t use_buf_pool; 21744961713Sgirish p_mblk_t rx_mblk_p; 21844961713Sgirish boolean_t rx_use_bcopy; 21944961713Sgirish } rx_msg_t, *p_rx_msg_t; 22044961713Sgirish 22144961713Sgirish typedef struct _rx_dma_handle_t { 22244961713Sgirish nxge_os_dma_handle_t dma_handle; /* DMA handle */ 22344961713Sgirish nxge_os_acc_handle_t acc_handle; /* DMA memory handle */ 22444961713Sgirish npi_handle_t npi_handle; 22544961713Sgirish } rx_dma_handle_t, *p_rx_dma_handle_t; 22644961713Sgirish 22744961713Sgirish #define RXCOMP_HIST_ELEMENTS 100000 22844961713Sgirish 22944961713Sgirish typedef struct _nxge_rxcomphist_t { 23044961713Sgirish uint_t comp_cnt; 23144961713Sgirish uint64_t rx_comp_entry; 23244961713Sgirish } nxge_rxcomphist_t, *p_nxge_rxcomphist_t; 23344961713Sgirish 23444961713Sgirish /* Receive Completion Ring */ 23544961713Sgirish typedef struct _rx_rcr_ring_t { 23644961713Sgirish nxge_os_dma_common_t rcr_desc; 23744961713Sgirish uint8_t rcr_page_num; 23844961713Sgirish uint8_t rcr_buf_page_num; 23944961713Sgirish 24044961713Sgirish struct _nxge_t *nxgep; 24144961713Sgirish 24244961713Sgirish p_nxge_rx_ring_stats_t rdc_stats; 24344961713Sgirish 24444961713Sgirish rcrcfig_a_t rcr_cfga; 24544961713Sgirish rcrcfig_b_t rcr_cfgb; 24644961713Sgirish boolean_t cfg_set; 24744961713Sgirish 24844961713Sgirish nxge_os_mutex_t lock; 24944961713Sgirish uint16_t index; 25044961713Sgirish uint16_t rdc; 25144961713Sgirish uint16_t rdc_grp_id; 25244961713Sgirish uint16_t ldg_group_id; 25344961713Sgirish boolean_t full_hdr_flag; /* 1: 18 bytes header */ 25444961713Sgirish uint16_t sw_priv_hdr_len; /* 0 - 192 bytes (SW) */ 25544961713Sgirish uint32_t comp_size; /* # of RCR entries */ 25644961713Sgirish uint64_t rcr_addr; 25744961713Sgirish uint_t comp_wrap_mask; 25844961713Sgirish uint_t comp_rd_index; 25944961713Sgirish uint_t comp_wt_index; 26044961713Sgirish 26144961713Sgirish p_rcr_entry_t rcr_desc_first_p; 26244961713Sgirish p_rcr_entry_t rcr_desc_first_pp; 26344961713Sgirish p_rcr_entry_t rcr_desc_last_p; 26444961713Sgirish p_rcr_entry_t rcr_desc_last_pp; 26544961713Sgirish 26644961713Sgirish p_rcr_entry_t rcr_desc_rd_head_p; /* software next read */ 26744961713Sgirish p_rcr_entry_t rcr_desc_rd_head_pp; 26844961713Sgirish 26944961713Sgirish p_rcr_entry_t rcr_desc_wt_tail_p; /* hardware write */ 27044961713Sgirish p_rcr_entry_t rcr_desc_wt_tail_pp; 27144961713Sgirish 27244961713Sgirish uint64_t rcr_tail_pp; 27344961713Sgirish uint64_t rcr_head_pp; 27444961713Sgirish struct _rx_rbr_ring_t *rx_rbr_p; 27514ea4bb7Ssd uint32_t intr_timeout; 27614ea4bb7Ssd uint32_t intr_threshold; 27744961713Sgirish uint64_t max_receive_pkts; 27844961713Sgirish p_mblk_t rx_first_mp; 27944961713Sgirish mac_resource_handle_t rcr_mac_handle; 280a3c5bd6dSspeer uint32_t rcvd_pkt_bytes; /* Received bytes of a packet */ 28144961713Sgirish } rx_rcr_ring_t, *p_rx_rcr_ring_t; 28244961713Sgirish 28344961713Sgirish 28444961713Sgirish 28544961713Sgirish /* Buffer index information */ 28644961713Sgirish typedef struct _rxbuf_index_info_t { 28744961713Sgirish uint32_t buf_index; 28844961713Sgirish uint32_t start_index; 28944961713Sgirish uint32_t buf_size; 29044961713Sgirish uint64_t dvma_addr; 29144961713Sgirish uint64_t kaddr; 29244961713Sgirish } rxbuf_index_info_t, *p_rxbuf_index_info_t; 29344961713Sgirish 29444961713Sgirish /* Buffer index information */ 29544961713Sgirish 29644961713Sgirish typedef struct _rxring_info_t { 29744961713Sgirish uint32_t hint[3]; 29844961713Sgirish uint32_t block_size_mask; 29944961713Sgirish uint16_t max_iterations; 30044961713Sgirish rxbuf_index_info_t buffer[NXGE_DMA_BLOCK]; 30144961713Sgirish } rxring_info_t, *p_rxring_info_t; 30244961713Sgirish 30344961713Sgirish 30444961713Sgirish /* Receive Buffer Block Ring */ 30544961713Sgirish typedef struct _rx_rbr_ring_t { 30644961713Sgirish nxge_os_dma_common_t rbr_desc; 30744961713Sgirish p_rx_msg_t *rx_msg_ring; 30844961713Sgirish p_nxge_dma_common_t *dma_bufp; 30944961713Sgirish rbr_cfig_a_t rbr_cfga; 31044961713Sgirish rbr_cfig_b_t rbr_cfgb; 31144961713Sgirish rbr_kick_t rbr_kick; 31244961713Sgirish log_page_vld_t page_valid; 31344961713Sgirish log_page_mask_t page_mask_1; 31444961713Sgirish log_page_mask_t page_mask_2; 31544961713Sgirish log_page_value_t page_value_1; 31644961713Sgirish log_page_value_t page_value_2; 31744961713Sgirish log_page_relo_t page_reloc_1; 31844961713Sgirish log_page_relo_t page_reloc_2; 31944961713Sgirish log_page_hdl_t page_hdl; 32044961713Sgirish 32144961713Sgirish boolean_t cfg_set; 32244961713Sgirish 32344961713Sgirish nxge_os_mutex_t lock; 32444961713Sgirish nxge_os_mutex_t post_lock; 32544961713Sgirish uint16_t index; 32644961713Sgirish struct _nxge_t *nxgep; 32744961713Sgirish uint16_t rdc; 32844961713Sgirish uint16_t rdc_grp_id; 32944961713Sgirish uint_t rbr_max_size; 33044961713Sgirish uint64_t rbr_addr; 33144961713Sgirish uint_t rbr_wrap_mask; 33244961713Sgirish uint_t rbb_max; 33344961713Sgirish uint_t rbb_added; 33444961713Sgirish uint_t block_size; 33544961713Sgirish uint_t num_blocks; 33644961713Sgirish uint_t tnblocks; 33744961713Sgirish uint_t pkt_buf_size0; 33844961713Sgirish uint_t pkt_buf_size0_bytes; 33944961713Sgirish uint_t npi_pkt_buf_size0; 34044961713Sgirish uint_t pkt_buf_size1; 34144961713Sgirish uint_t pkt_buf_size1_bytes; 34244961713Sgirish uint_t npi_pkt_buf_size1; 34344961713Sgirish uint_t pkt_buf_size2; 34444961713Sgirish uint_t pkt_buf_size2_bytes; 34544961713Sgirish uint_t npi_pkt_buf_size2; 34644961713Sgirish 34744961713Sgirish uint64_t rbr_head_pp; 34844961713Sgirish uint64_t rbr_tail_pp; 34944961713Sgirish uint32_t *rbr_desc_vp; 35044961713Sgirish 35144961713Sgirish p_rx_rcr_ring_t rx_rcr_p; 35244961713Sgirish 35344961713Sgirish rx_dma_ent_msk_t rx_dma_ent_mask; 35444961713Sgirish 35544961713Sgirish rbr_hdh_t rbr_head; 35644961713Sgirish rbr_hdl_t rbr_tail; 35744961713Sgirish uint_t rbr_wr_index; 35844961713Sgirish uint_t rbr_rd_index; 35944961713Sgirish uint_t rbr_hw_head_index; 36044961713Sgirish uint64_t rbr_hw_head_ptr; 36144961713Sgirish 36244961713Sgirish /* may not be needed */ 36344961713Sgirish p_nxge_rbb_t rbb_p; 36444961713Sgirish 36544961713Sgirish rxring_info_t *ring_info; 36644961713Sgirish #ifdef RX_USE_RECLAIM_POST 36744961713Sgirish uint32_t hw_freed; 36844961713Sgirish uint32_t sw_freed; 36944961713Sgirish uint32_t msg_rd_index; 37044961713Sgirish uint32_t msg_cnt; 37144961713Sgirish #endif 37244961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 37344961713Sgirish uint64_t hv_rx_buf_base_ioaddr_pp; 37444961713Sgirish uint64_t hv_rx_buf_ioaddr_size; 37544961713Sgirish uint64_t hv_rx_cntl_base_ioaddr_pp; 37644961713Sgirish uint64_t hv_rx_cntl_ioaddr_size; 37744961713Sgirish boolean_t hv_set; 37844961713Sgirish #endif 37944961713Sgirish uint_t rbr_consumed; 38044961713Sgirish uint_t rbr_threshold_hi; 38144961713Sgirish uint_t rbr_threshold_lo; 38244961713Sgirish nxge_rxbuf_type_t rbr_bufsize_type; 38344961713Sgirish boolean_t rbr_use_bcopy; 38444961713Sgirish } rx_rbr_ring_t, *p_rx_rbr_ring_t; 38544961713Sgirish 38644961713Sgirish /* Receive Mailbox */ 38744961713Sgirish typedef struct _rx_mbox_t { 38844961713Sgirish nxge_os_dma_common_t rx_mbox; 38944961713Sgirish rxdma_cfig1_t rx_cfg1; 39044961713Sgirish rxdma_cfig2_t rx_cfg2; 39144961713Sgirish uint64_t mbox_addr; 39244961713Sgirish boolean_t cfg_set; 39344961713Sgirish 39444961713Sgirish nxge_os_mutex_t lock; 39544961713Sgirish uint16_t index; 39644961713Sgirish struct _nxge_t *nxgep; 39744961713Sgirish uint16_t rdc; 39844961713Sgirish } rx_mbox_t, *p_rx_mbox_t; 39944961713Sgirish 40044961713Sgirish 40144961713Sgirish typedef struct _rx_rbr_rings_t { 40244961713Sgirish p_rx_rbr_ring_t *rbr_rings; 40344961713Sgirish uint32_t ndmas; 40444961713Sgirish boolean_t rxbuf_allocated; 40544961713Sgirish } rx_rbr_rings_t, *p_rx_rbr_rings_t; 40644961713Sgirish 40744961713Sgirish typedef struct _rx_rcr_rings_t { 40844961713Sgirish p_rx_rcr_ring_t *rcr_rings; 40944961713Sgirish uint32_t ndmas; 41044961713Sgirish boolean_t cntl_buf_allocated; 41144961713Sgirish } rx_rcr_rings_t, *p_rx_rcr_rings_t; 41244961713Sgirish 41344961713Sgirish typedef struct _rx_mbox_areas_t { 41444961713Sgirish p_rx_mbox_t *rxmbox_areas; 41544961713Sgirish uint32_t ndmas; 41644961713Sgirish boolean_t mbox_allocated; 41744961713Sgirish } rx_mbox_areas_t, *p_rx_mbox_areas_t; 41844961713Sgirish 41944961713Sgirish /* 42044961713Sgirish * Global register definitions per chip and they are initialized 42144961713Sgirish * using the function zero control registers. 42244961713Sgirish * . 42344961713Sgirish */ 42444961713Sgirish 42544961713Sgirish typedef struct _rxdma_globals { 42644961713Sgirish boolean_t mode32; 42744961713Sgirish uint16_t rxdma_ck_div_cnt; 42844961713Sgirish uint16_t rxdma_red_ran_init; 42944961713Sgirish uint32_t rxdma_eing_timeout; 43044961713Sgirish } rxdma_globals_t, *p_rxdma_globals; 43144961713Sgirish 43244961713Sgirish 43344961713Sgirish /* 43444961713Sgirish * Receive DMA Prototypes. 43544961713Sgirish */ 43644961713Sgirish nxge_status_t nxge_init_rxdma_channel_rcrflush(p_nxge_t, uint8_t); 43744961713Sgirish nxge_status_t nxge_init_rxdma_channels(p_nxge_t); 43844961713Sgirish void nxge_uninit_rxdma_channels(p_nxge_t); 43944961713Sgirish nxge_status_t nxge_reset_rxdma_channel(p_nxge_t, uint16_t); 44044961713Sgirish nxge_status_t nxge_init_rxdma_channel_cntl_stat(p_nxge_t, 44144961713Sgirish uint16_t, p_rx_dma_ctl_stat_t); 44244961713Sgirish nxge_status_t nxge_enable_rxdma_channel(p_nxge_t, 44344961713Sgirish uint16_t, p_rx_rbr_ring_t, p_rx_rcr_ring_t, 44444961713Sgirish p_rx_mbox_t); 44544961713Sgirish nxge_status_t nxge_init_rxdma_channel_event_mask(p_nxge_t, 44644961713Sgirish uint16_t, p_rx_dma_ent_msk_t); 44744961713Sgirish 44844961713Sgirish nxge_status_t nxge_rxdma_hw_mode(p_nxge_t, boolean_t); 44944961713Sgirish void nxge_hw_start_rx(p_nxge_t); 45044961713Sgirish void nxge_fixup_rxdma_rings(p_nxge_t); 45144961713Sgirish nxge_status_t nxge_dump_rxdma_channel(p_nxge_t, uint8_t); 45244961713Sgirish 45344961713Sgirish void nxge_rxdma_fix_channel(p_nxge_t, uint16_t); 45444961713Sgirish void nxge_rxdma_fixup_channel(p_nxge_t, uint16_t, int); 45544961713Sgirish int nxge_rxdma_get_ring_index(p_nxge_t, uint16_t); 45644961713Sgirish 45744961713Sgirish void nxge_rxdma_regs_dump_channels(p_nxge_t); 45844961713Sgirish nxge_status_t nxge_rxdma_handle_sys_errors(p_nxge_t); 45944961713Sgirish void nxge_rxdma_inject_err(p_nxge_t, uint32_t, uint8_t); 46044961713Sgirish 46144961713Sgirish 46244961713Sgirish #ifdef __cplusplus 46344961713Sgirish } 46444961713Sgirish #endif 46544961713Sgirish 46644961713Sgirish #endif /* _SYS_NXGE_NXGE_RXDMA_H */ 467