144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22d81011f0Ssbehera * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #ifndef _SYS_NXGE_NXGE_MII_H_ 2744961713Sgirish #define _SYS_NXGE_NXGE_MII_H_ 2844961713Sgirish 2944961713Sgirish #ifdef __cplusplus 3044961713Sgirish extern "C" { 3144961713Sgirish #endif 3244961713Sgirish 33*6b438925Ssbehera #include <sys/miiregs.h> 34*6b438925Ssbehera 3544961713Sgirish /* 3644961713Sgirish * Configuration Register space. 3744961713Sgirish */ 3844961713Sgirish 39*6b438925Ssbehera #define NXGE_MII_LPRXNPR 8 40*6b438925Ssbehera #define NXGE_MII_GCR 9 41*6b438925Ssbehera #define NXGE_MII_GSR 10 42*6b438925Ssbehera #define NXGE_MII_RES0 11 43*6b438925Ssbehera #define NXGE_MII_RES1 12 44*6b438925Ssbehera #define NXGE_MII_RES2 13 45*6b438925Ssbehera #define NXGE_MII_RES3 14 46*6b438925Ssbehera #define NXGE_MII_ESR 15 47*6b438925Ssbehera 48*6b438925Ssbehera #define NXGE_MII_SHADOW MII_VENDOR(0xc) 49d81011f0Ssbehera /* Shadow register definition */ 50*6b438925Ssbehera #define NXGE_MII_MODE_CONTROL_REG MII_VENDOR(0xf) 5144961713Sgirish 52*6b438925Ssbehera #define NXGE_MAX_MII_REGS 32 5344961713Sgirish 5444961713Sgirish /* 5544961713Sgirish * Configuration Register space. 5644961713Sgirish */ 5744961713Sgirish typedef struct _mii_regs { 5844961713Sgirish uchar_t bmcr; /* Basic mode control register */ 5944961713Sgirish uchar_t bmsr; /* Basic mode status register */ 6044961713Sgirish uchar_t idr1; /* Phy identifier register 1 */ 6144961713Sgirish uchar_t idr2; /* Phy identifier register 2 */ 6244961713Sgirish uchar_t anar; /* Auto-Negotiation advertisement register */ 6344961713Sgirish uchar_t anlpar; /* Auto-Negotiation link Partner ability reg */ 6444961713Sgirish uchar_t aner; /* Auto-Negotiation expansion register */ 6544961713Sgirish uchar_t nptxr; /* Next page transmit register */ 6644961713Sgirish uchar_t lprxnpr; /* Link partner received next page register */ 6744961713Sgirish uchar_t gcr; /* Gigabit basic mode control register. */ 6844961713Sgirish uchar_t gsr; /* Gigabit basic mode status register */ 6944961713Sgirish uchar_t mii_res1[4]; /* For future use by MII working group */ 7044961713Sgirish uchar_t esr; /* Extended status register. */ 71d81011f0Ssbehera uchar_t vendor_res[12]; /* For future use by Phy Vendors */ 72d81011f0Ssbehera uchar_t shadow; 73d81011f0Ssbehera uchar_t vendor_res2[3]; /* For future use by Phy Vendors */ 7444961713Sgirish } mii_regs_t, *p_mii_regs_t; 7544961713Sgirish 7644961713Sgirish /* 7744961713Sgirish * MII Register 0: Basic mode control register. 7844961713Sgirish */ 7944961713Sgirish typedef union _mii_bmcr { 8044961713Sgirish uint16_t value; 8144961713Sgirish struct { 8244961713Sgirish #if defined(_BIT_FIELDS_HTOL) 8344961713Sgirish uint16_t reset:1; 8444961713Sgirish uint16_t loopback:1; 8544961713Sgirish uint16_t speed_sel:1; 8644961713Sgirish uint16_t enable_autoneg:1; 8744961713Sgirish uint16_t power_down:1; 8844961713Sgirish uint16_t isolate:1; 8944961713Sgirish uint16_t restart_autoneg:1; 9044961713Sgirish uint16_t duplex_mode:1; 9144961713Sgirish uint16_t col_test:1; 9244961713Sgirish uint16_t speed_1000_sel:1; 9344961713Sgirish uint16_t res1:6; 9444961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 9544961713Sgirish uint16_t res1:6; 9644961713Sgirish uint16_t speed_1000_sel:1; 9744961713Sgirish uint16_t col_test:1; 9844961713Sgirish uint16_t duplex_mode:1; 9944961713Sgirish uint16_t restart_autoneg:1; 10044961713Sgirish uint16_t isolate:1; 10144961713Sgirish uint16_t power_down:1; 10244961713Sgirish uint16_t enable_autoneg:1; 10344961713Sgirish uint16_t speed_sel:1; 10444961713Sgirish uint16_t loopback:1; 10544961713Sgirish uint16_t reset:1; 10644961713Sgirish #endif 10744961713Sgirish } bits; 10844961713Sgirish } mii_bmcr_t, *p_mii_bmcr_t; 10944961713Sgirish 11044961713Sgirish /* 11144961713Sgirish * MII Register 1: Basic mode status register. 11244961713Sgirish */ 11344961713Sgirish typedef union _mii_bmsr { 11444961713Sgirish uint16_t value; 11544961713Sgirish struct { 11644961713Sgirish #if defined(_BIT_FIELDS_HTOL) 11744961713Sgirish uint16_t link_100T4:1; 11844961713Sgirish uint16_t link_100fdx:1; 11944961713Sgirish uint16_t link_100hdx:1; 12044961713Sgirish uint16_t link_10fdx:1; 12144961713Sgirish uint16_t link_10hdx:1; 12244961713Sgirish uint16_t res2:2; 12344961713Sgirish uint16_t extend_status:1; 12444961713Sgirish uint16_t res1:1; 12544961713Sgirish uint16_t preamble_supress:1; 12644961713Sgirish uint16_t auto_neg_complete:1; 12744961713Sgirish uint16_t remote_fault:1; 12844961713Sgirish uint16_t auto_neg_able:1; 12944961713Sgirish uint16_t link_status:1; 13044961713Sgirish uint16_t jabber_detect:1; 13144961713Sgirish uint16_t ext_cap:1; 13244961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 13344961713Sgirish int16_t ext_cap:1; 13444961713Sgirish uint16_t jabber_detect:1; 13544961713Sgirish uint16_t link_status:1; 13644961713Sgirish uint16_t auto_neg_able:1; 13744961713Sgirish uint16_t remote_fault:1; 13844961713Sgirish uint16_t auto_neg_complete:1; 13944961713Sgirish uint16_t preamble_supress:1; 14044961713Sgirish uint16_t res1:1; 14144961713Sgirish uint16_t extend_status:1; 14244961713Sgirish uint16_t res2:2; 14344961713Sgirish uint16_t link_10hdx:1; 14444961713Sgirish uint16_t link_10fdx:1; 14544961713Sgirish uint16_t link_100hdx:1; 14644961713Sgirish uint16_t link_100fdx:1; 14744961713Sgirish uint16_t link_100T4:1; 14844961713Sgirish #endif 14944961713Sgirish } bits; 15044961713Sgirish } mii_bmsr_t, *p_mii_bmsr_t; 15144961713Sgirish 15244961713Sgirish /* 15344961713Sgirish * MII Register 2: Physical Identifier 1. 15444961713Sgirish */ 15544961713Sgirish /* contains BCM OUI bits [3:18] */ 15644961713Sgirish typedef union _mii_idr1 { 15744961713Sgirish uint16_t value; 15844961713Sgirish struct { 15944961713Sgirish uint16_t ieee_address:16; 16044961713Sgirish } bits; 16144961713Sgirish } mii_idr1_t, *p_mii_idr1_t; 16244961713Sgirish 16344961713Sgirish /* 16444961713Sgirish * MII Register 3: Physical Identifier 2. 16544961713Sgirish */ 16644961713Sgirish typedef union _mii_idr2 { 16744961713Sgirish uint16_t value; 16844961713Sgirish struct { 16944961713Sgirish #if defined(_BIT_FIELDS_HTOL) 17044961713Sgirish uint16_t ieee_address:6; 17144961713Sgirish uint16_t model_no:6; 17244961713Sgirish uint16_t rev_no:4; 17344961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 17444961713Sgirish uint16_t rev_no:4; 17544961713Sgirish uint16_t model_no:6; 17644961713Sgirish uint16_t ieee_address:6; 17744961713Sgirish #endif 17844961713Sgirish } bits; 17944961713Sgirish } mii_idr2_t, *p_mii_idr2_t; 18044961713Sgirish 18144961713Sgirish /* 18244961713Sgirish * MII Register 4: Auto-negotiation advertisement register. 18344961713Sgirish */ 18444961713Sgirish typedef union _mii_anar { 18544961713Sgirish uint16_t value; 18644961713Sgirish struct { 18744961713Sgirish #if defined(_BIT_FIELDS_HTOL) 18844961713Sgirish uint16_t np_indication:1; 18944961713Sgirish uint16_t acknowledge:1; 19044961713Sgirish uint16_t remote_fault:1; 19144961713Sgirish uint16_t res1:1; 19244961713Sgirish uint16_t cap_asmpause:1; 19344961713Sgirish uint16_t cap_pause:1; 19444961713Sgirish uint16_t cap_100T4:1; 19544961713Sgirish uint16_t cap_100fdx:1; 19644961713Sgirish uint16_t cap_100hdx:1; 19744961713Sgirish uint16_t cap_10fdx:1; 19844961713Sgirish uint16_t cap_10hdx:1; 19944961713Sgirish uint16_t selector:5; 20044961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 20144961713Sgirish uint16_t selector:5; 20244961713Sgirish uint16_t cap_10hdx:1; 20344961713Sgirish uint16_t cap_10fdx:1; 20444961713Sgirish uint16_t cap_100hdx:1; 20544961713Sgirish uint16_t cap_100fdx:1; 20644961713Sgirish uint16_t cap_100T4:1; 20744961713Sgirish uint16_t cap_pause:1; 20844961713Sgirish uint16_t cap_asmpause:1; 20944961713Sgirish uint16_t res1:1; 21044961713Sgirish uint16_t remote_fault:1; 21144961713Sgirish uint16_t acknowledge:1; 21244961713Sgirish uint16_t np_indication:1; 21344961713Sgirish #endif 21444961713Sgirish } bits; 21544961713Sgirish } mii_anar_t, *p_mii_anar_t; 21644961713Sgirish 21744961713Sgirish /* 21844961713Sgirish * MII Register 5: Auto-negotiation link partner ability register. 21944961713Sgirish */ 22044961713Sgirish typedef mii_anar_t mii_anlpar_t, *pmii_anlpar_t; 22144961713Sgirish 22244961713Sgirish /* 22344961713Sgirish * MII Register 6: Auto-negotiation expansion register. 22444961713Sgirish */ 22544961713Sgirish typedef union _mii_aner { 22644961713Sgirish uint16_t value; 22744961713Sgirish struct { 22844961713Sgirish #if defined(_BIT_FIELDS_HTOL) 22944961713Sgirish uint16_t res:11; 23044961713Sgirish uint16_t mlf:1; 23144961713Sgirish uint16_t lp_np_able:1; 23244961713Sgirish uint16_t np_able:1; 23344961713Sgirish uint16_t page_rx:1; 23444961713Sgirish uint16_t lp_an_able:1; 23544961713Sgirish #else 23644961713Sgirish uint16_t lp_an_able:1; 23744961713Sgirish uint16_t page_rx:1; 23844961713Sgirish uint16_t np_able:1; 23944961713Sgirish uint16_t lp_np_able:1; 24044961713Sgirish uint16_t mlf:1; 24144961713Sgirish uint16_t res:11; 24244961713Sgirish #endif 24344961713Sgirish } bits; 24444961713Sgirish } mii_aner_t, *p_mii_aner_t; 24544961713Sgirish 24644961713Sgirish /* 24744961713Sgirish * MII Register 7: Next page transmit register. 24844961713Sgirish */ 24944961713Sgirish typedef union _mii_nptxr { 25044961713Sgirish uint16_t value; 25144961713Sgirish struct { 25244961713Sgirish #if defined(_BIT_FIELDS_HTOL) 25344961713Sgirish uint16_t np:1; 25444961713Sgirish uint16_t res:1; 25544961713Sgirish uint16_t msgp:1; 25644961713Sgirish uint16_t ack2:1; 25744961713Sgirish uint16_t toggle:1; 25844961713Sgirish uint16_t res1:11; 25944961713Sgirish #else 26044961713Sgirish uint16_t res1:11; 26144961713Sgirish uint16_t toggle:1; 26244961713Sgirish uint16_t ack2:1; 26344961713Sgirish uint16_t msgp:1; 26444961713Sgirish uint16_t res:1; 26544961713Sgirish uint16_t np:1; 26644961713Sgirish #endif 26744961713Sgirish } bits; 26844961713Sgirish } mii_nptxr_t, *p_mii_nptxr_t; 26944961713Sgirish 27044961713Sgirish /* 27144961713Sgirish * MII Register 8: Link partner received next page register. 27244961713Sgirish */ 27344961713Sgirish typedef union _mii_lprxnpr { 27444961713Sgirish uint16_t value; 27544961713Sgirish struct { 27644961713Sgirish #if defined(_BIT_FIELDS_HTOL) 27744961713Sgirish uint16_t np:1; 27844961713Sgirish uint16_t ack:1; 27944961713Sgirish uint16_t msgp:1; 28044961713Sgirish uint16_t ack2:1; 28144961713Sgirish uint16_t toggle:1; 28244961713Sgirish uint16_t mcf:11; 28344961713Sgirish #else 28444961713Sgirish uint16_t mcf:11; 28544961713Sgirish uint16_t toggle:1; 28644961713Sgirish uint16_t ack2:1; 28744961713Sgirish uint16_t msgp:1; 28844961713Sgirish uint16_t ack:1; 28944961713Sgirish uint16_t np:1; 29044961713Sgirish #endif 29144961713Sgirish } bits; 29244961713Sgirish } mii_lprxnpr_t, *p_mii_lprxnpr_t; 29344961713Sgirish 29444961713Sgirish /* 29544961713Sgirish * MII Register 9: 1000BaseT control register. 29644961713Sgirish */ 29744961713Sgirish typedef union _mii_gcr { 29844961713Sgirish uint16_t value; 29944961713Sgirish struct { 30044961713Sgirish #if defined(_BIT_FIELDS_HTOL) 30144961713Sgirish uint16_t test_mode:3; 30244961713Sgirish uint16_t ms_mode_en:1; 30344961713Sgirish uint16_t master:1; 30444961713Sgirish uint16_t dte_or_repeater:1; 30544961713Sgirish uint16_t link_1000fdx:1; 30644961713Sgirish uint16_t link_1000hdx:1; 30744961713Sgirish uint16_t res:8; 30844961713Sgirish #else 30944961713Sgirish uint16_t res:8; 31044961713Sgirish uint16_t link_1000hdx:1; 31144961713Sgirish uint16_t link_1000fdx:1; 31244961713Sgirish uint16_t dte_or_repeater:1; 31344961713Sgirish uint16_t master:1; 31444961713Sgirish uint16_t ms_mode_en:1; 31544961713Sgirish uint16_t test_mode:3; 31644961713Sgirish #endif 31744961713Sgirish } bits; 31844961713Sgirish } mii_gcr_t, *p_mii_gcr_t; 31944961713Sgirish 32044961713Sgirish /* 32144961713Sgirish * MII Register 10: 1000BaseT status register. 32244961713Sgirish */ 32344961713Sgirish typedef union _mii_gsr { 32444961713Sgirish uint16_t value; 32544961713Sgirish struct { 32644961713Sgirish #if defined(_BIT_FIELDS_HTOL) 32744961713Sgirish uint16_t ms_config_fault:1; 32844961713Sgirish uint16_t ms_resolve:1; 32944961713Sgirish uint16_t local_rx_status:1; 33044961713Sgirish uint16_t remote_rx_status:1; 33144961713Sgirish uint16_t link_1000fdx:1; 33244961713Sgirish uint16_t link_1000hdx:1; 33344961713Sgirish uint16_t res:2; 33444961713Sgirish uint16_t idle_err_cnt:8; 33544961713Sgirish #else 33644961713Sgirish uint16_t idle_err_cnt:8; 33744961713Sgirish uint16_t res:2; 33844961713Sgirish uint16_t link_1000hdx:1; 33944961713Sgirish uint16_t link_1000fdx:1; 34044961713Sgirish uint16_t remote_rx_status:1; 34144961713Sgirish uint16_t local_rx_status:1; 34244961713Sgirish uint16_t ms_resolve:1; 34344961713Sgirish uint16_t ms_config_fault:1; 34444961713Sgirish #endif 34544961713Sgirish } bits; 34644961713Sgirish } mii_gsr_t, *p_mii_gsr_t; 34744961713Sgirish 34844961713Sgirish /* 34944961713Sgirish * MII Register 15: Extended status register. 35044961713Sgirish */ 35144961713Sgirish typedef union _mii_esr { 35244961713Sgirish uint16_t value; 35344961713Sgirish struct { 35444961713Sgirish #if defined(_BIT_FIELDS_HTOL) 35544961713Sgirish uint16_t link_1000Xfdx:1; 35644961713Sgirish uint16_t link_1000Xhdx:1; 35744961713Sgirish uint16_t link_1000fdx:1; 35844961713Sgirish uint16_t link_1000hdx:1; 35944961713Sgirish uint16_t res:12; 36044961713Sgirish #else 36144961713Sgirish uint16_t res:12; 36244961713Sgirish uint16_t link_1000hdx:1; 36344961713Sgirish uint16_t link_1000fdx:1; 36444961713Sgirish uint16_t link_1000Xhdx:1; 36544961713Sgirish uint16_t link_1000Xfdx:1; 36644961713Sgirish #endif 36744961713Sgirish } bits; 36844961713Sgirish } mii_esr_t, *p_mii_esr_t; 36944961713Sgirish 370d81011f0Ssbehera #define NXGE_MODE_SELECT_FIBER 0x01 371d81011f0Ssbehera /* Shadow regiser 0x11111 */ 372d81011f0Ssbehera typedef union _mii_mode_control_stat { 373d81011f0Ssbehera uint16_t value; 374d81011f0Ssbehera struct { 375d81011f0Ssbehera #if defined(_BIT_FIELDS_HTOL) 376d81011f0Ssbehera uint16_t write_enable:1; 377d81011f0Ssbehera uint16_t shadow:5; 378d81011f0Ssbehera uint16_t rsv:1; 379d81011f0Ssbehera uint16_t change:1; 380d81011f0Ssbehera uint16_t copper:1; 381d81011f0Ssbehera uint16_t fiber:1; 382d81011f0Ssbehera uint16_t copper_energy:1; 383d81011f0Ssbehera uint16_t fiber_signal:1; 384d81011f0Ssbehera uint16_t rsv1:1; 385d81011f0Ssbehera uint16_t mode:2; 386d81011f0Ssbehera uint16_t enable:1; 387d81011f0Ssbehera #elif defined(_BIT_FIELDS_LTOH) 388d81011f0Ssbehera uint16_t enable:1; 389d81011f0Ssbehera uint16_t mode:2; 390d81011f0Ssbehera uint16_t rsv1:1; 391d81011f0Ssbehera uint16_t fiber_signal:1; 392d81011f0Ssbehera uint16_t copper_energy:1; 393d81011f0Ssbehera uint16_t fiber:1; 394d81011f0Ssbehera uint16_t copper:1; 395d81011f0Ssbehera uint16_t change:1; 396d81011f0Ssbehera uint16_t rsv:1; 397d81011f0Ssbehera uint16_t shadow:5; 398d81011f0Ssbehera uint16_t write_enable:1; 399d81011f0Ssbehera #endif 400d81011f0Ssbehera } bits; 401d81011f0Ssbehera } mii_mode_control_stat_t, *p_mode_control_stat_t; 402d81011f0Ssbehera 40344961713Sgirish #ifdef __cplusplus 40444961713Sgirish } 40544961713Sgirish #endif 40644961713Sgirish 40744961713Sgirish #endif /* _SYS_NXGE_NXGE_MII_H_ */ 408