144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22*678453a8Sspeer * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #ifndef _SYS_NXGE_NXGE_HW_H 2744961713Sgirish #define _SYS_NXGE_NXGE_HW_H 2844961713Sgirish 2944961713Sgirish #ifdef __cplusplus 3044961713Sgirish extern "C" { 3144961713Sgirish #endif 3244961713Sgirish 3344961713Sgirish #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) && \ 3444961713Sgirish !defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN) 3544961713Sgirish #error Host endianness not defined 3644961713Sgirish #endif 3744961713Sgirish 3844961713Sgirish #if !defined(_BIT_FIELDS_HTOL) && !defined(_BIT_FIELDS_LTOH) && \ 3944961713Sgirish !defined(__BIT_FIELDS_HTOL) && !defined(__BIT_FIELDS_LTOH) 4044961713Sgirish #error Bit ordering not defined 4144961713Sgirish #endif 4244961713Sgirish 4344961713Sgirish #include <nxge_fflp_hw.h> 4444961713Sgirish #include <nxge_ipp_hw.h> 4544961713Sgirish #include <nxge_mac_hw.h> 4644961713Sgirish #include <nxge_rxdma_hw.h> 4744961713Sgirish #include <nxge_txc_hw.h> 4844961713Sgirish #include <nxge_txdma_hw.h> 4944961713Sgirish #include <nxge_zcp_hw.h> 5044961713Sgirish #include <nxge_espc_hw.h> 5144961713Sgirish #include <nxge_n2_esr_hw.h> 5244961713Sgirish #include <nxge_sr_hw.h> 5344961713Sgirish #include <nxge_phy_hw.h> 5444961713Sgirish 5544961713Sgirish 56*678453a8Sspeer /* 57*678453a8Sspeer * The Neptune chip has 16 Receive DMA channels, but no more than 58*678453a8Sspeer * 24 Transmit DMA channels. 59*678453a8Sspeer */ 60*678453a8Sspeer typedef uint32_t dc_map_t; 61*678453a8Sspeer 62*678453a8Sspeer /* 63*678453a8Sspeer * The logical group map is a Crossbow addition. 64*678453a8Sspeer */ 65*678453a8Sspeer typedef uint32_t lg_map_t; 66*678453a8Sspeer 6744961713Sgirish /* Modes of NXGE core */ 6844961713Sgirish typedef enum nxge_mode_e { 6944961713Sgirish NXGE_MODE_NE = 1, 7044961713Sgirish NXGE_MODE_N2 = 2 7144961713Sgirish } nxge_mode_t; 7244961713Sgirish 7344961713Sgirish /* 7444961713Sgirish * Function control Register 7544961713Sgirish * (bit 31 is reset to 0. Read back 0 then free to use it. 7644961713Sgirish * (once done with it, bit 0:15 can be used to store SW status) 7744961713Sgirish */ 7844961713Sgirish #define DEV_FUNC_SR_REG (PIO + 0x10000) 7944961713Sgirish #define DEV_FUNC_SR_SR_SHIFT 0 8044961713Sgirish #define DEV_FUNC_SR_SR_MASK 0x000000000000FFFFULL 8144961713Sgirish #define DEV_FUNC_SR_FUNCID_SHIFT 16 8244961713Sgirish #define DEV_FUNC_SR_FUNCID_MASK 0x0000000000030000ULL 8344961713Sgirish #define DEV_FUNC_SR_TAS_SHIFT 31 8444961713Sgirish #define DEV_FUNC_SR_TAS_MASK 0x0000000080000000ULL 8544961713Sgirish 8644961713Sgirish typedef union _dev_func_sr_t { 8744961713Sgirish uint64_t value; 8844961713Sgirish struct { 8944961713Sgirish #if defined(_BIG_ENDIAN) 9044961713Sgirish uint32_t hdw; 9144961713Sgirish #endif 9244961713Sgirish struct { 9344961713Sgirish #if defined(_BIT_FIELDS_HTOL) 9444961713Sgirish uint32_t tas:1; 9544961713Sgirish uint32_t res2:13; 9644961713Sgirish uint32_t funcid:2; 9744961713Sgirish uint32_t sr:16; 9844961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 9944961713Sgirish uint32_t sr:16; 10044961713Sgirish uint32_t funcid:2; 10144961713Sgirish uint32_t res2:13; 10244961713Sgirish uint32_t tas:1; 10344961713Sgirish #endif 10444961713Sgirish } ldw; 10544961713Sgirish #if !defined(_BIG_ENDIAN) 10644961713Sgirish uint32_t hdw; 10744961713Sgirish #endif 10844961713Sgirish } bits; 10944961713Sgirish } dev_func_sr_t, *p_dev_func_sr_t; 11044961713Sgirish 11144961713Sgirish 11244961713Sgirish /* 11344961713Sgirish * Multi Parition Control Register (partitiion manager) 11444961713Sgirish */ 11544961713Sgirish #define MULTI_PART_CTL_REG (FZC_PIO + 0x00000) 11644961713Sgirish #define MULTI_PART_CTL_MPC 0x0000000000000001ULL 11744961713Sgirish 11844961713Sgirish typedef union _multi_part_ctl_t { 11944961713Sgirish uint64_t value; 12044961713Sgirish struct { 12144961713Sgirish #if defined(_BIG_ENDIAN) 12244961713Sgirish uint32_t hdw; 12344961713Sgirish #endif 12444961713Sgirish struct { 12544961713Sgirish #if defined(_BIT_FIELDS_HTOL) 12644961713Sgirish uint32_t res1:31; 12744961713Sgirish uint32_t mpc:1; 12844961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 12944961713Sgirish uint32_t mpc:1; 13044961713Sgirish uint32_t res1:31; 13144961713Sgirish #endif 13244961713Sgirish } ldw; 13344961713Sgirish #if !defined(_BIG_ENDIAN) 13444961713Sgirish uint32_t hdw; 13544961713Sgirish #endif 13644961713Sgirish } bits; 13744961713Sgirish } multi_part_ctl_t, *p_multi_part_ctl_t; 13844961713Sgirish 13944961713Sgirish /* 14044961713Sgirish * Virtual DMA CSR Address (partition manager) 14144961713Sgirish */ 14244961713Sgirish #define VADDR_REG (PIO_VADDR + 0x00000) 14344961713Sgirish 14444961713Sgirish /* 14544961713Sgirish * DMA Channel Binding Register (partition manager) 14644961713Sgirish */ 14744961713Sgirish #define DMA_BIND_REG (FZC_PIO + 0x10000) 14844961713Sgirish #define DMA_BIND_RX_SHIFT 0 14944961713Sgirish #define DMA_BIND_RX_MASK 0x000000000000001FULL 15044961713Sgirish #define DMA_BIND_RX_BIND_SHIFT 5 15144961713Sgirish #define DMA_BIND_RX_BIND_SET 0x0000000000000020ULL 15244961713Sgirish #define DMA_BIND_RX_BIND_MASK 0x0000000000000020ULL 15344961713Sgirish #define DMA_BIND_TX_SHIFT 8 15444961713Sgirish #define DMA_BIND_TX_MASK 0x0000000000001f00ULL 15544961713Sgirish #define DMA_BIND_TX_BIND_SHIFT 13 15644961713Sgirish #define DMA_BIND_TX_BIND_SET 0x0000000000002000ULL 15744961713Sgirish #define DMA_BIND_TX_BIND_MASK 0x0000000000002000ULL 15844961713Sgirish 15944961713Sgirish typedef union _dma_bind_t { 16044961713Sgirish uint64_t value; 16144961713Sgirish struct { 16244961713Sgirish #if defined(_BIG_ENDIAN) 16344961713Sgirish uint32_t hdw; 16444961713Sgirish #endif 16544961713Sgirish struct { 16644961713Sgirish #if defined(_BIT_FIELDS_HTOL) 16744961713Sgirish uint32_t res1_1:16; 16844961713Sgirish uint32_t tx_bind:1; 16944961713Sgirish uint32_t tx:5; 17044961713Sgirish uint32_t res2:2; 17144961713Sgirish uint32_t rx_bind:1; 17244961713Sgirish uint32_t rx:5; 17344961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 17444961713Sgirish uint32_t rx:5; 17544961713Sgirish uint32_t rx_bind:1; 17644961713Sgirish uint32_t res2:2; 17744961713Sgirish uint32_t tx:5; 17844961713Sgirish uint32_t tx_bind:1; 17944961713Sgirish uint32_t res1_1:16; 18044961713Sgirish #endif 18144961713Sgirish } ldw; 18244961713Sgirish #if !defined(_BIG_ENDIAN) 18344961713Sgirish uint32_t hdw; 18444961713Sgirish #endif 18544961713Sgirish } bits; 18644961713Sgirish } dma_bind_t, *p_dma_bind_t; 18744961713Sgirish 18844961713Sgirish /* 18944961713Sgirish * System interrupts: 19044961713Sgirish * Logical device and group definitions. 19144961713Sgirish */ 19244961713Sgirish #define NXGE_INT_MAX_LDS 69 19344961713Sgirish #define NXGE_INT_MAX_LDGS 64 19444961713Sgirish #define NXGE_LDGRP_PER_NIU_PORT (NXGE_INT_MAX_LDGS/2) 19544961713Sgirish #define NXGE_LDGRP_PER_NEP_PORT (NXGE_INT_MAX_LDGS/4) 19644961713Sgirish #define NXGE_LDGRP_PER_2PORTS (NXGE_INT_MAX_LDGS/2) 19744961713Sgirish #define NXGE_LDGRP_PER_4PORTS (NXGE_INT_MAX_LDGS/4) 19844961713Sgirish 19944961713Sgirish #define NXGE_RDMA_LD_START 0 20044961713Sgirish #define NXGE_TDMA_LD_START 32 20144961713Sgirish #define NXGE_MIF_LD 63 20244961713Sgirish #define NXGE_MAC_LD_START 64 20344961713Sgirish #define NXGE_MAC_LD_PORT0 64 20444961713Sgirish #define NXGE_MAC_LD_PORT1 65 20544961713Sgirish #define NXGE_MAC_LD_PORT2 66 20644961713Sgirish #define NXGE_MAC_LD_PORT3 67 20744961713Sgirish #define NXGE_SYS_ERROR_LD 68 20844961713Sgirish 20944961713Sgirish /* 21044961713Sgirish * Logical Device Group Number 21144961713Sgirish */ 21244961713Sgirish #define LDG_NUM_REG (FZC_PIO + 0x20000) 21344961713Sgirish #define LDG_NUM_NUM_SHIFT 0 21444961713Sgirish #define LDG_NUM_NUM_MASK 0x000000000000001FULL 21544961713Sgirish 21644961713Sgirish typedef union _ldg_num_t { 21744961713Sgirish uint64_t value; 21844961713Sgirish struct { 21944961713Sgirish #if defined(_BIG_ENDIAN) 22044961713Sgirish uint32_t hdw; 22144961713Sgirish #endif 22244961713Sgirish struct { 22344961713Sgirish #if defined(_BIT_FIELDS_HTOL) 22444961713Sgirish uint32_t res1_1:26; 22544961713Sgirish uint32_t num:6; 22644961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 22744961713Sgirish uint32_t num:6; 22844961713Sgirish uint32_t res1_1:26; 22944961713Sgirish #endif 23044961713Sgirish } ldw; 23144961713Sgirish #if !defined(_BIG_ENDIAN) 23244961713Sgirish uint32_t hdw; 23344961713Sgirish #endif 23444961713Sgirish } bits; 23544961713Sgirish } ldg_num_t, *p_ldg_num_t; 23644961713Sgirish 23744961713Sgirish /* 23844961713Sgirish * Logical Device State Vector 23944961713Sgirish */ 24044961713Sgirish #define LDSV0_REG (PIO_LDSV + 0x00000) 24144961713Sgirish #define LDSV0_LDF_SHIFT 0 24244961713Sgirish #define LDSV0_LDF_MASK 0x00000000000003FFULL 24344961713Sgirish #define LDG_NUM_NUM_MASK 0x000000000000001FULL 24444961713Sgirish #define LDSV_MASK_ALL 0x0000000000000001ULL 24544961713Sgirish 24644961713Sgirish /* 24744961713Sgirish * Logical Device State Vector 1 24844961713Sgirish */ 24944961713Sgirish #define LDSV1_REG (PIO_LDSV + 0x00008) 25044961713Sgirish 25144961713Sgirish /* 25244961713Sgirish * Logical Device State Vector 2 25344961713Sgirish */ 25444961713Sgirish #define LDSV2_REG (PIO_LDSV + 0x00010) 25544961713Sgirish 25644961713Sgirish /* For Logical Device State Vector 0 and 1 */ 25744961713Sgirish typedef union _ldsv_t { 25844961713Sgirish uint64_t value; 25944961713Sgirish struct { 26044961713Sgirish #if defined(_BIG_ENDIAN) 26144961713Sgirish uint32_t hdw; 26244961713Sgirish #endif 26344961713Sgirish uint32_t ldw; 26444961713Sgirish #if !defined(_BIG_ENDIAN) 26544961713Sgirish uint32_t hdw; 26644961713Sgirish #endif 26744961713Sgirish } bits; 26844961713Sgirish } ldsv_t, *p_ldsv_t; 26944961713Sgirish 27044961713Sgirish #define LDSV2_LDF0_SHIFT 0 27144961713Sgirish #define LDSV2_LDF0_MASK 0x000000000000001FULL 27244961713Sgirish #define LDSV2_LDF1_SHIFT 5 27344961713Sgirish #define LDSV2_LDF1_MASK 0x00000000000001E0ULL 27444961713Sgirish 27544961713Sgirish typedef union _ldsv2_t { 27644961713Sgirish uint64_t value; 27744961713Sgirish struct { 27844961713Sgirish #if defined(_BIG_ENDIAN) 27944961713Sgirish uint32_t hdw; 28044961713Sgirish #endif 28144961713Sgirish struct { 28244961713Sgirish #if defined(_BIT_FIELDS_HTOL) 28344961713Sgirish uint32_t res1_1:22; 28444961713Sgirish uint32_t ldf1:5; 28544961713Sgirish uint32_t ldf0:5; 28644961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 28744961713Sgirish uint32_t ldf0:5; 28844961713Sgirish uint32_t ldf1:5; 28944961713Sgirish uint32_t res1_1:22; 29044961713Sgirish #endif 29144961713Sgirish } ldw; 29244961713Sgirish #if !defined(_BIG_ENDIAN) 29344961713Sgirish uint32_t hdw; 29444961713Sgirish #endif 29544961713Sgirish } bits; 29644961713Sgirish } ldsv2_t, *p_ldsv2_t; 29744961713Sgirish 29844961713Sgirish /* 29944961713Sgirish * Logical Device Interrupt Mask 0 30044961713Sgirish */ 30144961713Sgirish #define LD_IM0_REG (PIO_IMASK0 + 0x00000) 30244961713Sgirish #define LD_IM0_SHIFT 0 30344961713Sgirish #define LD_IM0_MASK 0x0000000000000003ULL 30444961713Sgirish #define LD_IM_MASK 0x0000000000000003ULL 30544961713Sgirish 30644961713Sgirish /* 30744961713Sgirish * Logical Device Interrupt Mask 1 30844961713Sgirish */ 30944961713Sgirish #define LD_IM1_REG (PIO_IMASK1 + 0x00000) 31044961713Sgirish #define LD_IM1_SHIFT 0 31144961713Sgirish #define LD_IM1_MASK 0x0000000000000003ULL 31244961713Sgirish 31344961713Sgirish /* For Lofical Device Interrupt Mask 0 and 1 */ 31444961713Sgirish typedef union _ld_im_t { 31544961713Sgirish uint64_t value; 31644961713Sgirish struct { 31744961713Sgirish #if defined(_BIG_ENDIAN) 31844961713Sgirish uint32_t hdw; 31944961713Sgirish #endif 32044961713Sgirish struct { 32144961713Sgirish 32244961713Sgirish #if defined(_BIT_FIELDS_HTOL) 32344961713Sgirish uint32_t res1_1:30; 32444961713Sgirish uint32_t ldf_mask:2; 32544961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 32644961713Sgirish uint32_t ldf_mask:2; 32744961713Sgirish uint32_t res1_1:30; 32844961713Sgirish #endif 32944961713Sgirish } ldw; 33044961713Sgirish #if !defined(_BIG_ENDIAN) 33144961713Sgirish uint32_t hdw; 33244961713Sgirish #endif 33344961713Sgirish } bits; 33444961713Sgirish } ld_im_t, *p_ld_im_t; 33544961713Sgirish 33644961713Sgirish /* 33744961713Sgirish * Logical Device Group Interrupt Management 33844961713Sgirish */ 33944961713Sgirish #define LDGIMGN_REG (PIO_LDSV + 0x00018) 34044961713Sgirish #define LDGIMGN_TIMER_SHIFT 0 34144961713Sgirish #define LDGIMGM_TIMER_MASK 0x000000000000003FULL 34244961713Sgirish #define LDGIMGN_ARM_SHIFT 31 34344961713Sgirish #define LDGIMGM_ARM 0x0000000080000000ULL 34444961713Sgirish #define LDGIMGM_ARM_MASK 0x0000000080000000ULL 34544961713Sgirish 34644961713Sgirish typedef union _ldgimgm_t { 34744961713Sgirish uint64_t value; 34844961713Sgirish struct { 34944961713Sgirish #if defined(_BIG_ENDIAN) 35044961713Sgirish uint32_t hdw; 35144961713Sgirish #endif 35244961713Sgirish struct { 35344961713Sgirish #if defined(_BIT_FIELDS_HTOL) 35444961713Sgirish uint32_t arm:1; 35544961713Sgirish uint32_t res2:25; 35644961713Sgirish uint32_t timer:6; 35744961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 35844961713Sgirish uint32_t timer:6; 35944961713Sgirish uint32_t res2:25; 36044961713Sgirish uint32_t arm:1; 36144961713Sgirish #endif 36244961713Sgirish } ldw; 36344961713Sgirish #if !defined(_BIG_ENDIAN) 36444961713Sgirish uint32_t hdw; 36544961713Sgirish #endif 36644961713Sgirish } bits; 36744961713Sgirish } ldgimgm_t, *p_ldgimgm_t; 36844961713Sgirish 36944961713Sgirish /* 37044961713Sgirish * Logical Device Group Interrupt Timer Resolution 37144961713Sgirish */ 37244961713Sgirish #define LDGITMRES_REG (FZC_PIO + 0x00008) 37344961713Sgirish #define LDGTITMRES_RES_SHIFT 0 /* bits 19:0 */ 37444961713Sgirish #define LDGTITMRES_RES_MASK 0x00000000000FFFFFULL 37544961713Sgirish typedef union _ldgitmres_t { 37644961713Sgirish uint64_t value; 37744961713Sgirish struct { 37844961713Sgirish #if defined(_BIG_ENDIAN) 37944961713Sgirish uint32_t hdw; 38044961713Sgirish #endif 38144961713Sgirish struct { 38244961713Sgirish #if defined(_BIT_FIELDS_HTOL) 38344961713Sgirish uint32_t res1_1:12; 38444961713Sgirish uint32_t res:20; 38544961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 38644961713Sgirish uint32_t res:20; 38744961713Sgirish uint32_t res1_1:12; 38844961713Sgirish #endif 38944961713Sgirish } ldw; 39044961713Sgirish #if !defined(_BIG_ENDIAN) 39144961713Sgirish uint32_t hdw; 39244961713Sgirish #endif 39344961713Sgirish } bits; 39444961713Sgirish } ldgitmres_t, *p_ldgitmres_t; 39544961713Sgirish 39644961713Sgirish /* 39744961713Sgirish * System Interrupt Data 39844961713Sgirish */ 39944961713Sgirish #define SID_REG (FZC_PIO + 0x10200) 40044961713Sgirish #define SID_DATA_SHIFT 0 /* bits 6:0 */ 40144961713Sgirish #define SID_DATA_MASK 0x000000000000007FULL 40244961713Sgirish #define SID_DATA_INTNUM_SHIFT 0 /* bits 4:0 */ 40344961713Sgirish #define SID_DATA_INTNUM_MASK 0x000000000000001FULL 40444961713Sgirish #define SID_DATA_FUNCNUM_SHIFT 5 /* bits 6:5 */ 40544961713Sgirish #define SID_DATA_FUNCNUM_MASK 0x0000000000000060ULL 40644961713Sgirish #define SID_PCI_FUNCTION_SHIFT (1 << 5) 40744961713Sgirish #define SID_N2_INDEX (1 << 6) 40844961713Sgirish 40944961713Sgirish #define SID_DATA(f, v) ((f << SID_DATA_FUNCNUM_SHIFT) | \ 41044961713Sgirish ((v << SID_DATA_SHIFT) & SID_DATA_INTNUM_MASK)) 41144961713Sgirish 41244961713Sgirish #define SID_DATA_N2(v) (v | SID_N2_INDEX) 41344961713Sgirish 41444961713Sgirish typedef union _sid_t { 41544961713Sgirish uint64_t value; 41644961713Sgirish struct { 41744961713Sgirish #if defined(_BIG_ENDIAN) 41844961713Sgirish uint32_t hdw; 41944961713Sgirish #endif 42044961713Sgirish struct { 42144961713Sgirish #if defined(_BIT_FIELDS_HTOL) 42244961713Sgirish uint32_t res1_1:25; 42344961713Sgirish uint32_t data:7; 42444961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 42544961713Sgirish uint32_t data:7; 42644961713Sgirish uint32_t res1_1:25; 42744961713Sgirish #endif 42844961713Sgirish } ldw; 42944961713Sgirish #if !defined(_BIG_ENDIAN) 43044961713Sgirish uint32_t hdw; 43144961713Sgirish #endif 43244961713Sgirish } bits; 43344961713Sgirish } sid_t, *p_sid_t; 43444961713Sgirish 43544961713Sgirish /* 43644961713Sgirish * Reset Control 43744961713Sgirish */ 43844961713Sgirish #define RST_CTL_REG (FZC_PIO + 0x00038) 43944961713Sgirish #define RST_CTL_MAC_RST3 0x0000000000400000ULL 44044961713Sgirish #define RST_CTL_MAC_RST3_SHIFT 22 44144961713Sgirish #define RST_CTL_MAC_RST2 0x0000000000200000ULL 44244961713Sgirish #define RST_CTL_MAC_RST2_SHIFT 21 44344961713Sgirish #define RST_CTL_MAC_RST1 0x0000000000100000ULL 44444961713Sgirish #define RST_CTL_MAC_RST1_SHIFT 20 44544961713Sgirish #define RST_CTL_MAC_RST0 0x0000000000080000ULL 44644961713Sgirish #define RST_CTL_MAC_RST0_SHIFT 19 44744961713Sgirish #define RST_CTL_EN_ACK_TO 0x0000000000000800ULL 44844961713Sgirish #define RST_CTL_EN_ACK_TO_SHIFT 11 44944961713Sgirish #define RST_CTL_ACK_TO_MASK 0x00000000000007FEULL 45044961713Sgirish #define RST_CTL_ACK_TO_SHIFT 1 45144961713Sgirish 45244961713Sgirish 45344961713Sgirish typedef union _rst_ctl_t { 45444961713Sgirish uint64_t value; 45544961713Sgirish struct { 45644961713Sgirish #if defined(_BIG_ENDIAN) 45744961713Sgirish uint32_t hdw; 45844961713Sgirish #endif 45944961713Sgirish struct { 46044961713Sgirish #if defined(_BIT_FIELDS_HTOL) 46144961713Sgirish uint32_t res1:9; 46244961713Sgirish uint32_t mac_rst3:1; 46344961713Sgirish uint32_t mac_rst2:1; 46444961713Sgirish uint32_t mac_rst1:1; 46544961713Sgirish uint32_t mac_rst0:1; 46644961713Sgirish uint32_t res2:7; 46744961713Sgirish uint32_t ack_to_en:1; 46844961713Sgirish uint32_t ack_to_val:10; 46944961713Sgirish uint32_t res3:1; 47044961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 47144961713Sgirish uint32_t res3:1; 47244961713Sgirish uint32_t ack_to_val:10; 47344961713Sgirish uint32_t ack_to_en:1; 47444961713Sgirish uint32_t res2:7; 47544961713Sgirish uint32_t mac_rst0:1; 47644961713Sgirish uint32_t mac_rst1:1; 47744961713Sgirish uint32_t mac_rst2:1; 47844961713Sgirish uint32_t mac_rst3:1; 47944961713Sgirish uint32_t res1:9; 48044961713Sgirish #endif 48144961713Sgirish } ldw; 48244961713Sgirish #if !defined(_BIG_ENDIAN) 48344961713Sgirish uint32_t hdw; 48444961713Sgirish #endif 48544961713Sgirish } bits; 48644961713Sgirish } rst_ctl_t, *p_rst_ctl_t; 48744961713Sgirish 48844961713Sgirish /* 48944961713Sgirish * System Error Mask 49044961713Sgirish */ 49144961713Sgirish #define SYS_ERR_MASK_REG (FZC_PIO + 0x00090) 49244961713Sgirish 49344961713Sgirish /* 49444961713Sgirish * System Error Status 49544961713Sgirish */ 49644961713Sgirish #define SYS_ERR_STAT_REG (FZC_PIO + 0x00098) 49744961713Sgirish 49844961713Sgirish 49944961713Sgirish #define SYS_ERR_META2_MASK 0x0000000000000400ULL 50044961713Sgirish #define SYS_ERR_META2_SHIFT 10 50144961713Sgirish #define SYS_ERR_META1_MASK 0x0000000000000200ULL 50244961713Sgirish #define SYS_ERR_META1_SHIFT 9 50344961713Sgirish #define SYS_ERR_PEU_MASK 0x0000000000000100ULL 50444961713Sgirish #define SYS_ERR_PEU_SHIFT 8 50544961713Sgirish #define SYS_ERR_TXC_MASK 0x0000000000000080ULL 50644961713Sgirish #define SYS_ERR_TXC_SHIFT 7 50744961713Sgirish #define SYS_ERR_RDMC_MASK 0x0000000000000040ULL 50844961713Sgirish #define SYS_ERR_RDMC_SHIFT 6 50944961713Sgirish #define SYS_ERR_TDMC_MASK 0x0000000000000020ULL 51044961713Sgirish #define SYS_ERR_TDMC_SHIFT 5 51144961713Sgirish #define SYS_ERR_ZCP_MASK 0x0000000000000010ULL 51244961713Sgirish #define SYS_ERR_ZCP_SHIFT 4 51344961713Sgirish #define SYS_ERR_FFLP_MASK 0x0000000000000008ULL 51444961713Sgirish #define SYS_ERR_FFLP_SHIFT 3 51544961713Sgirish #define SYS_ERR_IPP_MASK 0x0000000000000004ULL 51644961713Sgirish #define SYS_ERR_IPP_SHIFT 2 51744961713Sgirish #define SYS_ERR_MAC_MASK 0x0000000000000002ULL 51844961713Sgirish #define SYS_ERR_MAC_SHIFT 1 51944961713Sgirish #define SYS_ERR_SMX_MASK 0x0000000000000001ULL 52044961713Sgirish #define SYS_ERR_SMX_SHIFT 0 52144961713Sgirish #define SYS_ERR_MASK_ALL (SYS_ERR_SMX_MASK | SYS_ERR_MAC_MASK | \ 52244961713Sgirish SYS_ERR_IPP_MASK | SYS_ERR_FFLP_MASK | \ 52344961713Sgirish SYS_ERR_ZCP_MASK | SYS_ERR_TDMC_MASK | \ 52444961713Sgirish SYS_ERR_RDMC_MASK | SYS_ERR_TXC_MASK | \ 52544961713Sgirish SYS_ERR_PEU_MASK | SYS_ERR_META1_MASK | \ 52644961713Sgirish SYS_ERR_META2_MASK) 52744961713Sgirish 52844961713Sgirish 52944961713Sgirish typedef union _sys_err_mask_t { 53044961713Sgirish uint64_t value; 53144961713Sgirish struct { 53244961713Sgirish #if defined(_BIG_ENDIAN) 53344961713Sgirish uint32_t hdw; 53444961713Sgirish #endif 53544961713Sgirish struct { 53644961713Sgirish #if defined(_BIT_FIELDS_HTOL) 53744961713Sgirish uint32_t res:21; 53844961713Sgirish uint32_t meta2:1; 53944961713Sgirish uint32_t meta1:1; 54044961713Sgirish uint32_t peu:1; 54144961713Sgirish uint32_t txc:1; 54244961713Sgirish uint32_t rdmc:1; 54344961713Sgirish uint32_t tdmc:1; 54444961713Sgirish uint32_t zcp:1; 54544961713Sgirish uint32_t fflp:1; 54644961713Sgirish uint32_t ipp:1; 54744961713Sgirish uint32_t mac:1; 54844961713Sgirish uint32_t smx:1; 54944961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 55044961713Sgirish uint32_t smx:1; 55144961713Sgirish uint32_t mac:1; 55244961713Sgirish uint32_t ipp:1; 55344961713Sgirish uint32_t fflp:1; 55444961713Sgirish uint32_t zcp:1; 55544961713Sgirish uint32_t tdmc:1; 55644961713Sgirish uint32_t rdmc:1; 55744961713Sgirish uint32_t txc:1; 55844961713Sgirish uint32_t peu:1; 55944961713Sgirish uint32_t meta1:1; 56044961713Sgirish uint32_t meta2:1; 56144961713Sgirish uint32_t res:21; 56244961713Sgirish #endif 56344961713Sgirish } ldw; 56444961713Sgirish #if !defined(_BIG_ENDIAN) 56544961713Sgirish uint32_t hdw; 56644961713Sgirish #endif 56744961713Sgirish } bits; 56844961713Sgirish } sys_err_mask_t, sys_err_stat_t, *p_sys_err_mask_t, *p_sys_err_stat_t; 56944961713Sgirish 57044961713Sgirish 57144961713Sgirish /* 57244961713Sgirish * Meta Arbiter Dirty Transaction ID Control 57344961713Sgirish */ 57444961713Sgirish 57544961713Sgirish #define DIRTY_TID_CTL_REG (FZC_PIO + 0x0010) 57644961713Sgirish #define DIRTY_TID_CTL_WR_THRES_MASK 0x00000000003F0000ULL 57744961713Sgirish #define DIRTY_TID_CTL_WR_THRES_SHIFT 16 57844961713Sgirish #define DIRTY_TID_CTL_RD_THRES_MASK 0x00000000000003F0ULL 57944961713Sgirish #define DIRTY_TID_CTL_RD_THRES_SHIFT 4 58044961713Sgirish #define DIRTY_TID_CTL_DTID_CLR 0x0000000000000002ULL 58144961713Sgirish #define DIRTY_TID_CTL_DTID_CLR_SHIFT 1 58244961713Sgirish #define DIRTY_TID_CTL_DTID_EN 0x0000000000000001ULL 58344961713Sgirish #define DIRTY_TID_CTL_DTID_EN_SHIFT 0 58444961713Sgirish 58544961713Sgirish typedef union _dty_tid_ctl_t { 58644961713Sgirish uint64_t value; 58744961713Sgirish struct { 58844961713Sgirish #if defined(_BIG_ENDIAN) 58944961713Sgirish uint32_t hdw; 59044961713Sgirish #endif 59144961713Sgirish struct { 59244961713Sgirish #if defined(_BIT_FIELDS_HTOL) 59344961713Sgirish uint32_t res1:10; 59444961713Sgirish uint32_t np_wr_thres_val:6; 59544961713Sgirish uint32_t res2:6; 59644961713Sgirish uint32_t np_rd_thres_val:6; 59744961713Sgirish uint32_t res3:2; 59844961713Sgirish uint32_t dty_tid_clr:1; 59944961713Sgirish uint32_t dty_tid_en:1; 60044961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 60144961713Sgirish uint32_t dty_tid_en:1; 60244961713Sgirish uint32_t dty_tid_clr:1; 60344961713Sgirish uint32_t res3:2; 60444961713Sgirish uint32_t np_rd_thres_val:6; 60544961713Sgirish uint32_t res2:6; 60644961713Sgirish uint32_t np_wr_thres_val:6; 60744961713Sgirish uint32_t res1:10; 60844961713Sgirish #endif 60944961713Sgirish } ldw; 61044961713Sgirish #if !defined(_BIG_ENDIAN) 61144961713Sgirish uint32_t hdw; 61244961713Sgirish #endif 61344961713Sgirish } bits; 61444961713Sgirish } dty_tid_ctl_t, *p_dty_tid_ctl_t; 61544961713Sgirish 61644961713Sgirish 61744961713Sgirish /* 61844961713Sgirish * Meta Arbiter Dirty Transaction ID Status 61944961713Sgirish */ 62044961713Sgirish #define DIRTY_TID_STAT_REG (FZC_PIO + 0x0018) 62144961713Sgirish #define DIRTY_TID_STAT_WR_TID_DTY_CNT_MASK 0x0000000000003F00ULL 62244961713Sgirish #define DIRTY_TID_STAT_WR_TID_DTY_CNT_SHIFT 8 62344961713Sgirish #define DIRTY_TID_STAT_RD_TID_DTY_CNT_MASK 0x000000000000003FULL 62444961713Sgirish #define DIRTY_TID_STAT_RD_TID_DTY_CNT_SHIFT 0 62544961713Sgirish 62644961713Sgirish typedef union _dty_tid_stat_t { 62744961713Sgirish uint64_t value; 62844961713Sgirish struct { 62944961713Sgirish #if defined(_BIG_ENDIAN) 63044961713Sgirish uint32_t hdw; 63144961713Sgirish #endif 63244961713Sgirish struct { 63344961713Sgirish #if defined(_BIT_FIELDS_HTOL) 63444961713Sgirish uint32_t res1:18; 63544961713Sgirish uint32_t wr_tid_dirty_cnt:6; 63644961713Sgirish uint32_t res2:2; 63744961713Sgirish uint32_t rd_tid_dirty_cnt:6; 63844961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 63944961713Sgirish uint32_t rd_tid_dirty_cnt:6; 64044961713Sgirish uint32_t res2:2; 64144961713Sgirish uint32_t wr_tid_dirty_cnt:6; 64244961713Sgirish uint32_t res1:18; 64344961713Sgirish #endif 64444961713Sgirish } ldw; 64544961713Sgirish #if !defined(_BIG_ENDIAN) 64644961713Sgirish uint32_t hdw; 64744961713Sgirish #endif 64844961713Sgirish } bits; 64944961713Sgirish } dty_tid_stat_t, *p_dty_tid_stat_t; 65044961713Sgirish 65144961713Sgirish 65244961713Sgirish /* 65344961713Sgirish * SMX Registers 65444961713Sgirish */ 65544961713Sgirish #define SMX_CFIG_DAT_REG (FZC_PIO + 0x00040) 65644961713Sgirish #define SMX_CFIG_DAT_RAS_DET_EN_MASK 0x0000000080000000ULL 65744961713Sgirish #define SMX_CFIG_DAT_RAS_DET_EN_SHIFT 31 65844961713Sgirish #define SMX_CFIG_DAT_RAS_INJ_EN_MASK 0x0000000040000000ULL 65944961713Sgirish #define SMX_CFIG_DAT_RAS_INJ_EN_SHIFT 30 66044961713Sgirish #define SMX_CFIG_DAT_TRANS_TO_MASK 0x000000000FFFFFFFULL 66144961713Sgirish #define SMX_CFIG_DAT_TRANS_TO_SHIFT 0 66244961713Sgirish 66344961713Sgirish typedef union _smx_cfg_dat_t { 66444961713Sgirish uint64_t value; 66544961713Sgirish struct { 66644961713Sgirish #if defined(_BIG_ENDIAN) 66744961713Sgirish uint32_t hdw; 66844961713Sgirish #endif 66944961713Sgirish struct { 67044961713Sgirish #if defined(_BIT_FIELDS_HTOL) 67144961713Sgirish uint32_t res_err_det:1; 67244961713Sgirish uint32_t ras_err_inj_en:1; 67344961713Sgirish uint32_t res:2; 67444961713Sgirish uint32_t trans_to_val:28; 67544961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 67644961713Sgirish uint32_t trans_to_val:28; 67744961713Sgirish uint32_t res:2; 67844961713Sgirish uint32_t ras_err_inj_en:1; 67944961713Sgirish uint32_t res_err_det:1; 68044961713Sgirish #endif 68144961713Sgirish } ldw; 68244961713Sgirish #if !defined(_BIG_ENDIAN) 68344961713Sgirish uint32_t hdw; 68444961713Sgirish #endif 68544961713Sgirish } bits; 68644961713Sgirish } smx_cfg_dat_t, *p_smx_cfg_dat_t; 68744961713Sgirish 68844961713Sgirish 68944961713Sgirish #define SMX_INT_STAT_REG (FZC_PIO + 0x00048) 69044961713Sgirish #define SMX_INT_STAT_SM_MASK 0x00000000FFFFFFC0ULL 69144961713Sgirish #define SMX_INT_STAT_SM_SHIFT 6 69244961713Sgirish 69344961713Sgirish typedef union _smx_int_stat_t { 69444961713Sgirish uint64_t value; 69544961713Sgirish struct { 69644961713Sgirish #if defined(_BIG_ENDIAN) 69744961713Sgirish uint32_t hdw; 69844961713Sgirish #endif 69944961713Sgirish struct { 70044961713Sgirish #if defined(_BIT_FIELDS_HTOL) 70144961713Sgirish uint32_t st_mc_stat:26; 70244961713Sgirish uint32_t res:6; 70344961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 70444961713Sgirish uint32_t res:6; 70544961713Sgirish uint32_t st_mc_stat:26; 70644961713Sgirish #endif 70744961713Sgirish } ldw; 70844961713Sgirish #if !defined(_BIG_ENDIAN) 70944961713Sgirish uint32_t hdw; 71044961713Sgirish #endif 71144961713Sgirish } bits; 71244961713Sgirish } smx_int_stat_t, *p_smx_int_stat_t; 71344961713Sgirish 71444961713Sgirish 71544961713Sgirish #define SMX_CTL_REG (FZC_PIO + 0x00050) 71644961713Sgirish 71744961713Sgirish typedef union _smx_ctl_t { 71844961713Sgirish uint64_t value; 71944961713Sgirish struct { 72044961713Sgirish #if defined(_BIG_ENDIAN) 72144961713Sgirish uint32_t hdw; 72244961713Sgirish #endif 72344961713Sgirish struct { 72444961713Sgirish #if defined(_BIT_FIELDS_HTOL) 72544961713Sgirish uint32_t res1:21; 72644961713Sgirish uint32_t resp_err_inj:3; 72744961713Sgirish uint32_t res2:1; 72844961713Sgirish uint32_t xtb_err_inj:3; 72944961713Sgirish uint32_t res3:1; 73044961713Sgirish uint32_t dbg_sel:3; 73144961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 73244961713Sgirish uint32_t dbg_sel:3; 73344961713Sgirish uint32_t res3:1; 73444961713Sgirish uint32_t xtb_err_inj:3; 73544961713Sgirish uint32_t res2:1; 73644961713Sgirish uint32_t resp_err_inj:3; 73744961713Sgirish uint32_t res1:21; 73844961713Sgirish #endif 73944961713Sgirish } ldw; 74044961713Sgirish #if !defined(_BIG_ENDIAN) 74144961713Sgirish uint32_t hdw; 74244961713Sgirish #endif 74344961713Sgirish } bits; 74444961713Sgirish } smx_ctl_t, *p_smx_ctl_t; 74544961713Sgirish 74644961713Sgirish 74744961713Sgirish #define SMX_DBG_VEC_REG (FZC_PIO + 0x00058) 74844961713Sgirish 74944961713Sgirish typedef union _smx_dbg_vec_t { 75044961713Sgirish uint64_t value; 75144961713Sgirish struct { 75244961713Sgirish #if defined(_BIG_ENDIAN) 75344961713Sgirish uint32_t hdw; 75444961713Sgirish #endif 75544961713Sgirish struct { 75644961713Sgirish uint32_t dbg_tng_vec; 75744961713Sgirish } ldw; 75844961713Sgirish #if !defined(_BIG_ENDIAN) 75944961713Sgirish uint32_t hdw; 76044961713Sgirish #endif 76144961713Sgirish } bits; 76244961713Sgirish } smx_dbg_vec_t, *p_smx_dbg_vec_t; 76344961713Sgirish 76444961713Sgirish 76544961713Sgirish /* 76644961713Sgirish * Debug registers 76744961713Sgirish */ 76844961713Sgirish 76944961713Sgirish #define PIO_DBG_SEL_REG (FZC_PIO + 0x00060) 77044961713Sgirish 77144961713Sgirish typedef union _pio_dbg_sel_t { 77244961713Sgirish uint64_t value; 77344961713Sgirish struct { 77444961713Sgirish #if defined(_BIG_ENDIAN) 77544961713Sgirish uint32_t hdw; 77644961713Sgirish #endif 77744961713Sgirish struct { 77844961713Sgirish uint32_t sel; 77944961713Sgirish } ldw; 78044961713Sgirish #if !defined(_BIG_ENDIAN) 78144961713Sgirish uint32_t hdw; 78244961713Sgirish #endif 78344961713Sgirish } bits; 78444961713Sgirish } pio_dbg_sel_t, *p_pio_dbg_sel_t; 78544961713Sgirish 78644961713Sgirish 78744961713Sgirish #define PIO_TRAIN_VEC_REG (FZC_PIO + 0x00068) 78844961713Sgirish 78944961713Sgirish typedef union _pio_tng_vec_t { 79044961713Sgirish uint64_t value; 79144961713Sgirish struct { 79244961713Sgirish #if defined(_BIG_ENDIAN) 79344961713Sgirish uint32_t hdw; 79444961713Sgirish #endif 79544961713Sgirish struct { 79644961713Sgirish uint32_t training_vec; 79744961713Sgirish } ldw; 79844961713Sgirish #if !defined(_BIG_ENDIAN) 79944961713Sgirish uint32_t hdw; 80044961713Sgirish #endif 80144961713Sgirish } bits; 80244961713Sgirish } pio_tng_vec_t, *p_pio_tng_vec_t; 80344961713Sgirish 80444961713Sgirish #define PIO_ARB_CTL_REG (FZC_PIO + 0x00070) 80544961713Sgirish 80644961713Sgirish typedef union _pio_arb_ctl_t { 80744961713Sgirish uint64_t value; 80844961713Sgirish struct { 80944961713Sgirish #if defined(_BIG_ENDIAN) 81044961713Sgirish uint32_t hdw; 81144961713Sgirish #endif 81244961713Sgirish struct { 81344961713Sgirish uint32_t ctl; 81444961713Sgirish } ldw; 81544961713Sgirish #if !defined(_BIG_ENDIAN) 81644961713Sgirish uint32_t hdw; 81744961713Sgirish #endif 81844961713Sgirish } bits; 81944961713Sgirish } pio_arb_ctl_t, *p_pio_arb_ctl_t; 82044961713Sgirish 82144961713Sgirish #define PIO_ARB_DBG_VEC_REG (FZC_PIO + 0x00078) 82244961713Sgirish 82344961713Sgirish typedef union _pio_arb_dbg_vec_t { 82444961713Sgirish uint64_t value; 82544961713Sgirish struct { 82644961713Sgirish #if defined(_BIG_ENDIAN) 82744961713Sgirish uint32_t hdw; 82844961713Sgirish #endif 82944961713Sgirish struct { 83044961713Sgirish uint32_t dbg_vector; 83144961713Sgirish } ldw; 83244961713Sgirish #if !defined(_BIG_ENDIAN) 83344961713Sgirish uint32_t hdw; 83444961713Sgirish #endif 83544961713Sgirish } bits; 83644961713Sgirish } pio_arb_dbg_vec_t, *p_pio_arb_dbg_vec_t; 83744961713Sgirish 83844961713Sgirish 83944961713Sgirish /* 84044961713Sgirish * GPIO Registers 84144961713Sgirish */ 84244961713Sgirish 84344961713Sgirish #define GPIO_EN_REG (FZC_PIO + 0x00028) 84444961713Sgirish #define GPIO_EN_ENABLE_MASK 0x000000000000FFFFULL 84544961713Sgirish #define GPIO_EN_ENABLE_SHIFT 0 84644961713Sgirish typedef union _gpio_en_t { 84744961713Sgirish uint64_t value; 84844961713Sgirish struct { 84944961713Sgirish #if defined(_BIG_ENDIAN) 85044961713Sgirish uint32_t hdw; 85144961713Sgirish #endif 85244961713Sgirish struct { 85344961713Sgirish #if defined(_BIT_FIELDS_HTOL) 85444961713Sgirish uint32_t res:16; 85544961713Sgirish uint32_t enable:16; 85644961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 85744961713Sgirish uint32_t enable:16; 85844961713Sgirish uint32_t res:16; 85944961713Sgirish #endif 86044961713Sgirish } ldw; 86144961713Sgirish #if !defined(_BIG_ENDIAN) 86244961713Sgirish uint32_t hdw; 86344961713Sgirish #endif 86444961713Sgirish } bits; 86544961713Sgirish } gpio_en_t, *p_gpio_en_t; 86644961713Sgirish 86744961713Sgirish #define GPIO_DATA_IN_REG (FZC_PIO + 0x00030) 86844961713Sgirish #define GPIO_DATA_IN_MASK 0x000000000000FFFFULL 86944961713Sgirish #define GPIO_DATA_IN_SHIFT 0 87044961713Sgirish typedef union _gpio_data_in_t { 87144961713Sgirish uint64_t value; 87244961713Sgirish struct { 87344961713Sgirish #if defined(_BIG_ENDIAN) 87444961713Sgirish uint32_t hdw; 87544961713Sgirish #endif 87644961713Sgirish struct { 87744961713Sgirish #if defined(_BIT_FIELDS_HTOL) 87844961713Sgirish uint32_t res:16; 87944961713Sgirish uint32_t data_in:16; 88044961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 88144961713Sgirish uint32_t data_in:16; 88244961713Sgirish uint32_t res:16; 88344961713Sgirish #endif 88444961713Sgirish } ldw; 88544961713Sgirish #if !defined(_BIG_ENDIAN) 88644961713Sgirish uint32_t hdw; 88744961713Sgirish #endif 88844961713Sgirish } bits; 88944961713Sgirish } gpio_data_in_t, *p_gpio_data_in_t; 89044961713Sgirish 89144961713Sgirish 89244961713Sgirish /* 89344961713Sgirish * PCI Express Interface Module (PIM) registers 89444961713Sgirish */ 89544961713Sgirish #define PIM_CONTROL_REG (FZC_PIM + 0x0) 89644961713Sgirish #define PIM_CONTROL_DBG_SEL_MASK 0x000000000000000FULL 89744961713Sgirish #define PIM_CONTROL_DBG_SEL_SHIFT 0 89844961713Sgirish typedef union _pim_ctl_t { 89944961713Sgirish uint64_t value; 90044961713Sgirish struct { 90144961713Sgirish #if defined(_BIG_ENDIAN) 90244961713Sgirish uint32_t hdw; 90344961713Sgirish #endif 90444961713Sgirish struct { 90544961713Sgirish #if defined(_BIT_FIELDS_HTOL) 90644961713Sgirish uint32_t res:28; 90744961713Sgirish uint32_t dbg_sel:4; 90844961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 90944961713Sgirish uint32_t dbg_sel:4; 91044961713Sgirish uint32_t res:28; 91144961713Sgirish #endif 91244961713Sgirish } ldw; 91344961713Sgirish #if !defined(_BIG_ENDIAN) 91444961713Sgirish uint32_t hdw; 91544961713Sgirish #endif 91644961713Sgirish } bits; 91744961713Sgirish } pim_ctl_t, *p_pim_ctl_t; 91844961713Sgirish 91944961713Sgirish #define PIM_DBG_TRAINING_VEC_REG (FZC_PIM + 0x00008) 92044961713Sgirish #define PIM_DBG_TRAINING_VEC_MASK 0x00000000FFFFFFFFULL 92144961713Sgirish 92244961713Sgirish #define PIM_INTR_STATUS_REG (FZC_PIM + 0x00010) 92344961713Sgirish #define PIM_INTR_STATUS_MASK 0x00000000FFFFFFFFULL 92444961713Sgirish 92544961713Sgirish #define PIM_INTERNAL_STATUS_REG (FZC_PIM + 0x00018) 92644961713Sgirish #define PIM_INTERNAL_STATUS_MASK 0x00000000FFFFFFFFULL 92744961713Sgirish 92844961713Sgirish #define PIM_INTR_MASK_REG (FZC_PIM + 0x00020) 92944961713Sgirish #define PIM_INTR_MASK_MASK 0x00000000FFFFFFFFULL 93044961713Sgirish 93144961713Sgirish /* 93244961713Sgirish * Partitioning Logical pages Definition registers. 93344961713Sgirish * (used by both receive and transmit DMA channels) 93444961713Sgirish */ 93544961713Sgirish 93644961713Sgirish /* Logical page definitions */ 93744961713Sgirish typedef union _log_page_vld_t { 93844961713Sgirish uint64_t value; 93944961713Sgirish struct { 94044961713Sgirish #if defined(_BIG_ENDIAN) 94144961713Sgirish uint32_t hdw; 94244961713Sgirish #endif 94344961713Sgirish struct { 94444961713Sgirish #if defined(_BIT_FIELDS_HTOL) 94544961713Sgirish uint32_t res1_1:28; 94644961713Sgirish uint32_t func:2; 94744961713Sgirish uint32_t page1:1; 94844961713Sgirish uint32_t page0:1; 94944961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 95044961713Sgirish uint32_t page0:1; 95144961713Sgirish uint32_t page1:1; 95244961713Sgirish uint32_t func:2; 95344961713Sgirish uint32_t res1_1:28; 95444961713Sgirish #endif 95544961713Sgirish } ldw; 95644961713Sgirish #if !defined(_BIG_ENDIAN) 95744961713Sgirish uint32_t hdw; 95844961713Sgirish #endif 95944961713Sgirish } bits; 96044961713Sgirish } log_page_vld_t, *p_log_page_vld_t; 96144961713Sgirish 96244961713Sgirish 96344961713Sgirish #define DMA_LOG_PAGE_MASK_SHIFT 0 96444961713Sgirish #define DMA_LOG_PAGE_MASK_MASK 0x00000000ffffffffULL 96544961713Sgirish 96644961713Sgirish /* Receive Logical Page Mask */ 96744961713Sgirish typedef union _log_page_mask_t { 96844961713Sgirish uint64_t value; 96944961713Sgirish struct { 97044961713Sgirish #if defined(_BIG_ENDIAN) 97144961713Sgirish uint32_t hdw; 97244961713Sgirish #endif 97344961713Sgirish struct { 97444961713Sgirish #if defined(_BIT_FIELDS_HTOL) 97544961713Sgirish uint32_t mask:32; 97644961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 97744961713Sgirish uint32_t mask:32; 97844961713Sgirish #endif 97944961713Sgirish } ldw; 98044961713Sgirish #if !defined(_BIG_ENDIAN) 98144961713Sgirish uint32_t hdw; 98244961713Sgirish #endif 98344961713Sgirish } bits; 98444961713Sgirish } log_page_mask_t, *p_log_page_mask_t; 98544961713Sgirish 98644961713Sgirish 98744961713Sgirish /* Receive Logical Page Value */ 98844961713Sgirish #define DMA_LOG_PAGE_VALUE_SHIFT 0 98944961713Sgirish #define DMA_LOG_PAGE_VALUE_MASK 0x00000000ffffffffULL 99044961713Sgirish 99144961713Sgirish /* Receive Logical Page Value */ 99244961713Sgirish typedef union _log_page_value_t { 99344961713Sgirish uint64_t value; 99444961713Sgirish struct { 99544961713Sgirish #if defined(_BIG_ENDIAN) 99644961713Sgirish uint32_t hdw; 99744961713Sgirish #endif 99844961713Sgirish struct { 99944961713Sgirish #if defined(_BIT_FIELDS_HTOL) 100044961713Sgirish uint32_t value:32; 100144961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 100244961713Sgirish uint32_t value:32; 100344961713Sgirish #endif 100444961713Sgirish } ldw; 100544961713Sgirish #if !defined(_BIG_ENDIAN) 100644961713Sgirish uint32_t hdw; 100744961713Sgirish #endif 100844961713Sgirish } bits; 100944961713Sgirish } log_page_value_t, *p_log_page_value_t; 101044961713Sgirish 101144961713Sgirish /* Receive Logical Page Relocation */ 101244961713Sgirish #define DMA_LOG_PAGE_RELO_SHIFT 0 /* bits 31:0 */ 101344961713Sgirish #define DMA_LOG_PAGE_RELO_MASK 0x00000000ffffffffULL 101444961713Sgirish 101544961713Sgirish /* Receive Logical Page Relocation */ 101644961713Sgirish typedef union _log_page_relo_t { 101744961713Sgirish uint64_t value; 101844961713Sgirish struct { 101944961713Sgirish #if defined(_BIG_ENDIAN) 102044961713Sgirish uint32_t hdw; 102144961713Sgirish #endif 102244961713Sgirish struct { 102344961713Sgirish #if defined(_BIT_FIELDS_HTOL) 102444961713Sgirish uint32_t relo:32; 102544961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 102644961713Sgirish uint32_t relo:32; 102744961713Sgirish #endif 102844961713Sgirish } ldw; 102944961713Sgirish #if !defined(_BIG_ENDIAN) 103044961713Sgirish uint32_t hdw; 103144961713Sgirish #endif 103244961713Sgirish } bits; 103344961713Sgirish } log_page_relo_t, *p_log_page_relo_t; 103444961713Sgirish 103544961713Sgirish 103644961713Sgirish /* Receive Logical Page Handle */ 103744961713Sgirish #define DMA_LOG_PAGE_HANDLE_SHIFT 0 /* bits 19:0 */ 103844961713Sgirish #define DMA_LOG_PAGE_HANDLE_MASK 0x00000000ffffffffULL 103944961713Sgirish 104044961713Sgirish /* Receive Logical Page Handle */ 104144961713Sgirish typedef union _log_page_hdl_t { 104244961713Sgirish uint64_t value; 104344961713Sgirish struct { 104444961713Sgirish #if defined(_BIG_ENDIAN) 104544961713Sgirish uint32_t hdw; 104644961713Sgirish #endif 104744961713Sgirish struct { 104844961713Sgirish #if defined(_BIT_FIELDS_HTOL) 104944961713Sgirish uint32_t res1_1:12; 105044961713Sgirish uint32_t handle:20; 105144961713Sgirish #elif defined(_BIT_FIELDS_LTOH) 105244961713Sgirish uint32_t handle:20; 105344961713Sgirish uint32_t res1_1:12; 105444961713Sgirish #endif 105544961713Sgirish } ldw; 105644961713Sgirish #if !defined(_BIG_ENDIAN) 105744961713Sgirish uint32_t hdw; 105844961713Sgirish #endif 105944961713Sgirish } bits; 106044961713Sgirish } log_page_hdl_t, *p_log_page_hdl_t; 106144961713Sgirish 106244961713Sgirish #ifdef __cplusplus 106344961713Sgirish } 106444961713Sgirish #endif 106544961713Sgirish 106644961713Sgirish #endif /* _SYS_NXGE_NXGE_HW_H */ 1067