xref: /illumos-gate/usr/src/uts/common/sys/nxge/nxge.h (revision 846a903d)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_NXGE_NXGE_H
27 #define	_SYS_NXGE_NXGE_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 #if defined(_KERNEL) || defined(COSIM)
36 #include <nxge_mac.h>
37 #include <nxge_ipp.h>
38 #include <nxge_fflp.h>
39 #endif
40 
41 /*
42  * NXGE diagnostics IOCTLS.
43  */
44 #define	NXGE_IOC		((((('N' << 8) + 'X') << 8) + 'G') << 8)
45 
46 #define	NXGE_GET64		(NXGE_IOC|1)
47 #define	NXGE_PUT64		(NXGE_IOC|2)
48 #define	NXGE_GET_TX_RING_SZ	(NXGE_IOC|3)
49 #define	NXGE_GET_TX_DESC	(NXGE_IOC|4)
50 #define	NXGE_GLOBAL_RESET	(NXGE_IOC|5)
51 #define	NXGE_TX_SIDE_RESET	(NXGE_IOC|6)
52 #define	NXGE_RX_SIDE_RESET	(NXGE_IOC|7)
53 #define	NXGE_RESET_MAC		(NXGE_IOC|8)
54 
55 #define	NXGE_GET_MII		(NXGE_IOC|11)
56 #define	NXGE_PUT_MII		(NXGE_IOC|12)
57 #define	NXGE_RTRACE		(NXGE_IOC|13)
58 #define	NXGE_RTRACE_TEST	(NXGE_IOC|20)
59 #define	NXGE_TX_REGS_DUMP	(NXGE_IOC|21)
60 #define	NXGE_RX_REGS_DUMP	(NXGE_IOC|22)
61 #define	NXGE_INT_REGS_DUMP	(NXGE_IOC|23)
62 #define	NXGE_VIR_REGS_DUMP	(NXGE_IOC|24)
63 #define	NXGE_VIR_INT_REGS_DUMP	(NXGE_IOC|25)
64 #define	NXGE_RDUMP		(NXGE_IOC|26)
65 #define	NXGE_RDC_GRPS_DUMP	(NXGE_IOC|27)
66 #define	NXGE_PIO_TEST		(NXGE_IOC|28)
67 
68 #define	NXGE_GET_TCAM		(NXGE_IOC|29)
69 #define	NXGE_PUT_TCAM		(NXGE_IOC|30)
70 #define	NXGE_INJECT_ERR		(NXGE_IOC|40)
71 
72 #if (defined(SOLARIS) && defined(_KERNEL)) || defined(COSIM)
73 #define	NXGE_OK			0
74 #define	NXGE_ERROR		0x40000000
75 #define	NXGE_DDI_FAILED		0x20000000
76 #define	NXGE_GET_PORT_NUM(n)	n
77 
78 /*
79  * Definitions for module_info.
80  */
81 #define	NXGE_IDNUM		(0)			/* module ID number */
82 #define	NXGE_DRIVER_NAME	"nxge"			/* module name */
83 
84 #define	NXGE_MINPSZ		(0)			/* min packet size */
85 #define	NXGE_MAXPSZ		(ETHERMTU)		/* max packet size */
86 #define	NXGE_HIWAT		(2048 * NXGE_MAXPSZ)	/* hi-water mark */
87 #define	NXGE_LOWAT		(1)			/* lo-water mark */
88 #define	NXGE_HIWAT_MAX		(192000 * NXGE_MAXPSZ)
89 #define	NXGE_HIWAT_MIN		(2 * NXGE_MAXPSZ)
90 #define	NXGE_LOWAT_MAX		(192000 * NXGE_MAXPSZ)
91 #define	NXGE_LOWAT_MIN		(1)
92 
93 #ifndef	D_HOTPLUG
94 #define	D_HOTPLUG		0x00
95 #endif
96 
97 #define	INIT_BUCKET_SIZE	16	/* Initial Hash Bucket Size */
98 
99 #define	NXGE_CHECK_TIMER	(5000)
100 
101 typedef enum {
102 	param_instance,
103 	param_main_instance,
104 	param_function_number,
105 	param_partition_id,
106 	param_read_write_mode,
107 	param_fw_version,
108 	param_niu_cfg_type,
109 	param_tx_quick_cfg,
110 	param_rx_quick_cfg,
111 	param_master_cfg_enable,
112 	param_master_cfg_value,
113 
114 	param_autoneg,
115 	param_anar_10gfdx,
116 	param_anar_10ghdx,
117 	param_anar_1000fdx,
118 	param_anar_1000hdx,
119 	param_anar_100T4,
120 	param_anar_100fdx,
121 	param_anar_100hdx,
122 	param_anar_10fdx,
123 	param_anar_10hdx,
124 
125 	param_anar_asmpause,
126 	param_anar_pause,
127 	param_use_int_xcvr,
128 	param_enable_ipg0,
129 	param_ipg0,
130 	param_ipg1,
131 	param_ipg2,
132 	param_accept_jumbo,
133 	param_txdma_weight,
134 	param_txdma_channels_begin,
135 
136 	param_txdma_channels,
137 	param_txdma_info,
138 	param_rxdma_channels_begin,
139 	param_rxdma_channels,
140 	param_rxdma_drr_weight,
141 	param_rxdma_full_header,
142 	param_rxdma_info,
143 	param_rxdma_rbr_size,
144 	param_rxdma_rcr_size,
145 	param_default_port_rdc,
146 	param_rxdma_intr_time,
147 	param_rxdma_intr_pkts,
148 
149 	param_rdc_grps_start,
150 	param_rx_rdc_grps,
151 	param_default_grp0_rdc,
152 	param_default_grp1_rdc,
153 	param_default_grp2_rdc,
154 	param_default_grp3_rdc,
155 	param_default_grp4_rdc,
156 	param_default_grp5_rdc,
157 	param_default_grp6_rdc,
158 	param_default_grp7_rdc,
159 
160 	param_info_rdc_groups,
161 	param_start_ldg,
162 	param_max_ldg,
163 	param_mac_2rdc_grp,
164 	param_vlan_2rdc_grp,
165 	param_fcram_part_cfg,
166 	param_fcram_access_ratio,
167 	param_tcam_access_ratio,
168 	param_tcam_enable,
169 	param_hash_lookup_enable,
170 	param_llc_snap_enable,
171 
172 	param_h1_init_value,
173 	param_h2_init_value,
174 	param_class_cfg_ether_usr1,
175 	param_class_cfg_ether_usr2,
176 	param_class_cfg_ip_usr4,
177 	param_class_cfg_ip_usr5,
178 	param_class_cfg_ip_usr6,
179 	param_class_cfg_ip_usr7,
180 	param_class_opt_ip_usr4,
181 	param_class_opt_ip_usr5,
182 	param_class_opt_ip_usr6,
183 	param_class_opt_ip_usr7,
184 	param_class_opt_ipv4_tcp,
185 	param_class_opt_ipv4_udp,
186 	param_class_opt_ipv4_ah,
187 	param_class_opt_ipv4_sctp,
188 	param_class_opt_ipv6_tcp,
189 	param_class_opt_ipv6_udp,
190 	param_class_opt_ipv6_ah,
191 	param_class_opt_ipv6_sctp,
192 	param_nxge_debug_flag,
193 	param_npi_debug_flag,
194 	param_dump_rdc,
195 	param_dump_tdc,
196 	param_dump_mac_regs,
197 	param_dump_ipp_regs,
198 	param_dump_fflp_regs,
199 	param_dump_vlan_table,
200 	param_dump_rdc_table,
201 	param_dump_ptrs,
202 	param_end
203 } nxge_param_index_t;
204 
205 
206 /*
207  * Named Dispatch Parameter Management Structure
208  */
209 typedef	int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *);
210 typedef	int (*nxge_ndsetf_t)(p_nxge_t, queue_t *,
211 	    MBLKP, char *, caddr_t, cred_t *);
212 
213 #define	NXGE_PARAM_READ			0x00000001ULL
214 #define	NXGE_PARAM_WRITE		0x00000002ULL
215 #define	NXGE_PARAM_SHARED		0x00000004ULL
216 #define	NXGE_PARAM_PRIV			0x00000008ULL
217 #define	NXGE_PARAM_RW			NXGE_PARAM_READ | NXGE_PARAM_WRITE
218 #define	NXGE_PARAM_RWS			NXGE_PARAM_RW | NXGE_PARAM_SHARED
219 #define	NXGE_PARAM_RWP			NXGE_PARAM_RW | NXGE_PARAM_PRIV
220 
221 #define	NXGE_PARAM_RXDMA		0x00000010ULL
222 #define	NXGE_PARAM_TXDMA		0x00000020ULL
223 #define	NXGE_PARAM_CLASS_GEN	0x00000040ULL
224 #define	NXGE_PARAM_MAC			0x00000080ULL
225 #define	NXGE_PARAM_CLASS_BIN	NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN
226 #define	NXGE_PARAM_CLASS_HEX	NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX
227 #define	NXGE_PARAM_CLASS		NXGE_PARAM_CLASS_HEX
228 
229 #define	NXGE_PARAM_CMPLX		0x00010000ULL
230 #define	NXGE_PARAM_NDD_WR_OK		0x00020000ULL
231 #define	NXGE_PARAM_INIT_ONLY		0x00040000ULL
232 #define	NXGE_PARAM_INIT_CONFIG		0x00080000ULL
233 
234 #define	NXGE_PARAM_READ_PROP		0x00100000ULL
235 #define	NXGE_PARAM_PROP_ARR32		0x00200000ULL
236 #define	NXGE_PARAM_PROP_ARR64		0x00400000ULL
237 #define	NXGE_PARAM_PROP_STR		0x00800000ULL
238 
239 #define	NXGE_PARAM_BASE_DEC		0x00000000ULL
240 #define	NXGE_PARAM_BASE_BIN		0x10000000ULL
241 #define	NXGE_PARAM_BASE_HEX		0x20000000ULL
242 #define	NXGE_PARAM_BASE_STR		0x40000000ULL
243 #define	NXGE_PARAM_DONT_SHOW		0x80000000ULL
244 
245 #define	NXGE_PARAM_ARRAY_CNT_MASK	0x0000ffff00000000ULL
246 #define	NXGE_PARAM_ARRAY_CNT_SHIFT	32ULL
247 #define	NXGE_PARAM_ARRAY_ALLOC_MASK	0xffff000000000000ULL
248 #define	NXGE_PARAM_ARRAY_ALLOC_SHIFT	48ULL
249 
250 typedef struct _nxge_param_t {
251 	int (*getf)();
252 	int (*setf)();   /* null for read only */
253 	uint64_t type;  /* R/W/ Common/Port/ .... */
254 	uint64_t minimum;
255 	uint64_t maximum;
256 	uint64_t value;	/* for array params, pointer to value array */
257 	uint64_t old_value; /* for array params, pointer to old_value array */
258 	char   *fcode_name;
259 	char   *name;
260 } nxge_param_t, *p_nxge_param_t;
261 
262 
263 
264 typedef enum {
265 	nxge_lb_normal,
266 	nxge_lb_ext10g,
267 	nxge_lb_ext1000,
268 	nxge_lb_ext100,
269 	nxge_lb_ext10,
270 	nxge_lb_phy10g,
271 	nxge_lb_phy1000,
272 	nxge_lb_phy,
273 	nxge_lb_serdes10g,
274 	nxge_lb_serdes1000,
275 	nxge_lb_serdes,
276 	nxge_lb_mac10g,
277 	nxge_lb_mac1000,
278 	nxge_lb_mac
279 } nxge_lb_t;
280 
281 enum nxge_mac_state {
282 	NXGE_MAC_STOPPED = 0,
283 	NXGE_MAC_STARTED
284 };
285 
286 /*
287  * Private DLPI full dlsap address format.
288  */
289 typedef struct _nxge_dladdr_t {
290 	ether_addr_st dl_phys;
291 	uint16_t dl_sap;
292 } nxge_dladdr_t, *p_nxge_dladdr_t;
293 
294 typedef struct _mc_addr_t {
295 	ether_addr_st multcast_addr;
296 	uint_t mc_addr_cnt;
297 } mc_addr_t, *p_mc_addr_t;
298 
299 typedef struct _mc_bucket_t {
300 	p_mc_addr_t addr_list;
301 	uint_t list_size;
302 } mc_bucket_t, *p_mc_bucket_t;
303 
304 typedef struct _mc_table_t {
305 	p_mc_bucket_t bucket_list;
306 	uint_t buckets_used;
307 } mc_table_t, *p_mc_table_t;
308 
309 typedef struct _filter_t {
310 	uint32_t all_phys_cnt;
311 	uint32_t all_multicast_cnt;
312 	uint32_t all_sap_cnt;
313 } filter_t, *p_filter_t;
314 
315 #if defined(_KERNEL) || defined(COSIM)
316 
317 
318 typedef struct _nxge_port_stats_t {
319 	/*
320 	 *  Overall structure size
321 	 */
322 	size_t			stats_size;
323 
324 	/*
325 	 * Link Input/Output stats
326 	 */
327 	uint64_t		ipackets;
328 	uint64_t		ierrors;
329 	uint64_t		opackets;
330 	uint64_t		oerrors;
331 	uint64_t		collisions;
332 
333 	/*
334 	 * MIB II variables
335 	 */
336 	uint64_t		rbytes;    /* # bytes received */
337 	uint64_t		obytes;    /* # bytes transmitted */
338 	uint32_t		multircv;  /* # multicast packets received */
339 	uint32_t		multixmt;  /* # multicast packets for xmit */
340 	uint32_t		brdcstrcv; /* # broadcast packets received */
341 	uint32_t		brdcstxmt; /* # broadcast packets for xmit */
342 	uint32_t		norcvbuf;  /* # rcv packets discarded */
343 	uint32_t		noxmtbuf;  /* # xmit packets discarded */
344 
345 	/*
346 	 * Lets the user know the MTU currently in use by
347 	 * the physical MAC port.
348 	 */
349 	nxge_lb_t		lb_mode;
350 	uint32_t		qos_mode;
351 	uint32_t		trunk_mode;
352 	uint32_t		poll_mode;
353 
354 	/*
355 	 * Tx Statistics.
356 	 */
357 	uint32_t		tx_inits;
358 	uint32_t		tx_starts;
359 	uint32_t		tx_nocanput;
360 	uint32_t		tx_msgdup_fail;
361 	uint32_t		tx_allocb_fail;
362 	uint32_t		tx_no_desc;
363 	uint32_t		tx_dma_bind_fail;
364 	uint32_t		tx_uflo;
365 	uint32_t		tx_hdr_pkts;
366 	uint32_t		tx_ddi_pkts;
367 	uint32_t		tx_dvma_pkts;
368 
369 	uint32_t		tx_max_pend;
370 
371 	/*
372 	 * Rx Statistics.
373 	 */
374 	uint32_t		rx_inits;
375 	uint32_t		rx_hdr_pkts;
376 	uint32_t		rx_mtu_pkts;
377 	uint32_t		rx_split_pkts;
378 	uint32_t		rx_no_buf;
379 	uint32_t		rx_no_comp_wb;
380 	uint32_t		rx_ov_flow;
381 	uint32_t		rx_len_mm;
382 	uint32_t		rx_tag_err;
383 	uint32_t		rx_nocanput;
384 	uint32_t		rx_msgdup_fail;
385 	uint32_t		rx_allocb_fail;
386 
387 	/*
388 	 * Receive buffer management statistics.
389 	 */
390 	uint32_t		rx_new_pages;
391 	uint32_t		rx_new_hdr_pgs;
392 	uint32_t		rx_new_mtu_pgs;
393 	uint32_t		rx_new_nxt_pgs;
394 	uint32_t		rx_reused_pgs;
395 	uint32_t		rx_hdr_drops;
396 	uint32_t		rx_mtu_drops;
397 	uint32_t		rx_nxt_drops;
398 
399 	/*
400 	 * Receive flow statistics
401 	 */
402 	uint32_t		rx_rel_flow;
403 	uint32_t		rx_rel_bit;
404 
405 	uint32_t		rx_pkts_dropped;
406 
407 	/*
408 	 * PCI-E Bus Statistics.
409 	 */
410 	uint32_t		pci_bus_speed;
411 	uint32_t		pci_err;
412 	uint32_t		pci_rta_err;
413 	uint32_t		pci_rma_err;
414 	uint32_t		pci_parity_err;
415 	uint32_t		pci_bad_ack_err;
416 	uint32_t		pci_drto_err;
417 	uint32_t		pci_dmawz_err;
418 	uint32_t		pci_dmarz_err;
419 
420 	uint32_t		rx_taskq_waits;
421 
422 	uint32_t		tx_jumbo_pkts;
423 
424 	/*
425 	 * Some statistics added to support bringup, these
426 	 * should be removed.
427 	 */
428 	uint32_t		user_defined;
429 } nxge_port_stats_t, *p_nxge_port_stats_t;
430 
431 
432 typedef struct _nxge_stats_t {
433 	/*
434 	 *  Overall structure size
435 	 */
436 	size_t			stats_size;
437 
438 	kstat_t			*ksp;
439 	kstat_t			*rdc_ksp[NXGE_MAX_RDCS];
440 	kstat_t			*tdc_ksp[NXGE_MAX_TDCS];
441 	kstat_t			*rdc_sys_ksp;
442 	kstat_t			*fflp_ksp[1];
443 	kstat_t			*ipp_ksp;
444 	kstat_t			*txc_ksp;
445 	kstat_t			*mac_ksp;
446 	kstat_t			*zcp_ksp;
447 	kstat_t			*port_ksp;
448 	kstat_t			*mmac_ksp;
449 
450 	nxge_mac_stats_t	mac_stats;	/* Common MAC Statistics */
451 	nxge_xmac_stats_t	xmac_stats;	/* XMAC Statistics */
452 	nxge_bmac_stats_t	bmac_stats;	/* BMAC Statistics */
453 
454 	nxge_rx_ring_stats_t	rx_stats;	/* per port RX stats */
455 	nxge_ipp_stats_t	ipp_stats;	/* per port IPP stats */
456 	nxge_zcp_stats_t	zcp_stats;	/* per port IPP stats */
457 	nxge_rx_ring_stats_t	rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */
458 	nxge_rdc_sys_stats_t	rdc_sys_stats;	/* per port RDC stats */
459 
460 	nxge_tx_ring_stats_t	tx_stats;	/* per port TX stats */
461 	nxge_txc_stats_t	txc_stats;	/* per port TX stats */
462 	nxge_tx_ring_stats_t	tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */
463 	nxge_fflp_stats_t	fflp_stats;	/* fflp stats */
464 	nxge_port_stats_t	port_stats;	/* fflp stats */
465 	nxge_mmac_stats_t	mmac_stats;	/* Multi mac. stats */
466 
467 } nxge_stats_t, *p_nxge_stats_t;
468 
469 
470 
471 typedef struct _nxge_intr_t {
472 	boolean_t		intr_registered; /* interrupts are registered */
473 	boolean_t		intr_enabled; 	/* interrupts are enabled */
474 	boolean_t		niu_msi_enable;	/* debug or configurable? */
475 	uint8_t			nldevs;		/* # of logical devices */
476 	int			intr_types;	/* interrupt types supported */
477 	int			intr_type;	/* interrupt type to add */
478 	int			max_int_cnt;	/* max MSIX/INT HW supports */
479 	int			start_inum;	/* start inum (in sequence?) */
480 	int			msi_intx_cnt;	/* # msi/intx ints returned */
481 	int			intr_added;	/* # ints actually needed */
482 	int			intr_cap;	/* interrupt capabilities */
483 	size_t			intr_size;	/* size of array to allocate */
484 	ddi_intr_handle_t 	*htable;	/* For array of interrupts */
485 	/* Add interrupt number for each interrupt vector */
486 	int			pri;
487 } nxge_intr_t, *p_nxge_intr_t;
488 
489 typedef struct _nxge_ldgv_t {
490 	uint8_t			ndma_ldvs;
491 	uint8_t			nldvs;
492 	uint8_t			start_ldg;
493 	uint8_t			start_ldg_tx;
494 	uint8_t			start_ldg_rx;
495 	uint8_t			maxldgs;
496 	uint8_t			maxldvs;
497 	uint8_t			ldg_intrs;
498 	boolean_t		own_sys_err;
499 	boolean_t		own_max_ldv;
500 	uint32_t		tmres;
501 	p_nxge_ldg_t		ldgp;
502 	p_nxge_ldv_t		ldvp;
503 	p_nxge_ldv_t		ldvp_syserr;
504 } nxge_ldgv_t, *p_nxge_ldgv_t;
505 
506 /*
507  * Neptune Device instance state information.
508  *
509  * Each instance is dynamically allocated on first attach.
510  */
511 struct _nxge_t {
512 	dev_info_t		*dip;		/* device instance */
513 	dev_info_t		*p_dip;		/* Parent's device instance */
514 	int			instance;	/* instance number */
515 	int			function_num;	/* device function number */
516 	int			nports;		/* # of ports on this device */
517 	int			board_ver;	/* Board Version */
518 	int			partition_id;	/* partition ID */
519 	int			use_partition;	/* partition is enabled */
520 	uint32_t		drv_state;	/* driver state bit flags */
521 	uint64_t		nxge_debug_level; /* driver state bit flags */
522 	kmutex_t		genlock[1];
523 	enum nxge_mac_state	nxge_mac_state;
524 	ddi_softintr_t		resched_id;	/* reschedule callback	*/
525 	boolean_t		resched_needed;
526 	boolean_t		resched_running;
527 
528 	p_dev_regs_t		dev_regs;
529 	npi_handle_t		npi_handle;
530 	npi_handle_t		npi_pci_handle;
531 	npi_handle_t		npi_reg_handle;
532 	npi_handle_t		npi_msi_handle;
533 	npi_handle_t		npi_vreg_handle;
534 	npi_handle_t		npi_v2reg_handle;
535 
536 	nxge_mac_t		mac;
537 	nxge_ipp_t		ipp;
538 	nxge_txc_t		txc;
539 	nxge_classify_t		classifier;
540 
541 	mac_handle_t		mach;	/* mac module handle */
542 	p_nxge_stats_t		statsp;
543 	uint32_t		param_count;
544 	p_nxge_param_t		param_arr;
545 	nxge_hw_list_t		*nxge_hw_p; 	/* pointer to per Neptune */
546 	niu_type_t		niu_type;
547 	boolean_t		os_addr_mode32;	/* set to 1 for 32 bit mode */
548 	uint8_t			nrdc;
549 	uint8_t			def_rdc;
550 	uint8_t			rdc[NXGE_MAX_RDCS];
551 	uint8_t			ntdc;
552 	uint8_t			tdc[NXGE_MAX_TDCS];
553 
554 	nxge_intr_t		nxge_intr_type;
555 	nxge_dma_pt_cfg_t 	pt_config;
556 	nxge_class_pt_cfg_t 	class_config;
557 
558 	/* Logical device and group data structures. */
559 	p_nxge_ldgv_t		ldgvp;
560 
561 	npi_vpd_info_t		vpd_info;
562 	caddr_t			param_list;	/* Parameter list */
563 
564 	ether_addr_st		factaddr;	/* factory mac address	    */
565 	ether_addr_st		ouraddr;	/* individual address	    */
566 	kmutex_t		ouraddr_lock;	/* lock to protect to uradd */
567 
568 	ddi_iblock_cookie_t	interrupt_cookie;
569 
570 	/*
571 	 * Blocks of memory may be pre-allocated by the
572 	 * partition manager or the driver. They may include
573 	 * blocks for configuration and buffers. The idea is
574 	 * to preallocate big blocks of contiguous areas in
575 	 * system memory (i.e. with IOMMU). These blocks then
576 	 * will be broken up to a fixed number of blocks with
577 	 * each block having the same block size (4K, 8K, 16K or
578 	 * 32K) in the case of buffer blocks. For systems that
579 	 * do not support DVMA, more than one big block will be
580 	 * allocated.
581 	 */
582 	uint32_t		rx_default_block_size;
583 	nxge_rx_block_size_t	rx_bksize_code;
584 
585 	p_nxge_dma_pool_t	rx_buf_pool_p;
586 	p_nxge_dma_pool_t	rx_cntl_pool_p;
587 
588 	p_nxge_dma_pool_t	tx_buf_pool_p;
589 	p_nxge_dma_pool_t	tx_cntl_pool_p;
590 
591 	/* Receive buffer block ring and completion ring. */
592 	p_rx_rbr_rings_t 	rx_rbr_rings;
593 	p_rx_rcr_rings_t 	rx_rcr_rings;
594 	p_rx_mbox_areas_t 	rx_mbox_areas_p;
595 
596 	p_rx_tx_params_t	rx_params;
597 	uint32_t		start_rdc;
598 	uint32_t		max_rdcs;
599 	uint32_t		rdc_mask;
600 
601 	/* Transmit descriptors rings */
602 	p_tx_rings_t 		tx_rings;
603 	p_tx_mbox_areas_t	tx_mbox_areas_p;
604 
605 	uint32_t		start_tdc;
606 	uint32_t		max_tdcs;
607 	uint32_t		tdc_mask;
608 
609 	p_rx_tx_params_t	tx_params;
610 
611 	ddi_dma_handle_t 	dmasparehandle;
612 
613 	ulong_t 		sys_page_sz;
614 	ulong_t 		sys_page_mask;
615 	int 			suspended;
616 
617 	mii_bmsr_t 		bmsr;		/* xcvr status at last poll. */
618 	mii_bmsr_t 		soft_bmsr;	/* xcvr status kept by SW. */
619 
620 	kmutex_t 		mif_lock;	/* Lock to protect the list. */
621 
622 	void 			(*mii_read)();
623 	void 			(*mii_write)();
624 	void 			(*mii_poll)();
625 	filter_t 		filter;		/* Current instance filter */
626 	p_hash_filter_t 	hash_filter;	/* Multicast hash filter. */
627 	krwlock_t		filter_lock;	/* Lock to protect filters. */
628 
629 	ulong_t 		sys_burst_sz;
630 
631 	uint8_t 		cache_line;
632 
633 	timeout_id_t 		nxge_link_poll_timerid;
634 	timeout_id_t 		nxge_timerid;
635 
636 	uint_t 			need_periodic_reclaim;
637 	timeout_id_t 		reclaim_timer;
638 
639 	uint8_t 		msg_min;
640 	uint8_t 		crc_size;
641 
642 	boolean_t 		hard_props_read;
643 
644 	boolean_t 		nxge_htraffic;
645 	uint32_t 		nxge_ncpus;
646 	uint32_t 		nxge_cpumask;
647 	uint16_t 		intr_timeout;
648 	uint16_t 		intr_threshold;
649 	uchar_t 		nxge_rxmode;
650 	uint32_t 		active_threads;
651 
652 	rtrace_t		rtrace;
653 	int			fm_capabilities; /* FMA capabilities */
654 
655 	uint32_t 		nxge_port_rbr_size;
656 	uint32_t 		nxge_port_rcr_size;
657 	uint32_t 		nxge_port_tx_ring_size;
658 	nxge_mmac_t		nxge_mmac_info;
659 #if	defined(sun4v)
660 	boolean_t		niu_hsvc_available;
661 	hsvc_info_t		niu_hsvc;
662 	uint64_t		niu_min_ver;
663 #endif
664 	boolean_t		link_notify;
665 };
666 
667 /*
668  * Driver state flags.
669  */
670 #define	STATE_REGS_MAPPED	0x000000001	/* device registers mapped */
671 #define	STATE_KSTATS_SETUP	0x000000002	/* kstats allocated	*/
672 #define	STATE_NODE_CREATED	0x000000004	/* device node created	*/
673 #define	STATE_HW_CONFIG_CREATED	0x000000008	/* hardware properties	*/
674 #define	STATE_HW_INITIALIZED	0x000000010	/* hardware initialized	*/
675 #define	STATE_MDIO_LOCK_INIT	0x000000020	/* mdio lock initialized */
676 #define	STATE_MII_LOCK_INIT	0x000000040	/* mii lock initialized */
677 
678 #define	STOP_POLL_THRESH 	9
679 #define	START_POLL_THRESH	2
680 
681 typedef struct _nxge_port_kstat_t {
682 	/*
683 	 * Transciever state informations.
684 	 */
685 	kstat_named_t	xcvr_inits;
686 	kstat_named_t	xcvr_inuse;
687 	kstat_named_t	xcvr_addr;
688 	kstat_named_t	xcvr_id;
689 	kstat_named_t	cap_autoneg;
690 	kstat_named_t	cap_10gfdx;
691 	kstat_named_t	cap_10ghdx;
692 	kstat_named_t	cap_1000fdx;
693 	kstat_named_t	cap_1000hdx;
694 	kstat_named_t	cap_100T4;
695 	kstat_named_t	cap_100fdx;
696 	kstat_named_t	cap_100hdx;
697 	kstat_named_t	cap_10fdx;
698 	kstat_named_t	cap_10hdx;
699 	kstat_named_t	cap_asmpause;
700 	kstat_named_t	cap_pause;
701 
702 	/*
703 	 * Link partner capabilities.
704 	 */
705 	kstat_named_t	lp_cap_autoneg;
706 	kstat_named_t	lp_cap_10gfdx;
707 	kstat_named_t	lp_cap_10ghdx;
708 	kstat_named_t	lp_cap_1000fdx;
709 	kstat_named_t	lp_cap_1000hdx;
710 	kstat_named_t	lp_cap_100T4;
711 	kstat_named_t	lp_cap_100fdx;
712 	kstat_named_t	lp_cap_100hdx;
713 	kstat_named_t	lp_cap_10fdx;
714 	kstat_named_t	lp_cap_10hdx;
715 	kstat_named_t	lp_cap_asmpause;
716 	kstat_named_t	lp_cap_pause;
717 
718 	/*
719 	 * Shared link setup.
720 	 */
721 	kstat_named_t	link_T4;
722 	kstat_named_t	link_speed;
723 	kstat_named_t	link_duplex;
724 	kstat_named_t	link_asmpause;
725 	kstat_named_t	link_pause;
726 	kstat_named_t	link_up;
727 
728 	/*
729 	 * Lets the user know the MTU currently in use by
730 	 * the physical MAC port.
731 	 */
732 	kstat_named_t	mac_mtu;
733 	kstat_named_t	lb_mode;
734 	kstat_named_t	qos_mode;
735 	kstat_named_t	trunk_mode;
736 
737 	/*
738 	 * Misc MAC statistics.
739 	 */
740 	kstat_named_t	ifspeed;
741 	kstat_named_t	promisc;
742 	kstat_named_t	rev_id;
743 
744 	/*
745 	 * Some statistics added to support bringup, these
746 	 * should be removed.
747 	 */
748 	kstat_named_t	user_defined;
749 } nxge_port_kstat_t, *p_nxge_port_kstat_t;
750 
751 typedef struct _nxge_rdc_kstat {
752 	/*
753 	 * Receive DMA channel statistics.
754 	 */
755 	kstat_named_t	ipackets;
756 	kstat_named_t	rbytes;
757 	kstat_named_t	errors;
758 	kstat_named_t	dcf_err;
759 	kstat_named_t	rcr_ack_err;
760 
761 	kstat_named_t	dc_fifoflow_err;
762 	kstat_named_t	rcr_sha_par_err;
763 	kstat_named_t	rbr_pre_par_err;
764 	kstat_named_t	wred_drop;
765 	kstat_named_t	rbr_pre_emty;
766 
767 	kstat_named_t	rcr_shadow_full;
768 	kstat_named_t	rbr_tmout;
769 	kstat_named_t	rsp_cnt_err;
770 	kstat_named_t	byte_en_bus;
771 	kstat_named_t	rsp_dat_err;
772 
773 	kstat_named_t	compl_l2_err;
774 	kstat_named_t	compl_l4_cksum_err;
775 	kstat_named_t	compl_zcp_soft_err;
776 	kstat_named_t	compl_fflp_soft_err;
777 	kstat_named_t	config_err;
778 
779 	kstat_named_t	rcrincon;
780 	kstat_named_t	rcrfull;
781 	kstat_named_t	rbr_empty;
782 	kstat_named_t	rbrfull;
783 	kstat_named_t	rbrlogpage;
784 
785 	kstat_named_t	cfiglogpage;
786 	kstat_named_t	port_drop_pkt;
787 	kstat_named_t	rcr_to;
788 	kstat_named_t	rcr_thresh;
789 	kstat_named_t	rcr_mex;
790 	kstat_named_t	id_mismatch;
791 	kstat_named_t	zcp_eop_err;
792 	kstat_named_t	ipp_eop_err;
793 } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t;
794 
795 typedef struct _nxge_rdc_sys_kstat {
796 	/*
797 	 * Receive DMA system statistics.
798 	 */
799 	kstat_named_t	pre_par;
800 	kstat_named_t	sha_par;
801 	kstat_named_t	id_mismatch;
802 	kstat_named_t	ipp_eop_err;
803 	kstat_named_t	zcp_eop_err;
804 } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t;
805 
806 typedef	struct _nxge_tdc_kstat {
807 	/*
808 	 * Transmit DMA channel statistics.
809 	 */
810 	kstat_named_t	opackets;
811 	kstat_named_t	obytes;
812 	kstat_named_t	oerrors;
813 	kstat_named_t	tx_inits;
814 	kstat_named_t	tx_no_buf;
815 
816 	kstat_named_t	mbox_err;
817 	kstat_named_t	pkt_size_err;
818 	kstat_named_t	tx_ring_oflow;
819 	kstat_named_t	pref_buf_ecc_err;
820 	kstat_named_t	nack_pref;
821 	kstat_named_t	nack_pkt_rd;
822 	kstat_named_t	conf_part_err;
823 	kstat_named_t	pkt_prt_err;
824 	kstat_named_t	reset_fail;
825 /* used to in the common (per port) counter */
826 
827 	kstat_named_t	tx_starts;
828 	kstat_named_t	tx_nocanput;
829 	kstat_named_t	tx_msgdup_fail;
830 	kstat_named_t	tx_allocb_fail;
831 	kstat_named_t	tx_no_desc;
832 	kstat_named_t	tx_dma_bind_fail;
833 	kstat_named_t	tx_uflo;
834 	kstat_named_t	tx_hdr_pkts;
835 	kstat_named_t	tx_ddi_pkts;
836 	kstat_named_t	tx_dvma_pkts;
837 	kstat_named_t	tx_max_pend;
838 } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t;
839 
840 typedef	struct _nxge_txc_kstat {
841 	/*
842 	 * Transmit port TXC block statistics.
843 	 */
844 	kstat_named_t	pkt_stuffed;
845 	kstat_named_t	pkt_xmit;
846 	kstat_named_t	ro_correct_err;
847 	kstat_named_t	ro_uncorrect_err;
848 	kstat_named_t	sf_correct_err;
849 	kstat_named_t	sf_uncorrect_err;
850 	kstat_named_t	address_failed;
851 	kstat_named_t	dma_failed;
852 	kstat_named_t	length_failed;
853 	kstat_named_t	pkt_assy_dead;
854 	kstat_named_t	reorder_err;
855 } nxge_txc_kstat_t, *p_nxge_txc_kstat_t;
856 
857 typedef struct _nxge_ipp_kstat {
858 	/*
859 	 * Receive port IPP block statistics.
860 	 */
861 	kstat_named_t	eop_miss;
862 	kstat_named_t	sop_miss;
863 	kstat_named_t	dfifo_ue;
864 	kstat_named_t	ecc_err_cnt;
865 	kstat_named_t	pfifo_perr;
866 	kstat_named_t	pfifo_over;
867 	kstat_named_t	pfifo_und;
868 	kstat_named_t	bad_cs_cnt;
869 	kstat_named_t	pkt_dis_cnt;
870 } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t;
871 
872 typedef	struct _nxge_zcp_kstat {
873 	/*
874 	 * ZCP statistics.
875 	 */
876 	kstat_named_t	errors;
877 	kstat_named_t	inits;
878 	kstat_named_t	rrfifo_underrun;
879 	kstat_named_t	rrfifo_overrun;
880 	kstat_named_t	rspfifo_uncorr_err;
881 	kstat_named_t	buffer_overflow;
882 	kstat_named_t	stat_tbl_perr;
883 	kstat_named_t	dyn_tbl_perr;
884 	kstat_named_t	buf_tbl_perr;
885 	kstat_named_t	tt_program_err;
886 	kstat_named_t	rsp_tt_index_err;
887 	kstat_named_t	slv_tt_index_err;
888 	kstat_named_t	zcp_tt_index_err;
889 	kstat_named_t	access_fail;
890 	kstat_named_t	cfifo_ecc;
891 } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t;
892 
893 typedef	struct _nxge_mac_kstat {
894 	/*
895 	 * Transmit MAC statistics.
896 	 */
897 	kstat_named_t	tx_frame_cnt;
898 	kstat_named_t	tx_underflow_err;
899 	kstat_named_t	tx_overflow_err;
900 	kstat_named_t	tx_maxpktsize_err;
901 	kstat_named_t	tx_fifo_xfr_err;
902 	kstat_named_t	tx_byte_cnt;
903 
904 	/*
905 	 * Receive MAC statistics.
906 	 */
907 	kstat_named_t	rx_frame_cnt;
908 	kstat_named_t	rx_underflow_err;
909 	kstat_named_t	rx_overflow_err;
910 	kstat_named_t	rx_len_err_cnt;
911 	kstat_named_t	rx_crc_err_cnt;
912 	kstat_named_t	rx_viol_err_cnt;
913 	kstat_named_t	rx_byte_cnt;
914 	kstat_named_t	rx_hist1_cnt;
915 	kstat_named_t	rx_hist2_cnt;
916 	kstat_named_t	rx_hist3_cnt;
917 	kstat_named_t	rx_hist4_cnt;
918 	kstat_named_t	rx_hist5_cnt;
919 	kstat_named_t	rx_hist6_cnt;
920 	kstat_named_t	rx_broadcast_cnt;
921 	kstat_named_t	rx_mult_cnt;
922 	kstat_named_t	rx_frag_cnt;
923 	kstat_named_t	rx_frame_align_err_cnt;
924 	kstat_named_t	rx_linkfault_err_cnt;
925 	kstat_named_t	rx_local_fault_err_cnt;
926 	kstat_named_t	rx_remote_fault_err_cnt;
927 } nxge_mac_kstat_t, *p_nxge_mac_kstat_t;
928 
929 typedef	struct _nxge_xmac_kstat {
930 	/*
931 	 * XMAC statistics.
932 	 */
933 	kstat_named_t	tx_frame_cnt;
934 	kstat_named_t	tx_underflow_err;
935 	kstat_named_t	tx_maxpktsize_err;
936 	kstat_named_t	tx_overflow_err;
937 	kstat_named_t	tx_fifo_xfr_err;
938 	kstat_named_t	tx_byte_cnt;
939 	kstat_named_t	rx_frame_cnt;
940 	kstat_named_t	rx_underflow_err;
941 	kstat_named_t	rx_overflow_err;
942 	kstat_named_t	rx_crc_err_cnt;
943 	kstat_named_t	rx_len_err_cnt;
944 	kstat_named_t	rx_viol_err_cnt;
945 	kstat_named_t	rx_byte_cnt;
946 	kstat_named_t	rx_hist1_cnt;
947 	kstat_named_t	rx_hist2_cnt;
948 	kstat_named_t	rx_hist3_cnt;
949 	kstat_named_t	rx_hist4_cnt;
950 	kstat_named_t	rx_hist5_cnt;
951 	kstat_named_t	rx_hist6_cnt;
952 	kstat_named_t	rx_hist7_cnt;
953 	kstat_named_t	rx_broadcast_cnt;
954 	kstat_named_t	rx_mult_cnt;
955 	kstat_named_t	rx_frag_cnt;
956 	kstat_named_t	rx_frame_align_err_cnt;
957 	kstat_named_t	rx_linkfault_err_cnt;
958 	kstat_named_t	rx_remote_fault_err_cnt;
959 	kstat_named_t	rx_local_fault_err_cnt;
960 	kstat_named_t	rx_pause_cnt;
961 	kstat_named_t	xpcs_deskew_err_cnt;
962 	kstat_named_t	xpcs_ln0_symbol_err_cnt;
963 	kstat_named_t	xpcs_ln1_symbol_err_cnt;
964 	kstat_named_t	xpcs_ln2_symbol_err_cnt;
965 	kstat_named_t	xpcs_ln3_symbol_err_cnt;
966 } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t;
967 
968 typedef	struct _nxge_bmac_kstat {
969 	/*
970 	 * BMAC statistics.
971 	 */
972 	kstat_named_t tx_frame_cnt;
973 	kstat_named_t tx_underrun_err;
974 	kstat_named_t tx_max_pkt_err;
975 	kstat_named_t tx_byte_cnt;
976 	kstat_named_t rx_frame_cnt;
977 	kstat_named_t rx_byte_cnt;
978 	kstat_named_t rx_overflow_err;
979 	kstat_named_t rx_align_err_cnt;
980 	kstat_named_t rx_crc_err_cnt;
981 	kstat_named_t rx_len_err_cnt;
982 	kstat_named_t rx_viol_err_cnt;
983 	kstat_named_t rx_pause_cnt;
984 	kstat_named_t tx_pause_state;
985 	kstat_named_t tx_nopause_state;
986 } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t;
987 
988 
989 typedef struct _nxge_fflp_kstat {
990 	/*
991 	 * FFLP statistics.
992 	 */
993 
994 	kstat_named_t	fflp_tcam_ecc_err;
995 	kstat_named_t	fflp_tcam_perr;
996 	kstat_named_t	fflp_vlan_perr;
997 	kstat_named_t	fflp_hasht_lookup_err;
998 	kstat_named_t	fflp_access_fail;
999 	kstat_named_t	fflp_hasht_data_err[MAX_PARTITION];
1000 } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t;
1001 
1002 typedef struct _nxge_mmac_kstat {
1003 	kstat_named_t	mmac_max_addr_cnt;
1004 	kstat_named_t	mmac_avail_addr_cnt;
1005 	kstat_named_t	mmac_addr1;
1006 	kstat_named_t	mmac_addr2;
1007 	kstat_named_t	mmac_addr3;
1008 	kstat_named_t	mmac_addr4;
1009 	kstat_named_t	mmac_addr5;
1010 	kstat_named_t	mmac_addr6;
1011 	kstat_named_t	mmac_addr7;
1012 	kstat_named_t	mmac_addr8;
1013 	kstat_named_t	mmac_addr9;
1014 	kstat_named_t	mmac_addr10;
1015 	kstat_named_t	mmac_addr11;
1016 	kstat_named_t	mmac_addr12;
1017 	kstat_named_t	mmac_addr13;
1018 	kstat_named_t	mmac_addr14;
1019 	kstat_named_t	mmac_addr15;
1020 	kstat_named_t	mmac_addr16;
1021 } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t;
1022 
1023 #endif	/* _KERNEL */
1024 
1025 /*
1026  * Prototype definitions.
1027  */
1028 nxge_status_t nxge_init(p_nxge_t);
1029 void nxge_uninit(p_nxge_t);
1030 void nxge_get64(p_nxge_t, p_mblk_t);
1031 void nxge_put64(p_nxge_t, p_mblk_t);
1032 void nxge_pio_loop(p_nxge_t, p_mblk_t);
1033 
1034 #ifndef COSIM
1035 typedef	void	(*fptrv_t)();
1036 timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int);
1037 void nxge_stop_timer(p_nxge_t, timeout_id_t);
1038 #endif
1039 #endif
1040 
1041 #ifdef	__cplusplus
1042 }
1043 #endif
1044 
1045 #endif	/* _SYS_NXGE_NXGE_H */
1046