144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22a3c5bd6dSspeer * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #ifndef _SYS_NXGE_NXGE_H 2744961713Sgirish #define _SYS_NXGE_NXGE_H 2844961713Sgirish 2944961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 3044961713Sgirish 3144961713Sgirish #ifdef __cplusplus 3244961713Sgirish extern "C" { 3344961713Sgirish #endif 3444961713Sgirish 3544961713Sgirish #if defined(_KERNEL) || defined(COSIM) 3644961713Sgirish #include <nxge_mac.h> 3744961713Sgirish #include <nxge_ipp.h> 3844961713Sgirish #include <nxge_fflp.h> 3944961713Sgirish #endif 4044961713Sgirish 4144961713Sgirish /* 4244961713Sgirish * NXGE diagnostics IOCTLS. 4344961713Sgirish */ 4444961713Sgirish #define NXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 4544961713Sgirish 4644961713Sgirish #define NXGE_GET64 (NXGE_IOC|1) 4744961713Sgirish #define NXGE_PUT64 (NXGE_IOC|2) 4844961713Sgirish #define NXGE_GET_TX_RING_SZ (NXGE_IOC|3) 4944961713Sgirish #define NXGE_GET_TX_DESC (NXGE_IOC|4) 5044961713Sgirish #define NXGE_GLOBAL_RESET (NXGE_IOC|5) 5144961713Sgirish #define NXGE_TX_SIDE_RESET (NXGE_IOC|6) 5244961713Sgirish #define NXGE_RX_SIDE_RESET (NXGE_IOC|7) 5344961713Sgirish #define NXGE_RESET_MAC (NXGE_IOC|8) 5444961713Sgirish 5544961713Sgirish #define NXGE_GET_MII (NXGE_IOC|11) 5644961713Sgirish #define NXGE_PUT_MII (NXGE_IOC|12) 5744961713Sgirish #define NXGE_RTRACE (NXGE_IOC|13) 5844961713Sgirish #define NXGE_RTRACE_TEST (NXGE_IOC|20) 5944961713Sgirish #define NXGE_TX_REGS_DUMP (NXGE_IOC|21) 6044961713Sgirish #define NXGE_RX_REGS_DUMP (NXGE_IOC|22) 6144961713Sgirish #define NXGE_INT_REGS_DUMP (NXGE_IOC|23) 6244961713Sgirish #define NXGE_VIR_REGS_DUMP (NXGE_IOC|24) 6344961713Sgirish #define NXGE_VIR_INT_REGS_DUMP (NXGE_IOC|25) 6444961713Sgirish #define NXGE_RDUMP (NXGE_IOC|26) 6544961713Sgirish #define NXGE_RDC_GRPS_DUMP (NXGE_IOC|27) 6644961713Sgirish #define NXGE_PIO_TEST (NXGE_IOC|28) 6744961713Sgirish 6844961713Sgirish #define NXGE_GET_TCAM (NXGE_IOC|29) 6944961713Sgirish #define NXGE_PUT_TCAM (NXGE_IOC|30) 7044961713Sgirish #define NXGE_INJECT_ERR (NXGE_IOC|40) 7144961713Sgirish 7244961713Sgirish #if (defined(SOLARIS) && defined(_KERNEL)) || defined(COSIM) 7344961713Sgirish #define NXGE_OK 0 7444961713Sgirish #define NXGE_ERROR 0x40000000 7544961713Sgirish #define NXGE_DDI_FAILED 0x20000000 7644961713Sgirish #define NXGE_GET_PORT_NUM(n) n 7744961713Sgirish 7844961713Sgirish /* 7944961713Sgirish * Definitions for module_info. 8044961713Sgirish */ 8144961713Sgirish #define NXGE_IDNUM (0) /* module ID number */ 8244961713Sgirish #define NXGE_DRIVER_NAME "nxge" /* module name */ 8344961713Sgirish 8444961713Sgirish #define NXGE_MINPSZ (0) /* min packet size */ 8544961713Sgirish #define NXGE_MAXPSZ (ETHERMTU) /* max packet size */ 8644961713Sgirish #define NXGE_HIWAT (2048 * NXGE_MAXPSZ) /* hi-water mark */ 8744961713Sgirish #define NXGE_LOWAT (1) /* lo-water mark */ 8844961713Sgirish #define NXGE_HIWAT_MAX (192000 * NXGE_MAXPSZ) 8944961713Sgirish #define NXGE_HIWAT_MIN (2 * NXGE_MAXPSZ) 9044961713Sgirish #define NXGE_LOWAT_MAX (192000 * NXGE_MAXPSZ) 9144961713Sgirish #define NXGE_LOWAT_MIN (1) 9244961713Sgirish 9344961713Sgirish #ifndef D_HOTPLUG 9444961713Sgirish #define D_HOTPLUG 0x00 9544961713Sgirish #endif 9644961713Sgirish 9744961713Sgirish #define INIT_BUCKET_SIZE 16 /* Initial Hash Bucket Size */ 9844961713Sgirish 9944961713Sgirish #define NXGE_CHECK_TIMER (5000) 10044961713Sgirish 10144961713Sgirish typedef enum { 10244961713Sgirish param_instance, 10344961713Sgirish param_main_instance, 10444961713Sgirish param_function_number, 10544961713Sgirish param_partition_id, 10644961713Sgirish param_read_write_mode, 10756d930aeSspeer param_fw_version, 10844961713Sgirish param_niu_cfg_type, 10944961713Sgirish param_tx_quick_cfg, 11044961713Sgirish param_rx_quick_cfg, 111a3c5bd6dSspeer param_master_cfg_enable, 112a3c5bd6dSspeer param_master_cfg_value, 11344961713Sgirish 11444961713Sgirish param_autoneg, 11544961713Sgirish param_anar_10gfdx, 11644961713Sgirish param_anar_10ghdx, 11744961713Sgirish param_anar_1000fdx, 11844961713Sgirish param_anar_1000hdx, 11944961713Sgirish param_anar_100T4, 12044961713Sgirish param_anar_100fdx, 12144961713Sgirish param_anar_100hdx, 12244961713Sgirish param_anar_10fdx, 12344961713Sgirish param_anar_10hdx, 12444961713Sgirish 12544961713Sgirish param_anar_asmpause, 12644961713Sgirish param_anar_pause, 12744961713Sgirish param_use_int_xcvr, 12844961713Sgirish param_enable_ipg0, 12944961713Sgirish param_ipg0, 13044961713Sgirish param_ipg1, 13144961713Sgirish param_ipg2, 13244961713Sgirish param_accept_jumbo, 13344961713Sgirish param_txdma_weight, 13444961713Sgirish param_txdma_channels_begin, 13544961713Sgirish 13644961713Sgirish param_txdma_channels, 13744961713Sgirish param_txdma_info, 13844961713Sgirish param_rxdma_channels_begin, 13944961713Sgirish param_rxdma_channels, 14044961713Sgirish param_rxdma_drr_weight, 14144961713Sgirish param_rxdma_full_header, 14244961713Sgirish param_rxdma_info, 14344961713Sgirish param_rxdma_rbr_size, 14444961713Sgirish param_rxdma_rcr_size, 14544961713Sgirish param_default_port_rdc, 14644961713Sgirish param_rxdma_intr_time, 14744961713Sgirish param_rxdma_intr_pkts, 14844961713Sgirish 14944961713Sgirish param_rdc_grps_start, 15044961713Sgirish param_rx_rdc_grps, 15144961713Sgirish param_default_grp0_rdc, 15244961713Sgirish param_default_grp1_rdc, 15344961713Sgirish param_default_grp2_rdc, 15444961713Sgirish param_default_grp3_rdc, 15544961713Sgirish param_default_grp4_rdc, 15644961713Sgirish param_default_grp5_rdc, 15744961713Sgirish param_default_grp6_rdc, 15844961713Sgirish param_default_grp7_rdc, 15944961713Sgirish 16044961713Sgirish param_info_rdc_groups, 16144961713Sgirish param_start_ldg, 16244961713Sgirish param_max_ldg, 16344961713Sgirish param_mac_2rdc_grp, 16444961713Sgirish param_vlan_2rdc_grp, 16544961713Sgirish param_fcram_part_cfg, 16644961713Sgirish param_fcram_access_ratio, 16744961713Sgirish param_tcam_access_ratio, 16844961713Sgirish param_tcam_enable, 16944961713Sgirish param_hash_lookup_enable, 17044961713Sgirish param_llc_snap_enable, 17144961713Sgirish 17244961713Sgirish param_h1_init_value, 17344961713Sgirish param_h2_init_value, 17444961713Sgirish param_class_cfg_ether_usr1, 17544961713Sgirish param_class_cfg_ether_usr2, 17644961713Sgirish param_class_cfg_ip_usr4, 17744961713Sgirish param_class_cfg_ip_usr5, 17844961713Sgirish param_class_cfg_ip_usr6, 17944961713Sgirish param_class_cfg_ip_usr7, 18044961713Sgirish param_class_opt_ip_usr4, 18144961713Sgirish param_class_opt_ip_usr5, 18244961713Sgirish param_class_opt_ip_usr6, 18344961713Sgirish param_class_opt_ip_usr7, 18444961713Sgirish param_class_opt_ipv4_tcp, 18544961713Sgirish param_class_opt_ipv4_udp, 18644961713Sgirish param_class_opt_ipv4_ah, 18744961713Sgirish param_class_opt_ipv4_sctp, 18844961713Sgirish param_class_opt_ipv6_tcp, 18944961713Sgirish param_class_opt_ipv6_udp, 19044961713Sgirish param_class_opt_ipv6_ah, 19144961713Sgirish param_class_opt_ipv6_sctp, 19244961713Sgirish param_nxge_debug_flag, 19344961713Sgirish param_npi_debug_flag, 19444961713Sgirish param_dump_rdc, 19544961713Sgirish param_dump_tdc, 19644961713Sgirish param_dump_mac_regs, 19744961713Sgirish param_dump_ipp_regs, 19844961713Sgirish param_dump_fflp_regs, 19944961713Sgirish param_dump_vlan_table, 20044961713Sgirish param_dump_rdc_table, 20144961713Sgirish param_dump_ptrs, 20244961713Sgirish param_end 20344961713Sgirish } nxge_param_index_t; 20444961713Sgirish 20544961713Sgirish 20644961713Sgirish /* 20744961713Sgirish * Named Dispatch Parameter Management Structure 20844961713Sgirish */ 20944961713Sgirish typedef int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *); 21044961713Sgirish typedef int (*nxge_ndsetf_t)(p_nxge_t, queue_t *, 211a3c5bd6dSspeer MBLKP, char *, caddr_t, cred_t *); 21244961713Sgirish 21344961713Sgirish #define NXGE_PARAM_READ 0x00000001ULL 21444961713Sgirish #define NXGE_PARAM_WRITE 0x00000002ULL 21544961713Sgirish #define NXGE_PARAM_SHARED 0x00000004ULL 21644961713Sgirish #define NXGE_PARAM_PRIV 0x00000008ULL 21744961713Sgirish #define NXGE_PARAM_RW NXGE_PARAM_READ | NXGE_PARAM_WRITE 21844961713Sgirish #define NXGE_PARAM_RWS NXGE_PARAM_RW | NXGE_PARAM_SHARED 21944961713Sgirish #define NXGE_PARAM_RWP NXGE_PARAM_RW | NXGE_PARAM_PRIV 22044961713Sgirish 22144961713Sgirish #define NXGE_PARAM_RXDMA 0x00000010ULL 22244961713Sgirish #define NXGE_PARAM_TXDMA 0x00000020ULL 22344961713Sgirish #define NXGE_PARAM_CLASS_GEN 0x00000040ULL 22444961713Sgirish #define NXGE_PARAM_MAC 0x00000080ULL 22544961713Sgirish #define NXGE_PARAM_CLASS_BIN NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN 22644961713Sgirish #define NXGE_PARAM_CLASS_HEX NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX 22744961713Sgirish #define NXGE_PARAM_CLASS NXGE_PARAM_CLASS_HEX 22844961713Sgirish 22944961713Sgirish #define NXGE_PARAM_CMPLX 0x00010000ULL 23044961713Sgirish #define NXGE_PARAM_NDD_WR_OK 0x00020000ULL 23144961713Sgirish #define NXGE_PARAM_INIT_ONLY 0x00040000ULL 23244961713Sgirish #define NXGE_PARAM_INIT_CONFIG 0x00080000ULL 23344961713Sgirish 23444961713Sgirish #define NXGE_PARAM_READ_PROP 0x00100000ULL 23544961713Sgirish #define NXGE_PARAM_PROP_ARR32 0x00200000ULL 23644961713Sgirish #define NXGE_PARAM_PROP_ARR64 0x00400000ULL 23744961713Sgirish #define NXGE_PARAM_PROP_STR 0x00800000ULL 23844961713Sgirish 23944961713Sgirish #define NXGE_PARAM_BASE_DEC 0x00000000ULL 24044961713Sgirish #define NXGE_PARAM_BASE_BIN 0x10000000ULL 24144961713Sgirish #define NXGE_PARAM_BASE_HEX 0x20000000ULL 24244961713Sgirish #define NXGE_PARAM_BASE_STR 0x40000000ULL 24344961713Sgirish #define NXGE_PARAM_DONT_SHOW 0x80000000ULL 24444961713Sgirish 24544961713Sgirish #define NXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 24644961713Sgirish #define NXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 24744961713Sgirish #define NXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 24844961713Sgirish #define NXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 24944961713Sgirish 25044961713Sgirish typedef struct _nxge_param_t { 25144961713Sgirish int (*getf)(); 25244961713Sgirish int (*setf)(); /* null for read only */ 25344961713Sgirish uint64_t type; /* R/W/ Common/Port/ .... */ 25444961713Sgirish uint64_t minimum; 25544961713Sgirish uint64_t maximum; 25644961713Sgirish uint64_t value; /* for array params, pointer to value array */ 25744961713Sgirish uint64_t old_value; /* for array params, pointer to old_value array */ 25844961713Sgirish char *fcode_name; 25944961713Sgirish char *name; 26044961713Sgirish } nxge_param_t, *p_nxge_param_t; 26144961713Sgirish 26244961713Sgirish 26344961713Sgirish 26444961713Sgirish typedef enum { 26544961713Sgirish nxge_lb_normal, 26644961713Sgirish nxge_lb_ext10g, 26744961713Sgirish nxge_lb_ext1000, 26844961713Sgirish nxge_lb_ext100, 26944961713Sgirish nxge_lb_ext10, 27044961713Sgirish nxge_lb_phy10g, 27144961713Sgirish nxge_lb_phy1000, 27244961713Sgirish nxge_lb_phy, 27344961713Sgirish nxge_lb_serdes10g, 27444961713Sgirish nxge_lb_serdes1000, 27544961713Sgirish nxge_lb_serdes, 27644961713Sgirish nxge_lb_mac10g, 27744961713Sgirish nxge_lb_mac1000, 27844961713Sgirish nxge_lb_mac 27944961713Sgirish } nxge_lb_t; 28044961713Sgirish 28144961713Sgirish enum nxge_mac_state { 28244961713Sgirish NXGE_MAC_STOPPED = 0, 28344961713Sgirish NXGE_MAC_STARTED 28444961713Sgirish }; 28544961713Sgirish 28644961713Sgirish /* 28744961713Sgirish * Private DLPI full dlsap address format. 28844961713Sgirish */ 28944961713Sgirish typedef struct _nxge_dladdr_t { 29044961713Sgirish ether_addr_st dl_phys; 29144961713Sgirish uint16_t dl_sap; 29244961713Sgirish } nxge_dladdr_t, *p_nxge_dladdr_t; 29344961713Sgirish 29444961713Sgirish typedef struct _mc_addr_t { 29544961713Sgirish ether_addr_st multcast_addr; 29644961713Sgirish uint_t mc_addr_cnt; 29744961713Sgirish } mc_addr_t, *p_mc_addr_t; 29844961713Sgirish 29944961713Sgirish typedef struct _mc_bucket_t { 30044961713Sgirish p_mc_addr_t addr_list; 30144961713Sgirish uint_t list_size; 30244961713Sgirish } mc_bucket_t, *p_mc_bucket_t; 30344961713Sgirish 30444961713Sgirish typedef struct _mc_table_t { 30544961713Sgirish p_mc_bucket_t bucket_list; 30644961713Sgirish uint_t buckets_used; 30744961713Sgirish } mc_table_t, *p_mc_table_t; 30844961713Sgirish 30944961713Sgirish typedef struct _filter_t { 31044961713Sgirish uint32_t all_phys_cnt; 31144961713Sgirish uint32_t all_multicast_cnt; 31244961713Sgirish uint32_t all_sap_cnt; 31344961713Sgirish } filter_t, *p_filter_t; 31444961713Sgirish 31544961713Sgirish #if defined(_KERNEL) || defined(COSIM) 31644961713Sgirish 31744961713Sgirish 31844961713Sgirish typedef struct _nxge_port_stats_t { 31944961713Sgirish /* 32044961713Sgirish * Overall structure size 32144961713Sgirish */ 32244961713Sgirish size_t stats_size; 32344961713Sgirish 32444961713Sgirish /* 32544961713Sgirish * Link Input/Output stats 32644961713Sgirish */ 32744961713Sgirish uint64_t ipackets; 32844961713Sgirish uint64_t ierrors; 32944961713Sgirish uint64_t opackets; 33044961713Sgirish uint64_t oerrors; 33144961713Sgirish uint64_t collisions; 33244961713Sgirish 33344961713Sgirish /* 33444961713Sgirish * MIB II variables 33544961713Sgirish */ 33644961713Sgirish uint64_t rbytes; /* # bytes received */ 33744961713Sgirish uint64_t obytes; /* # bytes transmitted */ 33844961713Sgirish uint32_t multircv; /* # multicast packets received */ 33944961713Sgirish uint32_t multixmt; /* # multicast packets for xmit */ 34044961713Sgirish uint32_t brdcstrcv; /* # broadcast packets received */ 34144961713Sgirish uint32_t brdcstxmt; /* # broadcast packets for xmit */ 34244961713Sgirish uint32_t norcvbuf; /* # rcv packets discarded */ 34344961713Sgirish uint32_t noxmtbuf; /* # xmit packets discarded */ 34444961713Sgirish 34544961713Sgirish /* 34644961713Sgirish * Lets the user know the MTU currently in use by 34744961713Sgirish * the physical MAC port. 34844961713Sgirish */ 34944961713Sgirish nxge_lb_t lb_mode; 35044961713Sgirish uint32_t qos_mode; 35144961713Sgirish uint32_t trunk_mode; 35244961713Sgirish uint32_t poll_mode; 35344961713Sgirish 35444961713Sgirish /* 35544961713Sgirish * Tx Statistics. 35644961713Sgirish */ 35744961713Sgirish uint32_t tx_inits; 35844961713Sgirish uint32_t tx_starts; 35944961713Sgirish uint32_t tx_nocanput; 36044961713Sgirish uint32_t tx_msgdup_fail; 36144961713Sgirish uint32_t tx_allocb_fail; 36244961713Sgirish uint32_t tx_no_desc; 36344961713Sgirish uint32_t tx_dma_bind_fail; 36444961713Sgirish uint32_t tx_uflo; 36544961713Sgirish uint32_t tx_hdr_pkts; 36644961713Sgirish uint32_t tx_ddi_pkts; 36744961713Sgirish uint32_t tx_dvma_pkts; 36844961713Sgirish 36944961713Sgirish uint32_t tx_max_pend; 37044961713Sgirish 37144961713Sgirish /* 37244961713Sgirish * Rx Statistics. 37344961713Sgirish */ 37444961713Sgirish uint32_t rx_inits; 37544961713Sgirish uint32_t rx_hdr_pkts; 37644961713Sgirish uint32_t rx_mtu_pkts; 37744961713Sgirish uint32_t rx_split_pkts; 37844961713Sgirish uint32_t rx_no_buf; 37944961713Sgirish uint32_t rx_no_comp_wb; 38044961713Sgirish uint32_t rx_ov_flow; 38144961713Sgirish uint32_t rx_len_mm; 38244961713Sgirish uint32_t rx_tag_err; 38344961713Sgirish uint32_t rx_nocanput; 38444961713Sgirish uint32_t rx_msgdup_fail; 38544961713Sgirish uint32_t rx_allocb_fail; 38644961713Sgirish 38744961713Sgirish /* 38844961713Sgirish * Receive buffer management statistics. 38944961713Sgirish */ 39044961713Sgirish uint32_t rx_new_pages; 39144961713Sgirish uint32_t rx_new_hdr_pgs; 39244961713Sgirish uint32_t rx_new_mtu_pgs; 39344961713Sgirish uint32_t rx_new_nxt_pgs; 39444961713Sgirish uint32_t rx_reused_pgs; 39544961713Sgirish uint32_t rx_hdr_drops; 39644961713Sgirish uint32_t rx_mtu_drops; 39744961713Sgirish uint32_t rx_nxt_drops; 39844961713Sgirish 39944961713Sgirish /* 40044961713Sgirish * Receive flow statistics 40144961713Sgirish */ 40244961713Sgirish uint32_t rx_rel_flow; 40344961713Sgirish uint32_t rx_rel_bit; 40444961713Sgirish 40544961713Sgirish uint32_t rx_pkts_dropped; 40644961713Sgirish 40744961713Sgirish /* 40844961713Sgirish * PCI-E Bus Statistics. 40944961713Sgirish */ 41044961713Sgirish uint32_t pci_bus_speed; 41144961713Sgirish uint32_t pci_err; 41244961713Sgirish uint32_t pci_rta_err; 41344961713Sgirish uint32_t pci_rma_err; 41444961713Sgirish uint32_t pci_parity_err; 41544961713Sgirish uint32_t pci_bad_ack_err; 41644961713Sgirish uint32_t pci_drto_err; 41744961713Sgirish uint32_t pci_dmawz_err; 41844961713Sgirish uint32_t pci_dmarz_err; 41944961713Sgirish 42044961713Sgirish uint32_t rx_taskq_waits; 42144961713Sgirish 42244961713Sgirish uint32_t tx_jumbo_pkts; 42344961713Sgirish 42444961713Sgirish /* 42544961713Sgirish * Some statistics added to support bringup, these 42644961713Sgirish * should be removed. 42744961713Sgirish */ 42844961713Sgirish uint32_t user_defined; 42944961713Sgirish } nxge_port_stats_t, *p_nxge_port_stats_t; 43044961713Sgirish 43144961713Sgirish 43244961713Sgirish typedef struct _nxge_stats_t { 43344961713Sgirish /* 43444961713Sgirish * Overall structure size 43544961713Sgirish */ 43644961713Sgirish size_t stats_size; 43744961713Sgirish 43844961713Sgirish kstat_t *ksp; 43944961713Sgirish kstat_t *rdc_ksp[NXGE_MAX_RDCS]; 44044961713Sgirish kstat_t *tdc_ksp[NXGE_MAX_TDCS]; 44144961713Sgirish kstat_t *rdc_sys_ksp; 44244961713Sgirish kstat_t *fflp_ksp[1]; 44344961713Sgirish kstat_t *ipp_ksp; 44444961713Sgirish kstat_t *txc_ksp; 44544961713Sgirish kstat_t *mac_ksp; 44644961713Sgirish kstat_t *zcp_ksp; 44744961713Sgirish kstat_t *port_ksp; 44844961713Sgirish kstat_t *mmac_ksp; 44944961713Sgirish 45044961713Sgirish nxge_mac_stats_t mac_stats; /* Common MAC Statistics */ 45144961713Sgirish nxge_xmac_stats_t xmac_stats; /* XMAC Statistics */ 45244961713Sgirish nxge_bmac_stats_t bmac_stats; /* BMAC Statistics */ 45344961713Sgirish 45444961713Sgirish nxge_rx_ring_stats_t rx_stats; /* per port RX stats */ 45544961713Sgirish nxge_ipp_stats_t ipp_stats; /* per port IPP stats */ 45644961713Sgirish nxge_zcp_stats_t zcp_stats; /* per port IPP stats */ 45744961713Sgirish nxge_rx_ring_stats_t rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */ 45844961713Sgirish nxge_rdc_sys_stats_t rdc_sys_stats; /* per port RDC stats */ 45944961713Sgirish 46044961713Sgirish nxge_tx_ring_stats_t tx_stats; /* per port TX stats */ 46144961713Sgirish nxge_txc_stats_t txc_stats; /* per port TX stats */ 46244961713Sgirish nxge_tx_ring_stats_t tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */ 46344961713Sgirish nxge_fflp_stats_t fflp_stats; /* fflp stats */ 46444961713Sgirish nxge_port_stats_t port_stats; /* fflp stats */ 46544961713Sgirish nxge_mmac_stats_t mmac_stats; /* Multi mac. stats */ 46644961713Sgirish 46744961713Sgirish } nxge_stats_t, *p_nxge_stats_t; 46844961713Sgirish 46944961713Sgirish 47044961713Sgirish 47144961713Sgirish typedef struct _nxge_intr_t { 47244961713Sgirish boolean_t intr_registered; /* interrupts are registered */ 47344961713Sgirish boolean_t intr_enabled; /* interrupts are enabled */ 47444961713Sgirish boolean_t niu_msi_enable; /* debug or configurable? */ 47544961713Sgirish uint8_t nldevs; /* # of logical devices */ 47644961713Sgirish int intr_types; /* interrupt types supported */ 47744961713Sgirish int intr_type; /* interrupt type to add */ 47844961713Sgirish int max_int_cnt; /* max MSIX/INT HW supports */ 47944961713Sgirish int start_inum; /* start inum (in sequence?) */ 48044961713Sgirish int msi_intx_cnt; /* # msi/intx ints returned */ 48144961713Sgirish int intr_added; /* # ints actually needed */ 48244961713Sgirish int intr_cap; /* interrupt capabilities */ 48344961713Sgirish size_t intr_size; /* size of array to allocate */ 48444961713Sgirish ddi_intr_handle_t *htable; /* For array of interrupts */ 48544961713Sgirish /* Add interrupt number for each interrupt vector */ 48644961713Sgirish int pri; 48744961713Sgirish } nxge_intr_t, *p_nxge_intr_t; 48844961713Sgirish 48944961713Sgirish typedef struct _nxge_ldgv_t { 49044961713Sgirish uint8_t ndma_ldvs; 49144961713Sgirish uint8_t nldvs; 49244961713Sgirish uint8_t start_ldg; 49344961713Sgirish uint8_t start_ldg_tx; 49444961713Sgirish uint8_t start_ldg_rx; 49544961713Sgirish uint8_t maxldgs; 49644961713Sgirish uint8_t maxldvs; 49744961713Sgirish uint8_t ldg_intrs; 49844961713Sgirish boolean_t own_sys_err; 49944961713Sgirish boolean_t own_max_ldv; 50044961713Sgirish uint32_t tmres; 50144961713Sgirish p_nxge_ldg_t ldgp; 50244961713Sgirish p_nxge_ldv_t ldvp; 50344961713Sgirish p_nxge_ldv_t ldvp_syserr; 50444961713Sgirish } nxge_ldgv_t, *p_nxge_ldgv_t; 50544961713Sgirish 50644961713Sgirish /* 50744961713Sgirish * Neptune Device instance state information. 50844961713Sgirish * 50944961713Sgirish * Each instance is dynamically allocated on first attach. 51044961713Sgirish */ 51144961713Sgirish struct _nxge_t { 51244961713Sgirish dev_info_t *dip; /* device instance */ 51344961713Sgirish dev_info_t *p_dip; /* Parent's device instance */ 51444961713Sgirish int instance; /* instance number */ 51544961713Sgirish int function_num; /* device function number */ 51644961713Sgirish int nports; /* # of ports on this device */ 51744961713Sgirish int board_ver; /* Board Version */ 51844961713Sgirish int partition_id; /* partition ID */ 51944961713Sgirish int use_partition; /* partition is enabled */ 52044961713Sgirish uint32_t drv_state; /* driver state bit flags */ 52144961713Sgirish uint64_t nxge_debug_level; /* driver state bit flags */ 52244961713Sgirish kmutex_t genlock[1]; 52344961713Sgirish enum nxge_mac_state nxge_mac_state; 52444961713Sgirish ddi_softintr_t resched_id; /* reschedule callback */ 52544961713Sgirish boolean_t resched_needed; 52644961713Sgirish boolean_t resched_running; 52744961713Sgirish 52844961713Sgirish p_dev_regs_t dev_regs; 52944961713Sgirish npi_handle_t npi_handle; 53044961713Sgirish npi_handle_t npi_pci_handle; 53144961713Sgirish npi_handle_t npi_reg_handle; 53244961713Sgirish npi_handle_t npi_msi_handle; 53344961713Sgirish npi_handle_t npi_vreg_handle; 53444961713Sgirish npi_handle_t npi_v2reg_handle; 53544961713Sgirish 53644961713Sgirish nxge_mac_t mac; 53744961713Sgirish nxge_ipp_t ipp; 53844961713Sgirish nxge_txc_t txc; 53944961713Sgirish nxge_classify_t classifier; 54044961713Sgirish 54114ea4bb7Ssd mac_handle_t mach; /* mac module handle */ 54244961713Sgirish p_nxge_stats_t statsp; 54344961713Sgirish uint32_t param_count; 54444961713Sgirish p_nxge_param_t param_arr; 54544961713Sgirish nxge_hw_list_t *nxge_hw_p; /* pointer to per Neptune */ 54644961713Sgirish niu_type_t niu_type; 54744961713Sgirish boolean_t os_addr_mode32; /* set to 1 for 32 bit mode */ 54844961713Sgirish uint8_t nrdc; 54944961713Sgirish uint8_t def_rdc; 55044961713Sgirish uint8_t rdc[NXGE_MAX_RDCS]; 55144961713Sgirish uint8_t ntdc; 55244961713Sgirish uint8_t tdc[NXGE_MAX_TDCS]; 55344961713Sgirish 55444961713Sgirish nxge_intr_t nxge_intr_type; 55544961713Sgirish nxge_dma_pt_cfg_t pt_config; 55644961713Sgirish nxge_class_pt_cfg_t class_config; 55744961713Sgirish 55844961713Sgirish /* Logical device and group data structures. */ 55944961713Sgirish p_nxge_ldgv_t ldgvp; 56044961713Sgirish 56156d930aeSspeer npi_vpd_info_t vpd_info; 56244961713Sgirish caddr_t param_list; /* Parameter list */ 56344961713Sgirish 56444961713Sgirish ether_addr_st factaddr; /* factory mac address */ 56544961713Sgirish ether_addr_st ouraddr; /* individual address */ 56644961713Sgirish kmutex_t ouraddr_lock; /* lock to protect to uradd */ 56744961713Sgirish 56844961713Sgirish ddi_iblock_cookie_t interrupt_cookie; 56944961713Sgirish 57044961713Sgirish /* 57144961713Sgirish * Blocks of memory may be pre-allocated by the 57244961713Sgirish * partition manager or the driver. They may include 57344961713Sgirish * blocks for configuration and buffers. The idea is 57444961713Sgirish * to preallocate big blocks of contiguous areas in 57544961713Sgirish * system memory (i.e. with IOMMU). These blocks then 57644961713Sgirish * will be broken up to a fixed number of blocks with 57744961713Sgirish * each block having the same block size (4K, 8K, 16K or 57844961713Sgirish * 32K) in the case of buffer blocks. For systems that 57944961713Sgirish * do not support DVMA, more than one big block will be 58044961713Sgirish * allocated. 58144961713Sgirish */ 58244961713Sgirish uint32_t rx_default_block_size; 58344961713Sgirish nxge_rx_block_size_t rx_bksize_code; 58444961713Sgirish 58544961713Sgirish p_nxge_dma_pool_t rx_buf_pool_p; 58644961713Sgirish p_nxge_dma_pool_t rx_cntl_pool_p; 58744961713Sgirish 58844961713Sgirish p_nxge_dma_pool_t tx_buf_pool_p; 58944961713Sgirish p_nxge_dma_pool_t tx_cntl_pool_p; 59044961713Sgirish 59144961713Sgirish /* Receive buffer block ring and completion ring. */ 59244961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 59344961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 59444961713Sgirish p_rx_mbox_areas_t rx_mbox_areas_p; 59544961713Sgirish 59644961713Sgirish p_rx_tx_params_t rx_params; 59744961713Sgirish uint32_t start_rdc; 59844961713Sgirish uint32_t max_rdcs; 59944961713Sgirish uint32_t rdc_mask; 60044961713Sgirish 60144961713Sgirish /* Transmit descriptors rings */ 60244961713Sgirish p_tx_rings_t tx_rings; 60344961713Sgirish p_tx_mbox_areas_t tx_mbox_areas_p; 60444961713Sgirish 60544961713Sgirish uint32_t start_tdc; 60644961713Sgirish uint32_t max_tdcs; 60744961713Sgirish uint32_t tdc_mask; 60844961713Sgirish 60944961713Sgirish p_rx_tx_params_t tx_params; 61044961713Sgirish 61144961713Sgirish ddi_dma_handle_t dmasparehandle; 61244961713Sgirish 61344961713Sgirish ulong_t sys_page_sz; 61444961713Sgirish ulong_t sys_page_mask; 61544961713Sgirish int suspended; 61644961713Sgirish 61744961713Sgirish mii_bmsr_t bmsr; /* xcvr status at last poll. */ 61844961713Sgirish mii_bmsr_t soft_bmsr; /* xcvr status kept by SW. */ 61944961713Sgirish 62044961713Sgirish kmutex_t mif_lock; /* Lock to protect the list. */ 62144961713Sgirish 62244961713Sgirish void (*mii_read)(); 62344961713Sgirish void (*mii_write)(); 62444961713Sgirish void (*mii_poll)(); 62544961713Sgirish filter_t filter; /* Current instance filter */ 62644961713Sgirish p_hash_filter_t hash_filter; /* Multicast hash filter. */ 62744961713Sgirish krwlock_t filter_lock; /* Lock to protect filters. */ 62844961713Sgirish 62944961713Sgirish ulong_t sys_burst_sz; 63044961713Sgirish 63144961713Sgirish uint8_t cache_line; 63244961713Sgirish 63344961713Sgirish timeout_id_t nxge_link_poll_timerid; 63444961713Sgirish timeout_id_t nxge_timerid; 63544961713Sgirish 63644961713Sgirish uint_t need_periodic_reclaim; 63744961713Sgirish timeout_id_t reclaim_timer; 63844961713Sgirish 63944961713Sgirish uint8_t msg_min; 64044961713Sgirish uint8_t crc_size; 64144961713Sgirish 64244961713Sgirish boolean_t hard_props_read; 64344961713Sgirish 64444961713Sgirish boolean_t nxge_htraffic; 64544961713Sgirish uint32_t nxge_ncpus; 64644961713Sgirish uint32_t nxge_cpumask; 64714ea4bb7Ssd uint16_t intr_timeout; 64814ea4bb7Ssd uint16_t intr_threshold; 64944961713Sgirish uchar_t nxge_rxmode; 65044961713Sgirish uint32_t active_threads; 65144961713Sgirish 65244961713Sgirish rtrace_t rtrace; 65344961713Sgirish int fm_capabilities; /* FMA capabilities */ 65444961713Sgirish 65544961713Sgirish uint32_t nxge_port_rbr_size; 65644961713Sgirish uint32_t nxge_port_rcr_size; 65744961713Sgirish uint32_t nxge_port_tx_ring_size; 65844961713Sgirish nxge_mmac_t nxge_mmac_info; 65944961713Sgirish #if defined(sun4v) 66044961713Sgirish boolean_t niu_hsvc_available; 66144961713Sgirish hsvc_info_t niu_hsvc; 66244961713Sgirish uint64_t niu_min_ver; 66344961713Sgirish #endif 664a3c5bd6dSspeer boolean_t link_notify; 665*98ecde52Stm 666*98ecde52Stm kmutex_t poll_lock; 667*98ecde52Stm kcondvar_t poll_cv; 668*98ecde52Stm link_mon_enable_t poll_state; 669*98ecde52Stm #define NXGE_MAGIC 0x3ab434e3 670*98ecde52Stm uint32_t nxge_magic; 67144961713Sgirish }; 67244961713Sgirish 67344961713Sgirish /* 67444961713Sgirish * Driver state flags. 67544961713Sgirish */ 67644961713Sgirish #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 67744961713Sgirish #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 67844961713Sgirish #define STATE_NODE_CREATED 0x000000004 /* device node created */ 67944961713Sgirish #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 68044961713Sgirish #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 68144961713Sgirish #define STATE_MDIO_LOCK_INIT 0x000000020 /* mdio lock initialized */ 68244961713Sgirish #define STATE_MII_LOCK_INIT 0x000000040 /* mii lock initialized */ 68344961713Sgirish 68444961713Sgirish #define STOP_POLL_THRESH 9 68544961713Sgirish #define START_POLL_THRESH 2 68644961713Sgirish 68744961713Sgirish typedef struct _nxge_port_kstat_t { 68844961713Sgirish /* 68944961713Sgirish * Transciever state informations. 69044961713Sgirish */ 69144961713Sgirish kstat_named_t xcvr_inits; 69244961713Sgirish kstat_named_t xcvr_inuse; 69344961713Sgirish kstat_named_t xcvr_addr; 69444961713Sgirish kstat_named_t xcvr_id; 69544961713Sgirish kstat_named_t cap_autoneg; 69644961713Sgirish kstat_named_t cap_10gfdx; 69744961713Sgirish kstat_named_t cap_10ghdx; 69844961713Sgirish kstat_named_t cap_1000fdx; 69944961713Sgirish kstat_named_t cap_1000hdx; 70044961713Sgirish kstat_named_t cap_100T4; 70144961713Sgirish kstat_named_t cap_100fdx; 70244961713Sgirish kstat_named_t cap_100hdx; 70344961713Sgirish kstat_named_t cap_10fdx; 70444961713Sgirish kstat_named_t cap_10hdx; 70544961713Sgirish kstat_named_t cap_asmpause; 70644961713Sgirish kstat_named_t cap_pause; 70744961713Sgirish 70844961713Sgirish /* 70944961713Sgirish * Link partner capabilities. 71044961713Sgirish */ 71144961713Sgirish kstat_named_t lp_cap_autoneg; 71244961713Sgirish kstat_named_t lp_cap_10gfdx; 71344961713Sgirish kstat_named_t lp_cap_10ghdx; 71444961713Sgirish kstat_named_t lp_cap_1000fdx; 71544961713Sgirish kstat_named_t lp_cap_1000hdx; 71644961713Sgirish kstat_named_t lp_cap_100T4; 71744961713Sgirish kstat_named_t lp_cap_100fdx; 71844961713Sgirish kstat_named_t lp_cap_100hdx; 71944961713Sgirish kstat_named_t lp_cap_10fdx; 72044961713Sgirish kstat_named_t lp_cap_10hdx; 72144961713Sgirish kstat_named_t lp_cap_asmpause; 72244961713Sgirish kstat_named_t lp_cap_pause; 72344961713Sgirish 72444961713Sgirish /* 72544961713Sgirish * Shared link setup. 72644961713Sgirish */ 72744961713Sgirish kstat_named_t link_T4; 72844961713Sgirish kstat_named_t link_speed; 72944961713Sgirish kstat_named_t link_duplex; 73044961713Sgirish kstat_named_t link_asmpause; 73144961713Sgirish kstat_named_t link_pause; 73244961713Sgirish kstat_named_t link_up; 73344961713Sgirish 73444961713Sgirish /* 73544961713Sgirish * Lets the user know the MTU currently in use by 73644961713Sgirish * the physical MAC port. 73744961713Sgirish */ 73844961713Sgirish kstat_named_t mac_mtu; 73944961713Sgirish kstat_named_t lb_mode; 74044961713Sgirish kstat_named_t qos_mode; 74144961713Sgirish kstat_named_t trunk_mode; 74244961713Sgirish 74344961713Sgirish /* 74444961713Sgirish * Misc MAC statistics. 74544961713Sgirish */ 74644961713Sgirish kstat_named_t ifspeed; 74744961713Sgirish kstat_named_t promisc; 74844961713Sgirish kstat_named_t rev_id; 74944961713Sgirish 75044961713Sgirish /* 75144961713Sgirish * Some statistics added to support bringup, these 75244961713Sgirish * should be removed. 75344961713Sgirish */ 75444961713Sgirish kstat_named_t user_defined; 75544961713Sgirish } nxge_port_kstat_t, *p_nxge_port_kstat_t; 75644961713Sgirish 75744961713Sgirish typedef struct _nxge_rdc_kstat { 75844961713Sgirish /* 75944961713Sgirish * Receive DMA channel statistics. 76044961713Sgirish */ 76144961713Sgirish kstat_named_t ipackets; 76244961713Sgirish kstat_named_t rbytes; 76344961713Sgirish kstat_named_t errors; 76444961713Sgirish kstat_named_t dcf_err; 76544961713Sgirish kstat_named_t rcr_ack_err; 76644961713Sgirish 76744961713Sgirish kstat_named_t dc_fifoflow_err; 76844961713Sgirish kstat_named_t rcr_sha_par_err; 76944961713Sgirish kstat_named_t rbr_pre_par_err; 77044961713Sgirish kstat_named_t wred_drop; 77144961713Sgirish kstat_named_t rbr_pre_emty; 77244961713Sgirish 77344961713Sgirish kstat_named_t rcr_shadow_full; 77444961713Sgirish kstat_named_t rbr_tmout; 77544961713Sgirish kstat_named_t rsp_cnt_err; 77644961713Sgirish kstat_named_t byte_en_bus; 77744961713Sgirish kstat_named_t rsp_dat_err; 77844961713Sgirish 77944961713Sgirish kstat_named_t compl_l2_err; 78044961713Sgirish kstat_named_t compl_l4_cksum_err; 78144961713Sgirish kstat_named_t compl_zcp_soft_err; 78244961713Sgirish kstat_named_t compl_fflp_soft_err; 78344961713Sgirish kstat_named_t config_err; 78444961713Sgirish 78544961713Sgirish kstat_named_t rcrincon; 78644961713Sgirish kstat_named_t rcrfull; 78744961713Sgirish kstat_named_t rbr_empty; 78844961713Sgirish kstat_named_t rbrfull; 78944961713Sgirish kstat_named_t rbrlogpage; 79044961713Sgirish 79144961713Sgirish kstat_named_t cfiglogpage; 79244961713Sgirish kstat_named_t port_drop_pkt; 79344961713Sgirish kstat_named_t rcr_to; 79444961713Sgirish kstat_named_t rcr_thresh; 79544961713Sgirish kstat_named_t rcr_mex; 79644961713Sgirish kstat_named_t id_mismatch; 79744961713Sgirish kstat_named_t zcp_eop_err; 79844961713Sgirish kstat_named_t ipp_eop_err; 79944961713Sgirish } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t; 80044961713Sgirish 80144961713Sgirish typedef struct _nxge_rdc_sys_kstat { 80244961713Sgirish /* 80344961713Sgirish * Receive DMA system statistics. 80444961713Sgirish */ 80544961713Sgirish kstat_named_t pre_par; 80644961713Sgirish kstat_named_t sha_par; 80744961713Sgirish kstat_named_t id_mismatch; 80844961713Sgirish kstat_named_t ipp_eop_err; 80944961713Sgirish kstat_named_t zcp_eop_err; 81044961713Sgirish } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t; 81144961713Sgirish 81244961713Sgirish typedef struct _nxge_tdc_kstat { 81344961713Sgirish /* 81444961713Sgirish * Transmit DMA channel statistics. 81544961713Sgirish */ 81644961713Sgirish kstat_named_t opackets; 81744961713Sgirish kstat_named_t obytes; 81844961713Sgirish kstat_named_t oerrors; 81944961713Sgirish kstat_named_t tx_inits; 82044961713Sgirish kstat_named_t tx_no_buf; 82144961713Sgirish 82244961713Sgirish kstat_named_t mbox_err; 82344961713Sgirish kstat_named_t pkt_size_err; 82444961713Sgirish kstat_named_t tx_ring_oflow; 82544961713Sgirish kstat_named_t pref_buf_ecc_err; 82644961713Sgirish kstat_named_t nack_pref; 82744961713Sgirish kstat_named_t nack_pkt_rd; 82844961713Sgirish kstat_named_t conf_part_err; 82944961713Sgirish kstat_named_t pkt_prt_err; 83044961713Sgirish kstat_named_t reset_fail; 83144961713Sgirish /* used to in the common (per port) counter */ 83244961713Sgirish 83344961713Sgirish kstat_named_t tx_starts; 83444961713Sgirish kstat_named_t tx_nocanput; 83544961713Sgirish kstat_named_t tx_msgdup_fail; 83644961713Sgirish kstat_named_t tx_allocb_fail; 83744961713Sgirish kstat_named_t tx_no_desc; 83844961713Sgirish kstat_named_t tx_dma_bind_fail; 83944961713Sgirish kstat_named_t tx_uflo; 84044961713Sgirish kstat_named_t tx_hdr_pkts; 84144961713Sgirish kstat_named_t tx_ddi_pkts; 84244961713Sgirish kstat_named_t tx_dvma_pkts; 84344961713Sgirish kstat_named_t tx_max_pend; 84444961713Sgirish } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t; 84544961713Sgirish 84644961713Sgirish typedef struct _nxge_txc_kstat { 84744961713Sgirish /* 84844961713Sgirish * Transmit port TXC block statistics. 84944961713Sgirish */ 85044961713Sgirish kstat_named_t pkt_stuffed; 85144961713Sgirish kstat_named_t pkt_xmit; 85244961713Sgirish kstat_named_t ro_correct_err; 85344961713Sgirish kstat_named_t ro_uncorrect_err; 85444961713Sgirish kstat_named_t sf_correct_err; 85544961713Sgirish kstat_named_t sf_uncorrect_err; 85644961713Sgirish kstat_named_t address_failed; 85744961713Sgirish kstat_named_t dma_failed; 85844961713Sgirish kstat_named_t length_failed; 85944961713Sgirish kstat_named_t pkt_assy_dead; 86044961713Sgirish kstat_named_t reorder_err; 86144961713Sgirish } nxge_txc_kstat_t, *p_nxge_txc_kstat_t; 86244961713Sgirish 86344961713Sgirish typedef struct _nxge_ipp_kstat { 86444961713Sgirish /* 86544961713Sgirish * Receive port IPP block statistics. 86644961713Sgirish */ 86744961713Sgirish kstat_named_t eop_miss; 86844961713Sgirish kstat_named_t sop_miss; 86944961713Sgirish kstat_named_t dfifo_ue; 87044961713Sgirish kstat_named_t ecc_err_cnt; 871846a903dSml kstat_named_t pfifo_perr; 87244961713Sgirish kstat_named_t pfifo_over; 87344961713Sgirish kstat_named_t pfifo_und; 87444961713Sgirish kstat_named_t bad_cs_cnt; 87544961713Sgirish kstat_named_t pkt_dis_cnt; 87644961713Sgirish } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t; 87744961713Sgirish 87844961713Sgirish typedef struct _nxge_zcp_kstat { 87944961713Sgirish /* 88044961713Sgirish * ZCP statistics. 88144961713Sgirish */ 88244961713Sgirish kstat_named_t errors; 88344961713Sgirish kstat_named_t inits; 88444961713Sgirish kstat_named_t rrfifo_underrun; 88544961713Sgirish kstat_named_t rrfifo_overrun; 88644961713Sgirish kstat_named_t rspfifo_uncorr_err; 88744961713Sgirish kstat_named_t buffer_overflow; 88844961713Sgirish kstat_named_t stat_tbl_perr; 88944961713Sgirish kstat_named_t dyn_tbl_perr; 89044961713Sgirish kstat_named_t buf_tbl_perr; 89144961713Sgirish kstat_named_t tt_program_err; 89244961713Sgirish kstat_named_t rsp_tt_index_err; 89344961713Sgirish kstat_named_t slv_tt_index_err; 89444961713Sgirish kstat_named_t zcp_tt_index_err; 89544961713Sgirish kstat_named_t access_fail; 89644961713Sgirish kstat_named_t cfifo_ecc; 89744961713Sgirish } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t; 89844961713Sgirish 89944961713Sgirish typedef struct _nxge_mac_kstat { 90044961713Sgirish /* 90144961713Sgirish * Transmit MAC statistics. 90244961713Sgirish */ 90344961713Sgirish kstat_named_t tx_frame_cnt; 90444961713Sgirish kstat_named_t tx_underflow_err; 90544961713Sgirish kstat_named_t tx_overflow_err; 90644961713Sgirish kstat_named_t tx_maxpktsize_err; 90744961713Sgirish kstat_named_t tx_fifo_xfr_err; 90844961713Sgirish kstat_named_t tx_byte_cnt; 90944961713Sgirish 91044961713Sgirish /* 91144961713Sgirish * Receive MAC statistics. 91244961713Sgirish */ 91344961713Sgirish kstat_named_t rx_frame_cnt; 91444961713Sgirish kstat_named_t rx_underflow_err; 91544961713Sgirish kstat_named_t rx_overflow_err; 91644961713Sgirish kstat_named_t rx_len_err_cnt; 91744961713Sgirish kstat_named_t rx_crc_err_cnt; 91844961713Sgirish kstat_named_t rx_viol_err_cnt; 91944961713Sgirish kstat_named_t rx_byte_cnt; 92044961713Sgirish kstat_named_t rx_hist1_cnt; 92144961713Sgirish kstat_named_t rx_hist2_cnt; 92244961713Sgirish kstat_named_t rx_hist3_cnt; 92344961713Sgirish kstat_named_t rx_hist4_cnt; 92444961713Sgirish kstat_named_t rx_hist5_cnt; 92544961713Sgirish kstat_named_t rx_hist6_cnt; 92644961713Sgirish kstat_named_t rx_broadcast_cnt; 92744961713Sgirish kstat_named_t rx_mult_cnt; 92844961713Sgirish kstat_named_t rx_frag_cnt; 92944961713Sgirish kstat_named_t rx_frame_align_err_cnt; 93044961713Sgirish kstat_named_t rx_linkfault_err_cnt; 93144961713Sgirish kstat_named_t rx_local_fault_err_cnt; 93244961713Sgirish kstat_named_t rx_remote_fault_err_cnt; 93344961713Sgirish } nxge_mac_kstat_t, *p_nxge_mac_kstat_t; 93444961713Sgirish 93544961713Sgirish typedef struct _nxge_xmac_kstat { 93644961713Sgirish /* 93744961713Sgirish * XMAC statistics. 93844961713Sgirish */ 93944961713Sgirish kstat_named_t tx_frame_cnt; 94044961713Sgirish kstat_named_t tx_underflow_err; 94144961713Sgirish kstat_named_t tx_maxpktsize_err; 94244961713Sgirish kstat_named_t tx_overflow_err; 94344961713Sgirish kstat_named_t tx_fifo_xfr_err; 94444961713Sgirish kstat_named_t tx_byte_cnt; 94544961713Sgirish kstat_named_t rx_frame_cnt; 94644961713Sgirish kstat_named_t rx_underflow_err; 94744961713Sgirish kstat_named_t rx_overflow_err; 94844961713Sgirish kstat_named_t rx_crc_err_cnt; 94944961713Sgirish kstat_named_t rx_len_err_cnt; 95044961713Sgirish kstat_named_t rx_viol_err_cnt; 95144961713Sgirish kstat_named_t rx_byte_cnt; 95244961713Sgirish kstat_named_t rx_hist1_cnt; 95344961713Sgirish kstat_named_t rx_hist2_cnt; 95444961713Sgirish kstat_named_t rx_hist3_cnt; 95544961713Sgirish kstat_named_t rx_hist4_cnt; 95644961713Sgirish kstat_named_t rx_hist5_cnt; 95744961713Sgirish kstat_named_t rx_hist6_cnt; 95844961713Sgirish kstat_named_t rx_hist7_cnt; 95944961713Sgirish kstat_named_t rx_broadcast_cnt; 96044961713Sgirish kstat_named_t rx_mult_cnt; 96144961713Sgirish kstat_named_t rx_frag_cnt; 96244961713Sgirish kstat_named_t rx_frame_align_err_cnt; 96344961713Sgirish kstat_named_t rx_linkfault_err_cnt; 96444961713Sgirish kstat_named_t rx_remote_fault_err_cnt; 96544961713Sgirish kstat_named_t rx_local_fault_err_cnt; 96644961713Sgirish kstat_named_t rx_pause_cnt; 96744961713Sgirish kstat_named_t xpcs_deskew_err_cnt; 96844961713Sgirish kstat_named_t xpcs_ln0_symbol_err_cnt; 96944961713Sgirish kstat_named_t xpcs_ln1_symbol_err_cnt; 97044961713Sgirish kstat_named_t xpcs_ln2_symbol_err_cnt; 97144961713Sgirish kstat_named_t xpcs_ln3_symbol_err_cnt; 97244961713Sgirish } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t; 97344961713Sgirish 97444961713Sgirish typedef struct _nxge_bmac_kstat { 97544961713Sgirish /* 97644961713Sgirish * BMAC statistics. 97744961713Sgirish */ 97844961713Sgirish kstat_named_t tx_frame_cnt; 97944961713Sgirish kstat_named_t tx_underrun_err; 98044961713Sgirish kstat_named_t tx_max_pkt_err; 98144961713Sgirish kstat_named_t tx_byte_cnt; 98244961713Sgirish kstat_named_t rx_frame_cnt; 98344961713Sgirish kstat_named_t rx_byte_cnt; 98444961713Sgirish kstat_named_t rx_overflow_err; 98544961713Sgirish kstat_named_t rx_align_err_cnt; 98644961713Sgirish kstat_named_t rx_crc_err_cnt; 98744961713Sgirish kstat_named_t rx_len_err_cnt; 98844961713Sgirish kstat_named_t rx_viol_err_cnt; 98944961713Sgirish kstat_named_t rx_pause_cnt; 99044961713Sgirish kstat_named_t tx_pause_state; 99144961713Sgirish kstat_named_t tx_nopause_state; 99244961713Sgirish } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t; 99344961713Sgirish 99444961713Sgirish 99544961713Sgirish typedef struct _nxge_fflp_kstat { 99644961713Sgirish /* 99744961713Sgirish * FFLP statistics. 99844961713Sgirish */ 99944961713Sgirish 100044961713Sgirish kstat_named_t fflp_tcam_ecc_err; 100144961713Sgirish kstat_named_t fflp_tcam_perr; 100244961713Sgirish kstat_named_t fflp_vlan_perr; 100344961713Sgirish kstat_named_t fflp_hasht_lookup_err; 100444961713Sgirish kstat_named_t fflp_access_fail; 100544961713Sgirish kstat_named_t fflp_hasht_data_err[MAX_PARTITION]; 100644961713Sgirish } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t; 100744961713Sgirish 100844961713Sgirish typedef struct _nxge_mmac_kstat { 100944961713Sgirish kstat_named_t mmac_max_addr_cnt; 101044961713Sgirish kstat_named_t mmac_avail_addr_cnt; 101144961713Sgirish kstat_named_t mmac_addr1; 101244961713Sgirish kstat_named_t mmac_addr2; 101344961713Sgirish kstat_named_t mmac_addr3; 101444961713Sgirish kstat_named_t mmac_addr4; 101544961713Sgirish kstat_named_t mmac_addr5; 101644961713Sgirish kstat_named_t mmac_addr6; 101744961713Sgirish kstat_named_t mmac_addr7; 101844961713Sgirish kstat_named_t mmac_addr8; 101944961713Sgirish kstat_named_t mmac_addr9; 102044961713Sgirish kstat_named_t mmac_addr10; 102144961713Sgirish kstat_named_t mmac_addr11; 102244961713Sgirish kstat_named_t mmac_addr12; 102344961713Sgirish kstat_named_t mmac_addr13; 102444961713Sgirish kstat_named_t mmac_addr14; 102544961713Sgirish kstat_named_t mmac_addr15; 102644961713Sgirish kstat_named_t mmac_addr16; 102744961713Sgirish } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t; 102844961713Sgirish 102944961713Sgirish #endif /* _KERNEL */ 103044961713Sgirish 103144961713Sgirish /* 103244961713Sgirish * Prototype definitions. 103344961713Sgirish */ 103444961713Sgirish nxge_status_t nxge_init(p_nxge_t); 103544961713Sgirish void nxge_uninit(p_nxge_t); 103644961713Sgirish void nxge_get64(p_nxge_t, p_mblk_t); 103744961713Sgirish void nxge_put64(p_nxge_t, p_mblk_t); 103844961713Sgirish void nxge_pio_loop(p_nxge_t, p_mblk_t); 103944961713Sgirish 104044961713Sgirish #ifndef COSIM 104144961713Sgirish typedef void (*fptrv_t)(); 104244961713Sgirish timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int); 104344961713Sgirish void nxge_stop_timer(p_nxge_t, timeout_id_t); 104444961713Sgirish #endif 104544961713Sgirish #endif 104644961713Sgirish 104744961713Sgirish #ifdef __cplusplus 104844961713Sgirish } 104944961713Sgirish #endif 105044961713Sgirish 105144961713Sgirish #endif /* _SYS_NXGE_NXGE_H */ 1052