1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_H 27 #define _SYS_NXGE_NXGE_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if defined(_KERNEL) || defined(COSIM) 36 #include <nxge_mac.h> 37 #include <nxge_ipp.h> 38 #include <nxge_fflp.h> 39 #endif 40 41 /* 42 * NXGE diagnostics IOCTLS. 43 */ 44 #define NXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 45 46 #define NXGE_GET64 (NXGE_IOC|1) 47 #define NXGE_PUT64 (NXGE_IOC|2) 48 #define NXGE_GET_TX_RING_SZ (NXGE_IOC|3) 49 #define NXGE_GET_TX_DESC (NXGE_IOC|4) 50 #define NXGE_GLOBAL_RESET (NXGE_IOC|5) 51 #define NXGE_TX_SIDE_RESET (NXGE_IOC|6) 52 #define NXGE_RX_SIDE_RESET (NXGE_IOC|7) 53 #define NXGE_RESET_MAC (NXGE_IOC|8) 54 55 #define NXGE_GET_MII (NXGE_IOC|11) 56 #define NXGE_PUT_MII (NXGE_IOC|12) 57 #define NXGE_RTRACE (NXGE_IOC|13) 58 #define NXGE_RTRACE_TEST (NXGE_IOC|20) 59 #define NXGE_TX_REGS_DUMP (NXGE_IOC|21) 60 #define NXGE_RX_REGS_DUMP (NXGE_IOC|22) 61 #define NXGE_INT_REGS_DUMP (NXGE_IOC|23) 62 #define NXGE_VIR_REGS_DUMP (NXGE_IOC|24) 63 #define NXGE_VIR_INT_REGS_DUMP (NXGE_IOC|25) 64 #define NXGE_RDUMP (NXGE_IOC|26) 65 #define NXGE_RDC_GRPS_DUMP (NXGE_IOC|27) 66 #define NXGE_PIO_TEST (NXGE_IOC|28) 67 68 #define NXGE_GET_TCAM (NXGE_IOC|29) 69 #define NXGE_PUT_TCAM (NXGE_IOC|30) 70 #define NXGE_INJECT_ERR (NXGE_IOC|40) 71 72 #if (defined(SOLARIS) && defined(_KERNEL)) || defined(COSIM) 73 #define NXGE_OK 0 74 #define NXGE_ERROR 0x40000000 75 #define NXGE_DDI_FAILED 0x20000000 76 #define NXGE_GET_PORT_NUM(n) n 77 78 /* 79 * Definitions for module_info. 80 */ 81 #define NXGE_IDNUM (0) /* module ID number */ 82 #ifdef SAM_MODEL 83 #define NXGE_DRIVER_NAME "ce" /* module name */ 84 #else 85 #define NXGE_DRIVER_NAME "nxge" /* module name */ 86 #endif 87 88 #define NXGE_MINPSZ (0) /* min packet size */ 89 #define NXGE_MAXPSZ (ETHERMTU) /* max packet size */ 90 #define NXGE_HIWAT (2048 * NXGE_MAXPSZ) /* hi-water mark */ 91 #define NXGE_LOWAT (1) /* lo-water mark */ 92 #define NXGE_HIWAT_MAX (192000 * NXGE_MAXPSZ) 93 #define NXGE_HIWAT_MIN (2 * NXGE_MAXPSZ) 94 #define NXGE_LOWAT_MAX (192000 * NXGE_MAXPSZ) 95 #define NXGE_LOWAT_MIN (1) 96 97 #ifndef D_HOTPLUG 98 #define D_HOTPLUG 0x00 99 #endif 100 101 #define INIT_BUCKET_SIZE 16 /* Initial Hash Bucket Size */ 102 103 #define NXGE_CHECK_TIMER (5000) 104 105 typedef enum { 106 param_instance, 107 param_main_instance, 108 param_function_number, 109 param_partition_id, 110 param_read_write_mode, 111 param_niu_cfg_type, 112 param_tx_quick_cfg, 113 param_rx_quick_cfg, 114 param_master_cfg_enable, 115 param_master_cfg_value, 116 117 param_autoneg, 118 param_anar_10gfdx, 119 param_anar_10ghdx, 120 param_anar_1000fdx, 121 param_anar_1000hdx, 122 param_anar_100T4, 123 param_anar_100fdx, 124 param_anar_100hdx, 125 param_anar_10fdx, 126 param_anar_10hdx, 127 128 param_anar_asmpause, 129 param_anar_pause, 130 param_use_int_xcvr, 131 param_enable_ipg0, 132 param_ipg0, 133 param_ipg1, 134 param_ipg2, 135 param_accept_jumbo, 136 param_txdma_weight, 137 param_txdma_channels_begin, 138 139 param_txdma_channels, 140 param_txdma_info, 141 param_rxdma_channels_begin, 142 param_rxdma_channels, 143 param_rxdma_drr_weight, 144 param_rxdma_full_header, 145 param_rxdma_info, 146 param_rxdma_rbr_size, 147 param_rxdma_rcr_size, 148 param_default_port_rdc, 149 param_rxdma_intr_time, 150 param_rxdma_intr_pkts, 151 152 param_rdc_grps_start, 153 param_rx_rdc_grps, 154 param_default_grp0_rdc, 155 param_default_grp1_rdc, 156 param_default_grp2_rdc, 157 param_default_grp3_rdc, 158 param_default_grp4_rdc, 159 param_default_grp5_rdc, 160 param_default_grp6_rdc, 161 param_default_grp7_rdc, 162 163 param_info_rdc_groups, 164 param_start_ldg, 165 param_max_ldg, 166 param_mac_2rdc_grp, 167 param_vlan_2rdc_grp, 168 param_fcram_part_cfg, 169 param_fcram_access_ratio, 170 param_tcam_access_ratio, 171 param_tcam_enable, 172 param_hash_lookup_enable, 173 param_llc_snap_enable, 174 175 param_h1_init_value, 176 param_h2_init_value, 177 param_class_cfg_ether_usr1, 178 param_class_cfg_ether_usr2, 179 param_class_cfg_ip_usr4, 180 param_class_cfg_ip_usr5, 181 param_class_cfg_ip_usr6, 182 param_class_cfg_ip_usr7, 183 param_class_opt_ip_usr4, 184 param_class_opt_ip_usr5, 185 param_class_opt_ip_usr6, 186 param_class_opt_ip_usr7, 187 param_class_opt_ipv4_tcp, 188 param_class_opt_ipv4_udp, 189 param_class_opt_ipv4_ah, 190 param_class_opt_ipv4_sctp, 191 param_class_opt_ipv6_tcp, 192 param_class_opt_ipv6_udp, 193 param_class_opt_ipv6_ah, 194 param_class_opt_ipv6_sctp, 195 param_nxge_debug_flag, 196 param_npi_debug_flag, 197 param_dump_rdc, 198 param_dump_tdc, 199 param_dump_mac_regs, 200 param_dump_ipp_regs, 201 param_dump_fflp_regs, 202 param_dump_vlan_table, 203 param_dump_rdc_table, 204 param_dump_ptrs, 205 param_end 206 } nxge_param_index_t; 207 208 209 /* 210 * Named Dispatch Parameter Management Structure 211 */ 212 213 214 typedef int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *); 215 typedef int (*nxge_ndsetf_t)(p_nxge_t, queue_t *, 216 MBLKP, char *, caddr_t, cred_t *); 217 218 #define NXGE_PARAM_READ 0x00000001ULL 219 #define NXGE_PARAM_WRITE 0x00000002ULL 220 #define NXGE_PARAM_SHARED 0x00000004ULL 221 #define NXGE_PARAM_PRIV 0x00000008ULL 222 #define NXGE_PARAM_RW NXGE_PARAM_READ | NXGE_PARAM_WRITE 223 #define NXGE_PARAM_RWS NXGE_PARAM_RW | NXGE_PARAM_SHARED 224 #define NXGE_PARAM_RWP NXGE_PARAM_RW | NXGE_PARAM_PRIV 225 226 #define NXGE_PARAM_RXDMA 0x00000010ULL 227 #define NXGE_PARAM_TXDMA 0x00000020ULL 228 #define NXGE_PARAM_CLASS_GEN 0x00000040ULL 229 #define NXGE_PARAM_MAC 0x00000080ULL 230 #define NXGE_PARAM_CLASS_BIN NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN 231 #define NXGE_PARAM_CLASS_HEX NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX 232 #define NXGE_PARAM_CLASS NXGE_PARAM_CLASS_HEX 233 234 #define NXGE_PARAM_CMPLX 0x00010000ULL 235 #define NXGE_PARAM_NDD_WR_OK 0x00020000ULL 236 #define NXGE_PARAM_INIT_ONLY 0x00040000ULL 237 #define NXGE_PARAM_INIT_CONFIG 0x00080000ULL 238 239 #define NXGE_PARAM_READ_PROP 0x00100000ULL 240 #define NXGE_PARAM_PROP_ARR32 0x00200000ULL 241 #define NXGE_PARAM_PROP_ARR64 0x00400000ULL 242 #define NXGE_PARAM_PROP_STR 0x00800000ULL 243 244 #define NXGE_PARAM_BASE_DEC 0x00000000ULL 245 #define NXGE_PARAM_BASE_BIN 0x10000000ULL 246 #define NXGE_PARAM_BASE_HEX 0x20000000ULL 247 #define NXGE_PARAM_BASE_STR 0x40000000ULL 248 #define NXGE_PARAM_DONT_SHOW 0x80000000ULL 249 250 #define NXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 251 #define NXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 252 #define NXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 253 #define NXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 254 255 typedef struct _nxge_param_t { 256 int (*getf)(); 257 int (*setf)(); /* null for read only */ 258 uint64_t type; /* R/W/ Common/Port/ .... */ 259 uint64_t minimum; 260 uint64_t maximum; 261 uint64_t value; /* for array params, pointer to value array */ 262 uint64_t old_value; /* for array params, pointer to old_value array */ 263 char *fcode_name; 264 char *name; 265 } nxge_param_t, *p_nxge_param_t; 266 267 268 269 typedef enum { 270 nxge_lb_normal, 271 nxge_lb_ext10g, 272 nxge_lb_ext1000, 273 nxge_lb_ext100, 274 nxge_lb_ext10, 275 nxge_lb_phy10g, 276 nxge_lb_phy1000, 277 nxge_lb_phy, 278 nxge_lb_serdes10g, 279 nxge_lb_serdes1000, 280 nxge_lb_serdes, 281 nxge_lb_mac10g, 282 nxge_lb_mac1000, 283 nxge_lb_mac 284 } nxge_lb_t; 285 286 enum nxge_mac_state { 287 NXGE_MAC_STOPPED = 0, 288 NXGE_MAC_STARTED 289 }; 290 291 /* 292 * Private DLPI full dlsap address format. 293 */ 294 typedef struct _nxge_dladdr_t { 295 ether_addr_st dl_phys; 296 uint16_t dl_sap; 297 } nxge_dladdr_t, *p_nxge_dladdr_t; 298 299 typedef struct _mc_addr_t { 300 ether_addr_st multcast_addr; 301 uint_t mc_addr_cnt; 302 } mc_addr_t, *p_mc_addr_t; 303 304 typedef struct _mc_bucket_t { 305 p_mc_addr_t addr_list; 306 uint_t list_size; 307 } mc_bucket_t, *p_mc_bucket_t; 308 309 typedef struct _mc_table_t { 310 p_mc_bucket_t bucket_list; 311 uint_t buckets_used; 312 } mc_table_t, *p_mc_table_t; 313 314 typedef struct _filter_t { 315 uint32_t all_phys_cnt; 316 uint32_t all_multicast_cnt; 317 uint32_t all_sap_cnt; 318 } filter_t, *p_filter_t; 319 320 #if defined(_KERNEL) || defined(COSIM) 321 322 323 typedef struct _nxge_port_stats_t { 324 /* 325 * Overall structure size 326 */ 327 size_t stats_size; 328 329 /* 330 * Link Input/Output stats 331 */ 332 uint64_t ipackets; 333 uint64_t ierrors; 334 uint64_t opackets; 335 uint64_t oerrors; 336 uint64_t collisions; 337 338 /* 339 * MIB II variables 340 */ 341 uint64_t rbytes; /* # bytes received */ 342 uint64_t obytes; /* # bytes transmitted */ 343 uint32_t multircv; /* # multicast packets received */ 344 uint32_t multixmt; /* # multicast packets for xmit */ 345 uint32_t brdcstrcv; /* # broadcast packets received */ 346 uint32_t brdcstxmt; /* # broadcast packets for xmit */ 347 uint32_t norcvbuf; /* # rcv packets discarded */ 348 uint32_t noxmtbuf; /* # xmit packets discarded */ 349 350 /* 351 * Lets the user know the MTU currently in use by 352 * the physical MAC port. 353 */ 354 nxge_lb_t lb_mode; 355 uint32_t qos_mode; 356 uint32_t trunk_mode; 357 uint32_t poll_mode; 358 359 /* 360 * Tx Statistics. 361 */ 362 uint32_t tx_inits; 363 uint32_t tx_starts; 364 uint32_t tx_nocanput; 365 uint32_t tx_msgdup_fail; 366 uint32_t tx_allocb_fail; 367 uint32_t tx_no_desc; 368 uint32_t tx_dma_bind_fail; 369 uint32_t tx_uflo; 370 uint32_t tx_hdr_pkts; 371 uint32_t tx_ddi_pkts; 372 uint32_t tx_dvma_pkts; 373 374 uint32_t tx_max_pend; 375 376 /* 377 * Rx Statistics. 378 */ 379 uint32_t rx_inits; 380 uint32_t rx_hdr_pkts; 381 uint32_t rx_mtu_pkts; 382 uint32_t rx_split_pkts; 383 uint32_t rx_no_buf; 384 uint32_t rx_no_comp_wb; 385 uint32_t rx_ov_flow; 386 uint32_t rx_len_mm; 387 uint32_t rx_tag_err; 388 uint32_t rx_nocanput; 389 uint32_t rx_msgdup_fail; 390 uint32_t rx_allocb_fail; 391 392 /* 393 * Receive buffer management statistics. 394 */ 395 uint32_t rx_new_pages; 396 uint32_t rx_new_hdr_pgs; 397 uint32_t rx_new_mtu_pgs; 398 uint32_t rx_new_nxt_pgs; 399 uint32_t rx_reused_pgs; 400 uint32_t rx_hdr_drops; 401 uint32_t rx_mtu_drops; 402 uint32_t rx_nxt_drops; 403 404 /* 405 * Receive flow statistics 406 */ 407 uint32_t rx_rel_flow; 408 uint32_t rx_rel_bit; 409 410 uint32_t rx_pkts_dropped; 411 412 /* 413 * PCI-E Bus Statistics. 414 */ 415 uint32_t pci_bus_speed; 416 uint32_t pci_err; 417 uint32_t pci_rta_err; 418 uint32_t pci_rma_err; 419 uint32_t pci_parity_err; 420 uint32_t pci_bad_ack_err; 421 uint32_t pci_drto_err; 422 uint32_t pci_dmawz_err; 423 uint32_t pci_dmarz_err; 424 425 uint32_t rx_taskq_waits; 426 427 uint32_t tx_jumbo_pkts; 428 429 /* 430 * Some statistics added to support bringup, these 431 * should be removed. 432 */ 433 uint32_t user_defined; 434 } nxge_port_stats_t, *p_nxge_port_stats_t; 435 436 437 typedef struct _nxge_stats_t { 438 /* 439 * Overall structure size 440 */ 441 size_t stats_size; 442 443 kstat_t *ksp; 444 kstat_t *rdc_ksp[NXGE_MAX_RDCS]; 445 kstat_t *tdc_ksp[NXGE_MAX_TDCS]; 446 kstat_t *rdc_sys_ksp; 447 kstat_t *fflp_ksp[1]; 448 kstat_t *ipp_ksp; 449 kstat_t *txc_ksp; 450 kstat_t *mac_ksp; 451 kstat_t *zcp_ksp; 452 kstat_t *port_ksp; 453 kstat_t *mmac_ksp; 454 455 nxge_mac_stats_t mac_stats; /* Common MAC Statistics */ 456 nxge_xmac_stats_t xmac_stats; /* XMAC Statistics */ 457 nxge_bmac_stats_t bmac_stats; /* BMAC Statistics */ 458 459 nxge_rx_ring_stats_t rx_stats; /* per port RX stats */ 460 nxge_ipp_stats_t ipp_stats; /* per port IPP stats */ 461 nxge_zcp_stats_t zcp_stats; /* per port IPP stats */ 462 nxge_rx_ring_stats_t rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */ 463 nxge_rdc_sys_stats_t rdc_sys_stats; /* per port RDC stats */ 464 465 nxge_tx_ring_stats_t tx_stats; /* per port TX stats */ 466 nxge_txc_stats_t txc_stats; /* per port TX stats */ 467 nxge_tx_ring_stats_t tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */ 468 nxge_fflp_stats_t fflp_stats; /* fflp stats */ 469 nxge_port_stats_t port_stats; /* fflp stats */ 470 nxge_mmac_stats_t mmac_stats; /* Multi mac. stats */ 471 472 } nxge_stats_t, *p_nxge_stats_t; 473 474 475 476 typedef struct _nxge_intr_t { 477 boolean_t intr_registered; /* interrupts are registered */ 478 boolean_t intr_enabled; /* interrupts are enabled */ 479 boolean_t niu_msi_enable; /* debug or configurable? */ 480 uint8_t nldevs; /* # of logical devices */ 481 int intr_types; /* interrupt types supported */ 482 int intr_type; /* interrupt type to add */ 483 int max_int_cnt; /* max MSIX/INT HW supports */ 484 int start_inum; /* start inum (in sequence?) */ 485 int msi_intx_cnt; /* # msi/intx ints returned */ 486 int intr_added; /* # ints actually needed */ 487 int intr_cap; /* interrupt capabilities */ 488 size_t intr_size; /* size of array to allocate */ 489 ddi_intr_handle_t *htable; /* For array of interrupts */ 490 /* Add interrupt number for each interrupt vector */ 491 int pri; 492 } nxge_intr_t, *p_nxge_intr_t; 493 494 typedef struct _nxge_ldgv_t { 495 uint8_t ndma_ldvs; 496 uint8_t nldvs; 497 uint8_t start_ldg; 498 uint8_t start_ldg_tx; 499 uint8_t start_ldg_rx; 500 uint8_t maxldgs; 501 uint8_t maxldvs; 502 uint8_t ldg_intrs; 503 boolean_t own_sys_err; 504 boolean_t own_max_ldv; 505 uint32_t tmres; 506 p_nxge_ldg_t ldgp; 507 p_nxge_ldv_t ldvp; 508 p_nxge_ldv_t ldvp_syserr; 509 } nxge_ldgv_t, *p_nxge_ldgv_t; 510 511 /* 512 * Neptune Device instance state information. 513 * 514 * Each instance is dynamically allocated on first attach. 515 */ 516 struct _nxge_t { 517 dev_info_t *dip; /* device instance */ 518 dev_info_t *p_dip; /* Parent's device instance */ 519 int instance; /* instance number */ 520 int function_num; /* device function number */ 521 int nports; /* # of ports on this device */ 522 int board_ver; /* Board Version */ 523 int partition_id; /* partition ID */ 524 int use_partition; /* partition is enabled */ 525 uint32_t drv_state; /* driver state bit flags */ 526 uint64_t nxge_debug_level; /* driver state bit flags */ 527 kmutex_t genlock[1]; 528 enum nxge_mac_state nxge_mac_state; 529 ddi_softintr_t resched_id; /* reschedule callback */ 530 boolean_t resched_needed; 531 boolean_t resched_running; 532 533 p_dev_regs_t dev_regs; 534 npi_handle_t npi_handle; 535 npi_handle_t npi_pci_handle; 536 npi_handle_t npi_reg_handle; 537 npi_handle_t npi_msi_handle; 538 npi_handle_t npi_vreg_handle; 539 npi_handle_t npi_v2reg_handle; 540 541 nxge_mac_t mac; 542 nxge_ipp_t ipp; 543 nxge_txc_t txc; 544 nxge_classify_t classifier; 545 546 mac_handle_t mach; /* mac module handle */ 547 p_nxge_stats_t statsp; 548 uint32_t param_count; 549 p_nxge_param_t param_arr; 550 nxge_hw_list_t *nxge_hw_p; /* pointer to per Neptune */ 551 niu_type_t niu_type; 552 boolean_t os_addr_mode32; /* set to 1 for 32 bit mode */ 553 uint8_t nrdc; 554 uint8_t def_rdc; 555 uint8_t rdc[NXGE_MAX_RDCS]; 556 uint8_t ntdc; 557 uint8_t tdc[NXGE_MAX_TDCS]; 558 559 nxge_intr_t nxge_intr_type; 560 nxge_dma_pt_cfg_t pt_config; 561 nxge_class_pt_cfg_t class_config; 562 563 /* Logical device and group data structures. */ 564 p_nxge_ldgv_t ldgvp; 565 566 caddr_t param_list; /* Parameter list */ 567 568 ether_addr_st factaddr; /* factory mac address */ 569 ether_addr_st ouraddr; /* individual address */ 570 kmutex_t ouraddr_lock; /* lock to protect to uradd */ 571 572 ddi_iblock_cookie_t interrupt_cookie; 573 574 /* 575 * Blocks of memory may be pre-allocated by the 576 * partition manager or the driver. They may include 577 * blocks for configuration and buffers. The idea is 578 * to preallocate big blocks of contiguous areas in 579 * system memory (i.e. with IOMMU). These blocks then 580 * will be broken up to a fixed number of blocks with 581 * each block having the same block size (4K, 8K, 16K or 582 * 32K) in the case of buffer blocks. For systems that 583 * do not support DVMA, more than one big block will be 584 * allocated. 585 */ 586 uint32_t rx_default_block_size; 587 nxge_rx_block_size_t rx_bksize_code; 588 589 p_nxge_dma_pool_t rx_buf_pool_p; 590 p_nxge_dma_pool_t rx_cntl_pool_p; 591 592 p_nxge_dma_pool_t tx_buf_pool_p; 593 p_nxge_dma_pool_t tx_cntl_pool_p; 594 595 /* Receive buffer block ring and completion ring. */ 596 p_rx_rbr_rings_t rx_rbr_rings; 597 p_rx_rcr_rings_t rx_rcr_rings; 598 p_rx_mbox_areas_t rx_mbox_areas_p; 599 600 p_rx_tx_params_t rx_params; 601 uint32_t start_rdc; 602 uint32_t max_rdcs; 603 uint32_t rdc_mask; 604 605 /* Transmit descriptors rings */ 606 p_tx_rings_t tx_rings; 607 p_tx_mbox_areas_t tx_mbox_areas_p; 608 609 uint32_t start_tdc; 610 uint32_t max_tdcs; 611 uint32_t tdc_mask; 612 613 p_rx_tx_params_t tx_params; 614 615 ddi_dma_handle_t dmasparehandle; 616 617 ulong_t sys_page_sz; 618 ulong_t sys_page_mask; 619 int suspended; 620 621 mii_bmsr_t bmsr; /* xcvr status at last poll. */ 622 mii_bmsr_t soft_bmsr; /* xcvr status kept by SW. */ 623 624 kmutex_t mif_lock; /* Lock to protect the list. */ 625 626 void (*mii_read)(); 627 void (*mii_write)(); 628 void (*mii_poll)(); 629 filter_t filter; /* Current instance filter */ 630 p_hash_filter_t hash_filter; /* Multicast hash filter. */ 631 krwlock_t filter_lock; /* Lock to protect filters. */ 632 633 ulong_t sys_burst_sz; 634 635 uint8_t cache_line; 636 637 timeout_id_t nxge_link_poll_timerid; 638 timeout_id_t nxge_timerid; 639 640 uint_t need_periodic_reclaim; 641 timeout_id_t reclaim_timer; 642 643 uint8_t msg_min; 644 uint8_t crc_size; 645 646 boolean_t hard_props_read; 647 648 boolean_t nxge_htraffic; 649 uint32_t nxge_ncpus; 650 uint32_t nxge_cpumask; 651 uint16_t intr_timeout; 652 uint16_t intr_threshold; 653 uchar_t nxge_rxmode; 654 uint32_t active_threads; 655 656 rtrace_t rtrace; 657 int fm_capabilities; /* FMA capabilities */ 658 659 uint32_t nxge_port_rbr_size; 660 uint32_t nxge_port_rcr_size; 661 uint32_t nxge_port_tx_ring_size; 662 nxge_mmac_t nxge_mmac_info; 663 #if defined(sun4v) 664 boolean_t niu_hsvc_available; 665 hsvc_info_t niu_hsvc; 666 uint64_t niu_min_ver; 667 #endif 668 }; 669 670 /* 671 * Driver state flags. 672 */ 673 #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 674 #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 675 #define STATE_NODE_CREATED 0x000000004 /* device node created */ 676 #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 677 #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 678 #define STATE_MDIO_LOCK_INIT 0x000000020 /* mdio lock initialized */ 679 #define STATE_MII_LOCK_INIT 0x000000040 /* mii lock initialized */ 680 681 #define STOP_POLL_THRESH 9 682 #define START_POLL_THRESH 2 683 684 typedef struct _nxge_port_kstat_t { 685 /* 686 * Link Input/Output stats 687 */ 688 kstat_named_t ipackets; 689 kstat_named_t ipackets64; 690 kstat_named_t ierrors; 691 kstat_named_t opackets; 692 kstat_named_t opackets64; 693 kstat_named_t oerrors; 694 kstat_named_t collisions; 695 696 /* 697 * required by kstat for MIB II objects(RFC 1213) 698 */ 699 kstat_named_t rbytes; /* # octets received */ 700 /* MIB - ifInOctets */ 701 kstat_named_t rbytes64; 702 kstat_named_t obytes; /* # octets transmitted */ 703 /* MIB - ifOutOctets */ 704 kstat_named_t obytes64; 705 kstat_named_t multircv; /* # multicast packets */ 706 /* delivered to upper layer */ 707 /* MIB - ifInNUcastPkts */ 708 kstat_named_t multixmt; /* # multicast packets */ 709 /* requested to be sent */ 710 /* MIB - ifOutNUcastPkts */ 711 kstat_named_t brdcstrcv; /* # broadcast packets */ 712 /* delivered to upper layer */ 713 /* MIB - ifInNUcastPkts */ 714 kstat_named_t brdcstxmt; /* # broadcast packets */ 715 /* requested to be sent */ 716 /* MIB - ifOutNUcastPkts */ 717 kstat_named_t norcvbuf; /* # rcv packets discarded */ 718 /* MIB - ifInDiscards */ 719 kstat_named_t noxmtbuf; /* # xmt packets discarded */ 720 /* MIB - ifOutDiscards */ 721 722 /* 723 * Transciever state informations. 724 */ 725 kstat_named_t xcvr_inits; 726 kstat_named_t xcvr_inuse; 727 kstat_named_t xcvr_addr; 728 kstat_named_t xcvr_id; 729 kstat_named_t cap_autoneg; 730 kstat_named_t cap_10gfdx; 731 kstat_named_t cap_10ghdx; 732 kstat_named_t cap_1000fdx; 733 kstat_named_t cap_1000hdx; 734 kstat_named_t cap_100T4; 735 kstat_named_t cap_100fdx; 736 kstat_named_t cap_100hdx; 737 kstat_named_t cap_10fdx; 738 kstat_named_t cap_10hdx; 739 kstat_named_t cap_asmpause; 740 kstat_named_t cap_pause; 741 742 /* 743 * Link partner capabilities. 744 */ 745 kstat_named_t lp_cap_autoneg; 746 kstat_named_t lp_cap_10gfdx; 747 kstat_named_t lp_cap_10ghdx; 748 kstat_named_t lp_cap_1000fdx; 749 kstat_named_t lp_cap_1000hdx; 750 kstat_named_t lp_cap_100T4; 751 kstat_named_t lp_cap_100fdx; 752 kstat_named_t lp_cap_100hdx; 753 kstat_named_t lp_cap_10fdx; 754 kstat_named_t lp_cap_10hdx; 755 kstat_named_t lp_cap_asmpause; 756 kstat_named_t lp_cap_pause; 757 758 /* 759 * Shared link setup. 760 */ 761 kstat_named_t link_T4; 762 kstat_named_t link_speed; 763 kstat_named_t link_duplex; 764 kstat_named_t link_asmpause; 765 kstat_named_t link_pause; 766 kstat_named_t link_up; 767 768 /* 769 * Lets the user know the MTU currently in use by 770 * the physical MAC port. 771 */ 772 kstat_named_t mac_mtu; 773 kstat_named_t lb_mode; 774 kstat_named_t qos_mode; 775 kstat_named_t trunk_mode; 776 777 /* 778 * Tx Statistics. 779 */ 780 kstat_named_t tx_inits; 781 kstat_named_t tx_starts; 782 kstat_named_t tx_nocanput; 783 kstat_named_t tx_msgdup_fail; 784 kstat_named_t tx_allocb_fail; 785 kstat_named_t tx_no_desc; 786 kstat_named_t tx_dma_bind_fail; 787 kstat_named_t tx_uflo; 788 kstat_named_t tx_hdr_pkts; 789 kstat_named_t tx_ddi_pkts; 790 kstat_named_t tx_dvma_pkts; 791 792 kstat_named_t tx_max_pend; 793 794 /* 795 * Rx Statistics. 796 */ 797 kstat_named_t rx_inits; 798 kstat_named_t rx_hdr_pkts; 799 kstat_named_t rx_mtu_pkts; 800 kstat_named_t rx_split_pkts; 801 kstat_named_t rx_no_buf; 802 kstat_named_t rx_no_comp_wb; 803 kstat_named_t rx_ov_flow; 804 kstat_named_t rx_len_mm; 805 kstat_named_t rx_tag_err; 806 kstat_named_t rx_nocanput; 807 kstat_named_t rx_msgdup_fail; 808 kstat_named_t rx_allocb_fail; 809 810 /* 811 * Receive buffer management statistics. 812 */ 813 kstat_named_t rx_new_pages; 814 kstat_named_t rx_new_hdr_pgs; 815 kstat_named_t rx_new_mtu_pgs; 816 kstat_named_t rx_new_nxt_pgs; 817 kstat_named_t rx_reused_pgs; 818 kstat_named_t rx_hdr_drops; 819 kstat_named_t rx_mtu_drops; 820 kstat_named_t rx_nxt_drops; 821 822 /* 823 * Receive flow statistics 824 */ 825 kstat_named_t rx_rel_flow; 826 kstat_named_t rx_rel_bit; 827 kstat_named_t rx_pkts_dropped; 828 829 /* 830 * Misc MAC statistics. 831 */ 832 kstat_named_t ifspeed; 833 kstat_named_t promisc; 834 kstat_named_t rev_id; 835 836 /* Global (entire NIU/Neptune device) statistics */ 837 838 /* 839 * PCI Bus Statistics. 840 */ 841 kstat_named_t pci_bus_speed; 842 kstat_named_t pci_err; 843 kstat_named_t pci_rta_err; 844 kstat_named_t pci_rma_err; 845 kstat_named_t pci_parity_err; 846 kstat_named_t pci_bad_ack_err; 847 kstat_named_t pci_drto_err; 848 kstat_named_t pci_dmawz_err; 849 kstat_named_t pci_dmarz_err; 850 851 kstat_named_t rx_taskq_waits; 852 853 /* 854 * Some statistics added to support bringup, these 855 * should be removed. 856 */ 857 kstat_named_t user_defined; 858 } nxge_port_kstat_t, *p_nxge_port_kstat_t; 859 860 typedef struct _nxge_rdc_kstat { 861 /* 862 * Receive DMA channel statistics. 863 */ 864 kstat_named_t ipackets; 865 kstat_named_t rbytes; 866 kstat_named_t errors; 867 kstat_named_t dcf_err; 868 kstat_named_t rcr_ack_err; 869 870 kstat_named_t dc_fifoflow_err; 871 kstat_named_t rcr_sha_par_err; 872 kstat_named_t rbr_pre_par_err; 873 kstat_named_t wred_drop; 874 kstat_named_t rbr_pre_emty; 875 876 kstat_named_t rcr_shadow_full; 877 kstat_named_t rbr_tmout; 878 kstat_named_t rsp_cnt_err; 879 kstat_named_t byte_en_bus; 880 kstat_named_t rsp_dat_err; 881 882 kstat_named_t compl_l2_err; 883 kstat_named_t compl_l4_cksum_err; 884 kstat_named_t compl_zcp_soft_err; 885 kstat_named_t compl_fflp_soft_err; 886 kstat_named_t config_err; 887 888 kstat_named_t rcrincon; 889 kstat_named_t rcrfull; 890 kstat_named_t rbr_empty; 891 kstat_named_t rbrfull; 892 kstat_named_t rbrlogpage; 893 894 kstat_named_t cfiglogpage; 895 kstat_named_t port_drop_pkt; 896 kstat_named_t rcr_to; 897 kstat_named_t rcr_thresh; 898 kstat_named_t rcr_mex; 899 kstat_named_t id_mismatch; 900 kstat_named_t zcp_eop_err; 901 kstat_named_t ipp_eop_err; 902 } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t; 903 904 typedef struct _nxge_rdc_sys_kstat { 905 /* 906 * Receive DMA system statistics. 907 */ 908 kstat_named_t pre_par; 909 kstat_named_t sha_par; 910 kstat_named_t id_mismatch; 911 kstat_named_t ipp_eop_err; 912 kstat_named_t zcp_eop_err; 913 } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t; 914 915 typedef struct _nxge_tdc_kstat { 916 /* 917 * Transmit DMA channel statistics. 918 */ 919 kstat_named_t opackets; 920 kstat_named_t obytes; 921 kstat_named_t oerrors; 922 kstat_named_t tx_inits; 923 kstat_named_t tx_no_buf; 924 925 kstat_named_t mbox_err; 926 kstat_named_t pkt_size_err; 927 kstat_named_t tx_ring_oflow; 928 kstat_named_t pref_buf_ecc_err; 929 kstat_named_t nack_pref; 930 kstat_named_t nack_pkt_rd; 931 kstat_named_t conf_part_err; 932 kstat_named_t pkt_prt_err; 933 kstat_named_t reset_fail; 934 /* used to in the common (per port) counter */ 935 936 kstat_named_t tx_starts; 937 kstat_named_t tx_nocanput; 938 kstat_named_t tx_msgdup_fail; 939 kstat_named_t tx_allocb_fail; 940 kstat_named_t tx_no_desc; 941 kstat_named_t tx_dma_bind_fail; 942 kstat_named_t tx_uflo; 943 kstat_named_t tx_hdr_pkts; 944 kstat_named_t tx_ddi_pkts; 945 kstat_named_t tx_dvma_pkts; 946 kstat_named_t tx_max_pend; 947 } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t; 948 949 typedef struct _nxge_txc_kstat { 950 /* 951 * Transmit port TXC block statistics. 952 */ 953 kstat_named_t pkt_stuffed; 954 kstat_named_t pkt_xmit; 955 kstat_named_t ro_correct_err; 956 kstat_named_t ro_uncorrect_err; 957 kstat_named_t sf_correct_err; 958 kstat_named_t sf_uncorrect_err; 959 kstat_named_t address_failed; 960 kstat_named_t dma_failed; 961 kstat_named_t length_failed; 962 kstat_named_t pkt_assy_dead; 963 kstat_named_t reorder_err; 964 } nxge_txc_kstat_t, *p_nxge_txc_kstat_t; 965 966 typedef struct _nxge_ipp_kstat { 967 /* 968 * Receive port IPP block statistics. 969 */ 970 kstat_named_t eop_miss; 971 kstat_named_t sop_miss; 972 kstat_named_t dfifo_ue; 973 kstat_named_t ecc_err_cnt; 974 kstat_named_t dfifo_perr; 975 kstat_named_t pfifo_over; 976 kstat_named_t pfifo_und; 977 kstat_named_t bad_cs_cnt; 978 kstat_named_t pkt_dis_cnt; 979 kstat_named_t cs_fail; 980 } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t; 981 982 typedef struct _nxge_zcp_kstat { 983 /* 984 * ZCP statistics. 985 */ 986 kstat_named_t errors; 987 kstat_named_t inits; 988 kstat_named_t rrfifo_underrun; 989 kstat_named_t rrfifo_overrun; 990 kstat_named_t rspfifo_uncorr_err; 991 kstat_named_t buffer_overflow; 992 kstat_named_t stat_tbl_perr; 993 kstat_named_t dyn_tbl_perr; 994 kstat_named_t buf_tbl_perr; 995 kstat_named_t tt_program_err; 996 kstat_named_t rsp_tt_index_err; 997 kstat_named_t slv_tt_index_err; 998 kstat_named_t zcp_tt_index_err; 999 kstat_named_t access_fail; 1000 kstat_named_t cfifo_ecc; 1001 } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t; 1002 1003 typedef struct _nxge_mac_kstat { 1004 /* 1005 * Transmit MAC statistics. 1006 */ 1007 kstat_named_t tx_frame_cnt; 1008 kstat_named_t tx_underflow_err; 1009 kstat_named_t tx_overflow_err; 1010 kstat_named_t tx_maxpktsize_err; 1011 kstat_named_t tx_fifo_xfr_err; 1012 kstat_named_t tx_byte_cnt; 1013 1014 /* 1015 * Receive MAC statistics. 1016 */ 1017 kstat_named_t rx_frame_cnt; 1018 kstat_named_t rx_underflow_err; 1019 kstat_named_t rx_overflow_err; 1020 kstat_named_t rx_len_err_cnt; 1021 kstat_named_t rx_crc_err_cnt; 1022 kstat_named_t rx_viol_err_cnt; 1023 kstat_named_t rx_byte_cnt; 1024 kstat_named_t rx_hist1_cnt; 1025 kstat_named_t rx_hist2_cnt; 1026 kstat_named_t rx_hist3_cnt; 1027 kstat_named_t rx_hist4_cnt; 1028 kstat_named_t rx_hist5_cnt; 1029 kstat_named_t rx_hist6_cnt; 1030 kstat_named_t rx_broadcast_cnt; 1031 kstat_named_t rx_mult_cnt; 1032 kstat_named_t rx_frag_cnt; 1033 kstat_named_t rx_frame_align_err_cnt; 1034 kstat_named_t rx_linkfault_err_cnt; 1035 kstat_named_t rx_local_fault_err_cnt; 1036 kstat_named_t rx_remote_fault_err_cnt; 1037 } nxge_mac_kstat_t, *p_nxge_mac_kstat_t; 1038 1039 typedef struct _nxge_xmac_kstat { 1040 /* 1041 * XMAC statistics. 1042 */ 1043 kstat_named_t tx_frame_cnt; 1044 kstat_named_t tx_underflow_err; 1045 kstat_named_t tx_maxpktsize_err; 1046 kstat_named_t tx_overflow_err; 1047 kstat_named_t tx_fifo_xfr_err; 1048 kstat_named_t tx_byte_cnt; 1049 kstat_named_t rx_frame_cnt; 1050 kstat_named_t rx_underflow_err; 1051 kstat_named_t rx_overflow_err; 1052 kstat_named_t rx_crc_err_cnt; 1053 kstat_named_t rx_len_err_cnt; 1054 kstat_named_t rx_viol_err_cnt; 1055 kstat_named_t rx_byte_cnt; 1056 kstat_named_t rx_hist1_cnt; 1057 kstat_named_t rx_hist2_cnt; 1058 kstat_named_t rx_hist3_cnt; 1059 kstat_named_t rx_hist4_cnt; 1060 kstat_named_t rx_hist5_cnt; 1061 kstat_named_t rx_hist6_cnt; 1062 kstat_named_t rx_hist7_cnt; 1063 kstat_named_t rx_broadcast_cnt; 1064 kstat_named_t rx_mult_cnt; 1065 kstat_named_t rx_frag_cnt; 1066 kstat_named_t rx_frame_align_err_cnt; 1067 kstat_named_t rx_linkfault_err_cnt; 1068 kstat_named_t rx_remote_fault_err_cnt; 1069 kstat_named_t rx_local_fault_err_cnt; 1070 kstat_named_t rx_pause_cnt; 1071 kstat_named_t xpcs_deskew_err_cnt; 1072 kstat_named_t xpcs_ln0_symbol_err_cnt; 1073 kstat_named_t xpcs_ln1_symbol_err_cnt; 1074 kstat_named_t xpcs_ln2_symbol_err_cnt; 1075 kstat_named_t xpcs_ln3_symbol_err_cnt; 1076 } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t; 1077 1078 typedef struct _nxge_bmac_kstat { 1079 /* 1080 * BMAC statistics. 1081 */ 1082 kstat_named_t tx_frame_cnt; 1083 kstat_named_t tx_underrun_err; 1084 kstat_named_t tx_max_pkt_err; 1085 kstat_named_t tx_byte_cnt; 1086 kstat_named_t rx_frame_cnt; 1087 kstat_named_t rx_byte_cnt; 1088 kstat_named_t rx_overflow_err; 1089 kstat_named_t rx_align_err_cnt; 1090 kstat_named_t rx_crc_err_cnt; 1091 kstat_named_t rx_len_err_cnt; 1092 kstat_named_t rx_viol_err_cnt; 1093 kstat_named_t rx_pause_cnt; 1094 kstat_named_t tx_pause_state; 1095 kstat_named_t tx_nopause_state; 1096 } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t; 1097 1098 1099 typedef struct _nxge_fflp_kstat { 1100 /* 1101 * FFLP statistics. 1102 */ 1103 1104 kstat_named_t fflp_tcam_ecc_err; 1105 kstat_named_t fflp_tcam_perr; 1106 kstat_named_t fflp_vlan_perr; 1107 kstat_named_t fflp_hasht_lookup_err; 1108 kstat_named_t fflp_access_fail; 1109 kstat_named_t fflp_hasht_data_err[MAX_PARTITION]; 1110 } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t; 1111 1112 typedef struct _nxge_mmac_kstat { 1113 kstat_named_t mmac_max_addr_cnt; 1114 kstat_named_t mmac_avail_addr_cnt; 1115 kstat_named_t mmac_addr1; 1116 kstat_named_t mmac_addr2; 1117 kstat_named_t mmac_addr3; 1118 kstat_named_t mmac_addr4; 1119 kstat_named_t mmac_addr5; 1120 kstat_named_t mmac_addr6; 1121 kstat_named_t mmac_addr7; 1122 kstat_named_t mmac_addr8; 1123 kstat_named_t mmac_addr9; 1124 kstat_named_t mmac_addr10; 1125 kstat_named_t mmac_addr11; 1126 kstat_named_t mmac_addr12; 1127 kstat_named_t mmac_addr13; 1128 kstat_named_t mmac_addr14; 1129 kstat_named_t mmac_addr15; 1130 kstat_named_t mmac_addr16; 1131 } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t; 1132 1133 #endif /* _KERNEL */ 1134 1135 /* 1136 * Prototype definitions. 1137 */ 1138 nxge_status_t nxge_init(p_nxge_t); 1139 void nxge_uninit(p_nxge_t); 1140 void nxge_get64(p_nxge_t, p_mblk_t); 1141 void nxge_put64(p_nxge_t, p_mblk_t); 1142 void nxge_pio_loop(p_nxge_t, p_mblk_t); 1143 1144 #ifndef COSIM 1145 typedef void (*fptrv_t)(); 1146 timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int); 1147 void nxge_stop_timer(p_nxge_t, timeout_id_t); 1148 #endif 1149 #endif 1150 1151 #ifdef __cplusplus 1152 } 1153 #endif 1154 1155 #endif /* _SYS_NXGE_NXGE_H */ 1156