14d0e5007SSukumar Swaminathan /* 24d0e5007SSukumar Swaminathan * CDDL HEADER START 34d0e5007SSukumar Swaminathan * 44d0e5007SSukumar Swaminathan * The contents of this file are subject to the terms of the 54d0e5007SSukumar Swaminathan * Common Development and Distribution License (the "License"). 64d0e5007SSukumar Swaminathan * You may not use this file except in compliance with the License. 74d0e5007SSukumar Swaminathan * 84d0e5007SSukumar Swaminathan * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 94d0e5007SSukumar Swaminathan * or http://www.opensolaris.org/os/licensing. 104d0e5007SSukumar Swaminathan * See the License for the specific language governing permissions 114d0e5007SSukumar Swaminathan * and limitations under the License. 124d0e5007SSukumar Swaminathan * 134d0e5007SSukumar Swaminathan * When distributing Covered Code, include this CDDL HEADER in each 144d0e5007SSukumar Swaminathan * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 154d0e5007SSukumar Swaminathan * If applicable, add the following below this CDDL HEADER, with the 164d0e5007SSukumar Swaminathan * fields enclosed by brackets "[]" replaced with your own identifying 174d0e5007SSukumar Swaminathan * information: Portions Copyright [yyyy] [name of copyright owner] 184d0e5007SSukumar Swaminathan * 194d0e5007SSukumar Swaminathan * CDDL HEADER END 204d0e5007SSukumar Swaminathan */ 214d0e5007SSukumar Swaminathan 22*3abb112fSGarrett D'Amore /* Copyright © 2003-2011 Emulex. All rights reserved. */ 234d0e5007SSukumar Swaminathan 244d0e5007SSukumar Swaminathan /* 254d0e5007SSukumar Swaminathan * Header file containing the command structures for Hardware 264d0e5007SSukumar Swaminathan */ 274d0e5007SSukumar Swaminathan 284d0e5007SSukumar Swaminathan #ifndef _OCE_HW_H_ 294d0e5007SSukumar Swaminathan #define _OCE_HW_H_ 304d0e5007SSukumar Swaminathan 314d0e5007SSukumar Swaminathan #ifdef __cplusplus 324d0e5007SSukumar Swaminathan extern "C" { 334d0e5007SSukumar Swaminathan #endif 344d0e5007SSukumar Swaminathan 354d0e5007SSukumar Swaminathan #include <sys/types.h> 364d0e5007SSukumar Swaminathan 374d0e5007SSukumar Swaminathan #pragma pack(1) 384d0e5007SSukumar Swaminathan 39*3abb112fSGarrett D'Amore #define OC_CNA_GEN2 0x2 40*3abb112fSGarrett D'Amore #define OC_CNA_GEN3 0x3 41*3abb112fSGarrett D'Amore #define DEVID_TIGERSHARK 0x700 42*3abb112fSGarrett D'Amore #define DEVID_TOMCAT 0x710 43*3abb112fSGarrett D'Amore 444d0e5007SSukumar Swaminathan /* PCI CSR offsets */ 45*3abb112fSGarrett D'Amore #define PCICFG_F1_CSR 0x0 /* F1 for NIC */ 46*3abb112fSGarrett D'Amore #define PCICFG_SEMAPHORE 0xbc 47*3abb112fSGarrett D'Amore #define PCICFG_SOFT_RESET 0x5c 484d0e5007SSukumar Swaminathan #define PCICFG_UE_STATUS_HI_MASK 0xac 494d0e5007SSukumar Swaminathan #define PCICFG_UE_STATUS_LO_MASK 0xa8 50*3abb112fSGarrett D'Amore #define PCICFG_ONLINE0 0xb0 51*3abb112fSGarrett D'Amore #define PCICFG_ONLINE1 0xb4 524d0e5007SSukumar Swaminathan #define INTR_EN 0x20000000 53*3abb112fSGarrett D'Amore #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */ 544d0e5007SSukumar Swaminathan 554d0e5007SSukumar Swaminathan /* CSR register offsets */ 56*3abb112fSGarrett D'Amore #define MPU_EP_CONTROL 0 57*3abb112fSGarrett D'Amore #define MPU_EP_SEMAPHORE 0xac 58*3abb112fSGarrett D'Amore #define PCICFG_INTR_CTRL 0xfc 59*3abb112fSGarrett D'Amore #define HOSTINTR_MASK (1 << 29) 60*3abb112fSGarrett D'Amore #define HOSTINTR_PFUNC_SHIFT 26 61*3abb112fSGarrett D'Amore #define HOSTINTR_PFUNC_MASK 7 624d0e5007SSukumar Swaminathan 634d0e5007SSukumar Swaminathan /* POST status reg struct */ 644d0e5007SSukumar Swaminathan #define POST_STAGE_POWER_ON_RESET 0x00 654d0e5007SSukumar Swaminathan #define POST_STAGE_AWAITING_HOST_RDY 0x01 664d0e5007SSukumar Swaminathan #define POST_STAGE_HOST_RDY 0x02 674d0e5007SSukumar Swaminathan #define POST_STAGE_CHIP_RESET 0x03 684d0e5007SSukumar Swaminathan #define POST_STAGE_ARMFW_READY 0xc000 694d0e5007SSukumar Swaminathan #define POST_STAGE_ARMFW_UE 0xf000 704d0e5007SSukumar Swaminathan 714d0e5007SSukumar Swaminathan /* DOORBELL registers */ 72*3abb112fSGarrett D'Amore #define PD_RXULP_DB 0x0100 73*3abb112fSGarrett D'Amore #define PD_TXULP_DB 0x0060 74*3abb112fSGarrett D'Amore #define DB_RQ_ID_MASK 0x3FF 754d0e5007SSukumar Swaminathan 76*3abb112fSGarrett D'Amore #define PD_CQ_DB 0x0120 77*3abb112fSGarrett D'Amore #define PD_EQ_DB PD_CQ_DB 78*3abb112fSGarrett D'Amore #define PD_MPU_MBOX_DB 0x0160 79*3abb112fSGarrett D'Amore #define PD_MQ_DB 0x0140 804d0e5007SSukumar Swaminathan 814d0e5007SSukumar Swaminathan /* EQE completion types */ 824d0e5007SSukumar Swaminathan #define EQ_MINOR_CODE_COMPLETION 0x00 83*3abb112fSGarrett D'Amore #define EQ_MINOR_CODE_OTHER 0x01 844d0e5007SSukumar Swaminathan #define EQ_MAJOR_CODE_COMPLETION 0x00 854d0e5007SSukumar Swaminathan 864d0e5007SSukumar Swaminathan /* Link Status field values */ 87*3abb112fSGarrett D'Amore #define PHY_LINK_FAULT_NONE 0x0 884d0e5007SSukumar Swaminathan #define PHY_LINK_FAULT_LOCAL 0x01 894d0e5007SSukumar Swaminathan #define PHY_LINK_FAULT_REMOTE 0x02 904d0e5007SSukumar Swaminathan 91*3abb112fSGarrett D'Amore #define PHY_LINK_SPEED_ZERO 0x0 /* No link */ 924d0e5007SSukumar Swaminathan #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 934d0e5007SSukumar Swaminathan #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 944d0e5007SSukumar Swaminathan #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 954d0e5007SSukumar Swaminathan #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 964d0e5007SSukumar Swaminathan 974d0e5007SSukumar Swaminathan #define PHY_LINK_DUPLEX_NONE 0x0 984d0e5007SSukumar Swaminathan #define PHY_LINK_DUPLEX_HALF 0x1 994d0e5007SSukumar Swaminathan #define PHY_LINK_DUPLEX_FULL 0x2 1004d0e5007SSukumar Swaminathan 1014d0e5007SSukumar Swaminathan #define NTWK_PORT_A 0x0 /* (Port A) */ 1024d0e5007SSukumar Swaminathan #define NTWK_PORT_B 0x1 /* (Port B) */ 1034d0e5007SSukumar Swaminathan 1044d0e5007SSukumar Swaminathan #define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */ 1054d0e5007SSukumar Swaminathan #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 1064d0e5007SSukumar Swaminathan #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 1074d0e5007SSukumar Swaminathan #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 1084d0e5007SSukumar Swaminathan #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 1094d0e5007SSukumar Swaminathan 1104d0e5007SSukumar Swaminathan /* Hardware Address types */ 1114d0e5007SSukumar Swaminathan #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */ 1124d0e5007SSukumar Swaminathan #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */ 1134d0e5007SSukumar Swaminathan #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */ 1144d0e5007SSukumar Swaminathan #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */ 1154d0e5007SSukumar Swaminathan #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */ 1164d0e5007SSukumar Swaminathan 1174d0e5007SSukumar Swaminathan /* CREATE_IFACE capability and cap_en flags */ 118*3abb112fSGarrett D'Amore #define MBX_RX_IFACE_FLAGS_RSS 0x4 119*3abb112fSGarrett D'Amore #define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8 120*3abb112fSGarrett D'Amore #define MBX_RX_IFACE_FLAGS_BROADCAST 0x10 121*3abb112fSGarrett D'Amore #define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20 122*3abb112fSGarrett D'Amore #define MBX_RX_IFACE_FLAGS_ULP 0x40 123*3abb112fSGarrett D'Amore #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80 124*3abb112fSGarrett D'Amore #define MBX_RX_IFACE_FLAGS_VLAN 0x100 1254d0e5007SSukumar Swaminathan #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200 126*3abb112fSGarrett D'Amore #define MBX_RX_IFACE_FLAGS_PASS_L2 0x400 127*3abb112fSGarrett D'Amore #define MBX_RX_IFACE_FLAGS_PASS_L3L4 0x800 1284d0e5007SSukumar Swaminathan 1294d0e5007SSukumar Swaminathan #define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */ 1304d0e5007SSukumar Swaminathan #define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */ 1314d0e5007SSukumar Swaminathan #define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */ 1324d0e5007SSukumar Swaminathan #define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */ 1334d0e5007SSukumar Swaminathan 1344d0e5007SSukumar Swaminathan 135*3abb112fSGarrett D'Amore #define MBX_DB_READY_BIT 0x1 136*3abb112fSGarrett D'Amore #define MBX_DB_HI_BIT 0x2 1374d0e5007SSukumar Swaminathan #define ASYNC_EVENT_CODE_LINK_STATE 0x1 138*3abb112fSGarrett D'Amore #define ASYNC_EVENT_LINK_UP 0x1 1394d0e5007SSukumar Swaminathan #define ASYNC_EVENT_LINK_DOWN 0x0 1404d0e5007SSukumar Swaminathan 1415b9d3151SSukumar Swaminathan /* port link_status */ 1425b9d3151SSukumar Swaminathan #define ASYNC_EVENT_LOGICAL 0x02 1435b9d3151SSukumar Swaminathan 1445b9d3151SSukumar Swaminathan /* Logical Link Status */ 1455b9d3151SSukumar Swaminathan #define NTWK_LOGICAL_LINK_DOWN 0 1465b9d3151SSukumar Swaminathan #define NTWK_LOGICAL_LINK_UP 1 1475b9d3151SSukumar Swaminathan 1484d0e5007SSukumar Swaminathan /* Rx filter bits */ 1494d0e5007SSukumar Swaminathan #define NTWK_RX_FILTER_IP_CKSUM 0x1 1504d0e5007SSukumar Swaminathan #define NTWK_RX_FILTER_TCP_CKSUM 0x2 1514d0e5007SSukumar Swaminathan #define NTWK_RX_FILTER_UDP_CKSUM 0x4 1524d0e5007SSukumar Swaminathan #define NTWK_RX_FILTER_STRIP_CRC 0x8 1534d0e5007SSukumar Swaminathan 1544d0e5007SSukumar Swaminathan /* max SGE per mbx */ 155*3abb112fSGarrett D'Amore #define MAX_MBX_SGE 19 1564d0e5007SSukumar Swaminathan 1574d0e5007SSukumar Swaminathan /* physical address structure to be used in MBX */ 1584d0e5007SSukumar Swaminathan struct phys_addr { 1594d0e5007SSukumar Swaminathan /* dw0 */ 1604d0e5007SSukumar Swaminathan uint32_t lo; 1614d0e5007SSukumar Swaminathan /* dw1 */ 1624d0e5007SSukumar Swaminathan uint32_t hi; 1634d0e5007SSukumar Swaminathan }; 1644d0e5007SSukumar Swaminathan 1654d0e5007SSukumar Swaminathan typedef union pcicfg_intr_ctl_u { 1664d0e5007SSukumar Swaminathan uint32_t dw0; 1674d0e5007SSukumar Swaminathan struct { 1684d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 1694d0e5007SSukumar Swaminathan uint32_t winselect:2; 1704d0e5007SSukumar Swaminathan uint32_t hostintr:1; 1714d0e5007SSukumar Swaminathan uint32_t pfnum:3; 1724d0e5007SSukumar Swaminathan uint32_t vf_cev_int_line_en:1; 1734d0e5007SSukumar Swaminathan uint32_t winaddr:23; 1744d0e5007SSukumar Swaminathan uint32_t membarwinen:1; 1754d0e5007SSukumar Swaminathan #else 1764d0e5007SSukumar Swaminathan uint32_t membarwinen:1; 1774d0e5007SSukumar Swaminathan uint32_t winaddr:23; 1784d0e5007SSukumar Swaminathan uint32_t vf_cev_int_line_en:1; 1794d0e5007SSukumar Swaminathan uint32_t pfnum:3; 1804d0e5007SSukumar Swaminathan uint32_t hostintr:1; 1814d0e5007SSukumar Swaminathan uint32_t winselect:2; 1824d0e5007SSukumar Swaminathan #endif 1834d0e5007SSukumar Swaminathan } bits; 1844d0e5007SSukumar Swaminathan }pcicfg_intr_ctl_t; 1854d0e5007SSukumar Swaminathan 1864d0e5007SSukumar Swaminathan typedef union pcicfg_semaphore_u { 1874d0e5007SSukumar Swaminathan uint32_t dw0; 1884d0e5007SSukumar Swaminathan struct { 1894d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 1904d0e5007SSukumar Swaminathan uint32_t rsvd:31; 1914d0e5007SSukumar Swaminathan uint32_t lock:1; 1924d0e5007SSukumar Swaminathan #else 1934d0e5007SSukumar Swaminathan uint32_t lock:1; 1944d0e5007SSukumar Swaminathan uint32_t rsvd:31; 1954d0e5007SSukumar Swaminathan #endif 1964d0e5007SSukumar Swaminathan }bits; 1974d0e5007SSukumar Swaminathan }pcicfg_semaphore_t; 1984d0e5007SSukumar Swaminathan 1994d0e5007SSukumar Swaminathan typedef union pcicfg_soft_reset_u { 2004d0e5007SSukumar Swaminathan uint32_t dw0; 2014d0e5007SSukumar Swaminathan struct { 2024d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 2034d0e5007SSukumar Swaminathan uint32_t nec_ll_rcvdetect:8; 2044d0e5007SSukumar Swaminathan uint32_t dbg_all_reqs_62_49:14; 2054d0e5007SSukumar Swaminathan uint32_t scratchpad0:1; 2064d0e5007SSukumar Swaminathan uint32_t exception_oe:1; 2074d0e5007SSukumar Swaminathan uint32_t soft_reset:1; 2084d0e5007SSukumar Swaminathan uint32_t rsvd0:7; 2094d0e5007SSukumar Swaminathan #else 2104d0e5007SSukumar Swaminathan uint32_t rsvd0:7; 2114d0e5007SSukumar Swaminathan uint32_t soft_reset:1; 2124d0e5007SSukumar Swaminathan uint32_t exception_oe:1; 2134d0e5007SSukumar Swaminathan uint32_t scratchpad0:1; 2144d0e5007SSukumar Swaminathan uint32_t dbg_all_reqs_62_49:14; 2154d0e5007SSukumar Swaminathan uint32_t nec_ll_rcvdetect:8; 2164d0e5007SSukumar Swaminathan #endif 2174d0e5007SSukumar Swaminathan }bits; 2184d0e5007SSukumar Swaminathan }pcicfg_soft_reset_t; 2194d0e5007SSukumar Swaminathan 2204d0e5007SSukumar Swaminathan typedef union pcicfg_online1_u { 2214d0e5007SSukumar Swaminathan uint32_t dw0; 2224d0e5007SSukumar Swaminathan struct { 2234d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 2244d0e5007SSukumar Swaminathan uint32_t host8_online:1; 2254d0e5007SSukumar Swaminathan uint32_t host7_online:1; 2264d0e5007SSukumar Swaminathan uint32_t host6_online:1; 2274d0e5007SSukumar Swaminathan uint32_t host5_online:1; 2284d0e5007SSukumar Swaminathan uint32_t host4_online:1; 2294d0e5007SSukumar Swaminathan uint32_t host3_online:1; 2304d0e5007SSukumar Swaminathan uint32_t host2_online:1; 2314d0e5007SSukumar Swaminathan uint32_t ipc_online:1; 2324d0e5007SSukumar Swaminathan uint32_t arm_online:1; 2334d0e5007SSukumar Swaminathan uint32_t txp_online:1; 2344d0e5007SSukumar Swaminathan uint32_t xaui_online:1; 2354d0e5007SSukumar Swaminathan uint32_t rxpp_online:1; 2364d0e5007SSukumar Swaminathan uint32_t txpb_online:1; 2374d0e5007SSukumar Swaminathan uint32_t rr_online:1; 2384d0e5007SSukumar Swaminathan uint32_t pmem_online:1; 2394d0e5007SSukumar Swaminathan uint32_t pctl1_online:1; 2404d0e5007SSukumar Swaminathan uint32_t pctl0_online:1; 2414d0e5007SSukumar Swaminathan uint32_t pcs1online_online:1; 2424d0e5007SSukumar Swaminathan uint32_t mpu_iram_online:1; 2434d0e5007SSukumar Swaminathan uint32_t pcs0online_online:1; 2444d0e5007SSukumar Swaminathan uint32_t mgmt_mac_online:1; 2454d0e5007SSukumar Swaminathan uint32_t lpcmemhost_online:1; 2464d0e5007SSukumar Swaminathan #else 2474d0e5007SSukumar Swaminathan uint32_t lpcmemhost_online:1; 2484d0e5007SSukumar Swaminathan uint32_t mgmt_mac_online:1; 2494d0e5007SSukumar Swaminathan uint32_t pcs0online_online:1; 2504d0e5007SSukumar Swaminathan uint32_t mpu_iram_online:1; 2514d0e5007SSukumar Swaminathan uint32_t pcs1online_online:1; 2524d0e5007SSukumar Swaminathan uint32_t pctl0_online:1; 2534d0e5007SSukumar Swaminathan uint32_t pctl1_online:1; 2544d0e5007SSukumar Swaminathan uint32_t pmem_online:1; 2554d0e5007SSukumar Swaminathan uint32_t rr_online:1; 2564d0e5007SSukumar Swaminathan uint32_t txpb_online:1; 2574d0e5007SSukumar Swaminathan uint32_t rxpp_online:1; 2584d0e5007SSukumar Swaminathan uint32_t xaui_online:1; 2594d0e5007SSukumar Swaminathan uint32_t txp_online:1; 2604d0e5007SSukumar Swaminathan uint32_t arm_online:1; 2614d0e5007SSukumar Swaminathan uint32_t ipc_online:1; 2624d0e5007SSukumar Swaminathan uint32_t host2_online:1; 2634d0e5007SSukumar Swaminathan uint32_t host3_online:1; 2644d0e5007SSukumar Swaminathan uint32_t host4_online:1; 2654d0e5007SSukumar Swaminathan uint32_t host5_online:1; 2664d0e5007SSukumar Swaminathan uint32_t host6_online:1; 2674d0e5007SSukumar Swaminathan uint32_t host7_online:1; 2684d0e5007SSukumar Swaminathan uint32_t host8_online:1; 2694d0e5007SSukumar Swaminathan #endif 2704d0e5007SSukumar Swaminathan }bits; 2714d0e5007SSukumar Swaminathan }pcicfg_online1_t; 2724d0e5007SSukumar Swaminathan 2734d0e5007SSukumar Swaminathan typedef union mpu_ep_semaphore_u { 2744d0e5007SSukumar Swaminathan uint32_t dw0; 2754d0e5007SSukumar Swaminathan struct { 2764d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 2774d0e5007SSukumar Swaminathan uint32_t error:1; 2784d0e5007SSukumar Swaminathan uint32_t backup_fw:1; 2794d0e5007SSukumar Swaminathan uint32_t iscsi_no_ip:1; 2804d0e5007SSukumar Swaminathan uint32_t iscsi_ip_conflict:1; 2814d0e5007SSukumar Swaminathan uint32_t option_rom_installed:1; 2824d0e5007SSukumar Swaminathan uint32_t iscsi_drv_loaded:1; 2834d0e5007SSukumar Swaminathan uint32_t rsvd0:10; 2844d0e5007SSukumar Swaminathan uint32_t stage:16; 2854d0e5007SSukumar Swaminathan #else 2864d0e5007SSukumar Swaminathan uint32_t stage:16; 2874d0e5007SSukumar Swaminathan uint32_t rsvd0:10; 2884d0e5007SSukumar Swaminathan uint32_t iscsi_drv_loaded:1; 2894d0e5007SSukumar Swaminathan uint32_t option_rom_installed:1; 2904d0e5007SSukumar Swaminathan uint32_t iscsi_ip_conflict:1; 2914d0e5007SSukumar Swaminathan uint32_t iscsi_no_ip:1; 2924d0e5007SSukumar Swaminathan uint32_t backup_fw:1; 2934d0e5007SSukumar Swaminathan uint32_t error:1; 2944d0e5007SSukumar Swaminathan #endif 2954d0e5007SSukumar Swaminathan }bits; 2964d0e5007SSukumar Swaminathan }mpu_ep_semaphore_t; 2974d0e5007SSukumar Swaminathan 2984d0e5007SSukumar Swaminathan typedef union mpu_ep_control_u { 2994d0e5007SSukumar Swaminathan uint32_t dw0; 3004d0e5007SSukumar Swaminathan struct { 3014d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 3024d0e5007SSukumar Swaminathan uint32_t cpu_reset:1; 3034d0e5007SSukumar Swaminathan uint32_t rsvd1:15; 3044d0e5007SSukumar Swaminathan uint32_t ep_ram_init_status:1; 3054d0e5007SSukumar Swaminathan uint32_t rsvd0:12; 3064d0e5007SSukumar Swaminathan uint32_t m2_rxpbuf:1; 3074d0e5007SSukumar Swaminathan uint32_t m1_rxpbuf:1; 3084d0e5007SSukumar Swaminathan uint32_t m0_rxpbuf:1; 3094d0e5007SSukumar Swaminathan #else 3104d0e5007SSukumar Swaminathan uint32_t m0_rxpbuf:1; 3114d0e5007SSukumar Swaminathan uint32_t m1_rxpbuf:1; 3124d0e5007SSukumar Swaminathan uint32_t m2_rxpbuf:1; 3134d0e5007SSukumar Swaminathan uint32_t rsvd0:12; 3144d0e5007SSukumar Swaminathan uint32_t ep_ram_init_status:1; 3154d0e5007SSukumar Swaminathan uint32_t rsvd1:15; 3164d0e5007SSukumar Swaminathan uint32_t cpu_reset:1; 3174d0e5007SSukumar Swaminathan #endif 3184d0e5007SSukumar Swaminathan }bits; 3194d0e5007SSukumar Swaminathan }mpu_ep_control_t; 3204d0e5007SSukumar Swaminathan 3214d0e5007SSukumar Swaminathan /* RX doorbell */ 3224d0e5007SSukumar Swaminathan typedef union pd_rxulp_db_u { 3234d0e5007SSukumar Swaminathan uint32_t dw0; 3244d0e5007SSukumar Swaminathan struct { 3254d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 3264d0e5007SSukumar Swaminathan uint32_t num_posted:8; 3274d0e5007SSukumar Swaminathan uint32_t invalidate:1; 3284d0e5007SSukumar Swaminathan uint32_t rsvd1:13; 3294d0e5007SSukumar Swaminathan uint32_t qid:10; 3304d0e5007SSukumar Swaminathan #else 3314d0e5007SSukumar Swaminathan uint32_t qid:10; 3324d0e5007SSukumar Swaminathan uint32_t rsvd1:13; 3334d0e5007SSukumar Swaminathan uint32_t invalidate:1; 3344d0e5007SSukumar Swaminathan uint32_t num_posted:8; 3354d0e5007SSukumar Swaminathan #endif 3364d0e5007SSukumar Swaminathan }bits; 3374d0e5007SSukumar Swaminathan }pd_rxulp_db_t; 3384d0e5007SSukumar Swaminathan 3394d0e5007SSukumar Swaminathan /* TX doorbell */ 3404d0e5007SSukumar Swaminathan typedef union pd_txulp_db_u { 3414d0e5007SSukumar Swaminathan uint32_t dw0; 3424d0e5007SSukumar Swaminathan struct { 3434d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 3444d0e5007SSukumar Swaminathan uint32_t rsvd1:2; 3454d0e5007SSukumar Swaminathan uint32_t num_posted:14; 3464d0e5007SSukumar Swaminathan uint32_t rsvd0:6; 3474d0e5007SSukumar Swaminathan uint32_t qid:10; 3484d0e5007SSukumar Swaminathan #else 3494d0e5007SSukumar Swaminathan uint32_t qid:10; 3504d0e5007SSukumar Swaminathan uint32_t rsvd0:6; 3514d0e5007SSukumar Swaminathan uint32_t num_posted:14; 3524d0e5007SSukumar Swaminathan uint32_t rsvd1:2; 3534d0e5007SSukumar Swaminathan #endif 3544d0e5007SSukumar Swaminathan }bits; 3554d0e5007SSukumar Swaminathan }pd_txulp_db_t; 3564d0e5007SSukumar Swaminathan 3574d0e5007SSukumar Swaminathan /* CQ doorbell */ 3584d0e5007SSukumar Swaminathan typedef union cq_db_u { 3594d0e5007SSukumar Swaminathan uint32_t dw0; 3604d0e5007SSukumar Swaminathan struct { 3614d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 3624d0e5007SSukumar Swaminathan uint32_t rsvd1:2; 3634d0e5007SSukumar Swaminathan uint32_t rearm:1; 3644d0e5007SSukumar Swaminathan uint32_t num_popped:13; 3654d0e5007SSukumar Swaminathan uint32_t rsvd0:5; 3664d0e5007SSukumar Swaminathan uint32_t event:1; 3674d0e5007SSukumar Swaminathan uint32_t qid:10; 3684d0e5007SSukumar Swaminathan #else 3694d0e5007SSukumar Swaminathan uint32_t qid:10; 3704d0e5007SSukumar Swaminathan uint32_t event:1; 3714d0e5007SSukumar Swaminathan uint32_t rsvd0:5; 3724d0e5007SSukumar Swaminathan uint32_t num_popped:13; 3734d0e5007SSukumar Swaminathan uint32_t rearm:1; 3744d0e5007SSukumar Swaminathan uint32_t rsvd1:2; 3754d0e5007SSukumar Swaminathan #endif 3764d0e5007SSukumar Swaminathan }bits; 3774d0e5007SSukumar Swaminathan }cq_db_t; 3784d0e5007SSukumar Swaminathan 3794d0e5007SSukumar Swaminathan /* EQ doorbell */ 3804d0e5007SSukumar Swaminathan typedef union eq_db_u { 3814d0e5007SSukumar Swaminathan uint32_t dw0; 3824d0e5007SSukumar Swaminathan struct { 3834d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 3844d0e5007SSukumar Swaminathan uint32_t rsvd1:2; 3854d0e5007SSukumar Swaminathan uint32_t rearm:1; 3864d0e5007SSukumar Swaminathan uint32_t num_popped:13; 3874d0e5007SSukumar Swaminathan uint32_t rsvd0:5; 3884d0e5007SSukumar Swaminathan uint32_t event:1; 3894d0e5007SSukumar Swaminathan uint32_t clrint:1; 3904d0e5007SSukumar Swaminathan uint32_t qid:9; 3914d0e5007SSukumar Swaminathan #else 3924d0e5007SSukumar Swaminathan uint32_t qid:9; 3934d0e5007SSukumar Swaminathan uint32_t clrint:1; 3944d0e5007SSukumar Swaminathan uint32_t event:1; 3954d0e5007SSukumar Swaminathan uint32_t rsvd0:5; 3964d0e5007SSukumar Swaminathan uint32_t num_popped:13; 3974d0e5007SSukumar Swaminathan uint32_t rearm:1; 3984d0e5007SSukumar Swaminathan uint32_t rsvd1:2; 3994d0e5007SSukumar Swaminathan #endif 4004d0e5007SSukumar Swaminathan }bits; 4014d0e5007SSukumar Swaminathan }eq_db_t; 4024d0e5007SSukumar Swaminathan 4034d0e5007SSukumar Swaminathan /* bootstrap mbox doorbell */ 4044d0e5007SSukumar Swaminathan typedef union pd_mpu_mbox_db_u { 4054d0e5007SSukumar Swaminathan uint32_t dw0; 4064d0e5007SSukumar Swaminathan struct { 4074d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 4084d0e5007SSukumar Swaminathan uint32_t address:30; 4094d0e5007SSukumar Swaminathan uint32_t hi:1; 4104d0e5007SSukumar Swaminathan uint32_t ready:1; 4114d0e5007SSukumar Swaminathan #else 4124d0e5007SSukumar Swaminathan uint32_t ready:1; 4134d0e5007SSukumar Swaminathan uint32_t hi:1; 4144d0e5007SSukumar Swaminathan uint32_t address:30; 4154d0e5007SSukumar Swaminathan #endif 4164d0e5007SSukumar Swaminathan }bits; 4174d0e5007SSukumar Swaminathan }pd_mpu_mbox_db_t; 4184d0e5007SSukumar Swaminathan 4194d0e5007SSukumar Swaminathan 4204d0e5007SSukumar Swaminathan /* MQ ring doorbell */ 4214d0e5007SSukumar Swaminathan typedef union pd_mq_db_u { 4224d0e5007SSukumar Swaminathan uint32_t dw0; 4234d0e5007SSukumar Swaminathan struct { 4244d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 4254d0e5007SSukumar Swaminathan uint32_t rsvd1:2; 4264d0e5007SSukumar Swaminathan uint32_t num_posted:14; 4274d0e5007SSukumar Swaminathan uint32_t rsvd0:5; 4284d0e5007SSukumar Swaminathan uint32_t mq_id:11; 4294d0e5007SSukumar Swaminathan #else 4304d0e5007SSukumar Swaminathan uint32_t mq_id:11; 4314d0e5007SSukumar Swaminathan uint32_t rsvd0:5; 4324d0e5007SSukumar Swaminathan uint32_t num_posted:14; 4334d0e5007SSukumar Swaminathan uint32_t rsvd1:2; 4344d0e5007SSukumar Swaminathan #endif 4354d0e5007SSukumar Swaminathan }bits; 4364d0e5007SSukumar Swaminathan }pd_mq_db_t; 4374d0e5007SSukumar Swaminathan 4384d0e5007SSukumar Swaminathan /* 4394d0e5007SSukumar Swaminathan * Event Queue Entry 4404d0e5007SSukumar Swaminathan */ 4414d0e5007SSukumar Swaminathan struct oce_eqe { 4424d0e5007SSukumar Swaminathan union { 4434d0e5007SSukumar Swaminathan struct { 4444d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 4454d0e5007SSukumar Swaminathan uint32_t resource_id:16; 4464d0e5007SSukumar Swaminathan uint32_t minor_code:12; 4474d0e5007SSukumar Swaminathan uint32_t major_code:3; 4484d0e5007SSukumar Swaminathan uint32_t valid:1; 4494d0e5007SSukumar Swaminathan #else 4504d0e5007SSukumar Swaminathan uint32_t valid:1; 4514d0e5007SSukumar Swaminathan uint32_t major_code:3; 4524d0e5007SSukumar Swaminathan uint32_t minor_code:12; 4534d0e5007SSukumar Swaminathan uint32_t resource_id:16; 4544d0e5007SSukumar Swaminathan #endif 4554d0e5007SSukumar Swaminathan }s; 4564d0e5007SSukumar Swaminathan uint32_t dw0; 4574d0e5007SSukumar Swaminathan }u0; 4584d0e5007SSukumar Swaminathan }; 4594d0e5007SSukumar Swaminathan 4604d0e5007SSukumar Swaminathan /* MQ scatter gather entry. Array of these make an SGL */ 4614d0e5007SSukumar Swaminathan struct oce_mq_sge { 4624d0e5007SSukumar Swaminathan uint32_t pa_lo; 4634d0e5007SSukumar Swaminathan uint32_t pa_hi; 4644d0e5007SSukumar Swaminathan uint32_t length; 4654d0e5007SSukumar Swaminathan }; 4664d0e5007SSukumar Swaminathan 4674d0e5007SSukumar Swaminathan /* 4684d0e5007SSukumar Swaminathan * payload can contain an SGL or an embedded array of upto 59 dwords 4694d0e5007SSukumar Swaminathan */ 4704d0e5007SSukumar Swaminathan struct oce_mbx_payload { 4714d0e5007SSukumar Swaminathan union { 4724d0e5007SSukumar Swaminathan union { 4734d0e5007SSukumar Swaminathan struct oce_mq_sge sgl[MAX_MBX_SGE]; 4744d0e5007SSukumar Swaminathan uint32_t embedded[59]; 4754d0e5007SSukumar Swaminathan }u1; 4764d0e5007SSukumar Swaminathan uint32_t dw[59]; 4774d0e5007SSukumar Swaminathan }u0; 4784d0e5007SSukumar Swaminathan }; 4794d0e5007SSukumar Swaminathan 4804d0e5007SSukumar Swaminathan /* 4814d0e5007SSukumar Swaminathan * MQ MBX structure 4824d0e5007SSukumar Swaminathan */ 4834d0e5007SSukumar Swaminathan struct oce_mbx { 4844d0e5007SSukumar Swaminathan union { 4854d0e5007SSukumar Swaminathan struct { 4864d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 4874d0e5007SSukumar Swaminathan uint32_t special : 8; 4884d0e5007SSukumar Swaminathan uint32_t rsvd1 : 16; 4894d0e5007SSukumar Swaminathan uint32_t sge_count : 5; 4904d0e5007SSukumar Swaminathan uint32_t rsvd0 : 2; 4914d0e5007SSukumar Swaminathan uint32_t embedded : 1; 4924d0e5007SSukumar Swaminathan #else 4934d0e5007SSukumar Swaminathan uint32_t embedded:1; 4944d0e5007SSukumar Swaminathan uint32_t rsvd0:2; 4954d0e5007SSukumar Swaminathan uint32_t sge_count:5; 4964d0e5007SSukumar Swaminathan uint32_t rsvd1:16; 4974d0e5007SSukumar Swaminathan uint32_t special:8; 4984d0e5007SSukumar Swaminathan #endif 4994d0e5007SSukumar Swaminathan }s; 5004d0e5007SSukumar Swaminathan uint32_t dw0; 5014d0e5007SSukumar Swaminathan }u0; 5024d0e5007SSukumar Swaminathan 5034d0e5007SSukumar Swaminathan uint32_t payload_length; 5044d0e5007SSukumar Swaminathan uint32_t tag[2]; 5054d0e5007SSukumar Swaminathan uint32_t rsvd2[1]; 5064d0e5007SSukumar Swaminathan struct oce_mbx_payload payload; 5074d0e5007SSukumar Swaminathan }; 5084d0e5007SSukumar Swaminathan 5094d0e5007SSukumar Swaminathan /* completion queue entry for MQ */ 5104d0e5007SSukumar Swaminathan struct oce_mq_cqe { 5114d0e5007SSukumar Swaminathan union { 5124d0e5007SSukumar Swaminathan struct { 5134d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 5144d0e5007SSukumar Swaminathan /* dw0 */ 5154d0e5007SSukumar Swaminathan uint32_t extended_status:16; 5164d0e5007SSukumar Swaminathan uint32_t completion_status:16; 5174d0e5007SSukumar Swaminathan /* dw1 dw2 */ 5184d0e5007SSukumar Swaminathan uint32_t mq_tag[2]; 5194d0e5007SSukumar Swaminathan /* dw3 */ 5204d0e5007SSukumar Swaminathan uint32_t valid:1; 5214d0e5007SSukumar Swaminathan uint32_t async_event:1; 5224d0e5007SSukumar Swaminathan uint32_t hpi_buffer_cmpl:1; 5234d0e5007SSukumar Swaminathan uint32_t completed:1; 5244d0e5007SSukumar Swaminathan uint32_t consumed:1; 5254d0e5007SSukumar Swaminathan uint32_t rsvd0:27; 5264d0e5007SSukumar Swaminathan #else 5274d0e5007SSukumar Swaminathan /* dw0 */ 5284d0e5007SSukumar Swaminathan uint32_t completion_status:16; 5294d0e5007SSukumar Swaminathan uint32_t extended_status:16; 5304d0e5007SSukumar Swaminathan /* dw1 dw2 */ 5314d0e5007SSukumar Swaminathan uint32_t mq_tag[2]; 5324d0e5007SSukumar Swaminathan /* dw3 */ 5334d0e5007SSukumar Swaminathan uint32_t rsvd0:27; 5344d0e5007SSukumar Swaminathan uint32_t consumed:1; 5354d0e5007SSukumar Swaminathan uint32_t completed:1; 5364d0e5007SSukumar Swaminathan uint32_t hpi_buffer_cmpl:1; 5374d0e5007SSukumar Swaminathan uint32_t async_event:1; 5384d0e5007SSukumar Swaminathan uint32_t valid:1; 5394d0e5007SSukumar Swaminathan #endif 5404d0e5007SSukumar Swaminathan }s; 5414d0e5007SSukumar Swaminathan uint32_t dw[4]; 5424d0e5007SSukumar Swaminathan }u0; 5434d0e5007SSukumar Swaminathan }; 5444d0e5007SSukumar Swaminathan 5454d0e5007SSukumar Swaminathan struct oce_async_cqe_link_state { 5464d0e5007SSukumar Swaminathan union { 5474d0e5007SSukumar Swaminathan struct { 5484d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 5494d0e5007SSukumar Swaminathan /* dw0 */ 5504d0e5007SSukumar Swaminathan uint8_t speed; 5514d0e5007SSukumar Swaminathan uint8_t duplex; 5524d0e5007SSukumar Swaminathan uint8_t link_status; 5534d0e5007SSukumar Swaminathan uint8_t phy_port; 5544d0e5007SSukumar Swaminathan /* dw1 */ 5554d0e5007SSukumar Swaminathan uint8_t rsvd0[3]; 5564d0e5007SSukumar Swaminathan uint8_t fault; 5574d0e5007SSukumar Swaminathan /* dw2 */ 5584d0e5007SSukumar Swaminathan uint32_t event_tag; 5594d0e5007SSukumar Swaminathan /* dw3 */ 5604d0e5007SSukumar Swaminathan uint32_t valid:1; 5614d0e5007SSukumar Swaminathan uint32_t async_event:1; 5624d0e5007SSukumar Swaminathan uint32_t rsvd2:6; 5634d0e5007SSukumar Swaminathan uint32_t event_type:8; 5644d0e5007SSukumar Swaminathan uint32_t event_code:8; 5654d0e5007SSukumar Swaminathan uint32_t rsvd1:8; 5664d0e5007SSukumar Swaminathan #else 5674d0e5007SSukumar Swaminathan /* dw0 */ 5684d0e5007SSukumar Swaminathan uint8_t phy_port; 5694d0e5007SSukumar Swaminathan uint8_t link_status; 5704d0e5007SSukumar Swaminathan uint8_t duplex; 5714d0e5007SSukumar Swaminathan uint8_t speed; 5724d0e5007SSukumar Swaminathan /* dw1 */ 5734d0e5007SSukumar Swaminathan uint8_t fault; 5744d0e5007SSukumar Swaminathan uint8_t rsvd0[3]; 5754d0e5007SSukumar Swaminathan /* dw2 */ 5764d0e5007SSukumar Swaminathan uint32_t event_tag; 5774d0e5007SSukumar Swaminathan /* dw3 */ 5784d0e5007SSukumar Swaminathan uint32_t rsvd1:8; 5794d0e5007SSukumar Swaminathan uint32_t event_code:8; 5804d0e5007SSukumar Swaminathan uint32_t event_type:8; 5814d0e5007SSukumar Swaminathan uint32_t rsvd2:6; 5824d0e5007SSukumar Swaminathan uint32_t async_event:1; 5834d0e5007SSukumar Swaminathan uint32_t valid:1; 5844d0e5007SSukumar Swaminathan #endif 5854d0e5007SSukumar Swaminathan }s; 5864d0e5007SSukumar Swaminathan uint32_t dw[4]; 5874d0e5007SSukumar Swaminathan }u0; 5884d0e5007SSukumar Swaminathan }; 5894d0e5007SSukumar Swaminathan 5904d0e5007SSukumar Swaminathan /* MQ mailbox structure */ 5914d0e5007SSukumar Swaminathan struct oce_bmbx { 5924d0e5007SSukumar Swaminathan struct oce_mbx mbx; 5934d0e5007SSukumar Swaminathan struct oce_mq_cqe cqe; 5944d0e5007SSukumar Swaminathan }; 5954d0e5007SSukumar Swaminathan 5964d0e5007SSukumar Swaminathan /* ---[ MBXs start here ]---------------------------------------------- */ 5974d0e5007SSukumar Swaminathan /* MBXs sub system codes */ 5984d0e5007SSukumar Swaminathan enum { 5994d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_RSVD = 0, 6004d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_COMMON = 1, 6014d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_COMMON_ISCSI = 2, 6024d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_NIC = 3, 6034d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_TOE = 4, 6044d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_PXE_UNDI = 5, 6054d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_ISCSI_INI = 6, 6064d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_ISCSI_TGT = 7, 6074d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_MILI_PTL = 8, 6084d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_MILI_TMD = 9, 6094d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_RDMA = 10, 6104d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_LOWLEVEL = 11, 6114d0e5007SSukumar Swaminathan MBX_SUBSYSTEM_LRO = 13, 6124d0e5007SSukumar Swaminathan IOCBMBX_SUBSYSTEM_DCBX = 15, 6134d0e5007SSukumar Swaminathan IOCBMBX_SUBSYSTEM_DIAG = 16, 6144d0e5007SSukumar Swaminathan IOCBMBX_SUBSYSTEM_VENDOR = 17 6154d0e5007SSukumar Swaminathan }; 6164d0e5007SSukumar Swaminathan 6174d0e5007SSukumar Swaminathan /* common ioctl opcodes */ 6184d0e5007SSukumar Swaminathan enum { 6194d0e5007SSukumar Swaminathan OPCODE_QUERY_COMMON_IFACE_MAC = 1, 6204d0e5007SSukumar Swaminathan OPCODE_SET_COMMON_IFACE_MAC = 2, 6214d0e5007SSukumar Swaminathan OPCODE_SET_COMMON_IFACE_MULTICAST = 3, 6224d0e5007SSukumar Swaminathan OPCODE_CONFIG_COMMON_IFACE_VLAN = 4, 6234d0e5007SSukumar Swaminathan OPCODE_QUERY_COMMON_LINK_STATUS = 5, 6244d0e5007SSukumar Swaminathan OPCODE_READ_COMMON_FLASHROM = 6, 6254d0e5007SSukumar Swaminathan OPCODE_WRITE_COMMON_FLASHROM = 7, 6264d0e5007SSukumar Swaminathan OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE = 8, 6274d0e5007SSukumar Swaminathan OPCODE_ADD_COMMON_PAGE_TABLES = 9, 6284d0e5007SSukumar Swaminathan OPCODE_REMOVE_COMMON_PAGE_TABLES = 10, 6294d0e5007SSukumar Swaminathan OPCODE_CREATE_COMMON_CQ = 12, 6304d0e5007SSukumar Swaminathan OPCODE_CREATE_COMMON_EQ = 13, 6314d0e5007SSukumar Swaminathan OPCODE_CREATE_COMMON_MQ = 21, 6324d0e5007SSukumar Swaminathan OPCODE_COMMON_JELL_CONFIG = 22, 6334d0e5007SSukumar Swaminathan OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS = 24, 6344d0e5007SSukumar Swaminathan OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS = 25, 6354d0e5007SSukumar Swaminathan OPCODE_COMMON_POST_ZERO_BUFFER = 26, 6364d0e5007SSukumar Swaminathan OPCODE_COMMON_GET_QOS = 27, 6374d0e5007SSukumar Swaminathan OPCODE_COMMON_SET_QOS = 28, 6384d0e5007SSukumar Swaminathan OPCODE_COMMON_TCP_GET_STATISTICS = 29, 6394d0e5007SSukumar Swaminathan OPCODE_READ_COMMON_SEEPROM = 30, 6404d0e5007SSukumar Swaminathan OPCODE_COMMON_TCP_STATE_QUERY = 31, 6414d0e5007SSukumar Swaminathan OPCODE_GET_COMMON_CNTL_ATTRIBUTES = 32, 6424d0e5007SSukumar Swaminathan OPCODE_COMMON_NOP = 33, 6434d0e5007SSukumar Swaminathan OPCODE_COMMON_NTWK_RX_FILTER = 34, 6444d0e5007SSukumar Swaminathan OPCODE_GET_COMMON_FW_VERSION = 35, 6454d0e5007SSukumar Swaminathan OPCODE_SET_COMMON_FLOW_CONTROL = 36, 6464d0e5007SSukumar Swaminathan OPCODE_GET_COMMON_FLOW_CONTROL = 37, 6474d0e5007SSukumar Swaminathan OPCODE_COMMON_SET_TCP_PARAMETERS = 38, 6484d0e5007SSukumar Swaminathan OPCODE_SET_COMMON_FRAME_SIZE = 39, 6494d0e5007SSukumar Swaminathan OPCODE_COMMON_GET_FAT = 40, 6504d0e5007SSukumar Swaminathan OPCODE_MODIFY_COMMON_EQ_DELAY = 41, 6514d0e5007SSukumar Swaminathan OPCODE_COMMON_FIRMWARE_CONFIG = 42, 6524d0e5007SSukumar Swaminathan OPCODE_COMMON_ENABLE_DISABLE_DOMAINS = 43, 6534d0e5007SSukumar Swaminathan OPCODE_COMMON_GET_DOMAIN_CONFIG = 44, 6544d0e5007SSukumar Swaminathan OPCODE_COMMON_GET_PORT_EQUALIZATION = 47, 6554d0e5007SSukumar Swaminathan OPCODE_COMMON_SET_PORT_EQUALIZATION = 48, 6564d0e5007SSukumar Swaminathan OPCODE_COMMON_RED_CONFIG = 49, 6574d0e5007SSukumar Swaminathan OPCODE_CREATE_COMMON_IFACE = 50, 6584d0e5007SSukumar Swaminathan OPCODE_DESTROY_COMMON_IFACE = 51, 6594d0e5007SSukumar Swaminathan OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES = 52, 6604d0e5007SSukumar Swaminathan OPCODE_DESTROY_COMMON_MQ = 53, 6614d0e5007SSukumar Swaminathan OPCODE_DESTROY_COMMON_CQ = 54, 6624d0e5007SSukumar Swaminathan OPCODE_DESTROY_COMMON_EQ = 55, 6634d0e5007SSukumar Swaminathan OPCODE_COMMON_TCP_UPL_OAD = 56, 6644d0e5007SSukumar Swaminathan OPCODE_SET_COMMON_LINK_SPEED = 57, 6654d0e5007SSukumar Swaminathan OPCODE_QUERY_COMMON_FIRMWARE_CONFIG = 58, 6664d0e5007SSukumar Swaminathan OPCODE_ADD_COMMON_IFACE_MAC = 59, 6674d0e5007SSukumar Swaminathan OPCODE_DEL_COMMON_IFACE_MAC = 60, 6684d0e5007SSukumar Swaminathan OPCODE_COMMON_FUNCTION_RESET = 61, 6694d0e5007SSukumar Swaminathan OPCODE_COMMON_FUNCTION_LINK_CONFIG = 80 6704d0e5007SSukumar Swaminathan }; 6714d0e5007SSukumar Swaminathan 6724d0e5007SSukumar Swaminathan /* common ioctl header */ 6734d0e5007SSukumar Swaminathan struct mbx_hdr { 6744d0e5007SSukumar Swaminathan union { 6754d0e5007SSukumar Swaminathan struct { 6764d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 6774d0e5007SSukumar Swaminathan uint8_t domain; 6784d0e5007SSukumar Swaminathan uint8_t port_number; 6794d0e5007SSukumar Swaminathan uint8_t subsystem; 6804d0e5007SSukumar Swaminathan uint8_t opcode; 6814d0e5007SSukumar Swaminathan #else 6824d0e5007SSukumar Swaminathan uint8_t opcode; 6834d0e5007SSukumar Swaminathan uint8_t subsystem; 6844d0e5007SSukumar Swaminathan uint8_t port_number; 6854d0e5007SSukumar Swaminathan uint8_t domain; 6864d0e5007SSukumar Swaminathan #endif 6874d0e5007SSukumar Swaminathan uint32_t timeout; 6884d0e5007SSukumar Swaminathan uint32_t request_length; 6894d0e5007SSukumar Swaminathan uint32_t rsvd0; 6904d0e5007SSukumar Swaminathan }req; 6914d0e5007SSukumar Swaminathan 6924d0e5007SSukumar Swaminathan struct { 6934d0e5007SSukumar Swaminathan /* dw 0 */ 6944d0e5007SSukumar Swaminathan uint8_t opcode; 6954d0e5007SSukumar Swaminathan uint8_t subsystem; 6964d0e5007SSukumar Swaminathan uint8_t rsvd0; 6974d0e5007SSukumar Swaminathan uint8_t domain; 6984d0e5007SSukumar Swaminathan /* dw 1 */ 6994d0e5007SSukumar Swaminathan uint8_t status; 7004d0e5007SSukumar Swaminathan uint8_t additional_status; 7014d0e5007SSukumar Swaminathan uint16_t rsvd1; 7024d0e5007SSukumar Swaminathan 7034d0e5007SSukumar Swaminathan uint32_t rsp_length; 7044d0e5007SSukumar Swaminathan uint32_t actual_rsp_length; 7054d0e5007SSukumar Swaminathan }rsp; 7064d0e5007SSukumar Swaminathan uint32_t dw[4]; 7074d0e5007SSukumar Swaminathan }u0; 7084d0e5007SSukumar Swaminathan }; 7094d0e5007SSukumar Swaminathan #define OCE_BMBX_RHDR_SZ 20 7104d0e5007SSukumar Swaminathan #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr) 7114d0e5007SSukumar Swaminathan #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status) 7124d0e5007SSukumar Swaminathan #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status) 7134d0e5007SSukumar Swaminathan 7144d0e5007SSukumar Swaminathan /* [05] OPCODE_QUERY_COMMON_LINK_STATUS */ 7154d0e5007SSukumar Swaminathan struct mbx_query_common_link_status { 7164d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 7174d0e5007SSukumar Swaminathan union { 7184d0e5007SSukumar Swaminathan struct { 7194d0e5007SSukumar Swaminathan uint32_t rsvd0; 7204d0e5007SSukumar Swaminathan }req; 7214d0e5007SSukumar Swaminathan 7224d0e5007SSukumar Swaminathan struct { 7234d0e5007SSukumar Swaminathan /* dw 0 */ 7244d0e5007SSukumar Swaminathan uint8_t physical_port; 7254d0e5007SSukumar Swaminathan uint8_t mac_duplex; 7264d0e5007SSukumar Swaminathan uint8_t mac_speed; 7274d0e5007SSukumar Swaminathan uint8_t mac_fault; 7284d0e5007SSukumar Swaminathan /* dw 1 */ 7294d0e5007SSukumar Swaminathan uint8_t mgmt_mac_duplex; 7304d0e5007SSukumar Swaminathan uint8_t mgmt_mac_speed; 7318d738d7dSSukumar Swaminathan uint16_t qos_link_speed; 7328d738d7dSSukumar Swaminathan uint32_t logical_link_status; 7334d0e5007SSukumar Swaminathan }rsp; 7344d0e5007SSukumar Swaminathan }params; 7354d0e5007SSukumar Swaminathan }; 7364d0e5007SSukumar Swaminathan 7374d0e5007SSukumar Swaminathan /* [57] OPCODE_SET_COMMON_LINK_SPEED */ 7384d0e5007SSukumar Swaminathan struct mbx_set_common_link_speed { 7394d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 7404d0e5007SSukumar Swaminathan union { 7414d0e5007SSukumar Swaminathan struct { 7424d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 7434d0e5007SSukumar Swaminathan uint8_t rsvd0; 7444d0e5007SSukumar Swaminathan uint8_t mac_speed; 7454d0e5007SSukumar Swaminathan uint8_t virtual_port; 7464d0e5007SSukumar Swaminathan uint8_t physical_port; 7474d0e5007SSukumar Swaminathan #else 7484d0e5007SSukumar Swaminathan uint8_t physical_port; 7494d0e5007SSukumar Swaminathan uint8_t virtual_port; 7504d0e5007SSukumar Swaminathan uint8_t mac_speed; 7514d0e5007SSukumar Swaminathan uint8_t rsvd0; 7524d0e5007SSukumar Swaminathan #endif 7534d0e5007SSukumar Swaminathan }req; 7544d0e5007SSukumar Swaminathan 7554d0e5007SSukumar Swaminathan struct { 7564d0e5007SSukumar Swaminathan uint32_t rsvd0; 7574d0e5007SSukumar Swaminathan }rsp; 7584d0e5007SSukumar Swaminathan 7594d0e5007SSukumar Swaminathan uint32_t dw; 7604d0e5007SSukumar Swaminathan }params; 7614d0e5007SSukumar Swaminathan }; 7624d0e5007SSukumar Swaminathan 7634d0e5007SSukumar Swaminathan struct mac_address_format { 7644d0e5007SSukumar Swaminathan uint16_t size_of_struct; 7654d0e5007SSukumar Swaminathan uint8_t mac_addr[6]; 7664d0e5007SSukumar Swaminathan }; 7674d0e5007SSukumar Swaminathan 7684d0e5007SSukumar Swaminathan /* [01] OPCODE_QUERY_COMMON_IFACE_MAC */ 7694d0e5007SSukumar Swaminathan struct mbx_query_common_iface_mac { 7704d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 7714d0e5007SSukumar Swaminathan union { 7724d0e5007SSukumar Swaminathan struct { 7734d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 7744d0e5007SSukumar Swaminathan uint16_t if_id; 7754d0e5007SSukumar Swaminathan uint8_t permanent; 7764d0e5007SSukumar Swaminathan uint8_t type; 7774d0e5007SSukumar Swaminathan #else 7784d0e5007SSukumar Swaminathan uint8_t type; 7794d0e5007SSukumar Swaminathan uint8_t permanent; 7804d0e5007SSukumar Swaminathan uint16_t if_id; 7814d0e5007SSukumar Swaminathan #endif 7824d0e5007SSukumar Swaminathan 7834d0e5007SSukumar Swaminathan }req; 7844d0e5007SSukumar Swaminathan 7854d0e5007SSukumar Swaminathan struct { 7864d0e5007SSukumar Swaminathan struct mac_address_format mac; 7874d0e5007SSukumar Swaminathan }rsp; 7884d0e5007SSukumar Swaminathan }params; 7894d0e5007SSukumar Swaminathan }; 7904d0e5007SSukumar Swaminathan 7914d0e5007SSukumar Swaminathan /* [02] OPCODE_SET_COMMON_IFACE_MAC */ 7924d0e5007SSukumar Swaminathan struct mbx_set_common_iface_mac { 7934d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 7944d0e5007SSukumar Swaminathan union { 7954d0e5007SSukumar Swaminathan struct { 7964d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 7974d0e5007SSukumar Swaminathan /* dw 0 */ 7984d0e5007SSukumar Swaminathan uint16_t if_id; 7994d0e5007SSukumar Swaminathan uint8_t invalidate; 8004d0e5007SSukumar Swaminathan uint8_t type; 8014d0e5007SSukumar Swaminathan #else 8024d0e5007SSukumar Swaminathan /* dw 0 */ 8034d0e5007SSukumar Swaminathan uint8_t type; 8044d0e5007SSukumar Swaminathan uint8_t invalidate; 8054d0e5007SSukumar Swaminathan uint16_t if_id; 8064d0e5007SSukumar Swaminathan #endif 8074d0e5007SSukumar Swaminathan /* dw 1 */ 8084d0e5007SSukumar Swaminathan struct mac_address_format mac; 8094d0e5007SSukumar Swaminathan }req; 8104d0e5007SSukumar Swaminathan 8114d0e5007SSukumar Swaminathan struct { 8124d0e5007SSukumar Swaminathan uint32_t rsvd0; 8134d0e5007SSukumar Swaminathan }rsp; 8144d0e5007SSukumar Swaminathan 8154d0e5007SSukumar Swaminathan uint32_t dw[2]; 8164d0e5007SSukumar Swaminathan }params; 8174d0e5007SSukumar Swaminathan }; 8184d0e5007SSukumar Swaminathan 8194d0e5007SSukumar Swaminathan /* [03] OPCODE_SET_COMMON_IFACE_MULTICAST */ 8204d0e5007SSukumar Swaminathan struct mbx_set_common_iface_multicast { 8214d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 8224d0e5007SSukumar Swaminathan union { 8234d0e5007SSukumar Swaminathan struct { 8244d0e5007SSukumar Swaminathan /* dw 0 */ 8254d0e5007SSukumar Swaminathan uint16_t num_mac; 8264d0e5007SSukumar Swaminathan uint8_t promiscuous; 8274d0e5007SSukumar Swaminathan uint8_t if_id; 8284d0e5007SSukumar Swaminathan /* dw 1-48 */ 8294d0e5007SSukumar Swaminathan struct { 8304d0e5007SSukumar Swaminathan uint8_t byte[6]; 8314d0e5007SSukumar Swaminathan } mac[32]; 8324d0e5007SSukumar Swaminathan 8334d0e5007SSukumar Swaminathan }req; 8344d0e5007SSukumar Swaminathan 8354d0e5007SSukumar Swaminathan struct { 8364d0e5007SSukumar Swaminathan uint32_t rsvd0; 8374d0e5007SSukumar Swaminathan }rsp; 8384d0e5007SSukumar Swaminathan 8394d0e5007SSukumar Swaminathan uint32_t dw[49]; 8404d0e5007SSukumar Swaminathan }params; 8414d0e5007SSukumar Swaminathan }; 8424d0e5007SSukumar Swaminathan 8434d0e5007SSukumar Swaminathan struct qinq_vlan { 8444d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 8454d0e5007SSukumar Swaminathan uint16_t inner; 8464d0e5007SSukumar Swaminathan uint16_t outer; 8474d0e5007SSukumar Swaminathan #else 8484d0e5007SSukumar Swaminathan uint16_t outer; 8494d0e5007SSukumar Swaminathan uint16_t inner; 8504d0e5007SSukumar Swaminathan #endif 8514d0e5007SSukumar Swaminathan }; 8524d0e5007SSukumar Swaminathan 8534d0e5007SSukumar Swaminathan struct normal_vlan { 8544d0e5007SSukumar Swaminathan uint16_t vtag; 8554d0e5007SSukumar Swaminathan }; 8564d0e5007SSukumar Swaminathan 8574d0e5007SSukumar Swaminathan struct ntwk_if_vlan_tag { 8584d0e5007SSukumar Swaminathan union { 8594d0e5007SSukumar Swaminathan struct normal_vlan normal; 8604d0e5007SSukumar Swaminathan struct qinq_vlan qinq; 8614d0e5007SSukumar Swaminathan }u0; 8624d0e5007SSukumar Swaminathan }; 8634d0e5007SSukumar Swaminathan 8644d0e5007SSukumar Swaminathan /* [50] OPCODE_CREATE_COMMON_IFACE */ 8654d0e5007SSukumar Swaminathan struct mbx_create_common_iface { 8664d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 8674d0e5007SSukumar Swaminathan union { 8684d0e5007SSukumar Swaminathan struct { 8694d0e5007SSukumar Swaminathan uint32_t version; 8704d0e5007SSukumar Swaminathan uint32_t cap_flags; 8714d0e5007SSukumar Swaminathan uint32_t enable_flags; 8724d0e5007SSukumar Swaminathan uint8_t mac_addr[6]; 8734d0e5007SSukumar Swaminathan uint8_t rsvd0; 8744d0e5007SSukumar Swaminathan uint8_t mac_invalid; 8754d0e5007SSukumar Swaminathan struct ntwk_if_vlan_tag vlan_tag; 8764d0e5007SSukumar Swaminathan }req; 8774d0e5007SSukumar Swaminathan 8784d0e5007SSukumar Swaminathan struct { 8794d0e5007SSukumar Swaminathan uint32_t if_id; 8804d0e5007SSukumar Swaminathan uint32_t pmac_id; 8814d0e5007SSukumar Swaminathan }rsp; 8824d0e5007SSukumar Swaminathan uint32_t dw[4]; 8834d0e5007SSukumar Swaminathan }params; 8844d0e5007SSukumar Swaminathan }; 8854d0e5007SSukumar Swaminathan 8864d0e5007SSukumar Swaminathan /* [51] OPCODE_DESTROY_COMMON_IFACE */ 8874d0e5007SSukumar Swaminathan struct mbx_destroy_common_iface { 8884d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 8894d0e5007SSukumar Swaminathan union { 8904d0e5007SSukumar Swaminathan struct { 8914d0e5007SSukumar Swaminathan uint32_t if_id; 8924d0e5007SSukumar Swaminathan }req; 8934d0e5007SSukumar Swaminathan 8944d0e5007SSukumar Swaminathan struct { 8954d0e5007SSukumar Swaminathan uint32_t rsvd0; 8964d0e5007SSukumar Swaminathan }rsp; 8974d0e5007SSukumar Swaminathan 8984d0e5007SSukumar Swaminathan uint32_t dw; 8994d0e5007SSukumar Swaminathan }params; 9004d0e5007SSukumar Swaminathan }; 9014d0e5007SSukumar Swaminathan 9024d0e5007SSukumar Swaminathan /* event queue context structure */ 9034d0e5007SSukumar Swaminathan struct oce_eq_ctx { 9044d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 9054d0e5007SSukumar Swaminathan /* dw0 */ 9064d0e5007SSukumar Swaminathan uint32_t size:1; 9074d0e5007SSukumar Swaminathan uint32_t rsvd1:1; 9084d0e5007SSukumar Swaminathan uint32_t valid:1; 9094d0e5007SSukumar Swaminathan uint32_t epidx:13; 9104d0e5007SSukumar Swaminathan uint32_t rsvd0:3; 9114d0e5007SSukumar Swaminathan uint32_t cidx:13; 9124d0e5007SSukumar Swaminathan 9134d0e5007SSukumar Swaminathan /* dw1 */ 9144d0e5007SSukumar Swaminathan uint32_t armed:1; 9154d0e5007SSukumar Swaminathan uint32_t stalled:1; 9164d0e5007SSukumar Swaminathan uint32_t sol_event:1; 9174d0e5007SSukumar Swaminathan uint32_t count:3; 9184d0e5007SSukumar Swaminathan uint32_t pd:10; 9194d0e5007SSukumar Swaminathan uint32_t rsvd2:3; 9204d0e5007SSukumar Swaminathan uint32_t pidx:13; 9214d0e5007SSukumar Swaminathan 9224d0e5007SSukumar Swaminathan /* dw2 */ 9234d0e5007SSukumar Swaminathan uint32_t rsvd6:4; 9244d0e5007SSukumar Swaminathan uint32_t nodelay:1; 9254d0e5007SSukumar Swaminathan uint32_t phase:2; 9264d0e5007SSukumar Swaminathan uint32_t rsvd5:2; 9274d0e5007SSukumar Swaminathan uint32_t delay_mult:10; 9284d0e5007SSukumar Swaminathan uint32_t rsvd4:1; 9294d0e5007SSukumar Swaminathan uint32_t function:8; 9304d0e5007SSukumar Swaminathan uint32_t rsvd3:4; 9314d0e5007SSukumar Swaminathan 9324d0e5007SSukumar Swaminathan /* dw 3 */ 9334d0e5007SSukumar Swaminathan uint32_t rsvd7; 9344d0e5007SSukumar Swaminathan #else 9354d0e5007SSukumar Swaminathan /* dw0 */ 9364d0e5007SSukumar Swaminathan uint32_t cidx:13; 9374d0e5007SSukumar Swaminathan uint32_t rsvd0:3; 9384d0e5007SSukumar Swaminathan uint32_t epidx:13; 9394d0e5007SSukumar Swaminathan uint32_t valid:1; 9404d0e5007SSukumar Swaminathan uint32_t rsvd1:1; 9414d0e5007SSukumar Swaminathan uint32_t size:1; 9424d0e5007SSukumar Swaminathan 9434d0e5007SSukumar Swaminathan /* dw1 */ 9444d0e5007SSukumar Swaminathan uint32_t pidx:13; 9454d0e5007SSukumar Swaminathan uint32_t rsvd2:3; 9464d0e5007SSukumar Swaminathan uint32_t pd:10; 9474d0e5007SSukumar Swaminathan uint32_t count:3; 9484d0e5007SSukumar Swaminathan uint32_t sol_event:1; 9494d0e5007SSukumar Swaminathan uint32_t stalled:1; 9504d0e5007SSukumar Swaminathan uint32_t armed:1; 9514d0e5007SSukumar Swaminathan 9524d0e5007SSukumar Swaminathan /* dw2 */ 9534d0e5007SSukumar Swaminathan uint32_t rsvd3:4; 9544d0e5007SSukumar Swaminathan uint32_t function:8; 9554d0e5007SSukumar Swaminathan uint32_t rsvd4:1; 9564d0e5007SSukumar Swaminathan uint32_t delay_mult:10; 9574d0e5007SSukumar Swaminathan uint32_t rsvd5:2; 9584d0e5007SSukumar Swaminathan uint32_t phase:2; 9594d0e5007SSukumar Swaminathan uint32_t nodelay:1; 9604d0e5007SSukumar Swaminathan uint32_t rsvd6:4; 9614d0e5007SSukumar Swaminathan 9624d0e5007SSukumar Swaminathan /* dw3 */ 9634d0e5007SSukumar Swaminathan uint32_t rsvd7; 9644d0e5007SSukumar Swaminathan #endif 9654d0e5007SSukumar Swaminathan }; 9664d0e5007SSukumar Swaminathan 9674d0e5007SSukumar Swaminathan /* [13] OPCODE_CREATE_COMMON_EQ */ 9684d0e5007SSukumar Swaminathan struct mbx_create_common_eq { 9694d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 9704d0e5007SSukumar Swaminathan union { 9714d0e5007SSukumar Swaminathan struct { 9724d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 9734d0e5007SSukumar Swaminathan uint16_t rsvd0; 9744d0e5007SSukumar Swaminathan uint16_t num_pages; 9754d0e5007SSukumar Swaminathan #else 9764d0e5007SSukumar Swaminathan uint16_t num_pages; 9774d0e5007SSukumar Swaminathan uint16_t rsvd0; 9784d0e5007SSukumar Swaminathan #endif 9794d0e5007SSukumar Swaminathan struct oce_eq_ctx eq_ctx; 9804d0e5007SSukumar Swaminathan struct phys_addr pages[8]; 9814d0e5007SSukumar Swaminathan }req; 9824d0e5007SSukumar Swaminathan 9834d0e5007SSukumar Swaminathan struct { 9844d0e5007SSukumar Swaminathan uint16_t eq_id; 9854d0e5007SSukumar Swaminathan uint16_t rsvd0; 9864d0e5007SSukumar Swaminathan }rsp; 9874d0e5007SSukumar Swaminathan }params; 9884d0e5007SSukumar Swaminathan }; 9894d0e5007SSukumar Swaminathan 9904d0e5007SSukumar Swaminathan /* [55] OPCODE_DESTROY_COMMON_EQ */ 9914d0e5007SSukumar Swaminathan struct mbx_destroy_common_eq { 9924d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 9934d0e5007SSukumar Swaminathan union { 9944d0e5007SSukumar Swaminathan struct { 9954d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 9964d0e5007SSukumar Swaminathan uint16_t rsvd0; 9974d0e5007SSukumar Swaminathan uint16_t id; 9984d0e5007SSukumar Swaminathan #else 9994d0e5007SSukumar Swaminathan uint16_t id; 10004d0e5007SSukumar Swaminathan uint16_t rsvd0; 10014d0e5007SSukumar Swaminathan #endif 10024d0e5007SSukumar Swaminathan }req; 10034d0e5007SSukumar Swaminathan 10044d0e5007SSukumar Swaminathan struct { 10054d0e5007SSukumar Swaminathan uint32_t rsvd0; 10064d0e5007SSukumar Swaminathan }rsp; 10074d0e5007SSukumar Swaminathan }params; 10084d0e5007SSukumar Swaminathan }; 10094d0e5007SSukumar Swaminathan 10104d0e5007SSukumar Swaminathan struct oce_cq_ctx { 10114d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 10124d0e5007SSukumar Swaminathan /* dw0 */ 10134d0e5007SSukumar Swaminathan uint32_t eventable:1; 10144d0e5007SSukumar Swaminathan uint32_t sol_event:1; 10154d0e5007SSukumar Swaminathan uint32_t valid:1; 10164d0e5007SSukumar Swaminathan uint32_t count:2; 10174d0e5007SSukumar Swaminathan uint32_t rsvd1:1; 10184d0e5007SSukumar Swaminathan uint32_t epidx:11; 10194d0e5007SSukumar Swaminathan uint32_t nodelay:1; 10204d0e5007SSukumar Swaminathan uint32_t coalesce_wm:2; 10214d0e5007SSukumar Swaminathan uint32_t rsvd0:1; 10224d0e5007SSukumar Swaminathan uint32_t cidx:11; 10234d0e5007SSukumar Swaminathan 10244d0e5007SSukumar Swaminathan /* dw1 */ 10254d0e5007SSukumar Swaminathan uint32_t armed:1; 10264d0e5007SSukumar Swaminathan uint32_t stalled:1; 10274d0e5007SSukumar Swaminathan uint32_t eq_id:8; 10284d0e5007SSukumar Swaminathan uint32_t pd:10; 10294d0e5007SSukumar Swaminathan uint32_t rsvd2:1; 10304d0e5007SSukumar Swaminathan uint32_t pidx:11; 10314d0e5007SSukumar Swaminathan 10324d0e5007SSukumar Swaminathan /* dw2 */ 10334d0e5007SSukumar Swaminathan uint32_t rsvd4:20; 10344d0e5007SSukumar Swaminathan uint32_t function:8; 10354d0e5007SSukumar Swaminathan uint32_t rsvd3:4; 10364d0e5007SSukumar Swaminathan #else 10374d0e5007SSukumar Swaminathan /* dw0 */ 10384d0e5007SSukumar Swaminathan uint32_t cidx:11; 10394d0e5007SSukumar Swaminathan uint32_t rsvd0:1; 10404d0e5007SSukumar Swaminathan uint32_t coalesce_wm:2; 10414d0e5007SSukumar Swaminathan uint32_t nodelay:1; 10424d0e5007SSukumar Swaminathan uint32_t epidx:11; 10434d0e5007SSukumar Swaminathan uint32_t rsvd1:1; 10444d0e5007SSukumar Swaminathan uint32_t count:2; 10454d0e5007SSukumar Swaminathan uint32_t valid:1; 10464d0e5007SSukumar Swaminathan uint32_t sol_event:1; 10474d0e5007SSukumar Swaminathan uint32_t eventable:1; 10484d0e5007SSukumar Swaminathan 10494d0e5007SSukumar Swaminathan /* dw1 */ 10504d0e5007SSukumar Swaminathan uint32_t pidx:11; 10514d0e5007SSukumar Swaminathan uint32_t rsvd2:1; 10524d0e5007SSukumar Swaminathan uint32_t pd:10; 10534d0e5007SSukumar Swaminathan uint32_t eq_id:8; 10544d0e5007SSukumar Swaminathan uint32_t stalled:1; 10554d0e5007SSukumar Swaminathan uint32_t armed:1; 10564d0e5007SSukumar Swaminathan 10574d0e5007SSukumar Swaminathan /* dw2 */ 10584d0e5007SSukumar Swaminathan uint32_t rsvd3:4; 10594d0e5007SSukumar Swaminathan uint32_t function:8; 10604d0e5007SSukumar Swaminathan uint32_t rsvd4:20; 10614d0e5007SSukumar Swaminathan #endif 10624d0e5007SSukumar Swaminathan uint32_t rsvd5; 10634d0e5007SSukumar Swaminathan }; 10644d0e5007SSukumar Swaminathan 10654d0e5007SSukumar Swaminathan /* [12] OPCODE_CREATE_COMMON_CQ */ 10664d0e5007SSukumar Swaminathan struct mbx_create_common_cq { 10674d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 10684d0e5007SSukumar Swaminathan union { 10694d0e5007SSukumar Swaminathan struct { 10704d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 10714d0e5007SSukumar Swaminathan uint16_t rsvd0; 10724d0e5007SSukumar Swaminathan uint16_t num_pages; 10734d0e5007SSukumar Swaminathan #else 10744d0e5007SSukumar Swaminathan uint16_t num_pages; 10754d0e5007SSukumar Swaminathan uint16_t rsvd0; 10764d0e5007SSukumar Swaminathan #endif 10774d0e5007SSukumar Swaminathan struct oce_cq_ctx cq_ctx; 10788d738d7dSSukumar Swaminathan struct phys_addr pages[4]; 10794d0e5007SSukumar Swaminathan }req; 10804d0e5007SSukumar Swaminathan 10814d0e5007SSukumar Swaminathan struct { 10824d0e5007SSukumar Swaminathan uint16_t cq_id; 10834d0e5007SSukumar Swaminathan uint16_t rsvd0; 10844d0e5007SSukumar Swaminathan }rsp; 10854d0e5007SSukumar Swaminathan }params; 10864d0e5007SSukumar Swaminathan }; 10874d0e5007SSukumar Swaminathan 10884d0e5007SSukumar Swaminathan /* [54] OPCODE_DESTROY_COMMON_CQ */ 10894d0e5007SSukumar Swaminathan struct mbx_destroy_common_cq { 10904d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 10914d0e5007SSukumar Swaminathan union { 10924d0e5007SSukumar Swaminathan struct { 10934d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 10944d0e5007SSukumar Swaminathan uint16_t rsvd0; 10954d0e5007SSukumar Swaminathan uint16_t id; 10964d0e5007SSukumar Swaminathan #else 10974d0e5007SSukumar Swaminathan uint16_t id; 10984d0e5007SSukumar Swaminathan uint16_t rsvd0; 10994d0e5007SSukumar Swaminathan #endif 11004d0e5007SSukumar Swaminathan }req; 11014d0e5007SSukumar Swaminathan 11024d0e5007SSukumar Swaminathan struct { 11034d0e5007SSukumar Swaminathan uint32_t rsvd0; 11044d0e5007SSukumar Swaminathan }rsp; 11054d0e5007SSukumar Swaminathan }params; 11064d0e5007SSukumar Swaminathan }; 11074d0e5007SSukumar Swaminathan 11084d0e5007SSukumar Swaminathan struct mq_ring_ctx { 11094d0e5007SSukumar Swaminathan union { 11104d0e5007SSukumar Swaminathan struct { 11114d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 11124d0e5007SSukumar Swaminathan /* dw 0 */ 11134d0e5007SSukumar Swaminathan uint32_t cq_id:10; 11144d0e5007SSukumar Swaminathan uint32_t fetch_r2t:1; 11154d0e5007SSukumar Swaminathan uint32_t fetch_wrb:1; 11164d0e5007SSukumar Swaminathan uint32_t ring_size:4; 11174d0e5007SSukumar Swaminathan uint32_t rsvd0:2; 11184d0e5007SSukumar Swaminathan uint32_t con_index:14; 11194d0e5007SSukumar Swaminathan 11204d0e5007SSukumar Swaminathan /* dw1 */ 11214d0e5007SSukumar Swaminathan uint32_t valid:1; 11224d0e5007SSukumar Swaminathan uint32_t pdid:9; 11234d0e5007SSukumar Swaminathan uint32_t fid:8; 11244d0e5007SSukumar Swaminathan uint32_t prod_index:14; 11254d0e5007SSukumar Swaminathan 11264d0e5007SSukumar Swaminathan /* dw 2 */ 11274d0e5007SSukumar Swaminathan uint32_t rsvd1:21; 11284d0e5007SSukumar Swaminathan uint32_t async_cq_id:10; 11294d0e5007SSukumar Swaminathan uint32_t async_cq_valid:1; 11304d0e5007SSukumar Swaminathan #else 11314d0e5007SSukumar Swaminathan /* dw 0 */ 11324d0e5007SSukumar Swaminathan uint32_t con_index:14; 11334d0e5007SSukumar Swaminathan uint32_t rsvd0:2; 11344d0e5007SSukumar Swaminathan uint32_t ring_size:4; 11354d0e5007SSukumar Swaminathan uint32_t fetch_wrb:1; 11364d0e5007SSukumar Swaminathan uint32_t fetch_r2t:1; 11374d0e5007SSukumar Swaminathan uint32_t cq_id:10; 11384d0e5007SSukumar Swaminathan 11394d0e5007SSukumar Swaminathan /* dw1 */ 11404d0e5007SSukumar Swaminathan uint32_t prod_index:14; 11414d0e5007SSukumar Swaminathan uint32_t fid:8; 11424d0e5007SSukumar Swaminathan uint32_t pdid:9; 11434d0e5007SSukumar Swaminathan uint32_t valid:1; 11444d0e5007SSukumar Swaminathan 11454d0e5007SSukumar Swaminathan /* dw 2 */ 11464d0e5007SSukumar Swaminathan uint32_t async_cq_valid:1; 11474d0e5007SSukumar Swaminathan uint32_t async_cq_id:10; 11484d0e5007SSukumar Swaminathan uint32_t rsvd1:21; 11494d0e5007SSukumar Swaminathan #endif 11504d0e5007SSukumar Swaminathan /* dw3 */ 11514d0e5007SSukumar Swaminathan uint32_t rsvd3; 11524d0e5007SSukumar Swaminathan }s; 11534d0e5007SSukumar Swaminathan uint32_t dw[4]; 11544d0e5007SSukumar Swaminathan }u0; 11554d0e5007SSukumar Swaminathan }; 11564d0e5007SSukumar Swaminathan 11574d0e5007SSukumar Swaminathan /* [21] OPCODE_CREATE_COMMON_MQ */ 11584d0e5007SSukumar Swaminathan struct mbx_create_common_mq { 11594d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 11604d0e5007SSukumar Swaminathan union { 11614d0e5007SSukumar Swaminathan struct { 11624d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 11634d0e5007SSukumar Swaminathan uint16_t rsvd0; 11644d0e5007SSukumar Swaminathan uint16_t num_pages; 11654d0e5007SSukumar Swaminathan #else 11664d0e5007SSukumar Swaminathan uint16_t num_pages; 11674d0e5007SSukumar Swaminathan uint16_t rsvd0; 11684d0e5007SSukumar Swaminathan #endif 11694d0e5007SSukumar Swaminathan struct mq_ring_ctx context; 11704d0e5007SSukumar Swaminathan struct phys_addr pages[8]; 11714d0e5007SSukumar Swaminathan }req; 11724d0e5007SSukumar Swaminathan 11734d0e5007SSukumar Swaminathan struct { 11744d0e5007SSukumar Swaminathan uint32_t mq_id:16; 11754d0e5007SSukumar Swaminathan uint32_t rsvd0:16; 11764d0e5007SSukumar Swaminathan }rsp; 11774d0e5007SSukumar Swaminathan }params; 11784d0e5007SSukumar Swaminathan }; 11794d0e5007SSukumar Swaminathan 11804d0e5007SSukumar Swaminathan /* [53] OPCODE_DESTROY_COMMON_MQ */ 11814d0e5007SSukumar Swaminathan struct mbx_destroy_common_mq { 11824d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 11834d0e5007SSukumar Swaminathan union { 11844d0e5007SSukumar Swaminathan struct { 11854d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 11864d0e5007SSukumar Swaminathan uint16_t rsvd0; 11874d0e5007SSukumar Swaminathan uint16_t id; 11884d0e5007SSukumar Swaminathan #else 11894d0e5007SSukumar Swaminathan uint16_t id; 11904d0e5007SSukumar Swaminathan uint16_t rsvd0; 11914d0e5007SSukumar Swaminathan #endif 11924d0e5007SSukumar Swaminathan }req; 11934d0e5007SSukumar Swaminathan 11944d0e5007SSukumar Swaminathan struct { 11954d0e5007SSukumar Swaminathan uint32_t rsvd0; 11964d0e5007SSukumar Swaminathan }rsp; 11974d0e5007SSukumar Swaminathan }params; 11984d0e5007SSukumar Swaminathan }; 11994d0e5007SSukumar Swaminathan 12004d0e5007SSukumar Swaminathan /* [35] OPCODE_GET_COMMON_ FW_VERSION */ 12014d0e5007SSukumar Swaminathan struct mbx_get_common_fw_version { 12024d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 12034d0e5007SSukumar Swaminathan union { 12044d0e5007SSukumar Swaminathan struct { 12054d0e5007SSukumar Swaminathan uint32_t rsvd0; 12064d0e5007SSukumar Swaminathan }req; 12074d0e5007SSukumar Swaminathan 12084d0e5007SSukumar Swaminathan struct { 12094d0e5007SSukumar Swaminathan uint8_t fw_ver_str[32]; 12104d0e5007SSukumar Swaminathan uint8_t fw_on_flash_ver_str[32]; 12114d0e5007SSukumar Swaminathan }rsp; 12124d0e5007SSukumar Swaminathan }params; 12134d0e5007SSukumar Swaminathan }; 12144d0e5007SSukumar Swaminathan 12154d0e5007SSukumar Swaminathan /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */ 12164d0e5007SSukumar Swaminathan struct mbx_common_cev_modify_msi_messages { 12174d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 12184d0e5007SSukumar Swaminathan union { 12194d0e5007SSukumar Swaminathan struct { 12204d0e5007SSukumar Swaminathan uint32_t num_msi_msgs; 12214d0e5007SSukumar Swaminathan }req; 12224d0e5007SSukumar Swaminathan 12234d0e5007SSukumar Swaminathan struct { 12244d0e5007SSukumar Swaminathan uint32_t rsvd0; 12254d0e5007SSukumar Swaminathan }rsp; 12264d0e5007SSukumar Swaminathan }params; 12274d0e5007SSukumar Swaminathan }; 12284d0e5007SSukumar Swaminathan 12294d0e5007SSukumar Swaminathan /* [36] OPCODE_SET_COMMON_FLOW_CONTROL */ 12304d0e5007SSukumar Swaminathan /* [37] OPCODE_GET_COMMON_FLOW_CONTROL */ 12314d0e5007SSukumar Swaminathan struct mbx_common_get_set_flow_control { 12324d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 12334d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 12344d0e5007SSukumar Swaminathan uint16_t tx_flow_control; 12354d0e5007SSukumar Swaminathan uint16_t rx_flow_control; 12364d0e5007SSukumar Swaminathan #else 12374d0e5007SSukumar Swaminathan uint16_t rx_flow_control; 12384d0e5007SSukumar Swaminathan uint16_t tx_flow_control; 12394d0e5007SSukumar Swaminathan #endif 12404d0e5007SSukumar Swaminathan }; 12414d0e5007SSukumar Swaminathan 12424d0e5007SSukumar Swaminathan enum e_flash_opcode { 12434d0e5007SSukumar Swaminathan MGMT_FLASHROM_OPCODE_FLASH = 1, 12444d0e5007SSukumar Swaminathan MGMT_FLASHROM_OPCODE_SAVE = 2 12454d0e5007SSukumar Swaminathan }; 12464d0e5007SSukumar Swaminathan 12474d0e5007SSukumar Swaminathan /* [06] OPCODE_READ_COMMON_FLASHROM */ 12484d0e5007SSukumar Swaminathan /* [07] OPCODE_WRITE_COMMON_FLASHROM */ 12494d0e5007SSukumar Swaminathan 12504d0e5007SSukumar Swaminathan struct mbx_common_read_write_flashrom { 12514d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 12524d0e5007SSukumar Swaminathan uint32_t flash_op_code; 12534d0e5007SSukumar Swaminathan uint32_t flash_op_type; 12544d0e5007SSukumar Swaminathan uint32_t data_buffer_size; 12554d0e5007SSukumar Swaminathan uint32_t data_offset; 12564d0e5007SSukumar Swaminathan uint8_t data_buffer[4]; /* + IMAGE_TRANSFER_SIZE */ 12574d0e5007SSukumar Swaminathan }; 12584d0e5007SSukumar Swaminathan 12595b9d3151SSukumar Swaminathan /* ULP MODE SUPPORTED */ 12605b9d3151SSukumar Swaminathan enum { 12615b9d3151SSukumar Swaminathan ULP_TOE_MODE = 0x1, 12625b9d3151SSukumar Swaminathan ULP_NIC_MODE = 0x2, 12635b9d3151SSukumar Swaminathan ULP_RDMA_MODE = 0x4, 12645b9d3151SSukumar Swaminathan ULP_ISCSI_INI_MODE = 0x10, 12655b9d3151SSukumar Swaminathan ULP_ISCSI_TGT_MODE = 0x20, 12665b9d3151SSukumar Swaminathan ULP_FCOE_INI_MODE = 0x40, 12675b9d3151SSukumar Swaminathan ULP_FCOE_TGT_MODE = 0x80, 12685b9d3151SSukumar Swaminathan ULP_DAL_MODE = 0x100, 12695b9d3151SSukumar Swaminathan ULP_LRO_MODE = 0x200 12705b9d3151SSukumar Swaminathan }; 12715b9d3151SSukumar Swaminathan 12725b9d3151SSukumar Swaminathan /* Function Mode Supported */ 12735b9d3151SSukumar Swaminathan enum { 12745b9d3151SSukumar Swaminathan TOE_MODE = 0x1, /* TCP offload */ 12755b9d3151SSukumar Swaminathan NIC_MODE = 0x2, /* Raw Ethernet */ 12765b9d3151SSukumar Swaminathan RDMA_MODE = 0x4, /* RDMA */ 12775b9d3151SSukumar Swaminathan VM_MODE = 0x8, /* VM */ 12785b9d3151SSukumar Swaminathan ISCSI_INI_MODE = 0x10, /* iSCSI initiator */ 12795b9d3151SSukumar Swaminathan ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */ 12805b9d3151SSukumar Swaminathan FCOE_INI_MODE = 0x40, /* FCoE Initiator */ 12815b9d3151SSukumar Swaminathan FCOE_TGT_MODE = 0x80, /* FCoE target */ 12825b9d3151SSukumar Swaminathan DAL_MODE = 0x100, /* DAL */ 12835b9d3151SSukumar Swaminathan LRO_MODE = 0x200, /* LRO */ 12845b9d3151SSukumar Swaminathan FLEX10_MODE = 0x400, /* FLEX-10 or VNIC */ 12855b9d3151SSukumar Swaminathan NCSI_MODE = 0x800, /* NCSI */ 12865b9d3151SSukumar Swaminathan INVALID_MODE = 0x8000 /* Invalid */ 12875b9d3151SSukumar Swaminathan }; 12885b9d3151SSukumar Swaminathan 12894d0e5007SSukumar Swaminathan struct mbx_common_query_fw_config { 12904d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 12914d0e5007SSukumar Swaminathan union { 12924d0e5007SSukumar Swaminathan struct { 12934d0e5007SSukumar Swaminathan uint32_t rsvd0[30]; 12944d0e5007SSukumar Swaminathan }req; 12954d0e5007SSukumar Swaminathan 12964d0e5007SSukumar Swaminathan struct { 12974d0e5007SSukumar Swaminathan uint32_t config_number; 12984d0e5007SSukumar Swaminathan uint32_t asic_revision; 12994d0e5007SSukumar Swaminathan uint32_t port_id; /* used for stats retrieval */ 13004d0e5007SSukumar Swaminathan uint32_t function_mode; 13015b9d3151SSukumar Swaminathan struct { 13025b9d3151SSukumar Swaminathan 13035b9d3151SSukumar Swaminathan uint32_t mode; 13045b9d3151SSukumar Swaminathan uint32_t wq_base; 13055b9d3151SSukumar Swaminathan uint32_t wq_count; 13065b9d3151SSukumar Swaminathan uint32_t sq_base; 13075b9d3151SSukumar Swaminathan uint32_t sq_count; 13085b9d3151SSukumar Swaminathan uint32_t rq_base; 13095b9d3151SSukumar Swaminathan uint32_t rq_count; 13105b9d3151SSukumar Swaminathan uint32_t dq_base; 13115b9d3151SSukumar Swaminathan uint32_t dq_count; 13125b9d3151SSukumar Swaminathan uint32_t lro_base; 13135b9d3151SSukumar Swaminathan uint32_t lro_count; 13145b9d3151SSukumar Swaminathan uint32_t icd_base; 13155b9d3151SSukumar Swaminathan uint32_t icd_count; 13165b9d3151SSukumar Swaminathan } ulp[2]; 13175b9d3151SSukumar Swaminathan uint32_t function_caps; 13184d0e5007SSukumar Swaminathan }rsp; 13194d0e5007SSukumar Swaminathan }params; 13204d0e5007SSukumar Swaminathan }; 13214d0e5007SSukumar Swaminathan 13224d0e5007SSukumar Swaminathan struct mbx_common_config_vlan { 13234d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 13244d0e5007SSukumar Swaminathan union { 13254d0e5007SSukumar Swaminathan struct { 13264d0e5007SSukumar Swaminathan #ifdef _BIG_ENDIAN 13274d0e5007SSukumar Swaminathan uint8_t num_vlans; 13284d0e5007SSukumar Swaminathan uint8_t untagged; 13294d0e5007SSukumar Swaminathan uint8_t promisc; 13304d0e5007SSukumar Swaminathan uint8_t if_id; 13314d0e5007SSukumar Swaminathan #else 13324d0e5007SSukumar Swaminathan uint8_t if_id; 13334d0e5007SSukumar Swaminathan uint8_t promisc; 13344d0e5007SSukumar Swaminathan uint8_t untagged; 13354d0e5007SSukumar Swaminathan uint8_t num_vlans; 13364d0e5007SSukumar Swaminathan #endif 13374d0e5007SSukumar Swaminathan union { 13384d0e5007SSukumar Swaminathan struct normal_vlan normal_vlans[64]; 13394d0e5007SSukumar Swaminathan struct qinq_vlan qinq_vlans[32]; 13404d0e5007SSukumar Swaminathan }tags; 13414d0e5007SSukumar Swaminathan }req; 13424d0e5007SSukumar Swaminathan 13434d0e5007SSukumar Swaminathan struct { 13444d0e5007SSukumar Swaminathan uint32_t rsvd; 13454d0e5007SSukumar Swaminathan }rsp; 13464d0e5007SSukumar Swaminathan }params; 13474d0e5007SSukumar Swaminathan }; 13484d0e5007SSukumar Swaminathan 13494d0e5007SSukumar Swaminathan /* [34] OPCODE_COMMON_NTWK_RX_FILTER */ 13504d0e5007SSukumar Swaminathan struct mbx_set_common_ntwk_rx_filter { 13514d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 13524d0e5007SSukumar Swaminathan uint32_t global_flags_mask; 13534d0e5007SSukumar Swaminathan uint32_t global_flags; 13544d0e5007SSukumar Swaminathan uint32_t iface_flags_mask; 13554d0e5007SSukumar Swaminathan uint32_t iface_flags; 13564d0e5007SSukumar Swaminathan uint32_t if_id; 13574d0e5007SSukumar Swaminathan uint32_t num_mcast; 13584d0e5007SSukumar Swaminathan struct { 13594d0e5007SSukumar Swaminathan uint8_t byte[6]; 13604d0e5007SSukumar Swaminathan }mac[32]; 13614d0e5007SSukumar Swaminathan }; 13624d0e5007SSukumar Swaminathan /* [41] OPCODE_MODIFY_COMMON_EQ_DELAY */ 13634d0e5007SSukumar Swaminathan struct mbx_modify_common_eq_delay { 13644d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 13654d0e5007SSukumar Swaminathan union { 13664d0e5007SSukumar Swaminathan struct { 13674d0e5007SSukumar Swaminathan uint32_t num_eq; 13684d0e5007SSukumar Swaminathan struct { 13694d0e5007SSukumar Swaminathan uint32_t eq_id; 13704d0e5007SSukumar Swaminathan uint32_t phase; 13714d0e5007SSukumar Swaminathan uint32_t dm; 13724d0e5007SSukumar Swaminathan }delay[8]; 13734d0e5007SSukumar Swaminathan }req; 13744d0e5007SSukumar Swaminathan 13754d0e5007SSukumar Swaminathan struct { 13764d0e5007SSukumar Swaminathan uint32_t rsvd0; 13774d0e5007SSukumar Swaminathan }rsp; 13784d0e5007SSukumar Swaminathan }params; 13794d0e5007SSukumar Swaminathan }; 13804d0e5007SSukumar Swaminathan /* [59] OPCODE_ADD_COMMON_IFACE_MAC */ 13814d0e5007SSukumar Swaminathan struct mbx_add_common_iface_mac { 13824d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 13834d0e5007SSukumar Swaminathan union { 13844d0e5007SSukumar Swaminathan struct { 13854d0e5007SSukumar Swaminathan uint32_t if_id; 13864d0e5007SSukumar Swaminathan uint8_t mac_address[6]; 13874d0e5007SSukumar Swaminathan uint8_t rsvd0[2]; 13884d0e5007SSukumar Swaminathan }req; 13894d0e5007SSukumar Swaminathan struct { 13904d0e5007SSukumar Swaminathan uint32_t pmac_id; 13914d0e5007SSukumar Swaminathan }rsp; 13924d0e5007SSukumar Swaminathan } params; 13934d0e5007SSukumar Swaminathan }; 13944d0e5007SSukumar Swaminathan 13954d0e5007SSukumar Swaminathan /* [60] OPCODE_DEL_COMMON_IFACE_MAC */ 13964d0e5007SSukumar Swaminathan struct mbx_del_common_iface_mac { 13974d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 13984d0e5007SSukumar Swaminathan union { 13994d0e5007SSukumar Swaminathan struct { 14004d0e5007SSukumar Swaminathan uint32_t if_id; 14014d0e5007SSukumar Swaminathan uint32_t pmac_id; 14024d0e5007SSukumar Swaminathan }req; 14034d0e5007SSukumar Swaminathan struct { 14044d0e5007SSukumar Swaminathan uint32_t rsvd0; 14054d0e5007SSukumar Swaminathan }rsp; 14064d0e5007SSukumar Swaminathan } params; 14074d0e5007SSukumar Swaminathan }; 14084d0e5007SSukumar Swaminathan 14094d0e5007SSukumar Swaminathan /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */ 14104d0e5007SSukumar Swaminathan struct mbx_query_common_max_mbx_buffer_size { 14114d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 14124d0e5007SSukumar Swaminathan struct { 14134d0e5007SSukumar Swaminathan uint32_t max_ioctl_bufsz; 14144d0e5007SSukumar Swaminathan } rsp; 14154d0e5007SSukumar Swaminathan }; 14164d0e5007SSukumar Swaminathan 14174d0e5007SSukumar Swaminathan /* [61] OPCODE_COMMON_FUNCTION_RESET */ 14184d0e5007SSukumar Swaminathan struct ioctl_common_function_reset { 14194d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 14204d0e5007SSukumar Swaminathan }; 14214d0e5007SSukumar Swaminathan 14224d0e5007SSukumar Swaminathan /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */ 14234d0e5007SSukumar Swaminathan struct mbx_common_func_link_cfg { 14244d0e5007SSukumar Swaminathan struct mbx_hdr hdr; 14254d0e5007SSukumar Swaminathan union { 14264d0e5007SSukumar Swaminathan struct { 14274d0e5007SSukumar Swaminathan uint32_t enable; 14284d0e5007SSukumar Swaminathan }req; 14294d0e5007SSukumar Swaminathan struct { 14304d0e5007SSukumar Swaminathan uint32_t rsvd0; 14314d0e5007SSukumar Swaminathan }rsp; 14324d0e5007SSukumar Swaminathan } params; 14334d0e5007SSukumar Swaminathan }; 14344d0e5007SSukumar Swaminathan 14354d0e5007SSukumar Swaminathan #pragma pack() 14364d0e5007SSukumar Swaminathan 14374d0e5007SSukumar Swaminathan #ifdef __cplusplus 14384d0e5007SSukumar Swaminathan } 14394d0e5007SSukumar Swaminathan #endif 14404d0e5007SSukumar Swaminathan 14414d0e5007SSukumar Swaminathan #endif /* _OCE_HW_H_ */ 1442