1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _EMLXS_OS_H 28 #define _EMLXS_OS_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #define EMLXS_MODREV2 2 /* Old Solaris 8 & 9 interface */ 35 #define EMLXS_MODREV3 3 /* New Solaris 10 & 11 interface */ 36 #define EMLXS_MODREV4 4 /* Sun FC packet change */ 37 /* Symbolic Node Name interface */ 38 #define EMLXS_MODREV5 5 /* New Sun NPIV Interface */ 39 40 #define EMLXS_MODREV2X 2 /* Old Solaris 8 & 9 x86 interface */ 41 #define EMLXS_MODREV3X 3 /* New Solaris 10 & 11 x86 interface */ 42 43 44 /* 45 * DRIVER LEVEL FEATURES 46 */ 47 #define DHCHAP_SUPPORT /* 2.21 driver */ 48 49 #define SATURN_MSI_SUPPORT /* 2.30 driver */ 50 #define MENLO_SUPPORT /* 2.30 driver */ 51 #define MBOX_EXT_SUPPORT /* 2.30 driver */ 52 53 #define DUMP_SUPPORT /* 2.40 driver */ 54 #define SAN_DIAG_SUPPORT /* 2.40 driver */ 55 #define FMA_SUPPORT /* 2.40 driver */ 56 57 /* #define IDLE_TIMER Not yet - untested */ 58 59 /* 60 * OS LEVEL FEATURES 61 */ 62 #ifdef S10 63 #define EMLXS_MODREV EMLXS_MODREV3 64 #define MSI_SUPPORT 65 66 67 #ifdef EMLXS_I386 68 #define EMLXS_MODREVX EMLXS_MODREV2X 69 #endif /* i386 */ 70 #endif /* S10 */ 71 72 73 #ifdef S11 74 #define MSI_SUPPORT 75 #define SFCT_SUPPORT /* COMSTAR Support */ 76 #define MODFW_SUPPORT /* Dynamic firmware module support */ 77 #define EMLXS_MODREV EMLXS_MODREV5 /* Sun NPIV Enhancement */ 78 79 #ifdef EMLXS_I386 80 #define EMLXS_MODREVX EMLXS_MODREV2X 81 #endif /* i386 */ 82 #endif /* S11 */ 83 84 /* 85 * SUBFEATURES 86 */ 87 #ifdef SFCT_SUPPORT 88 #define MODSYM_SUPPORT /* Dynamic Module Loading Support */ 89 #define FCIO_SUPPORT /* FCIO IOCTL support */ 90 #endif /* SFCT_SUPPORT */ 91 92 93 #ifndef EMLXS_MODREV 94 #define EMLXS_MODREV 0 95 #endif /* EMLXS_MODREV */ 96 97 #ifndef EMLXS_MODREVX 98 #define EMLXS_MODREVX 0 99 #endif /* EMLXS_MODREVX */ 100 101 /* Create combined definition */ 102 #if defined(S10) || defined(S11) 103 #define S10S11 104 #endif /* S10 or S11 */ 105 106 #define DRIVER_NAME "emlxs" 107 108 #include <sys/types.h> 109 #include <sys/varargs.h> 110 #include <sys/devops.h> 111 #include <sys/param.h> 112 #include <sys/user.h> 113 #include <sys/buf.h> 114 #include <sys/ioctl.h> 115 #include <sys/uio.h> 116 #include <sys/fcntl.h> 117 118 #include <sys/cmn_err.h> 119 #include <sys/stropts.h> 120 #include <sys/kmem.h> 121 122 #include <sys/errno.h> 123 #include <sys/open.h> 124 #include <sys/kmem.h> 125 #include <sys/poll.h> 126 #include <sys/thread.h> 127 #include <sys/taskq.h> 128 #include <sys/debug.h> 129 #include <sys/cpu.h> 130 #include <sys/autoconf.h> 131 #include <sys/conf.h> 132 #include <sys/stat.h> 133 #include <sys/var.h> 134 135 #include <sys/map.h> 136 #include <sys/file.h> 137 #include <sys/syslog.h> 138 #include <sys/disp.h> 139 #include <sys/taskq.h> 140 141 #include <sys/ddi.h> 142 #include <sys/sunddi.h> 143 #include <sys/promif.h> 144 #include <sys/ethernet.h> 145 #include <vm/seg_kmem.h> 146 #include <sys/utsname.h> 147 #include <sys/modctl.h> 148 #include <sys/scsi/scsi.h> 149 #include <sys/varargs.h> 150 #include <sys/atomic.h> 151 #ifdef S11 152 #include <sys/pci.h> 153 #else /* !S11 */ 154 /* 155 * Capabilities linked list entry offsets 156 */ 157 #define PCI_CAP_ID 0x0 /* capability identifier, 1 byte */ 158 #define PCI_CAP_NEXT_PTR 0x1 /* next entry pointer, 1 byte */ 159 #define PCI_CAP_ID_REGS_OFF 0x2 /* cap id register offset */ 160 #define PCI_CAP_MAX_PTR 0x30 /* maximum number of cap pointers */ 161 #define PCI_CAP_PTR_OFF 0x40 /* minimum cap pointer offset */ 162 #define PCI_CAP_PTR_MASK 0xFC /* mask for capability pointer */ 163 164 /* 165 * Capability identifier values 166 */ 167 #define PCI_CAP_ID_PM 0x1 /* power management entry */ 168 #define PCI_CAP_ID_AGP 0x2 /* AGP supported */ 169 #define PCI_CAP_ID_VPD 0x3 /* VPD supported */ 170 #define PCI_CAP_ID_SLOT_ID 0x4 /* Slot Identification supported */ 171 #define PCI_CAP_ID_MSI 0x5 /* MSI supported */ 172 #define PCI_CAP_ID_cPCI_HS 0x6 /* CompactPCI Host Swap supported */ 173 #define PCI_CAP_ID_PCIX 0x7 /* PCI-X supported */ 174 #define PCI_CAP_ID_HT 0x8 /* HyperTransport supported */ 175 #define PCI_CAP_ID_VS 0x9 /* Vendor Specific */ 176 #define PCI_CAP_ID_DEBUG_PORT 0xA /* Debug Port supported */ 177 #define PCI_CAP_ID_cPCI_CRC 0xB /* CompactPCI central resource ctrl */ 178 #define PCI_CAP_ID_PCI_HOTPLUG 0xC /* PCI Hot Plug supported */ 179 #define PCI_CAP_ID_P2P_SUBSYS 0xD /* PCI bridge Sub-system ID */ 180 #define PCI_CAP_ID_AGP_8X 0xE /* AGP 8X supported */ 181 #define PCI_CAP_ID_SECURE_DEV 0xF /* Secure Device supported */ 182 #define PCI_CAP_ID_PCI_E 0x10 /* PCI Express supported */ 183 #define PCI_CAP_ID_MSI_X 0x11 /* MSI-X supported */ 184 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Config supported */ 185 #define PCI_CAP_ID_FLR 0x13 /* Function Level Reset supported */ 186 187 /* 188 * PCI power management (PM) capability entry offsets 189 */ 190 #define PCI_PMCAP 0x2 /* PM capabilities, 2 bytes */ 191 #define PCI_PMCSR 0x4 /* PM control/status reg, 2 bytes */ 192 #define PCI_PMCSR_BSE 0x6 /* PCI-PCI bridge extensions, 1 byte */ 193 #define PCI_PMDATA 0x7 /* PM data, 1 byte */ 194 195 /* 196 * PM control/status values - 2 bytes 197 */ 198 #define PCI_PMCSR_D0 0x0 /* power state D0 */ 199 #define PCI_PMCSR_D1 0x1 /* power state D1 */ 200 #define PCI_PMCSR_D2 0x2 /* power state D2 */ 201 #define PCI_PMCSR_D3HOT 0x3 /* power state D3hot */ 202 #endif /* S11 */ 203 204 #include <emlxs_hbaapi.h> 205 206 #ifdef FMA_SUPPORT 207 #include <sys/ddifm.h> 208 #include <sys/fm/protocol.h> 209 #include <sys/fm/util.h> 210 #endif /* FMA_SUPPORT */ 211 #include <sys/fm/io/ddi.h> 212 213 #ifdef S11 214 215 /* ULP header files */ 216 #include <sys/fibre-channel/fc.h> 217 #include <sys/fibre-channel/impl/fc_fcaif.h> 218 219 #else /* !S11 */ 220 221 /* ULP header files */ 222 #include <sys/fibre-channel/fcio.h> 223 #include <sys/fibre-channel/fc.h> 224 #include <sys/fibre-channel/fc_appif.h> 225 #include <sys/fibre-channel/fc_types.h> 226 #include <sys/fibre-channel/impl/fc_error.h> 227 #include <sys/fibre-channel/impl/fc_fla.h> 228 #include <sys/fibre-channel/impl/fc_linkapp.h> 229 #include <sys/fibre-channel/impl/fcal.h> 230 #include <sys/fibre-channel/impl/fcgs2.h> 231 #include <sys/fibre-channel/impl/fcph.h> 232 #include <sys/fibre-channel/impl/fc_ulpif.h> 233 #include <sys/fibre-channel/impl/fc_fcaif.h> 234 #include <sys/fibre-channel/impl/fctl.h> 235 #include <sys/fibre-channel/impl/fctl_private.h> 236 #include <sys/fibre-channel/ulp/fcp.h> 237 #include <sys/fibre-channel/ulp/fcp_util.h> 238 239 #endif /* S11 */ 240 241 #ifndef FC_HBA_PORTSPEED_8GBIT 242 #define FC_HBA_PORTSPEED_8GBIT 16 243 #endif /* FC_HBA_PORTSPEED_8GBIT */ 244 245 #ifndef FP_DEFAULT_SID 246 #define FP_DEFAULT_SID (0x000AE) 247 #endif /* FP_DEFAULT_SID */ 248 249 #ifndef FP_DEFAULT_DID 250 #define FP_DEFAULT_DID (0x000EA) 251 #endif /* FP_DEFAULT_DID */ 252 253 #ifdef MSI_SUPPORT 254 #pragma weak ddi_intr_get_supported_types 255 #pragma weak ddi_intr_get_nintrs 256 #pragma weak ddi_intr_add_handler 257 #pragma weak ddi_intr_remove_handler 258 #pragma weak ddi_intr_get_hilevel_pri 259 #pragma weak ddi_intr_enable 260 #pragma weak ddi_intr_disable 261 #pragma weak ddi_intr_get_cap 262 #pragma weak ddi_intr_get_pri 263 #pragma weak ddi_intr_alloc 264 #pragma weak ddi_intr_free 265 #pragma weak ddi_intr_block_enable 266 #pragma weak ddi_intr_block_disable 267 extern int ddi_intr_get_supported_types(); 268 #endif /* MSI_SUPPORT */ 269 270 #ifndef MODSYM_SUPPORT 271 #pragma weak fc_fca_init 272 #pragma weak fc_fca_attach 273 #pragma weak fc_fca_detach 274 #endif /* MODSYM_SUPPORT */ 275 276 /* S11 flag for dma_attr_flags for ddi_dma_attr_t */ 277 #ifndef DDI_DMA_RELAXED_ORDERING 278 #define DDI_DMA_RELAXED_ORDERING 0x400 279 #endif /* DDI_DMA_RELAXED_ORDERING */ 280 281 #ifdef FMA_SUPPORT 282 /* FMA Support */ 283 #pragma weak ddi_fm_acc_err_clear 284 extern void ddi_fm_acc_err_clear(); 285 #endif /* FMA_SUPPORT */ 286 287 #ifdef EMLXS_SPARC 288 #define EMLXS_BIG_ENDIAN 289 #endif /* EMLXS_SPARC */ 290 291 #ifdef EMLXS_I386 292 #define EMLXS_LITTLE_ENDIAN 293 #endif /* EMLXS_I386 */ 294 295 296 /* Solaris 8 does not define this */ 297 #ifndef TASKQ_DYNAMIC 298 #define TASKQ_DYNAMIC 0x0004 299 #endif /* TASKQ_DYNAMIC */ 300 301 #ifdef _LP64 302 #define DEAD_PTR 0xdeadbeefdeadbeef 303 #else 304 #define DEAD_PTR 0xdeadbeef 305 #endif /* _LP64 */ 306 307 #ifndef FC_STATE_8GBIT_SPEED 308 /* This was obtained from OpenSolaris */ 309 #define FC_STATE_8GBIT_SPEED 0x0700 /* 8 Gbit/sec */ 310 #endif /* FC_STATE_8GBIT_SPEED */ 311 312 #define FC_STATE_QUAD_SPEED 0x0500 313 314 #ifndef BURSTSIZE 315 #define BURSTSIZE 316 #define BURST1 0x01 317 #define BURST2 0x02 318 #define BURST4 0x04 319 #define BURST8 0x08 320 #define BURST16 0x10 321 #define BURST32 0x20 322 #define BURST64 0x40 323 #ifdef _LP64 324 #define BURSTSIZE_MASK 0x7f 325 #else 326 #define BURSTSIZE_MASK 0x3f 327 #endif /* _LP64 */ 328 #define DEFAULT_BURSTSIZE (BURSTSIZE_MASK) /* all burst sizes */ 329 #endif /* BURSTSIZE */ 330 331 #define PADDR_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xffffffff)) 332 #define PADDR_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 333 #define PADDR(high, low) ((uint64_t)((((uint64_t)(high)) << 32) \ 334 | (((uint64_t)(low)) & 0xffffffff))) 335 336 #ifndef TRUE 337 #define TRUE 1 338 #endif /* TRUE */ 339 340 #ifndef FALSE 341 #define FALSE 0 342 #endif /* FALSE */ 343 344 #define DMA_READ_WRITE 0 345 #define DMA_READ_ONLY 1 346 #define DMA_WRITE_ONLY 2 347 348 #define DMA_SUCC 1 349 350 #define MAX_FC_BRDS 256 /* Maximum # boards per system */ 351 352 #define DELAYMS(ms) drv_usecwait((ms*1000)) 353 #define DELAYUS(us) drv_usecwait(us) 354 355 #define EMLXS_MPDATA_SYNC(h, a, b, c) \ 356 if (h) { \ 357 (void) ddi_dma_sync((ddi_dma_handle_t)(h), \ 358 (off_t)(a), (size_t)(b), (uint_t)c); \ 359 } 360 361 #define PKT2PRIV(pkt) ((emlxs_buf_t *)(pkt)->pkt_fca_private) 362 #define PRIV2PKT(sbp) sbp->pkt 363 364 #define EMLXS_INUMBER 0 365 #define EMLXS_MSI_INUMBER 0 366 367 #define EMLXS_DMA_ALIGN BURST16 368 369 /* 370 * Register indices in PCI configuration space. 371 */ 372 #define SBUS_FLASH_RD 0 /* FCODE-Flash Read only */ 373 /* index */ 374 #define SBUS_FLASH_RDWR 1 /* FCODE-Flash Read/Write */ 375 /* index */ 376 #define SBUS_DFLY_SLIM_RINDEX 2 /* DragonFly SLIM regs index */ 377 #define SBUS_DFLY_CSR_RINDEX 3 /* DragonFly I/O regs index */ 378 #define SBUS_TITAN_CORE_RINDEX 4 /* TITAN Core register index */ 379 #define SBUS_DFLY_PCI_CFG_RINDEX 5 /* DragonFly PCI ConfigSpace */ 380 /* regs index */ 381 #define SBUS_TITAN_PCI_CFG_RINDEX 6 /* TITAN PCI ConfigSpace regs */ 382 /* index */ 383 #define SBUS_TITAN_CSR_RINDEX 7 /* TITAN Control/Status regs */ 384 /* index */ 385 386 #define PCI_CFG_RINDEX 0 387 #define PCI_SLIM_RINDEX 1 388 #define PCI_CSR_RINDEX 2 389 390 #define PCI_BAR1_RINDEX 2 391 #define PCI_BAR2_RINDEX 3 392 393 394 #define EMLXS_MAX_UBUFS 65535 395 396 /* Tokens < EMLXS_UB_TOKEN_OFFSET are reserved for ELS response oxids */ 397 #define EMLXS_UB_TOKEN_OFFSET 0x100 398 399 typedef struct emlxs_ub_priv 400 { 401 fc_unsol_buf_t *ubp; 402 void *port; 403 404 uint32_t bpl_size; 405 uint8_t *bpl_virt; /* virtual address ptr */ 406 uint64_t bpl_phys; /* mapped address */ 407 void *bpl_data_handle; 408 void *bpl_dma_handle; 409 410 uint32_t ip_ub_size; 411 uint8_t *ip_ub_virt; /* virtual address ptr */ 412 ddi_dma_cookie_t ip_ub_dma_cookies[64]; 413 ddi_acc_handle_t ip_ub_data_handle; 414 ddi_dma_handle_t ip_ub_dma_handle; 415 uint32_t ip_ub_cookie_cnt; 416 uint32_t FC4type; 417 418 uint16_t flags; 419 #define EMLXS_UB_FREE 0x0000 420 #define EMLXS_UB_IN_USE 0x0001 421 #define EMLXS_UB_REPLY 0x0002 422 #define EMLXS_UB_RESV 0x0004 423 #define EMLXS_UB_TIMEOUT 0x0008 424 #define EMLXS_UB_INTERCEPT 0x0010 425 426 uint16_t available; 427 428 uint32_t timeout; /* Timeout period in seconds */ 429 uint32_t time; /* EMLXS_UB_IN_USE timestamp */ 430 uint32_t cmd; 431 uint32_t token; 432 433 struct emlxs_unsol_buf *pool; 434 struct emlxs_ub_priv *next; 435 } emlxs_ub_priv_t; 436 437 438 typedef struct emlxs_unsol_buf 439 { 440 struct emlxs_unsol_buf *pool_prev; /* ptr to prev type */ 441 /* of unsol_buf hdr */ 442 struct emlxs_unsol_buf *pool_next; /* ptr to next type */ 443 /* of unsol_buf hdr */ 444 445 uint32_t pool_type; /* FC-4 type */ 446 uint32_t pool_buf_size; /* buffer size for */ 447 /* this pool */ 448 449 uint32_t pool_nentries; /* no. of bufs in */ 450 /* pool */ 451 uint32_t pool_available; /* no. of bufs avail */ 452 /* in pool */ 453 454 uint32_t pool_flags; 455 #define POOL_DESTROY 0x00000001 /* Pool is marked for */ 456 /* destruction */ 457 458 uint32_t pool_free; /* Number of free */ 459 /* buffers */ 460 uint32_t pool_free_resv; /* Number of free */ 461 /* reserved buffers */ 462 463 uint32_t pool_first_token; /* First token */ 464 /* in pool */ 465 uint32_t pool_last_token; /* Last token */ 466 /* in pool */ 467 468 fc_unsol_buf_t *fc_ubufs; /* array of unsol buf */ 469 /* structs */ 470 } emlxs_unsol_buf_t; 471 472 473 #ifndef FC_REASON_NONE 474 #define FC_REASON_NONE 0 475 #endif /* FC_REASON_NONE */ 476 477 #ifndef FC_ACTION_NONE 478 #define FC_ACTION_NONE 0 479 #endif /* FC_ACTION_NONE */ 480 481 /* 482 * emlx status translation table 483 */ 484 typedef struct emlxs_xlat_err 485 { 486 uint32_t emlxs_status; 487 uint32_t pkt_state; 488 uint32_t pkt_reason; 489 uint32_t pkt_expln; 490 uint32_t pkt_action; 491 } emlxs_xlat_err_t; 492 493 494 typedef struct emlxs_table 495 { 496 uint32_t code; 497 char string[32]; 498 } emlxs_table_t; 499 500 501 /* PATCH MASK DEFINES */ 502 #define EMLXS_PATCH1 0x00000001 503 #define EMLXS_PATCH2 0x00000002 504 #define EMLXS_PATCH3 0x00000004 505 #define EMLXS_PATCH4 0x00000008 506 #define EMLXS_PATCH5 0x00000010 507 #define EMLXS_PATCH6 0x00000020 508 #define EMLXS_PATCH7 0x00000040 509 #define EMLXS_PATCH8 0x00000080 510 #define EMLXS_PATCH9 0x00000100 511 #define EMLXS_PATCH10 0x00000200 512 #define EMLXS_PATCH11 0x00000400 513 #define EMLXS_PATCH12 0x00000800 514 #define EMLXS_PATCH13 0x00001000 515 #define EMLXS_PATCH14 0x00002000 516 #define EMLXS_PATCH15 0x00004000 517 #define EMLXS_PATCH16 0x00008000 518 #define EMLXS_PATCH17 0x00010000 519 #define EMLXS_PATCH18 0x00020000 520 #define EMLXS_PATCH19 0x00040000 521 #define EMLXS_PATCH20 0x00080000 522 #define EMLXS_PATCH21 0x00100000 523 #define EMLXS_PATCH22 0x00200000 524 #define EMLXS_PATCH23 0x00400000 525 #define EMLXS_PATCH24 0x00800000 526 #define EMLXS_PATCH25 0x01000000 527 #define EMLXS_PATCH26 0x02000000 528 #define EMLXS_PATCH27 0x04000000 529 #define EMLXS_PATCH28 0x08000000 530 #define EMLXS_PATCH29 0x10000000 531 #define EMLXS_PATCH30 0x20000000 532 #define EMLXS_PATCH31 0x40000000 533 #define EMLXS_PATCH32 0x80000000 534 535 536 /* ULP Patches: */ 537 538 /* This patch enables the driver to auto respond to unsolicited LOGO's */ 539 /* This is needed because ULP is sometimes doesn't reply itself */ 540 #define ULP_PATCH2 EMLXS_PATCH2 541 542 /* This patch enables the driver to auto respond to unsolicited PRLI's */ 543 /* This is needed because ULP is known to panic sometimes */ 544 #define ULP_PATCH3 EMLXS_PATCH3 545 546 /* This patch enables the driver to auto respond to unsolicited PRLO's */ 547 /* This is needed because ULP is known to panic sometimes */ 548 #define ULP_PATCH4 EMLXS_PATCH4 549 550 /* This patch enables the driver to fail pkt abort requests */ 551 #define ULP_PATCH5 EMLXS_PATCH5 552 553 /* This patch enables the driver to generate an RSCN for unsolicited PRLO's */ 554 /* and LOGO's */ 555 #define ULP_PATCH6 EMLXS_PATCH6 556 557 /* Sun Disk Array Patches: */ 558 559 /* This patch enables the driver to fix a residual underrun issue with */ 560 /* check conditions */ 561 #define FCP_UNDERRUN_PATCH1 EMLXS_PATCH9 562 563 /* This patch enables the driver to fix a residual underrun issue with */ 564 /* SCSI inquiry commands */ 565 #define FCP_UNDERRUN_PATCH2 EMLXS_PATCH10 566 567 568 #define DEFAULT_PATCHES (ULP_PATCH2 | ULP_PATCH3 | \ 569 ULP_PATCH5 | ULP_PATCH6 | \ 570 FCP_UNDERRUN_PATCH1 | FCP_UNDERRUN_PATCH2) 571 572 #ifdef __cplusplus 573 } 574 #endif 575 576 #endif /* _EMLXS_OS_H */ 577