1fcf3ce44SJohn Forte /*
2fcf3ce44SJohn Forte  * CDDL HEADER START
3fcf3ce44SJohn Forte  *
4fcf3ce44SJohn Forte  * The contents of this file are subject to the terms of the
5fcf3ce44SJohn Forte  * Common Development and Distribution License (the "License").
6fcf3ce44SJohn Forte  * You may not use this file except in compliance with the License.
7fcf3ce44SJohn Forte  *
8*8f23e9faSHans Rosenfeld  * You can obtain a copy of the license at
9*8f23e9faSHans Rosenfeld  * http://www.opensource.org/licenses/cddl1.txt.
10fcf3ce44SJohn Forte  * See the License for the specific language governing permissions
11fcf3ce44SJohn Forte  * and limitations under the License.
12fcf3ce44SJohn Forte  *
13fcf3ce44SJohn Forte  * When distributing Covered Code, include this CDDL HEADER in each
14fcf3ce44SJohn Forte  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15fcf3ce44SJohn Forte  * If applicable, add the following below this CDDL HEADER, with the
16fcf3ce44SJohn Forte  * fields enclosed by brackets "[]" replaced with your own identifying
17fcf3ce44SJohn Forte  * information: Portions Copyright [yyyy] [name of copyright owner]
18fcf3ce44SJohn Forte  *
19fcf3ce44SJohn Forte  * CDDL HEADER END
20fcf3ce44SJohn Forte  */
21fcf3ce44SJohn Forte 
22fcf3ce44SJohn Forte /*
23*8f23e9faSHans Rosenfeld  * Copyright (c) 2004-2011 Emulex. All rights reserved.
2482527734SSukumar Swaminathan  * Use is subject to license terms.
25fcf3ce44SJohn Forte  */
26fcf3ce44SJohn Forte 
27fcf3ce44SJohn Forte #ifndef _EMLXS_OS_H
28fcf3ce44SJohn Forte #define	_EMLXS_OS_H
29fcf3ce44SJohn Forte 
30fcf3ce44SJohn Forte #ifdef	__cplusplus
31fcf3ce44SJohn Forte extern "C" {
32fcf3ce44SJohn Forte #endif
33fcf3ce44SJohn Forte 
34291a2b48SSukumar Swaminathan #define	EMLXS_MODREV2    2	/* Old Solaris 8 & 9 interface */
35291a2b48SSukumar Swaminathan #define	EMLXS_MODREV3    3	/* New Solaris 10 & 11 interface */
36291a2b48SSukumar Swaminathan #define	EMLXS_MODREV4    4	/* Sun FC packet change */
37291a2b48SSukumar Swaminathan 				/* Symbolic Node Name interface */
38291a2b48SSukumar Swaminathan #define	EMLXS_MODREV5    5	/* New Sun NPIV Interface */
39fcf3ce44SJohn Forte 
40291a2b48SSukumar Swaminathan #define	EMLXS_MODREV2X   2	/* Old Solaris 8 & 9 x86 interface */
41291a2b48SSukumar Swaminathan #define	EMLXS_MODREV3X   3	/* New Solaris 10 & 11 x86 interface */
42fcf3ce44SJohn Forte 
43fcf3ce44SJohn Forte 
44fcf3ce44SJohn Forte /*
45291a2b48SSukumar Swaminathan  * DRIVER LEVEL FEATURES
46fcf3ce44SJohn Forte  */
47fcf3ce44SJohn Forte #define	DHCHAP_SUPPORT		/* 2.21 driver */
48fcf3ce44SJohn Forte 
49fcf3ce44SJohn Forte #define	SATURN_MSI_SUPPORT	/* 2.30 driver */
50fcf3ce44SJohn Forte #define	MENLO_SUPPORT		/* 2.30 driver */
51fcf3ce44SJohn Forte #define	MBOX_EXT_SUPPORT	/* 2.30 driver */
52fcf3ce44SJohn Forte 
53291a2b48SSukumar Swaminathan #define	DUMP_SUPPORT		/* 2.40 driver */
54291a2b48SSukumar Swaminathan #define	SAN_DIAG_SUPPORT	/* 2.40 driver */
554baa2c25SSukumar Swaminathan #define	FMA_SUPPORT		/* 2.40 driver */
56fcf3ce44SJohn Forte 
57*8f23e9faSHans Rosenfeld #define	NODE_THROTTLE_SUPPORT	/* 2.70 driver */
58*8f23e9faSHans Rosenfeld 
59291a2b48SSukumar Swaminathan /* #define	IDLE_TIMER	 Not yet - untested */
60fcf3ce44SJohn Forte 
61fcf3ce44SJohn Forte /*
62291a2b48SSukumar Swaminathan  * OS LEVEL FEATURES
63fcf3ce44SJohn Forte  */
64fcf3ce44SJohn Forte 
65fcf3ce44SJohn Forte 
66fcf3ce44SJohn Forte #ifdef S11
67fcf3ce44SJohn Forte #define	MSI_SUPPORT
68291a2b48SSukumar Swaminathan #define	SFCT_SUPPORT  /* COMSTAR Support */
69291a2b48SSukumar Swaminathan #define	MODFW_SUPPORT /* Dynamic firmware module support */
70*8f23e9faSHans Rosenfeld #define	EMLXS_MODREV EMLXS_MODREV5 /* Sun NPIV Enhancement */
71fcf3ce44SJohn Forte 
72fcf3ce44SJohn Forte #ifdef EMLXS_I386
7382527734SSukumar Swaminathan #define	EMLXS_MODREVX EMLXS_MODREV2X
74*8f23e9faSHans Rosenfeld #endif /* i386 */
75*8f23e9faSHans Rosenfeld #endif /* S11 */
76fcf3ce44SJohn Forte 
77fcf3ce44SJohn Forte /*
78291a2b48SSukumar Swaminathan  * SUBFEATURES
79fcf3ce44SJohn Forte  */
80fcf3ce44SJohn Forte #ifdef SFCT_SUPPORT
81291a2b48SSukumar Swaminathan #define	MODSYM_SUPPORT		/* Dynamic Module Loading Support */
82291a2b48SSukumar Swaminathan #define	FCIO_SUPPORT		/* FCIO IOCTL support */
83291a2b48SSukumar Swaminathan #endif /* SFCT_SUPPORT */
84fcf3ce44SJohn Forte 
85fcf3ce44SJohn Forte 
86fcf3ce44SJohn Forte #ifndef EMLXS_MODREV
87fcf3ce44SJohn Forte #define	EMLXS_MODREV			0
88291a2b48SSukumar Swaminathan #endif /* EMLXS_MODREV */
89fcf3ce44SJohn Forte 
90fcf3ce44SJohn Forte #ifndef EMLXS_MODREVX
91fcf3ce44SJohn Forte #define	EMLXS_MODREVX			0
92291a2b48SSukumar Swaminathan #endif /* EMLXS_MODREVX */
93fcf3ce44SJohn Forte 
94fcf3ce44SJohn Forte /* Create combined definition */
95fcf3ce44SJohn Forte #if defined(S10) || defined(S11)
96fcf3ce44SJohn Forte #define	S10S11
97291a2b48SSukumar Swaminathan #endif /* S10 or S11 */
98fcf3ce44SJohn Forte 
99fcf3ce44SJohn Forte #include <sys/types.h>
100fcf3ce44SJohn Forte #include <sys/varargs.h>
101fcf3ce44SJohn Forte #include <sys/devops.h>
102fcf3ce44SJohn Forte #include <sys/param.h>
103fcf3ce44SJohn Forte #include <sys/user.h>
104fcf3ce44SJohn Forte #include <sys/buf.h>
105fcf3ce44SJohn Forte #include <sys/ioctl.h>
106fcf3ce44SJohn Forte #include <sys/uio.h>
107fcf3ce44SJohn Forte #include <sys/fcntl.h>
108fcf3ce44SJohn Forte 
109fcf3ce44SJohn Forte #include <sys/cmn_err.h>
110fcf3ce44SJohn Forte #include <sys/stropts.h>
111fcf3ce44SJohn Forte #include <sys/kmem.h>
112fcf3ce44SJohn Forte 
113fcf3ce44SJohn Forte #include <sys/errno.h>
114fcf3ce44SJohn Forte #include <sys/open.h>
115fcf3ce44SJohn Forte #include <sys/kmem.h>
116fcf3ce44SJohn Forte #include <sys/poll.h>
117fcf3ce44SJohn Forte #include <sys/thread.h>
118fcf3ce44SJohn Forte #include <sys/taskq.h>
119fcf3ce44SJohn Forte #include <sys/debug.h>
120fcf3ce44SJohn Forte #include <sys/cpu.h>
121fcf3ce44SJohn Forte #include <sys/autoconf.h>
122fcf3ce44SJohn Forte #include <sys/conf.h>
123fcf3ce44SJohn Forte #include <sys/stat.h>
124fcf3ce44SJohn Forte #include <sys/var.h>
125fcf3ce44SJohn Forte 
126fcf3ce44SJohn Forte #include <sys/map.h>
127fcf3ce44SJohn Forte #include <sys/file.h>
128fcf3ce44SJohn Forte #include <sys/syslog.h>
129fcf3ce44SJohn Forte #include <sys/disp.h>
130fcf3ce44SJohn Forte #include <sys/taskq.h>
131fcf3ce44SJohn Forte 
132fcf3ce44SJohn Forte #include <sys/ddi.h>
133fcf3ce44SJohn Forte #include <sys/sunddi.h>
134fcf3ce44SJohn Forte #include <sys/promif.h>
135fcf3ce44SJohn Forte #include <sys/ethernet.h>
136fcf3ce44SJohn Forte #include <vm/seg_kmem.h>
137fcf3ce44SJohn Forte #include <sys/utsname.h>
138fcf3ce44SJohn Forte #include <sys/modctl.h>
139fcf3ce44SJohn Forte #include <sys/scsi/scsi.h>
140fcf3ce44SJohn Forte #include <sys/varargs.h>
141fcf3ce44SJohn Forte #include <sys/atomic.h>
142a9800bebSGarrett D'Amore #ifdef S11
143a9800bebSGarrett D'Amore #include <sys/pci.h>
144*8f23e9faSHans Rosenfeld #include <sys/pcie.h>
145a9800bebSGarrett D'Amore #else	/* !S11 */
146a9800bebSGarrett D'Amore /*
147a9800bebSGarrett D'Amore  * Capabilities linked list entry offsets
148a9800bebSGarrett D'Amore  */
149a9800bebSGarrett D'Amore #define	PCI_CAP_ID		0x0	/* capability identifier, 1 byte */
150a9800bebSGarrett D'Amore #define	PCI_CAP_NEXT_PTR	0x1	/* next entry pointer, 1 byte */
151a9800bebSGarrett D'Amore #define	PCI_CAP_ID_REGS_OFF	0x2	/* cap id register offset */
152a9800bebSGarrett D'Amore #define	PCI_CAP_MAX_PTR		0x30	/* maximum number of cap pointers */
153a9800bebSGarrett D'Amore #define	PCI_CAP_PTR_OFF		0x40	/* minimum cap pointer offset */
154a9800bebSGarrett D'Amore #define	PCI_CAP_PTR_MASK	0xFC	/* mask for capability pointer */
155a9800bebSGarrett D'Amore 
156a9800bebSGarrett D'Amore /*
157a9800bebSGarrett D'Amore  * Capability identifier values
158a9800bebSGarrett D'Amore  */
159a9800bebSGarrett D'Amore #define	PCI_CAP_ID_PM		0x1	/* power management entry */
160a9800bebSGarrett D'Amore #define	PCI_CAP_ID_AGP		0x2	/* AGP supported */
161a9800bebSGarrett D'Amore #define	PCI_CAP_ID_VPD		0x3	/* VPD supported */
162a9800bebSGarrett D'Amore #define	PCI_CAP_ID_SLOT_ID	0x4	/* Slot Identification supported */
163a9800bebSGarrett D'Amore #define	PCI_CAP_ID_MSI		0x5	/* MSI supported */
164a9800bebSGarrett D'Amore #define	PCI_CAP_ID_cPCI_HS	0x6	/* CompactPCI Host Swap supported */
165a9800bebSGarrett D'Amore #define	PCI_CAP_ID_PCIX		0x7	/* PCI-X supported */
166a9800bebSGarrett D'Amore #define	PCI_CAP_ID_HT		0x8	/* HyperTransport supported */
167a9800bebSGarrett D'Amore #define	PCI_CAP_ID_VS		0x9	/* Vendor Specific */
168a9800bebSGarrett D'Amore #define	PCI_CAP_ID_DEBUG_PORT	0xA	/* Debug Port supported */
169a9800bebSGarrett D'Amore #define	PCI_CAP_ID_cPCI_CRC	0xB	/* CompactPCI central resource ctrl */
170a9800bebSGarrett D'Amore #define	PCI_CAP_ID_PCI_HOTPLUG	0xC	/* PCI Hot Plug supported */
171a9800bebSGarrett D'Amore #define	PCI_CAP_ID_P2P_SUBSYS	0xD	/* PCI bridge Sub-system ID */
172a9800bebSGarrett D'Amore #define	PCI_CAP_ID_AGP_8X	0xE	/* AGP 8X supported */
173a9800bebSGarrett D'Amore #define	PCI_CAP_ID_SECURE_DEV	0xF	/* Secure Device supported */
174a9800bebSGarrett D'Amore #define	PCI_CAP_ID_PCI_E	0x10	/* PCI Express supported */
175a9800bebSGarrett D'Amore #define	PCI_CAP_ID_MSI_X	0x11	/* MSI-X supported */
176a9800bebSGarrett D'Amore #define	PCI_CAP_ID_SATA		0x12	/* SATA Data/Index Config supported */
177a9800bebSGarrett D'Amore #define	PCI_CAP_ID_FLR		0x13	/* Function Level Reset supported */
178a9800bebSGarrett D'Amore 
179a9800bebSGarrett D'Amore /*
180a9800bebSGarrett D'Amore  * PCI power management (PM) capability entry offsets
181a9800bebSGarrett D'Amore  */
182a9800bebSGarrett D'Amore #define	PCI_PMCAP		0x2	/* PM capabilities, 2 bytes */
183a9800bebSGarrett D'Amore #define	PCI_PMCSR		0x4	/* PM control/status reg, 2 bytes */
184a9800bebSGarrett D'Amore #define	PCI_PMCSR_BSE		0x6	/* PCI-PCI bridge extensions, 1 byte */
185a9800bebSGarrett D'Amore #define	PCI_PMDATA		0x7	/* PM data, 1 byte */
186a9800bebSGarrett D'Amore 
187a9800bebSGarrett D'Amore /*
188a9800bebSGarrett D'Amore  * PM control/status values - 2 bytes
189a9800bebSGarrett D'Amore  */
190a9800bebSGarrett D'Amore #define	PCI_PMCSR_D0			0x0	/* power state D0 */
191a9800bebSGarrett D'Amore #define	PCI_PMCSR_D1			0x1	/* power state D1 */
192a9800bebSGarrett D'Amore #define	PCI_PMCSR_D2			0x2	/* power state D2 */
193a9800bebSGarrett D'Amore #define	PCI_PMCSR_D3HOT			0x3	/* power state D3hot */
194*8f23e9faSHans Rosenfeld 
195*8f23e9faSHans Rosenfeld 
196*8f23e9faSHans Rosenfeld /*
197*8f23e9faSHans Rosenfeld  * PCI Express capability registers in PCI configuration space relative to
198*8f23e9faSHans Rosenfeld  * the PCI Express Capability structure.
199*8f23e9faSHans Rosenfeld  */
200*8f23e9faSHans Rosenfeld #define	PCIE_CAP_ID			PCI_CAP_ID
201*8f23e9faSHans Rosenfeld #define	PCIE_CAP_NEXT_PTR		PCI_CAP_NEXT_PTR
202*8f23e9faSHans Rosenfeld #define	PCIE_PCIECAP			0x02	/* PCI-e Capability Reg */
203*8f23e9faSHans Rosenfeld #define	PCIE_DEVCAP			0x04	/* Device Capability */
204*8f23e9faSHans Rosenfeld #define	PCIE_DEVCTL			0x08	/* Device Control */
205*8f23e9faSHans Rosenfeld #define	PCIE_DEVSTS			0x0A	/* Device Status */
206*8f23e9faSHans Rosenfeld #define	PCIE_LINKCAP			0x0C	/* Link Capability */
207*8f23e9faSHans Rosenfeld #define	PCIE_LINKCTL			0x10	/* Link Control */
208*8f23e9faSHans Rosenfeld #define	PCIE_LINKSTS			0x12	/* Link Status */
209*8f23e9faSHans Rosenfeld #define	PCIE_SLOTCAP			0x14	/* Slot Capability */
210*8f23e9faSHans Rosenfeld #define	PCIE_SLOTCTL			0x18	/* Slot Control */
211*8f23e9faSHans Rosenfeld #define	PCIE_SLOTSTS			0x1A	/* Slot Status */
212*8f23e9faSHans Rosenfeld #define	PCIE_ROOTCTL			0x1C	/* Root Control */
213*8f23e9faSHans Rosenfeld #define	PCIE_ROOTSTS			0x20	/* Root Status */
214*8f23e9faSHans Rosenfeld 
215*8f23e9faSHans Rosenfeld /*
216*8f23e9faSHans Rosenfeld  * PCI-Express Enhanced Capabilities Link Entry Bit Offsets
217*8f23e9faSHans Rosenfeld  */
218*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP			0x100	/* Base Address of Ext Cap */
219*8f23e9faSHans Rosenfeld 
220*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_SHIFT		0	/* PCI-e Ext Cap ID */
221*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_MASK		0xFFFF
222*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_VER_SHIFT		16	/* PCI-e Ext Cap Ver */
223*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_VER_MASK		0xF
224*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_NEXT_PTR_SHIFT	20	/* PCI-e Ext Cap Next Ptr */
225*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_NEXT_PTR_MASK	0xFFF
226*8f23e9faSHans Rosenfeld 
227*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_NEXT_PTR_NULL	0x0
228*8f23e9faSHans Rosenfeld 
229*8f23e9faSHans Rosenfeld /*
230*8f23e9faSHans Rosenfeld  * PCI-Express Enhanced Capability Identifier Values
231*8f23e9faSHans Rosenfeld  */
232*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_AER		0x1	/* Advanced Error Handling */
233*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_VC		0x2	/* Virtual Channel, no MFVC */
234*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_SER		0x3	/* Serial Number */
235*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_PWR_BUDGET	0x4	/* Power Budgeting */
236*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_RC_LINK_DECL	0x5	/* RC Link Declaration */
237*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_RC_INT_LINKCTRL	0x6	/* RC Internal Link Control */
238*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_RC_EVNT_CEA	0x7	/* RC Event Collector */
239*8f23e9faSHans Rosenfeld 						/* Endpoint Association */
240*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_MFVC		0x8	/* Multi-func Virtual Channel */
241*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_VC_WITH_MFVC	0x9	/* Virtual Channel w/ MFVC */
242*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_RCRB		0xA	/* Root Complex Register Blck */
243*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_VS		0xB	/* Vendor Spec Extended Cap */
244*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_CAC		0xC	/* Config Access Correlation */
245*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_ACS		0xD	/* Access Control Services */
246*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_ARI		0xE	/* Alternative Routing ID */
247*8f23e9faSHans Rosenfeld #define	PCIE_EXT_CAP_ID_ATS		0xF	/* Address Translation Svcs */
248a9800bebSGarrett D'Amore #endif	/* S11 */
249fcf3ce44SJohn Forte 
250fcf3ce44SJohn Forte #include <emlxs_hbaapi.h>
251fcf3ce44SJohn Forte 
252291a2b48SSukumar Swaminathan #ifdef FMA_SUPPORT
253291a2b48SSukumar Swaminathan #include <sys/ddifm.h>
254291a2b48SSukumar Swaminathan #include <sys/fm/protocol.h>
255291a2b48SSukumar Swaminathan #include <sys/fm/util.h>
256291a2b48SSukumar Swaminathan #endif	/* FMA_SUPPORT */
257291a2b48SSukumar Swaminathan #include <sys/fm/io/ddi.h>
258fcf3ce44SJohn Forte 
259fcf3ce44SJohn Forte #ifdef S11
260fcf3ce44SJohn Forte 
261fcf3ce44SJohn Forte /* ULP header files */
262fcf3ce44SJohn Forte #include <sys/fibre-channel/fc.h>
263fcf3ce44SJohn Forte #include <sys/fibre-channel/impl/fc_fcaif.h>
264fcf3ce44SJohn Forte 
265fcf3ce44SJohn Forte #else	/* !S11 */
266fcf3ce44SJohn Forte 
267fcf3ce44SJohn Forte /* ULP header files */
268fcf3ce44SJohn Forte #include <sys/fibre-channel/fcio.h>
269fcf3ce44SJohn Forte #include <sys/fibre-channel/fc.h>
270fcf3ce44SJohn Forte #include <sys/fibre-channel/fc_appif.h>
271fcf3ce44SJohn Forte #include <sys/fibre-channel/fc_types.h>
272fcf3ce44SJohn Forte #include <sys/fibre-channel/impl/fc_error.h>
273fcf3ce44SJohn Forte #include <sys/fibre-channel/impl/fc_fla.h>
274fcf3ce44SJohn Forte #include <sys/fibre-channel/impl/fc_linkapp.h>
275fcf3ce44SJohn Forte #include <sys/fibre-channel/impl/fcal.h>
276fcf3ce44SJohn Forte #include <sys/fibre-channel/impl/fcgs2.h>
277fcf3ce44SJohn Forte #include <sys/fibre-channel/impl/fcph.h>
278fcf3ce44SJohn Forte #include <sys/fibre-channel/impl/fc_ulpif.h>
279fcf3ce44SJohn Forte #include <sys/fibre-channel/impl/fc_fcaif.h>
280fcf3ce44SJohn Forte #include <sys/fibre-channel/impl/fctl.h>
281fcf3ce44SJohn Forte #include <sys/fibre-channel/impl/fctl_private.h>
282fcf3ce44SJohn Forte #include <sys/fibre-channel/ulp/fcp.h>
283fcf3ce44SJohn Forte #include <sys/fibre-channel/ulp/fcp_util.h>
284fcf3ce44SJohn Forte 
285fcf3ce44SJohn Forte #endif	/* S11 */
286fcf3ce44SJohn Forte 
287fcf3ce44SJohn Forte #ifndef FC_HBA_PORTSPEED_8GBIT
288fcf3ce44SJohn Forte #define	FC_HBA_PORTSPEED_8GBIT		16
289fcf3ce44SJohn Forte #endif	/* FC_HBA_PORTSPEED_8GBIT */
290fcf3ce44SJohn Forte 
291fcf3ce44SJohn Forte #ifndef FP_DEFAULT_SID
292fcf3ce44SJohn Forte #define	FP_DEFAULT_SID		(0x000AE)
293fcf3ce44SJohn Forte #endif	/* FP_DEFAULT_SID */
294fcf3ce44SJohn Forte 
295fcf3ce44SJohn Forte #ifndef FP_DEFAULT_DID
296fcf3ce44SJohn Forte #define	FP_DEFAULT_DID		(0x000EA)
297fcf3ce44SJohn Forte #endif	/* FP_DEFAULT_DID */
298fcf3ce44SJohn Forte 
299fcf3ce44SJohn Forte #ifdef MSI_SUPPORT
300fcf3ce44SJohn Forte #pragma weak ddi_intr_get_supported_types
301fcf3ce44SJohn Forte #pragma weak ddi_intr_get_nintrs
302fcf3ce44SJohn Forte #pragma weak ddi_intr_add_handler
303fcf3ce44SJohn Forte #pragma weak ddi_intr_remove_handler
304fcf3ce44SJohn Forte #pragma weak ddi_intr_get_hilevel_pri
305fcf3ce44SJohn Forte #pragma weak ddi_intr_enable
306fcf3ce44SJohn Forte #pragma weak ddi_intr_disable
307fcf3ce44SJohn Forte #pragma weak ddi_intr_get_cap
308fcf3ce44SJohn Forte #pragma weak ddi_intr_get_pri
309fcf3ce44SJohn Forte #pragma weak ddi_intr_alloc
310fcf3ce44SJohn Forte #pragma weak ddi_intr_free
311fcf3ce44SJohn Forte #pragma weak ddi_intr_block_enable
312fcf3ce44SJohn Forte #pragma weak ddi_intr_block_disable
313fcf3ce44SJohn Forte extern int ddi_intr_get_supported_types();
314fcf3ce44SJohn Forte #endif	/* MSI_SUPPORT */
315fcf3ce44SJohn Forte 
316fcf3ce44SJohn Forte #ifndef MODSYM_SUPPORT
317fcf3ce44SJohn Forte #pragma weak fc_fca_init
318fcf3ce44SJohn Forte #pragma weak fc_fca_attach
319fcf3ce44SJohn Forte #pragma weak fc_fca_detach
320291a2b48SSukumar Swaminathan #endif /* MODSYM_SUPPORT */
321fcf3ce44SJohn Forte 
322fcf3ce44SJohn Forte /* S11 flag for dma_attr_flags for ddi_dma_attr_t */
323fcf3ce44SJohn Forte #ifndef DDI_DMA_RELAXED_ORDERING
324fcf3ce44SJohn Forte #define	DDI_DMA_RELAXED_ORDERING	0x400
325fcf3ce44SJohn Forte #endif	/* DDI_DMA_RELAXED_ORDERING */
326fcf3ce44SJohn Forte 
327291a2b48SSukumar Swaminathan #ifdef FMA_SUPPORT
328291a2b48SSukumar Swaminathan /* FMA Support */
329291a2b48SSukumar Swaminathan #pragma weak ddi_fm_acc_err_clear
330bb63f56eSSukumar Swaminathan extern void ddi_fm_acc_err_clear();
331291a2b48SSukumar Swaminathan #endif	/* FMA_SUPPORT */
332fcf3ce44SJohn Forte 
333fcf3ce44SJohn Forte #ifdef EMLXS_SPARC
334fcf3ce44SJohn Forte #define	EMLXS_BIG_ENDIAN
335fcf3ce44SJohn Forte #endif	/* EMLXS_SPARC */
336fcf3ce44SJohn Forte 
337fcf3ce44SJohn Forte #ifdef EMLXS_I386
338fcf3ce44SJohn Forte #define	EMLXS_LITTLE_ENDIAN
339fcf3ce44SJohn Forte #endif	/* EMLXS_I386 */
340fcf3ce44SJohn Forte 
341fcf3ce44SJohn Forte 
342fcf3ce44SJohn Forte /* Solaris 8 does not define this */
343fcf3ce44SJohn Forte #ifndef TASKQ_DYNAMIC
344291a2b48SSukumar Swaminathan #define	TASKQ_DYNAMIC	0x0004
345fcf3ce44SJohn Forte #endif	/* TASKQ_DYNAMIC */
346fcf3ce44SJohn Forte 
347fcf3ce44SJohn Forte #ifdef _LP64
348291a2b48SSukumar Swaminathan #define	DEAD_PTR   0xdeadbeefdeadbeef
349fcf3ce44SJohn Forte #else
350291a2b48SSukumar Swaminathan #define	DEAD_PTR   0xdeadbeef
351fcf3ce44SJohn Forte #endif	/* _LP64 */
352fcf3ce44SJohn Forte 
353fcf3ce44SJohn Forte #ifndef FC_STATE_8GBIT_SPEED
354fcf3ce44SJohn Forte /* This was obtained from OpenSolaris */
355fcf3ce44SJohn Forte #define	FC_STATE_8GBIT_SPEED		0x0700	/* 8 Gbit/sec */
356fcf3ce44SJohn Forte #endif	/* FC_STATE_8GBIT_SPEED */
357fcf3ce44SJohn Forte 
358fcf3ce44SJohn Forte #define	FC_STATE_QUAD_SPEED		0x0500
359fcf3ce44SJohn Forte 
360fcf3ce44SJohn Forte #ifndef BURSTSIZE
361fcf3ce44SJohn Forte #define	BURSTSIZE
362291a2b48SSukumar Swaminathan #define	BURST1			0x01
363291a2b48SSukumar Swaminathan #define	BURST2			0x02
364291a2b48SSukumar Swaminathan #define	BURST4			0x04
365291a2b48SSukumar Swaminathan #define	BURST8			0x08
366291a2b48SSukumar Swaminathan #define	BURST16			0x10
367291a2b48SSukumar Swaminathan #define	BURST32			0x20
368291a2b48SSukumar Swaminathan #define	BURST64			0x40
369fcf3ce44SJohn Forte #ifdef _LP64
370291a2b48SSukumar Swaminathan #define	BURSTSIZE_MASK		0x7f
371fcf3ce44SJohn Forte #else
372291a2b48SSukumar Swaminathan #define	BURSTSIZE_MASK		0x3f
373fcf3ce44SJohn Forte #endif	/* _LP64 */
374fcf3ce44SJohn Forte #define	DEFAULT_BURSTSIZE	(BURSTSIZE_MASK)	/* all burst sizes */
375fcf3ce44SJohn Forte #endif	/* BURSTSIZE */
376fcf3ce44SJohn Forte 
37782527734SSukumar Swaminathan #define	PADDR_LO(addr)		((uint32_t)(((uint64_t)(addr)) & 0xffffffff))
37882527734SSukumar Swaminathan #define	PADDR_HI(addr)		((uint32_t)(((uint64_t)(addr)) >> 32))
37982527734SSukumar Swaminathan #define	PADDR(high, low)	((uint64_t)((((uint64_t)(high)) << 32) \
380291a2b48SSukumar Swaminathan 					| (((uint64_t)(low)) & 0xffffffff)))
381fcf3ce44SJohn Forte 
382fcf3ce44SJohn Forte #ifndef TRUE
383fcf3ce44SJohn Forte #define	TRUE	1
384fcf3ce44SJohn Forte #endif	/* TRUE */
385fcf3ce44SJohn Forte 
386fcf3ce44SJohn Forte #ifndef FALSE
387fcf3ce44SJohn Forte #define	FALSE	0
388fcf3ce44SJohn Forte #endif	/* FALSE */
389fcf3ce44SJohn Forte 
390291a2b48SSukumar Swaminathan #define	DMA_READ_WRITE		0
391291a2b48SSukumar Swaminathan #define	DMA_READ_ONLY		1
392291a2b48SSukumar Swaminathan #define	DMA_WRITE_ONLY		2
393fcf3ce44SJohn Forte 
394291a2b48SSukumar Swaminathan #define	DMA_SUCC		1
395fcf3ce44SJohn Forte 
396291a2b48SSukumar Swaminathan #define	MAX_FC_BRDS		256	/* Maximum # boards per system */
397fcf3ce44SJohn Forte 
398*8f23e9faSHans Rosenfeld #define	BUSYWAIT_MS(ms)		drv_usecwait((ms*1000))
399*8f23e9faSHans Rosenfeld #define	BUSYWAIT_US(us)		drv_usecwait(us)
400fcf3ce44SJohn Forte 
40182527734SSukumar Swaminathan #define	EMLXS_MPDATA_SYNC(h, a, b, c)  \
402291a2b48SSukumar Swaminathan 	if (h)  { \
403291a2b48SSukumar Swaminathan 		(void) ddi_dma_sync((ddi_dma_handle_t)(h), \
404291a2b48SSukumar Swaminathan 			(off_t)(a), (size_t)(b), (uint_t)c); \
405fcf3ce44SJohn Forte 	}
406fcf3ce44SJohn Forte 
407fcf3ce44SJohn Forte #define	PKT2PRIV(pkt)		((emlxs_buf_t *)(pkt)->pkt_fca_private)
408fcf3ce44SJohn Forte #define	PRIV2PKT(sbp)		sbp->pkt
409fcf3ce44SJohn Forte 
410fcf3ce44SJohn Forte #define	EMLXS_INUMBER		0
411fcf3ce44SJohn Forte #define	EMLXS_MSI_INUMBER 	0
412fcf3ce44SJohn Forte 
413fcf3ce44SJohn Forte #define	EMLXS_DMA_ALIGN		BURST16
414fcf3ce44SJohn Forte 
415fcf3ce44SJohn Forte /*
416291a2b48SSukumar Swaminathan  * Register indices in PCI configuration space.
417fcf3ce44SJohn Forte  */
418291a2b48SSukumar Swaminathan #define	SBUS_FLASH_RD			0	/* FCODE-Flash Read only */
419291a2b48SSukumar Swaminathan 						/* index */
420291a2b48SSukumar Swaminathan #define	SBUS_FLASH_RDWR			1	/* FCODE-Flash Read/Write */
421291a2b48SSukumar Swaminathan 						/* index */
422291a2b48SSukumar Swaminathan #define	SBUS_DFLY_SLIM_RINDEX	  2	/* DragonFly SLIM regs index */
423291a2b48SSukumar Swaminathan #define	SBUS_DFLY_CSR_RINDEX	  3	/* DragonFly I/O regs index */
424291a2b48SSukumar Swaminathan #define	SBUS_TITAN_CORE_RINDEX	  4	/* TITAN Core register index */
425291a2b48SSukumar Swaminathan #define	SBUS_DFLY_PCI_CFG_RINDEX	5	/* DragonFly PCI ConfigSpace */
426291a2b48SSukumar Swaminathan 						/* regs index */
427291a2b48SSukumar Swaminathan #define	SBUS_TITAN_PCI_CFG_RINDEX	6	/* TITAN PCI ConfigSpace regs */
428291a2b48SSukumar Swaminathan 						/* index */
429291a2b48SSukumar Swaminathan #define	SBUS_TITAN_CSR_RINDEX		7	/* TITAN Control/Status regs */
430291a2b48SSukumar Swaminathan 						/* index */
431291a2b48SSukumar Swaminathan 
432291a2b48SSukumar Swaminathan #define	PCI_CFG_RINDEX		  0
433291a2b48SSukumar Swaminathan #define	PCI_SLIM_RINDEX		  1
434291a2b48SSukumar Swaminathan #define	PCI_CSR_RINDEX		  2
435fcf3ce44SJohn Forte 
436*8f23e9faSHans Rosenfeld #define	PCI_BAR0_RINDEX		  1
43782527734SSukumar Swaminathan #define	PCI_BAR1_RINDEX		  2
43882527734SSukumar Swaminathan #define	PCI_BAR2_RINDEX		  3
43982527734SSukumar Swaminathan 
44082527734SSukumar Swaminathan 
441fcf3ce44SJohn Forte #define	EMLXS_MAX_UBUFS		65535
442fcf3ce44SJohn Forte 
443fcf3ce44SJohn Forte /* Tokens < EMLXS_UB_TOKEN_OFFSET are reserved for ELS response oxids */
444291a2b48SSukumar Swaminathan #define	EMLXS_UB_TOKEN_OFFSET	0x100
445fcf3ce44SJohn Forte 
446291a2b48SSukumar Swaminathan typedef struct emlxs_ub_priv
447291a2b48SSukumar Swaminathan {
448291a2b48SSukumar Swaminathan 	fc_unsol_buf_t	*ubp;
449291a2b48SSukumar Swaminathan 	void		*port;
450fcf3ce44SJohn Forte 
451291a2b48SSukumar Swaminathan 	uint32_t	bpl_size;
452291a2b48SSukumar Swaminathan 	uint8_t		*bpl_virt;	/* virtual address ptr */
453291a2b48SSukumar Swaminathan 	uint64_t	bpl_phys;	/* mapped address */
454291a2b48SSukumar Swaminathan 	void		*bpl_data_handle;
455291a2b48SSukumar Swaminathan 	void		*bpl_dma_handle;
456fcf3ce44SJohn Forte 
457291a2b48SSukumar Swaminathan 	uint32_t	ip_ub_size;
458291a2b48SSukumar Swaminathan 	uint8_t		*ip_ub_virt;	/* virtual address ptr */
459fcf3ce44SJohn Forte 	ddi_dma_cookie_t ip_ub_dma_cookies[64];
460fcf3ce44SJohn Forte 	ddi_acc_handle_t ip_ub_data_handle;
461fcf3ce44SJohn Forte 	ddi_dma_handle_t ip_ub_dma_handle;
462291a2b48SSukumar Swaminathan 	uint32_t	ip_ub_cookie_cnt;
463291a2b48SSukumar Swaminathan 	uint32_t	FC4type;
464fcf3ce44SJohn Forte 
465291a2b48SSukumar Swaminathan 	uint16_t	flags;
466fcf3ce44SJohn Forte #define	EMLXS_UB_FREE		0x0000
467fcf3ce44SJohn Forte #define	EMLXS_UB_IN_USE		0x0001
468fcf3ce44SJohn Forte #define	EMLXS_UB_REPLY		0x0002
469fcf3ce44SJohn Forte #define	EMLXS_UB_RESV		0x0004
470fcf3ce44SJohn Forte #define	EMLXS_UB_TIMEOUT	0x0008
471fcf3ce44SJohn Forte #define	EMLXS_UB_INTERCEPT	0x0010
472fcf3ce44SJohn Forte 
473291a2b48SSukumar Swaminathan 	uint16_t	available;
474fcf3ce44SJohn Forte 
475291a2b48SSukumar Swaminathan 	uint32_t	timeout;	/* Timeout period in seconds */
476291a2b48SSukumar Swaminathan 	uint32_t	time;	/* EMLXS_UB_IN_USE timestamp */
477291a2b48SSukumar Swaminathan 	uint32_t	cmd;
478291a2b48SSukumar Swaminathan 	uint32_t	token;
479fcf3ce44SJohn Forte 
480fcf3ce44SJohn Forte 	struct emlxs_unsol_buf *pool;
481fcf3ce44SJohn Forte 	struct emlxs_ub_priv *next;
482fcf3ce44SJohn Forte } emlxs_ub_priv_t;
483fcf3ce44SJohn Forte 
484fcf3ce44SJohn Forte 
485291a2b48SSukumar Swaminathan typedef struct emlxs_unsol_buf
486291a2b48SSukumar Swaminathan {
487291a2b48SSukumar Swaminathan 	struct emlxs_unsol_buf	*pool_prev;		/* ptr to prev type */
488291a2b48SSukumar Swaminathan 							/* of unsol_buf hdr */
489291a2b48SSukumar Swaminathan 	struct emlxs_unsol_buf	*pool_next;		/* ptr to next type */
490291a2b48SSukumar Swaminathan 							/* of unsol_buf hdr */
491fcf3ce44SJohn Forte 
492291a2b48SSukumar Swaminathan 	uint32_t		pool_type;		/* FC-4 type */
493291a2b48SSukumar Swaminathan 	uint32_t		pool_buf_size;		/* buffer size for */
494291a2b48SSukumar Swaminathan 							/* this pool */
495fcf3ce44SJohn Forte 
496291a2b48SSukumar Swaminathan 	uint32_t		pool_nentries;		/* no. of bufs in */
497291a2b48SSukumar Swaminathan 							/* pool */
498291a2b48SSukumar Swaminathan 	uint32_t		pool_available;		/* no. of bufs avail */
499291a2b48SSukumar Swaminathan 							/* in pool */
500fcf3ce44SJohn Forte 
501291a2b48SSukumar Swaminathan 	uint32_t		pool_flags;
502291a2b48SSukumar Swaminathan #define	POOL_DESTROY		0x00000001		/* Pool is marked for */
503291a2b48SSukumar Swaminathan 							/* destruction */
504fcf3ce44SJohn Forte 
505291a2b48SSukumar Swaminathan 	uint32_t		pool_free;		/* Number of free */
506291a2b48SSukumar Swaminathan 							/* buffers */
507291a2b48SSukumar Swaminathan 	uint32_t		pool_free_resv;		/* Number of free */
508291a2b48SSukumar Swaminathan 							/* reserved buffers */
509fcf3ce44SJohn Forte 
510291a2b48SSukumar Swaminathan 	uint32_t		pool_first_token;	/* First token */
511291a2b48SSukumar Swaminathan 							/* in pool */
512291a2b48SSukumar Swaminathan 	uint32_t		pool_last_token;	/* Last token */
513291a2b48SSukumar Swaminathan 							/* in pool */
514fcf3ce44SJohn Forte 
515291a2b48SSukumar Swaminathan 	fc_unsol_buf_t		*fc_ubufs;		/* array of unsol buf */
516291a2b48SSukumar Swaminathan 							/* structs */
517fcf3ce44SJohn Forte } emlxs_unsol_buf_t;
518fcf3ce44SJohn Forte 
519fcf3ce44SJohn Forte 
520fcf3ce44SJohn Forte #ifndef FC_REASON_NONE
521fcf3ce44SJohn Forte #define	FC_REASON_NONE			0
522291a2b48SSukumar Swaminathan #endif /* FC_REASON_NONE */
523fcf3ce44SJohn Forte 
524fcf3ce44SJohn Forte #ifndef FC_ACTION_NONE
525fcf3ce44SJohn Forte #define	FC_ACTION_NONE			0
526291a2b48SSukumar Swaminathan #endif /* FC_ACTION_NONE */
527fcf3ce44SJohn Forte 
528fcf3ce44SJohn Forte /*
529fcf3ce44SJohn Forte  * emlx status translation table
530fcf3ce44SJohn Forte  */
531291a2b48SSukumar Swaminathan typedef struct emlxs_xlat_err
532291a2b48SSukumar Swaminathan {
533291a2b48SSukumar Swaminathan 	uint32_t	emlxs_status;
534291a2b48SSukumar Swaminathan 	uint32_t	pkt_state;
535291a2b48SSukumar Swaminathan 	uint32_t	pkt_reason;
536291a2b48SSukumar Swaminathan 	uint32_t	pkt_expln;
537291a2b48SSukumar Swaminathan 	uint32_t	pkt_action;
538fcf3ce44SJohn Forte } emlxs_xlat_err_t;
539fcf3ce44SJohn Forte 
540fcf3ce44SJohn Forte 
541291a2b48SSukumar Swaminathan typedef struct emlxs_table
542291a2b48SSukumar Swaminathan {
543291a2b48SSukumar Swaminathan 	uint32_t	code;
544*8f23e9faSHans Rosenfeld 	char		string[48];
545fcf3ce44SJohn Forte } emlxs_table_t;
546fcf3ce44SJohn Forte 
54782527734SSukumar Swaminathan 
54882527734SSukumar Swaminathan /* PATCH MASK DEFINES */
54982527734SSukumar Swaminathan #define	EMLXS_PATCH1		0x00000001
55082527734SSukumar Swaminathan #define	EMLXS_PATCH2		0x00000002
55182527734SSukumar Swaminathan #define	EMLXS_PATCH3		0x00000004
55282527734SSukumar Swaminathan #define	EMLXS_PATCH4		0x00000008
55382527734SSukumar Swaminathan #define	EMLXS_PATCH5		0x00000010
55482527734SSukumar Swaminathan #define	EMLXS_PATCH6		0x00000020
55582527734SSukumar Swaminathan #define	EMLXS_PATCH7		0x00000040
55682527734SSukumar Swaminathan #define	EMLXS_PATCH8		0x00000080
55782527734SSukumar Swaminathan #define	EMLXS_PATCH9		0x00000100
55882527734SSukumar Swaminathan #define	EMLXS_PATCH10		0x00000200
55982527734SSukumar Swaminathan #define	EMLXS_PATCH11		0x00000400
56082527734SSukumar Swaminathan #define	EMLXS_PATCH12		0x00000800
56182527734SSukumar Swaminathan #define	EMLXS_PATCH13		0x00001000
56282527734SSukumar Swaminathan #define	EMLXS_PATCH14		0x00002000
56382527734SSukumar Swaminathan #define	EMLXS_PATCH15		0x00004000
56482527734SSukumar Swaminathan #define	EMLXS_PATCH16		0x00008000
56582527734SSukumar Swaminathan #define	EMLXS_PATCH17		0x00010000
56682527734SSukumar Swaminathan #define	EMLXS_PATCH18		0x00020000
56782527734SSukumar Swaminathan #define	EMLXS_PATCH19		0x00040000
56882527734SSukumar Swaminathan #define	EMLXS_PATCH20		0x00080000
56982527734SSukumar Swaminathan #define	EMLXS_PATCH21		0x00100000
57082527734SSukumar Swaminathan #define	EMLXS_PATCH22		0x00200000
57182527734SSukumar Swaminathan #define	EMLXS_PATCH23		0x00400000
57282527734SSukumar Swaminathan #define	EMLXS_PATCH24		0x00800000
57382527734SSukumar Swaminathan #define	EMLXS_PATCH25		0x01000000
57482527734SSukumar Swaminathan #define	EMLXS_PATCH26		0x02000000
57582527734SSukumar Swaminathan #define	EMLXS_PATCH27		0x04000000
57682527734SSukumar Swaminathan #define	EMLXS_PATCH28		0x08000000
57782527734SSukumar Swaminathan #define	EMLXS_PATCH29		0x10000000
57882527734SSukumar Swaminathan #define	EMLXS_PATCH30		0x20000000
57982527734SSukumar Swaminathan #define	EMLXS_PATCH31		0x40000000
58082527734SSukumar Swaminathan #define	EMLXS_PATCH32		0x80000000
58182527734SSukumar Swaminathan 
58282527734SSukumar Swaminathan 
58382527734SSukumar Swaminathan /* ULP Patches: */
58482527734SSukumar Swaminathan 
58582527734SSukumar Swaminathan /* This patch enables the driver to auto respond to unsolicited LOGO's */
58682527734SSukumar Swaminathan /* This is needed because ULP is sometimes doesn't reply itself */
58782527734SSukumar Swaminathan #define	ULP_PATCH2	EMLXS_PATCH2
58882527734SSukumar Swaminathan 
58982527734SSukumar Swaminathan /* This patch enables the driver to auto respond to unsolicited PRLI's */
59082527734SSukumar Swaminathan /* This is needed because ULP is known to panic sometimes */
59182527734SSukumar Swaminathan #define	ULP_PATCH3	EMLXS_PATCH3
59282527734SSukumar Swaminathan 
59382527734SSukumar Swaminathan /* This patch enables the driver to auto respond to unsolicited PRLO's */
59482527734SSukumar Swaminathan /* This is needed because ULP is known to panic sometimes */
59582527734SSukumar Swaminathan #define	ULP_PATCH4	EMLXS_PATCH4
59682527734SSukumar Swaminathan 
59782527734SSukumar Swaminathan /* This patch enables the driver to fail pkt abort requests */
59882527734SSukumar Swaminathan #define	ULP_PATCH5	EMLXS_PATCH5
59982527734SSukumar Swaminathan 
60082527734SSukumar Swaminathan /* This patch enables the driver to generate an RSCN for unsolicited PRLO's */
60182527734SSukumar Swaminathan /* and LOGO's */
60282527734SSukumar Swaminathan #define	ULP_PATCH6	EMLXS_PATCH6
60382527734SSukumar Swaminathan 
60482527734SSukumar Swaminathan /* Sun Disk Array Patches: */
60582527734SSukumar Swaminathan 
60682527734SSukumar Swaminathan /* This patch enables the driver to fix a residual underrun issue with */
60782527734SSukumar Swaminathan /* check conditions */
60882527734SSukumar Swaminathan #define	FCP_UNDERRUN_PATCH1	EMLXS_PATCH9
60982527734SSukumar Swaminathan 
61082527734SSukumar Swaminathan /* This patch enables the driver to fix a residual underrun issue with */
61182527734SSukumar Swaminathan /* SCSI inquiry commands */
61282527734SSukumar Swaminathan #define	FCP_UNDERRUN_PATCH2	EMLXS_PATCH10
61382527734SSukumar Swaminathan 
61482527734SSukumar Swaminathan 
61582527734SSukumar Swaminathan #define	DEFAULT_PATCHES	(ULP_PATCH2 | ULP_PATCH3 | \
61682527734SSukumar Swaminathan 			    ULP_PATCH5 | ULP_PATCH6 | \
61782527734SSukumar Swaminathan 			    FCP_UNDERRUN_PATCH1 | FCP_UNDERRUN_PATCH2)
61882527734SSukumar Swaminathan 
619fcf3ce44SJohn Forte #ifdef	__cplusplus
620fcf3ce44SJohn Forte }
621fcf3ce44SJohn Forte #endif
622fcf3ce44SJohn Forte 
623fcf3ce44SJohn Forte #endif	/* _EMLXS_OS_H */