182527734SSukumar Swaminathan /* 282527734SSukumar Swaminathan * CDDL HEADER START 382527734SSukumar Swaminathan * 482527734SSukumar Swaminathan * The contents of this file are subject to the terms of the 582527734SSukumar Swaminathan * Common Development and Distribution License (the "License"). 682527734SSukumar Swaminathan * You may not use this file except in compliance with the License. 782527734SSukumar Swaminathan * 88f23e9faSHans Rosenfeld * You can obtain a copy of the license at 98f23e9faSHans Rosenfeld * http://www.opensource.org/licenses/cddl1.txt. 1082527734SSukumar Swaminathan * See the License for the specific language governing permissions 1182527734SSukumar Swaminathan * and limitations under the License. 1282527734SSukumar Swaminathan * 1382527734SSukumar Swaminathan * When distributing Covered Code, include this CDDL HEADER in each 1482527734SSukumar Swaminathan * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1582527734SSukumar Swaminathan * If applicable, add the following below this CDDL HEADER, with the 1682527734SSukumar Swaminathan * fields enclosed by brackets "[]" replaced with your own identifying 1782527734SSukumar Swaminathan * information: Portions Copyright [yyyy] [name of copyright owner] 1882527734SSukumar Swaminathan * 1982527734SSukumar Swaminathan * CDDL HEADER END 2082527734SSukumar Swaminathan */ 2182527734SSukumar Swaminathan 2282527734SSukumar Swaminathan /* 238f23e9faSHans Rosenfeld * Copyright (c) 2004-2012 Emulex. All rights reserved. 2482527734SSukumar Swaminathan * Use is subject to license terms. 25a3170057SPaul Winder * Copyright 2020 RackTop Systems, Inc. 2682527734SSukumar Swaminathan */ 2782527734SSukumar Swaminathan 2882527734SSukumar Swaminathan #ifndef _EMLXS_MBOX_H 2982527734SSukumar Swaminathan #define _EMLXS_MBOX_H 3082527734SSukumar Swaminathan 3182527734SSukumar Swaminathan #ifdef __cplusplus 3282527734SSukumar Swaminathan extern "C" { 3382527734SSukumar Swaminathan #endif 3482527734SSukumar Swaminathan 3582527734SSukumar Swaminathan /* SLI 2/3 Mailbox defines */ 3682527734SSukumar Swaminathan 3782527734SSukumar Swaminathan #define MBOX_SIZE 256 3882527734SSukumar Swaminathan #define MBOX_EXTENSION_OFFSET MBOX_SIZE 3982527734SSukumar Swaminathan 4082527734SSukumar Swaminathan #ifdef MBOX_EXT_SUPPORT 4182527734SSukumar Swaminathan #define MBOX_EXTENSION_SIZE 1024 4282527734SSukumar Swaminathan #else 4382527734SSukumar Swaminathan #define MBOX_EXTENSION_SIZE 0 4482527734SSukumar Swaminathan #endif /* MBOX_EXT_SUPPORT */ 4582527734SSukumar Swaminathan 4682527734SSukumar Swaminathan 4782527734SSukumar Swaminathan 4882527734SSukumar Swaminathan /* ==== Mailbox Commands ==== */ 4982527734SSukumar Swaminathan #define MBX_SHUTDOWN 0x00 /* terminate testing */ 5082527734SSukumar Swaminathan #define MBX_LOAD_SM 0x01 5182527734SSukumar Swaminathan #define MBX_READ_NV 0x02 5282527734SSukumar Swaminathan #define MBX_WRITE_NV 0x03 5382527734SSukumar Swaminathan #define MBX_RUN_BIU_DIAG 0x04 5482527734SSukumar Swaminathan #define MBX_INIT_LINK 0x05 5582527734SSukumar Swaminathan #define MBX_DOWN_LINK 0x06 5682527734SSukumar Swaminathan #define MBX_CONFIG_LINK 0x07 5782527734SSukumar Swaminathan #define MBX_PART_SLIM 0x08 5882527734SSukumar Swaminathan #define MBX_CONFIG_RING 0x09 5982527734SSukumar Swaminathan #define MBX_RESET_RING 0x0A 6082527734SSukumar Swaminathan #define MBX_READ_CONFIG 0x0B 6182527734SSukumar Swaminathan #define MBX_READ_RCONFIG 0x0C 6282527734SSukumar Swaminathan #define MBX_READ_SPARM 0x0D 6382527734SSukumar Swaminathan #define MBX_READ_STATUS 0x0E 6482527734SSukumar Swaminathan #define MBX_READ_RPI 0x0F 6582527734SSukumar Swaminathan #define MBX_READ_XRI 0x10 6682527734SSukumar Swaminathan #define MBX_READ_REV 0x11 6782527734SSukumar Swaminathan #define MBX_READ_LNK_STAT 0x12 6882527734SSukumar Swaminathan #define MBX_REG_LOGIN 0x13 6982527734SSukumar Swaminathan #define MBX_UNREG_LOGIN 0x14 /* SLI2/3 */ 7082527734SSukumar Swaminathan #define MBX_UNREG_RPI 0x14 /* SLI4 */ 7182527734SSukumar Swaminathan #define MBX_READ_LA 0x15 7282527734SSukumar Swaminathan #define MBX_CLEAR_LA 0x16 7382527734SSukumar Swaminathan #define MBX_DUMP_MEMORY 0x17 7482527734SSukumar Swaminathan #define MBX_DUMP_CONTEXT 0x18 7582527734SSukumar Swaminathan #define MBX_RUN_DIAGS 0x19 7682527734SSukumar Swaminathan #define MBX_RESTART 0x1A 7782527734SSukumar Swaminathan #define MBX_UPDATE_CFG 0x1B 7882527734SSukumar Swaminathan #define MBX_DOWN_LOAD 0x1C 7982527734SSukumar Swaminathan #define MBX_DEL_LD_ENTRY 0x1D 8082527734SSukumar Swaminathan #define MBX_RUN_PROGRAM 0x1E 8182527734SSukumar Swaminathan #define MBX_SET_MASK 0x20 8282527734SSukumar Swaminathan #define MBX_SET_VARIABLE 0x21 8382527734SSukumar Swaminathan #define MBX_UNREG_D_ID 0x23 8482527734SSukumar Swaminathan #define MBX_KILL_BOARD 0x24 8582527734SSukumar Swaminathan #define MBX_CONFIG_FARP 0x25 8682527734SSukumar Swaminathan #define MBX_BEACON 0x2A 8782527734SSukumar Swaminathan #define MBX_READ_VPI 0x2B 8882527734SSukumar Swaminathan #define MBX_CONFIG_MSIX 0x30 8982527734SSukumar Swaminathan #define MBX_HEARTBEAT 0x31 9082527734SSukumar Swaminathan #define MBX_WRITE_VPARMS 0x32 9182527734SSukumar Swaminathan #define MBX_ASYNC_EVENT 0x33 9282527734SSukumar Swaminathan 9382527734SSukumar Swaminathan #define MBX_READ_EVENT_LOG_STATUS 0x37 9482527734SSukumar Swaminathan #define MBX_READ_EVENT_LOG 0x38 9582527734SSukumar Swaminathan #define MBX_WRITE_EVENT_LOG 0x39 9682527734SSukumar Swaminathan #define MBX_NV_LOG 0x3A 9782527734SSukumar Swaminathan #define MBX_PORT_CAPABILITIES 0x3B 9882527734SSukumar Swaminathan #define MBX_IOV_CONTROL 0x3C 9982527734SSukumar Swaminathan #define MBX_IOV_MBX 0x3D 10082527734SSukumar Swaminathan 10182527734SSukumar Swaminathan 10282527734SSukumar Swaminathan #define MBX_CONFIG_HBQ 0x7C /* SLI3 */ 10382527734SSukumar Swaminathan #define MBX_LOAD_AREA 0x81 10482527734SSukumar Swaminathan #define MBX_RUN_BIU_DIAG64 0x84 10582527734SSukumar Swaminathan #define MBX_GET_DEBUG 0x86 10682527734SSukumar Swaminathan #define MBX_CONFIG_PORT 0x88 10782527734SSukumar Swaminathan #define MBX_READ_SPARM64 0x8D 10882527734SSukumar Swaminathan #define MBX_READ_RPI64 0x8F 10982527734SSukumar Swaminathan #define MBX_CONFIG_MSI 0x90 1108f23e9faSHans Rosenfeld #define MBX_REG_LOGIN64 0x93 /* SLI2/3 */ 1118f23e9faSHans Rosenfeld #define MBX_REG_RPI 0x93 /* SLI4 */ 1128f23e9faSHans Rosenfeld #define MBX_READ_LA64 0x95 /* SLI2/3 */ 1138f23e9faSHans Rosenfeld #define MBX_READ_TOPOLOGY 0x95 /* SLI4 */ 1148f23e9faSHans Rosenfeld #define MBX_REG_VPI 0x96 /* NPIV */ 1158f23e9faSHans Rosenfeld #define MBX_UNREG_VPI 0x97 /* NPIV */ 11682527734SSukumar Swaminathan #define MBX_FLASH_WR_ULA 0x98 11782527734SSukumar Swaminathan #define MBX_SET_DEBUG 0x99 11882527734SSukumar Swaminathan #define MBX_SLI_CONFIG 0x9B 11982527734SSukumar Swaminathan #define MBX_LOAD_EXP_ROM 0x9C 12082527734SSukumar Swaminathan #define MBX_REQUEST_FEATURES 0x9D 12182527734SSukumar Swaminathan #define MBX_RESUME_RPI 0x9E 12282527734SSukumar Swaminathan #define MBX_REG_VFI 0x9F 12382527734SSukumar Swaminathan #define MBX_REG_FCFI 0xA0 12482527734SSukumar Swaminathan #define MBX_UNREG_VFI 0xA1 12582527734SSukumar Swaminathan #define MBX_UNREG_FCFI 0xA2 12682527734SSukumar Swaminathan #define MBX_INIT_VFI 0xA3 12782527734SSukumar Swaminathan #define MBX_INIT_VPI 0xA4 12882527734SSukumar Swaminathan #define MBX_ACCESS_VDATA 0xA5 12982527734SSukumar Swaminathan #define MBX_MAX_CMDS 0xA6 13082527734SSukumar Swaminathan 13182527734SSukumar Swaminathan 13282527734SSukumar Swaminathan /* 13382527734SSukumar Swaminathan * Define Status 13482527734SSukumar Swaminathan */ 13582527734SSukumar Swaminathan #define MBX_SUCCESS 0x0 13682527734SSukumar Swaminathan #define MBX_FAILURE 0x1 13782527734SSukumar Swaminathan #define MBXERR_NUM_IOCBS 0x2 13882527734SSukumar Swaminathan #define MBXERR_IOCBS_EXCEEDED 0x3 13982527734SSukumar Swaminathan #define MBXERR_BAD_RING_NUMBER 0x4 14082527734SSukumar Swaminathan #define MBXERR_MASK_ENTRIES_RANGE 0x5 14182527734SSukumar Swaminathan #define MBXERR_MASKS_EXCEEDED 0x6 14282527734SSukumar Swaminathan #define MBXERR_BAD_PROFILE 0x7 14382527734SSukumar Swaminathan #define MBXERR_BAD_DEF_CLASS 0x8 14482527734SSukumar Swaminathan #define MBXERR_BAD_MAX_RESPONDER 0x9 14582527734SSukumar Swaminathan #define MBXERR_BAD_MAX_ORIGINATOR 0xA 14682527734SSukumar Swaminathan #define MBXERR_RPI_REGISTERED 0xB 14782527734SSukumar Swaminathan #define MBXERR_RPI_FULL 0xC 14882527734SSukumar Swaminathan #define MBXERR_NO_RESOURCES 0xD 14982527734SSukumar Swaminathan #define MBXERR_BAD_RCV_LENGTH 0xE 15082527734SSukumar Swaminathan #define MBXERR_DMA_ERROR 0xF 15182527734SSukumar Swaminathan #define MBXERR_NOT_SUPPORTED 0x10 15282527734SSukumar Swaminathan #define MBXERR_UNSUPPORTED_FEATURE 0x11 15382527734SSukumar Swaminathan #define MBXERR_UNKNOWN_COMMAND 0x12 1548f23e9faSHans Rosenfeld #define MBXERR_BAD_IP_BIT 0x13 1558f23e9faSHans Rosenfeld #define MBXERR_BAD_PCB_ALIGN 0x14 1568f23e9faSHans Rosenfeld #define MBXERR_BAD_HBQ_ID 0x15 1578f23e9faSHans Rosenfeld #define MBXERR_BAD_HBQ_STATE 0x16 1588f23e9faSHans Rosenfeld #define MBXERR_BAD_HBQ_MASK_NUM 0x17 1598f23e9faSHans Rosenfeld #define MBXERR_BAD_HBQ_MASK_SUBSET 0x18 1608f23e9faSHans Rosenfeld #define MBXERR_HBQ_CREATE_FAIL 0x19 1618f23e9faSHans Rosenfeld #define MBXERR_HBQ_EXISTING 0x1A 1628f23e9faSHans Rosenfeld #define MBXERR_HBQ_RSPRING_FULL 0x1B 1638f23e9faSHans Rosenfeld #define MBXERR_HBQ_DUP_MASK 0x1C 1648f23e9faSHans Rosenfeld #define MBXERR_HBQ_INVAL_GET_PTR 0x1D 1658f23e9faSHans Rosenfeld #define MBXERR_BAD_HBQ_SIZE 0x1E 1668f23e9faSHans Rosenfeld #define MBXERR_BAD_HBQ_ORDER 0x1F 1678f23e9faSHans Rosenfeld #define MBXERR_INVALID_ID 0x20 1688f23e9faSHans Rosenfeld 1698f23e9faSHans Rosenfeld #define MBXERR_INVALID_VFI 0x30 1708f23e9faSHans Rosenfeld 1718f23e9faSHans Rosenfeld #define MBXERR_FLASH_WRITE_FAILED 0x100 1728f23e9faSHans Rosenfeld 1738f23e9faSHans Rosenfeld #define MBXERR_INVALID_LINKSPEED 0x500 1748f23e9faSHans Rosenfeld 1758f23e9faSHans Rosenfeld #define MBXERR_BAD_REDIRECT 0x900 1768f23e9faSHans Rosenfeld #define MBXERR_RING_ALREADY_CONFIG 0x901 1778f23e9faSHans Rosenfeld 1788f23e9faSHans Rosenfeld #define MBXERR_RING_INACTIVE 0xA00 1798f23e9faSHans Rosenfeld 1808f23e9faSHans Rosenfeld #define MBXERR_RPI_INACTIVE 0xF00 1818f23e9faSHans Rosenfeld 1828f23e9faSHans Rosenfeld #define MBXERR_NO_ACTIVE_XRI 0x1100 1838f23e9faSHans Rosenfeld #define MBXERR_XRI_NOT_ACTIVE 0x1101 1848f23e9faSHans Rosenfeld 1858f23e9faSHans Rosenfeld #define MBXERR_RPI_INUSE 0x1400 1868f23e9faSHans Rosenfeld 1878f23e9faSHans Rosenfeld #define MBXERR_NO_LINK_ATTENTION 0x1500 1888f23e9faSHans Rosenfeld 1898f23e9faSHans Rosenfeld #define MBXERR_INVALID_SLI_MODE 0x8800 1908f23e9faSHans Rosenfeld #define MBXERR_INVALID_HOST_PTR 0x8801 1918f23e9faSHans Rosenfeld #define MBXERR_CANT_CFG_SLI_MODE 0x8802 1928f23e9faSHans Rosenfeld #define MBXERR_BAD_OVERLAY 0x8803 1938f23e9faSHans Rosenfeld #define MBXERR_INVALID_FEAT_REQ 0x8804 1948f23e9faSHans Rosenfeld 1958f23e9faSHans Rosenfeld #define MBXERR_CONFIG_CANT_COMPLETE 0x88FF 1968f23e9faSHans Rosenfeld 1978f23e9faSHans Rosenfeld #define MBXERR_DID_ALREADY_REGISTERED 0x9600 1988f23e9faSHans Rosenfeld #define MBXERR_DID_INCONSISTENT 0x9601 1998f23e9faSHans Rosenfeld #define MBXERR_VPI_TOO_LARGE 0x9603 2008f23e9faSHans Rosenfeld 2018f23e9faSHans Rosenfeld #define MBXERR_STILL_ASSOCIATED 0x9700 2028f23e9faSHans Rosenfeld 2038f23e9faSHans Rosenfeld #define MBXERR_INVALID_VF_STATE 0x9F00 2048f23e9faSHans Rosenfeld #define MBXERR_VFI_ALREADY_REGISTERED 0x9F02 2058f23e9faSHans Rosenfeld #define MBXERR_VFI_TOO_LARGE 0x9F03 2068f23e9faSHans Rosenfeld 2078f23e9faSHans Rosenfeld #define MBXERR_LOAD_FW_FAILED 0xFFFE 2088f23e9faSHans Rosenfeld #define MBXERR_FIND_FW_FAILED 0xFFFF 20982527734SSukumar Swaminathan 21082527734SSukumar Swaminathan /* Driver special codes */ 21182527734SSukumar Swaminathan #define MBX_DRIVER_RESERVED 0xF9 /* Set to lowest drv status */ 21282527734SSukumar Swaminathan #define MBX_NONEMBED_ERROR 0xF9 21382527734SSukumar Swaminathan #define MBX_OVERTEMP_ERROR 0xFA 21482527734SSukumar Swaminathan #define MBX_HARDWARE_ERROR 0xFB 21582527734SSukumar Swaminathan #define MBX_DRVR_ERROR 0xFC 21682527734SSukumar Swaminathan #define MBX_BUSY 0xFD 21782527734SSukumar Swaminathan #define MBX_TIMEOUT 0xFE 21882527734SSukumar Swaminathan #define MBX_NOT_FINISHED 0xFF 21982527734SSukumar Swaminathan 22082527734SSukumar Swaminathan /* 22182527734SSukumar Swaminathan * flags for EMLXS_SLI_ISSUE_MBOX_CMD() 22282527734SSukumar Swaminathan */ 22382527734SSukumar Swaminathan #define MBX_POLL 0x01 /* poll mailbox till command done, */ 22482527734SSukumar Swaminathan /* then return */ 22582527734SSukumar Swaminathan #define MBX_SLEEP 0x02 /* sleep till mailbox intr cmpl */ 22682527734SSukumar Swaminathan /* wakes thread up */ 22782527734SSukumar Swaminathan #define MBX_WAIT 0x03 /* wait for comand done, then return */ 22882527734SSukumar Swaminathan #define MBX_NOWAIT 0x04 /* issue command then return immediately */ 22982527734SSukumar Swaminathan #define MBX_BOOTSTRAP 0x80 /* issue a command on the bootstrap mbox */ 23082527734SSukumar Swaminathan 23182527734SSukumar Swaminathan 23282527734SSukumar Swaminathan 23382527734SSukumar Swaminathan /* 23482527734SSukumar Swaminathan * Begin Structure Definitions for Mailbox Commands 23582527734SSukumar Swaminathan */ 23682527734SSukumar Swaminathan 23782527734SSukumar Swaminathan typedef struct revcompat 23882527734SSukumar Swaminathan { 23982527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 24082527734SSukumar Swaminathan uint32_t ldflag:1; /* Set in SRAM descriptor */ 24182527734SSukumar Swaminathan uint32_t ldcount:7; /* For use by program load */ 24282527734SSukumar Swaminathan uint32_t kernel:4; /* Kernel ID */ 24382527734SSukumar Swaminathan uint32_t kver:4; /* Kernel compatibility version */ 24482527734SSukumar Swaminathan uint32_t SMver:4; /* Sequence Manager version */ 24582527734SSukumar Swaminathan /* 0 if none */ 24682527734SSukumar Swaminathan uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */ 24782527734SSukumar Swaminathan uint32_t BIUtype:4; /* PCI = 0 */ 24882527734SSukumar Swaminathan uint32_t BIUver:4; /* BIU version, 0 if none */ 24982527734SSukumar Swaminathan #endif 25082527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 25182527734SSukumar Swaminathan uint32_t BIUver:4; /* BIU version, 0 if none */ 25282527734SSukumar Swaminathan uint32_t BIUtype:4; /* PCI = 0 */ 25382527734SSukumar Swaminathan uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */ 25482527734SSukumar Swaminathan uint32_t SMver:4; /* Sequence Manager version */ 25582527734SSukumar Swaminathan /* 0 if none */ 25682527734SSukumar Swaminathan uint32_t kver:4; /* Kernel compatibility version */ 25782527734SSukumar Swaminathan uint32_t kernel:4; /* Kernel ID */ 25882527734SSukumar Swaminathan uint32_t ldcount:7; /* For use by program load */ 25982527734SSukumar Swaminathan uint32_t ldflag:1; /* Set in SRAM descriptor */ 26082527734SSukumar Swaminathan #endif 26182527734SSukumar Swaminathan } REVCOMPAT; 26282527734SSukumar Swaminathan 26382527734SSukumar Swaminathan typedef struct id_word 26482527734SSukumar Swaminathan { 26582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 26682527734SSukumar Swaminathan uint8_t Type; 26782527734SSukumar Swaminathan uint8_t Id; 26882527734SSukumar Swaminathan uint8_t Ver; 26982527734SSukumar Swaminathan uint8_t Rev; 27082527734SSukumar Swaminathan #endif 27182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 27282527734SSukumar Swaminathan uint8_t Rev; 27382527734SSukumar Swaminathan uint8_t Ver; 27482527734SSukumar Swaminathan uint8_t Id; 27582527734SSukumar Swaminathan uint8_t Type; 27682527734SSukumar Swaminathan #endif 27782527734SSukumar Swaminathan union 27882527734SSukumar Swaminathan { 27982527734SSukumar Swaminathan REVCOMPAT cp; 28082527734SSukumar Swaminathan uint32_t revcomp; 28182527734SSukumar Swaminathan } un; 28282527734SSukumar Swaminathan } PROG_ID; 28382527734SSukumar Swaminathan 28482527734SSukumar Swaminathan typedef struct 28582527734SSukumar Swaminathan { 28682527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 28782527734SSukumar Swaminathan uint8_t tval; 28882527734SSukumar Swaminathan uint8_t tmask; 28982527734SSukumar Swaminathan uint8_t rval; 29082527734SSukumar Swaminathan uint8_t rmask; 29182527734SSukumar Swaminathan #endif 29282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 29382527734SSukumar Swaminathan uint8_t rmask; 29482527734SSukumar Swaminathan uint8_t rval; 29582527734SSukumar Swaminathan uint8_t tmask; 29682527734SSukumar Swaminathan uint8_t tval; 29782527734SSukumar Swaminathan #endif 29882527734SSukumar Swaminathan } RR_REG; 29982527734SSukumar Swaminathan 30082527734SSukumar Swaminathan 30182527734SSukumar Swaminathan /* Structure used for a HBQ entry */ 30282527734SSukumar Swaminathan typedef struct 30382527734SSukumar Swaminathan { 30482527734SSukumar Swaminathan ULP_BDE64 bde; 30582527734SSukumar Swaminathan union UN_TAG 30682527734SSukumar Swaminathan { 30782527734SSukumar Swaminathan uint32_t w; 30882527734SSukumar Swaminathan struct 30982527734SSukumar Swaminathan { 31082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 31182527734SSukumar Swaminathan uint32_t HBQ_tag:4; 31282527734SSukumar Swaminathan uint32_t HBQE_tag:28; 31382527734SSukumar Swaminathan #endif 31482527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 31582527734SSukumar Swaminathan uint32_t HBQE_tag:28; 31682527734SSukumar Swaminathan uint32_t HBQ_tag:4; 31782527734SSukumar Swaminathan #endif 31882527734SSukumar Swaminathan } ext; 31982527734SSukumar Swaminathan } unt; 32082527734SSukumar Swaminathan } HBQE_t; 32182527734SSukumar Swaminathan 32282527734SSukumar Swaminathan typedef struct 32382527734SSukumar Swaminathan { 32482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 32582527734SSukumar Swaminathan uint8_t tmatch; 32682527734SSukumar Swaminathan uint8_t tmask; 32782527734SSukumar Swaminathan uint8_t rctlmatch; 32882527734SSukumar Swaminathan uint8_t rctlmask; 32982527734SSukumar Swaminathan #endif 33082527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 33182527734SSukumar Swaminathan uint8_t rctlmask; 33282527734SSukumar Swaminathan uint8_t rctlmatch; 33382527734SSukumar Swaminathan uint8_t tmask; 33482527734SSukumar Swaminathan uint8_t tmatch; 33582527734SSukumar Swaminathan #endif 33682527734SSukumar Swaminathan } HBQ_MASK; 33782527734SSukumar Swaminathan 33882527734SSukumar Swaminathan #define EMLXS_MAX_HBQ_BUFFERS 4096 33982527734SSukumar Swaminathan 34082527734SSukumar Swaminathan typedef struct 34182527734SSukumar Swaminathan { 34282527734SSukumar Swaminathan uint32_t HBQ_num_mask; /* number of mask entries in */ 34382527734SSukumar Swaminathan /* port array */ 34482527734SSukumar Swaminathan uint32_t HBQ_recvNotify; /* Rcv buffer notification */ 34582527734SSukumar Swaminathan uint32_t HBQ_numEntries; /* # of entries in HBQ */ 34682527734SSukumar Swaminathan uint32_t HBQ_headerLen; /* 0 if not profile 4 or 5 */ 34782527734SSukumar Swaminathan uint32_t HBQ_logEntry; /* Set to 1 if this HBQ used */ 34882527734SSukumar Swaminathan /* for LogEntry */ 34982527734SSukumar Swaminathan uint32_t HBQ_profile; /* Selection profile 0=all, */ 35082527734SSukumar Swaminathan /* 7=logentry */ 35182527734SSukumar Swaminathan uint32_t HBQ_ringMask; /* Binds HBQ to a ring e.g. */ 35282527734SSukumar Swaminathan /* Ring0=b0001, ring2=b0100 */ 35382527734SSukumar Swaminathan uint32_t HBQ_id; /* index of this hbq in ring */ 35482527734SSukumar Swaminathan /* of HBQs[] */ 35582527734SSukumar Swaminathan uint32_t HBQ_PutIdx_next; /* Index to next HBQ slot to */ 35682527734SSukumar Swaminathan /* use */ 35782527734SSukumar Swaminathan uint32_t HBQ_PutIdx; /* HBQ slot to use */ 35882527734SSukumar Swaminathan uint32_t HBQ_GetIdx; /* Local copy of Get index */ 35982527734SSukumar Swaminathan /* from Port */ 36082527734SSukumar Swaminathan uint16_t HBQ_PostBufCnt; /* Current number of entries */ 36182527734SSukumar Swaminathan /* in list */ 36282527734SSukumar Swaminathan MATCHMAP *HBQ_PostBufs[EMLXS_MAX_HBQ_BUFFERS]; 36382527734SSukumar Swaminathan MATCHMAP HBQ_host_buf; /* HBQ host buffer for HBQEs */ 36482527734SSukumar Swaminathan HBQ_MASK HBQ_Masks[6]; 36582527734SSukumar Swaminathan 36682527734SSukumar Swaminathan union 36782527734SSukumar Swaminathan { 36882527734SSukumar Swaminathan uint32_t allprofiles[12]; 36982527734SSukumar Swaminathan 37082527734SSukumar Swaminathan struct 37182527734SSukumar Swaminathan { 37282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 37382527734SSukumar Swaminathan uint32_t seqlenoff:16; 37482527734SSukumar Swaminathan uint32_t maxlen:16; 37582527734SSukumar Swaminathan #endif 37682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 37782527734SSukumar Swaminathan uint32_t maxlen:16; 37882527734SSukumar Swaminathan uint32_t seqlenoff:16; 37982527734SSukumar Swaminathan #endif 38082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 38182527734SSukumar Swaminathan uint32_t rsvd1:28; 38282527734SSukumar Swaminathan uint32_t seqlenbcnt:4; 38382527734SSukumar Swaminathan #endif 38482527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 38582527734SSukumar Swaminathan uint32_t seqlenbcnt:4; 38682527734SSukumar Swaminathan uint32_t rsvd1:28; 38782527734SSukumar Swaminathan #endif 38882527734SSukumar Swaminathan uint32_t rsvd[10]; 38982527734SSukumar Swaminathan } profile2; 39082527734SSukumar Swaminathan 39182527734SSukumar Swaminathan struct 39282527734SSukumar Swaminathan { 39382527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 39482527734SSukumar Swaminathan uint32_t seqlenoff:16; 39582527734SSukumar Swaminathan uint32_t maxlen:16; 39682527734SSukumar Swaminathan #endif 39782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 39882527734SSukumar Swaminathan uint32_t maxlen:16; 39982527734SSukumar Swaminathan uint32_t seqlenoff:16; 40082527734SSukumar Swaminathan #endif 40182527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 40282527734SSukumar Swaminathan uint32_t cmdcodeoff:28; 40382527734SSukumar Swaminathan uint32_t rsvd1:12; 40482527734SSukumar Swaminathan uint32_t seqlenbcnt:4; 40582527734SSukumar Swaminathan #endif 40682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 40782527734SSukumar Swaminathan uint32_t seqlenbcnt:4; 40882527734SSukumar Swaminathan uint32_t rsvd1:12; 40982527734SSukumar Swaminathan uint32_t cmdcodeoff:28; 41082527734SSukumar Swaminathan #endif 41182527734SSukumar Swaminathan uint32_t cmdmatch[8]; 41282527734SSukumar Swaminathan 41382527734SSukumar Swaminathan uint32_t rsvd[2]; 41482527734SSukumar Swaminathan } profile3; 41582527734SSukumar Swaminathan 41682527734SSukumar Swaminathan struct 41782527734SSukumar Swaminathan { 41882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 41982527734SSukumar Swaminathan uint32_t seqlenoff:16; 42082527734SSukumar Swaminathan uint32_t maxlen:16; 42182527734SSukumar Swaminathan #endif 42282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 42382527734SSukumar Swaminathan uint32_t maxlen:16; 42482527734SSukumar Swaminathan uint32_t seqlenoff:16; 42582527734SSukumar Swaminathan #endif 42682527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 42782527734SSukumar Swaminathan uint32_t cmdcodeoff:28; 42882527734SSukumar Swaminathan uint32_t rsvd1:12; 42982527734SSukumar Swaminathan uint32_t seqlenbcnt:4; 43082527734SSukumar Swaminathan #endif 43182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 43282527734SSukumar Swaminathan uint32_t seqlenbcnt:4; 43382527734SSukumar Swaminathan uint32_t rsvd1:12; 43482527734SSukumar Swaminathan uint32_t cmdcodeoff:28; 43582527734SSukumar Swaminathan #endif 43682527734SSukumar Swaminathan uint32_t cmdmatch[8]; 43782527734SSukumar Swaminathan 43882527734SSukumar Swaminathan uint32_t rsvd[2]; 43982527734SSukumar Swaminathan } profile5; 44082527734SSukumar Swaminathan } profiles; 44182527734SSukumar Swaminathan } HBQ_INIT_t; 44282527734SSukumar Swaminathan 44382527734SSukumar Swaminathan 44482527734SSukumar Swaminathan 44582527734SSukumar Swaminathan /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 44682527734SSukumar Swaminathan 44782527734SSukumar Swaminathan 44882527734SSukumar Swaminathan typedef struct 44982527734SSukumar Swaminathan { 45082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 4516a573d82SSukumar Swaminathan uint32_t rsvd2:24; 4526a573d82SSukumar Swaminathan uint32_t keep:1; 45382527734SSukumar Swaminathan uint32_t acknowledgment:1; 45482527734SSukumar Swaminathan uint32_t version:1; 45582527734SSukumar Swaminathan uint32_t erase_or_prog:1; 45682527734SSukumar Swaminathan uint32_t update_flash:1; 45782527734SSukumar Swaminathan uint32_t update_ram:1; 45882527734SSukumar Swaminathan uint32_t method:1; 45982527734SSukumar Swaminathan uint32_t load_cmplt:1; 46082527734SSukumar Swaminathan #endif 46182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 46282527734SSukumar Swaminathan uint32_t load_cmplt:1; 46382527734SSukumar Swaminathan uint32_t method:1; 46482527734SSukumar Swaminathan uint32_t update_ram:1; 46582527734SSukumar Swaminathan uint32_t update_flash:1; 46682527734SSukumar Swaminathan uint32_t erase_or_prog:1; 46782527734SSukumar Swaminathan uint32_t version:1; 46882527734SSukumar Swaminathan uint32_t acknowledgment:1; 4696a573d82SSukumar Swaminathan uint32_t keep:1; 4706a573d82SSukumar Swaminathan uint32_t rsvd2:24; 47182527734SSukumar Swaminathan #endif 47282527734SSukumar Swaminathan 47382527734SSukumar Swaminathan #define DL_FROM_BDE 0 /* method */ 47482527734SSukumar Swaminathan #define DL_FROM_SLIM 1 47582527734SSukumar Swaminathan 47682527734SSukumar Swaminathan #define PROGRAM_FLASH 0 /* erase_or_prog */ 47782527734SSukumar Swaminathan #define ERASE_FLASH 1 47882527734SSukumar Swaminathan 47982527734SSukumar Swaminathan uint32_t dl_to_adr; 48082527734SSukumar Swaminathan uint32_t dl_len; 48182527734SSukumar Swaminathan union 48282527734SSukumar Swaminathan { 48382527734SSukumar Swaminathan uint32_t dl_from_slim_offset; 48482527734SSukumar Swaminathan ULP_BDE dl_from_bde; 48582527734SSukumar Swaminathan ULP_BDE64 dl_from_bde64; 48682527734SSukumar Swaminathan PROG_ID prog_id; 48782527734SSukumar Swaminathan } un; 48882527734SSukumar Swaminathan } LOAD_SM_VAR; 48982527734SSukumar Swaminathan 49082527734SSukumar Swaminathan 49182527734SSukumar Swaminathan /* Structure for MB Command READ_NVPARM (02) */ 49282527734SSukumar Swaminathan /* Good for SLI2/3 and SLI4 */ 49382527734SSukumar Swaminathan 49482527734SSukumar Swaminathan typedef struct 49582527734SSukumar Swaminathan { 49682527734SSukumar Swaminathan uint32_t rsvd1[3]; /* Read as all one's */ 49782527734SSukumar Swaminathan uint32_t rsvd2; /* Read as all zero's */ 49882527734SSukumar Swaminathan uint32_t portname[2]; /* N_PORT name */ 49982527734SSukumar Swaminathan uint32_t nodename[2]; /* NODE name */ 50082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 50182527734SSukumar Swaminathan uint32_t pref_DID:24; 50282527734SSukumar Swaminathan uint32_t hardAL_PA:8; 50382527734SSukumar Swaminathan #endif 50482527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 50582527734SSukumar Swaminathan uint32_t hardAL_PA:8; 50682527734SSukumar Swaminathan uint32_t pref_DID:24; 50782527734SSukumar Swaminathan #endif 50882527734SSukumar Swaminathan uint32_t rsvd3[21]; /* Read as all one's */ 50982527734SSukumar Swaminathan } READ_NV_VAR; 51082527734SSukumar Swaminathan 51182527734SSukumar Swaminathan 51282527734SSukumar Swaminathan /* Structure for MB Command WRITE_NVPARMS (03) */ 51382527734SSukumar Swaminathan /* Good for SLI2/3 and SLI4 */ 51482527734SSukumar Swaminathan 51582527734SSukumar Swaminathan typedef struct 51682527734SSukumar Swaminathan { 51782527734SSukumar Swaminathan uint32_t rsvd1[3]; /* Must be all one's */ 51882527734SSukumar Swaminathan uint32_t rsvd2; /* Must be all zero's */ 51982527734SSukumar Swaminathan uint32_t portname[2]; /* N_PORT name */ 52082527734SSukumar Swaminathan uint32_t nodename[2]; /* NODE name */ 52182527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 52282527734SSukumar Swaminathan uint32_t pref_DID:24; 52382527734SSukumar Swaminathan uint32_t hardAL_PA:8; 52482527734SSukumar Swaminathan #endif 52582527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 52682527734SSukumar Swaminathan uint32_t hardAL_PA:8; 52782527734SSukumar Swaminathan uint32_t pref_DID:24; 52882527734SSukumar Swaminathan #endif 52982527734SSukumar Swaminathan uint32_t rsvd3[21]; /* Must be all one's */ 53082527734SSukumar Swaminathan } WRITE_NV_VAR; 53182527734SSukumar Swaminathan 53282527734SSukumar Swaminathan 53382527734SSukumar Swaminathan /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 53482527734SSukumar Swaminathan /* Good for SLI2/3 and SLI4 */ 53582527734SSukumar Swaminathan 53682527734SSukumar Swaminathan typedef struct 53782527734SSukumar Swaminathan { 53882527734SSukumar Swaminathan uint32_t rsvd1; 53982527734SSukumar Swaminathan union 54082527734SSukumar Swaminathan { 54182527734SSukumar Swaminathan struct 54282527734SSukumar Swaminathan { 54382527734SSukumar Swaminathan ULP_BDE64 xmit_bde64; 54482527734SSukumar Swaminathan ULP_BDE64 rcv_bde64; 54582527734SSukumar Swaminathan } s2; 54682527734SSukumar Swaminathan } un; 54782527734SSukumar Swaminathan } BIU_DIAG_VAR; 54882527734SSukumar Swaminathan 54982527734SSukumar Swaminathan 55082527734SSukumar Swaminathan /* Structure for MB Command INIT_LINK (05) */ 55182527734SSukumar Swaminathan /* Good for SLI2/3 and SLI4 */ 55282527734SSukumar Swaminathan 55382527734SSukumar Swaminathan typedef struct 55482527734SSukumar Swaminathan { 55582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 55682527734SSukumar Swaminathan uint32_t rsvd1:24; 55782527734SSukumar Swaminathan uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective */ 55882527734SSukumar Swaminathan /* Reset to */ 55982527734SSukumar Swaminathan #endif 56082527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 56182527734SSukumar Swaminathan uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective */ 56282527734SSukumar Swaminathan /* Reset to */ 56382527734SSukumar Swaminathan uint32_t rsvd1:24; 56482527734SSukumar Swaminathan #endif 56582527734SSukumar Swaminathan 56682527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 56782527734SSukumar Swaminathan uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 56882527734SSukumar Swaminathan uint8_t rsvd2; 56982527734SSukumar Swaminathan uint16_t link_flags; 57082527734SSukumar Swaminathan #endif 57182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 57282527734SSukumar Swaminathan uint16_t link_flags; 57382527734SSukumar Swaminathan uint8_t rsvd2; 57482527734SSukumar Swaminathan uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 57582527734SSukumar Swaminathan #endif 57682527734SSukumar Swaminathan #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) */ 57782527734SSukumar Swaminathan /* ENDEC loopback */ 57882527734SSukumar Swaminathan #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 57982527734SSukumar Swaminathan #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 58082527734SSukumar Swaminathan #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 58182527734SSukumar Swaminathan #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 58282527734SSukumar Swaminathan #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 58382527734SSukumar Swaminathan 58482527734SSukumar Swaminathan #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 58582527734SSukumar Swaminathan #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 58682527734SSukumar Swaminathan #define FLAGS_PREABORT_RETURN 0x4000 /* Bit 14 */ 58782527734SSukumar Swaminathan 58882527734SSukumar Swaminathan uint32_t link_speed; /* NEW_FEATURE */ 589a3170057SPaul Winder #define LINK_SPEED_AUTO 0x0 /* Auto selection */ 590a3170057SPaul Winder #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 591a3170057SPaul Winder #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 592a3170057SPaul Winder #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 593a3170057SPaul Winder #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 594a3170057SPaul Winder #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 595a3170057SPaul Winder #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 596a3170057SPaul Winder #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */ 597a3170057SPaul Winder 59882527734SSukumar Swaminathan } INIT_LINK_VAR; 59982527734SSukumar Swaminathan 60082527734SSukumar Swaminathan 60182527734SSukumar Swaminathan /* Structure for MB Command DOWN_LINK (06) */ 60282527734SSukumar Swaminathan /* Good for SLI2/3 and SLI4 */ 60382527734SSukumar Swaminathan 60482527734SSukumar Swaminathan typedef struct 60582527734SSukumar Swaminathan { 60682527734SSukumar Swaminathan uint32_t rsvd1; 60782527734SSukumar Swaminathan } DOWN_LINK_VAR; 60882527734SSukumar Swaminathan 60982527734SSukumar Swaminathan 61082527734SSukumar Swaminathan /* Structure for MB Command CONFIG_LINK (07) */ 61182527734SSukumar Swaminathan 61282527734SSukumar Swaminathan typedef struct 61382527734SSukumar Swaminathan { 61482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 61582527734SSukumar Swaminathan uint32_t cr:1; 61682527734SSukumar Swaminathan uint32_t ci:1; 61782527734SSukumar Swaminathan uint32_t cr_delay:6; 61882527734SSukumar Swaminathan uint32_t cr_count:8; 61982527734SSukumar Swaminathan uint32_t rsvd1:8; 62082527734SSukumar Swaminathan uint32_t MaxBBC:8; 62182527734SSukumar Swaminathan #endif 62282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 623*e2d1a434SCarsten Grzemba uint32_t MaxBBC:8; /* Word 0 */ 62482527734SSukumar Swaminathan uint32_t rsvd1:8; 62582527734SSukumar Swaminathan uint32_t cr_count:8; 62682527734SSukumar Swaminathan uint32_t cr_delay:6; 62782527734SSukumar Swaminathan uint32_t ci:1; 62882527734SSukumar Swaminathan uint32_t cr:1; 62982527734SSukumar Swaminathan #endif 630*e2d1a434SCarsten Grzemba uint32_t myId; /* Word 1: alpa,n_port_id */ 63182527734SSukumar Swaminathan uint32_t rsvd2; 632*e2d1a434SCarsten Grzemba uint32_t edtov; /* Word 3 */ 633*e2d1a434SCarsten Grzemba uint32_t arbtov; /* Word 4, lp_tov */ 634*e2d1a434SCarsten Grzemba uint32_t ratov; /* Word 5 */ 63582527734SSukumar Swaminathan uint32_t rttov; 636*e2d1a434SCarsten Grzemba uint32_t altov; /* Word 7 */ 637*e2d1a434SCarsten Grzemba uint32_t crtov; /* Word 8, rsvd9 */ 63882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 63982527734SSukumar Swaminathan uint32_t rrq_enable:1; 64082527734SSukumar Swaminathan uint32_t rrq_immed:1; 64182527734SSukumar Swaminathan uint32_t rsvd4:29; 64282527734SSukumar Swaminathan uint32_t ack0_enable:1; 643*e2d1a434SCarsten Grzemba uint32_t rsvd5:19; 644*e2d1a434SCarsten Grzemba uint32_t cscn:1; 645*e2d1a434SCarsten Grzemba uint32_t bbscn:4; 646*e2d1a434SCarsten Grzemba uint32_t rsvd3:8; /* Word 9 */ 64782527734SSukumar Swaminathan #endif 64882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 649*e2d1a434SCarsten Grzemba uint32_t rsvd3:8; /* Word 9 */ 650*e2d1a434SCarsten Grzemba uint32_t bbscn:4; 651*e2d1a434SCarsten Grzemba uint32_t cscn:1; 652*e2d1a434SCarsten Grzemba uint32_t rsvd5:19; 653*e2d1a434SCarsten Grzemba uint32_t ack0_enable:1; /* Word 10, BSD dont have, but Linux */ 65482527734SSukumar Swaminathan uint32_t rsvd4:29; 65582527734SSukumar Swaminathan uint32_t rrq_immed:1; 65682527734SSukumar Swaminathan uint32_t rrq_enable:1; 65782527734SSukumar Swaminathan #endif 65882527734SSukumar Swaminathan } CONFIG_LINK; 65982527734SSukumar Swaminathan 66082527734SSukumar Swaminathan 66182527734SSukumar Swaminathan /* Structure for MB Command PART_SLIM (08) */ 66282527734SSukumar Swaminathan 66382527734SSukumar Swaminathan typedef struct 66482527734SSukumar Swaminathan { 66582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 66682527734SSukumar Swaminathan uint32_t unused1:24; 66782527734SSukumar Swaminathan uint32_t numRing:8; 66882527734SSukumar Swaminathan #endif 66982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 67082527734SSukumar Swaminathan uint32_t numRing:8; 67182527734SSukumar Swaminathan uint32_t unused1:24; 67282527734SSukumar Swaminathan #endif 67382527734SSukumar Swaminathan emlxs_ring_def_t ringdef[4]; 67482527734SSukumar Swaminathan uint32_t hbainit; 67582527734SSukumar Swaminathan } PART_SLIM_VAR; 67682527734SSukumar Swaminathan 67782527734SSukumar Swaminathan 67882527734SSukumar Swaminathan /* Structure for MB Command CONFIG_RING (09) */ 67982527734SSukumar Swaminathan 68082527734SSukumar Swaminathan typedef struct 68182527734SSukumar Swaminathan { 68282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 68382527734SSukumar Swaminathan uint32_t unused2:6; 68482527734SSukumar Swaminathan uint32_t recvSeq:1; 68582527734SSukumar Swaminathan uint32_t recvNotify:1; 68682527734SSukumar Swaminathan uint32_t numMask:8; 68782527734SSukumar Swaminathan uint32_t profile:8; 68882527734SSukumar Swaminathan uint32_t unused1:4; 68982527734SSukumar Swaminathan uint32_t ring:4; 69082527734SSukumar Swaminathan #endif 69182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 69282527734SSukumar Swaminathan uint32_t ring:4; 69382527734SSukumar Swaminathan uint32_t unused1:4; 69482527734SSukumar Swaminathan uint32_t profile:8; 69582527734SSukumar Swaminathan uint32_t numMask:8; 69682527734SSukumar Swaminathan uint32_t recvNotify:1; 69782527734SSukumar Swaminathan uint32_t recvSeq:1; 69882527734SSukumar Swaminathan uint32_t unused2:6; 69982527734SSukumar Swaminathan #endif 70082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 70182527734SSukumar Swaminathan uint16_t maxRespXchg; 70282527734SSukumar Swaminathan uint16_t maxOrigXchg; 70382527734SSukumar Swaminathan #endif 70482527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 70582527734SSukumar Swaminathan uint16_t maxOrigXchg; 70682527734SSukumar Swaminathan uint16_t maxRespXchg; 70782527734SSukumar Swaminathan #endif 70882527734SSukumar Swaminathan RR_REG rrRegs[6]; 70982527734SSukumar Swaminathan } CONFIG_RING_VAR; 71082527734SSukumar Swaminathan 71182527734SSukumar Swaminathan 71282527734SSukumar Swaminathan /* Structure for MB Command RESET_RING (10) */ 71382527734SSukumar Swaminathan 71482527734SSukumar Swaminathan typedef struct 71582527734SSukumar Swaminathan { 71682527734SSukumar Swaminathan uint32_t ring_no; 71782527734SSukumar Swaminathan } RESET_RING_VAR; 71882527734SSukumar Swaminathan 71982527734SSukumar Swaminathan 72082527734SSukumar Swaminathan /* Structure for MB Command READ_CONFIG (11) */ 72182527734SSukumar Swaminathan /* Good for SLI2/3 only */ 72282527734SSukumar Swaminathan 72382527734SSukumar Swaminathan typedef struct 72482527734SSukumar Swaminathan { 72582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 72682527734SSukumar Swaminathan uint32_t cr:1; 72782527734SSukumar Swaminathan uint32_t ci:1; 72882527734SSukumar Swaminathan uint32_t cr_delay:6; 72982527734SSukumar Swaminathan uint32_t cr_count:8; 73082527734SSukumar Swaminathan uint32_t InitBBC:8; 73182527734SSukumar Swaminathan uint32_t MaxBBC:8; 73282527734SSukumar Swaminathan #endif 73382527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 73482527734SSukumar Swaminathan uint32_t MaxBBC:8; 73582527734SSukumar Swaminathan uint32_t InitBBC:8; 73682527734SSukumar Swaminathan uint32_t cr_count:8; 73782527734SSukumar Swaminathan uint32_t cr_delay:6; 73882527734SSukumar Swaminathan uint32_t ci:1; 73982527734SSukumar Swaminathan uint32_t cr:1; 74082527734SSukumar Swaminathan #endif 74182527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 74282527734SSukumar Swaminathan uint32_t topology:8; 74382527734SSukumar Swaminathan uint32_t myDid:24; 74482527734SSukumar Swaminathan #endif 74582527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 74682527734SSukumar Swaminathan uint32_t myDid:24; 74782527734SSukumar Swaminathan uint32_t topology:8; 74882527734SSukumar Swaminathan #endif 74982527734SSukumar Swaminathan /* Defines for topology (defined previously) */ 75082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 75182527734SSukumar Swaminathan uint32_t AR:1; 75282527734SSukumar Swaminathan uint32_t IR:1; 75382527734SSukumar Swaminathan uint32_t rsvd1:29; 75482527734SSukumar Swaminathan uint32_t ack0:1; 75582527734SSukumar Swaminathan #endif 75682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 75782527734SSukumar Swaminathan uint32_t ack0:1; 75882527734SSukumar Swaminathan uint32_t rsvd1:29; 75982527734SSukumar Swaminathan uint32_t IR:1; 76082527734SSukumar Swaminathan uint32_t AR:1; 76182527734SSukumar Swaminathan #endif 76282527734SSukumar Swaminathan uint32_t edtov; 76382527734SSukumar Swaminathan uint32_t arbtov; 76482527734SSukumar Swaminathan uint32_t ratov; 76582527734SSukumar Swaminathan uint32_t rttov; 76682527734SSukumar Swaminathan uint32_t altov; 76782527734SSukumar Swaminathan uint32_t lmt; 76882527734SSukumar Swaminathan 76982527734SSukumar Swaminathan #define LMT_1GB_CAPABLE 0x0004 77082527734SSukumar Swaminathan #define LMT_2GB_CAPABLE 0x0008 77182527734SSukumar Swaminathan #define LMT_4GB_CAPABLE 0x0040 77282527734SSukumar Swaminathan #define LMT_8GB_CAPABLE 0x0080 77382527734SSukumar Swaminathan #define LMT_10GB_CAPABLE 0x0100 7748f23e9faSHans Rosenfeld #define LMT_16GB_CAPABLE 0x0200 775a3170057SPaul Winder #define LMT_32GB_CAPABLE 0x0400 77682527734SSukumar Swaminathan /* E2E supported on adapters >= 8GB */ 77782527734SSukumar Swaminathan #define LMT_E2E_CAPABLE (LMT_8GB_CAPABLE|LMT_10GB_CAPABLE) 77882527734SSukumar Swaminathan 77982527734SSukumar Swaminathan uint32_t rsvd2; 78082527734SSukumar Swaminathan uint32_t rsvd3; 78182527734SSukumar Swaminathan uint32_t max_xri; 78282527734SSukumar Swaminathan uint32_t max_iocb; 78382527734SSukumar Swaminathan uint32_t max_rpi; 78482527734SSukumar Swaminathan uint32_t avail_xri; 78582527734SSukumar Swaminathan uint32_t avail_iocb; 78682527734SSukumar Swaminathan uint32_t avail_rpi; 78782527734SSukumar Swaminathan uint32_t max_vpi; 78882527734SSukumar Swaminathan uint32_t max_alpa; 78982527734SSukumar Swaminathan uint32_t rsvd4; 79082527734SSukumar Swaminathan uint32_t avail_vpi; 79182527734SSukumar Swaminathan 79282527734SSukumar Swaminathan } READ_CONFIG_VAR; 79382527734SSukumar Swaminathan 79482527734SSukumar Swaminathan 79582527734SSukumar Swaminathan /* Structure for MB Command READ_CONFIG(0x11) */ 79682527734SSukumar Swaminathan /* Good for SLI4 only */ 79782527734SSukumar Swaminathan 79882527734SSukumar Swaminathan typedef struct 79982527734SSukumar Swaminathan { 80082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 8018f23e9faSHans Rosenfeld uint32_t extents:1; /* Word 1 */ 8028f23e9faSHans Rosenfeld uint32_t rsvd1:31; 8038f23e9faSHans Rosenfeld 8048f23e9faSHans Rosenfeld uint32_t topology:8; /* Word 2 */ 805*e2d1a434SCarsten Grzemba uint32_t ptv:1; 806*e2d1a434SCarsten Grzemba uint32_t tf:1; 807*e2d1a434SCarsten Grzemba uint32_t pt:2; 808*e2d1a434SCarsten Grzemba uint32_t :4; 809*e2d1a434SCarsten Grzemba uint32_t trunk:4; 810*e2d1a434SCarsten Grzemba uint32_t :3; 8118f23e9faSHans Rosenfeld uint32_t ldv:1; 8128f23e9faSHans Rosenfeld uint32_t link_type:2; 8138f23e9faSHans Rosenfeld uint32_t link_number:6; 81482527734SSukumar Swaminathan #endif 81582527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 8168f23e9faSHans Rosenfeld uint32_t rsvd1:31; /* Word 1 */ 8178f23e9faSHans Rosenfeld uint32_t extents:1; 8188f23e9faSHans Rosenfeld 8198f23e9faSHans Rosenfeld uint32_t link_number:6; /* Word 2 */ 8208f23e9faSHans Rosenfeld uint32_t link_type:2; 8218f23e9faSHans Rosenfeld uint32_t ldv:1; 822*e2d1a434SCarsten Grzemba uint32_t :3; 823*e2d1a434SCarsten Grzemba uint32_t trunk:4; 824*e2d1a434SCarsten Grzemba uint32_t :4; 825*e2d1a434SCarsten Grzemba uint32_t pt:2; 826*e2d1a434SCarsten Grzemba uint32_t tf:1; 827*e2d1a434SCarsten Grzemba uint32_t ptv:1; 82882527734SSukumar Swaminathan uint32_t topology:8; 82982527734SSukumar Swaminathan #endif 83082527734SSukumar Swaminathan uint32_t rsvd3; /* Word 3 */ 831*e2d1a434SCarsten Grzemba uint32_t edtov; /* Word 4 E_D_TOV timer value */ 83282527734SSukumar Swaminathan uint32_t rsvd4; /* Word 5 */ 833*e2d1a434SCarsten Grzemba uint32_t ratov; /* Word 6 R_A_TOV timer value */ 83482527734SSukumar Swaminathan uint32_t rsvd5; /* Word 7 */ 83582527734SSukumar Swaminathan uint32_t rsvd6; /* Word 8 */ 83682527734SSukumar Swaminathan uint32_t lmt; /* Word 9 */ 83782527734SSukumar Swaminathan uint32_t rsvd8; /* Word 10 */ 83882527734SSukumar Swaminathan uint32_t rsvd9; /* Word 11 */ 83982527734SSukumar Swaminathan 84082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 84182527734SSukumar Swaminathan uint16_t XRICount; /* Word 12 */ 84282527734SSukumar Swaminathan uint16_t XRIBase; /* Word 12 */ 84382527734SSukumar Swaminathan 84482527734SSukumar Swaminathan uint16_t RPICount; /* Word 13 */ 84582527734SSukumar Swaminathan uint16_t RPIBase; /* Word 13 */ 84682527734SSukumar Swaminathan 84782527734SSukumar Swaminathan uint16_t VPICount; /* Word 14 */ 84882527734SSukumar Swaminathan uint16_t VPIBase; /* Word 14 */ 84982527734SSukumar Swaminathan 85082527734SSukumar Swaminathan uint16_t VFICount; /* Word 15 */ 85182527734SSukumar Swaminathan uint16_t VFIBase; /* Word 15 */ 85282527734SSukumar Swaminathan 85382527734SSukumar Swaminathan uint16_t FCFICount; /* Word 16 */ 85482527734SSukumar Swaminathan uint16_t rsvd10; /* Word 16 */ 85582527734SSukumar Swaminathan 85682527734SSukumar Swaminathan uint16_t EQCount; /* Word 17 */ 85782527734SSukumar Swaminathan uint16_t RQCount; /* Word 17 */ 85882527734SSukumar Swaminathan 85982527734SSukumar Swaminathan uint16_t CQCount; /* Word 18 */ 86082527734SSukumar Swaminathan uint16_t WQCount; /* Word 18 */ 86182527734SSukumar Swaminathan #endif 86282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 86382527734SSukumar Swaminathan uint16_t XRIBase; /* Word 12 */ 86482527734SSukumar Swaminathan uint16_t XRICount; /* Word 12 */ 86582527734SSukumar Swaminathan 86682527734SSukumar Swaminathan uint16_t RPIBase; /* Word 13 */ 86782527734SSukumar Swaminathan uint16_t RPICount; /* Word 13 */ 86882527734SSukumar Swaminathan 86982527734SSukumar Swaminathan uint16_t VPIBase; /* Word 14 */ 87082527734SSukumar Swaminathan uint16_t VPICount; /* Word 14 */ 87182527734SSukumar Swaminathan 87282527734SSukumar Swaminathan uint16_t VFIBase; /* Word 15 */ 87382527734SSukumar Swaminathan uint16_t VFICount; /* Word 15 */ 87482527734SSukumar Swaminathan 87582527734SSukumar Swaminathan uint16_t rsvd10; /* Word 16 */ 87682527734SSukumar Swaminathan uint16_t FCFICount; /* Word 16 */ 87782527734SSukumar Swaminathan 87882527734SSukumar Swaminathan uint16_t RQCount; /* Word 17 */ 8798f23e9faSHans Rosenfeld uint16_t EQCount; /* Word 17 */ 88082527734SSukumar Swaminathan 88182527734SSukumar Swaminathan uint16_t WQCount; /* Word 18 */ 8828f23e9faSHans Rosenfeld uint16_t CQCount; /* Word 18 */ 88382527734SSukumar Swaminathan #endif 88482527734SSukumar Swaminathan 88582527734SSukumar Swaminathan } READ_CONFIG4_VAR; 88682527734SSukumar Swaminathan 88782527734SSukumar Swaminathan /* Structure for MB Command READ_RCONFIG (12) */ 88882527734SSukumar Swaminathan 88982527734SSukumar Swaminathan typedef struct 89082527734SSukumar Swaminathan { 89182527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 89282527734SSukumar Swaminathan uint32_t rsvd2:7; 89382527734SSukumar Swaminathan uint32_t recvNotify:1; 89482527734SSukumar Swaminathan uint32_t numMask:8; 89582527734SSukumar Swaminathan uint32_t profile:8; 89682527734SSukumar Swaminathan uint32_t rsvd1:4; 89782527734SSukumar Swaminathan uint32_t ring:4; 89882527734SSukumar Swaminathan #endif 89982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 90082527734SSukumar Swaminathan uint32_t ring:4; 90182527734SSukumar Swaminathan uint32_t rsvd1:4; 90282527734SSukumar Swaminathan uint32_t profile:8; 90382527734SSukumar Swaminathan uint32_t numMask:8; 90482527734SSukumar Swaminathan uint32_t recvNotify:1; 90582527734SSukumar Swaminathan uint32_t rsvd2:7; 90682527734SSukumar Swaminathan #endif 90782527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 90882527734SSukumar Swaminathan uint16_t maxResp; 90982527734SSukumar Swaminathan uint16_t maxOrig; 91082527734SSukumar Swaminathan #endif 91182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 91282527734SSukumar Swaminathan uint16_t maxOrig; 91382527734SSukumar Swaminathan uint16_t maxResp; 91482527734SSukumar Swaminathan #endif 91582527734SSukumar Swaminathan RR_REG rrRegs[6]; 91682527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 91782527734SSukumar Swaminathan uint16_t cmdRingOffset; 91882527734SSukumar Swaminathan uint16_t cmdEntryCnt; 91982527734SSukumar Swaminathan uint16_t rspRingOffset; 92082527734SSukumar Swaminathan uint16_t rspEntryCnt; 92182527734SSukumar Swaminathan uint16_t nextCmdOffset; 92282527734SSukumar Swaminathan uint16_t rsvd3; 92382527734SSukumar Swaminathan uint16_t nextRspOffset; 92482527734SSukumar Swaminathan uint16_t rsvd4; 92582527734SSukumar Swaminathan #endif 92682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 92782527734SSukumar Swaminathan uint16_t cmdEntryCnt; 92882527734SSukumar Swaminathan uint16_t cmdRingOffset; 92982527734SSukumar Swaminathan uint16_t rspEntryCnt; 93082527734SSukumar Swaminathan uint16_t rspRingOffset; 93182527734SSukumar Swaminathan uint16_t rsvd3; 93282527734SSukumar Swaminathan uint16_t nextCmdOffset; 93382527734SSukumar Swaminathan uint16_t rsvd4; 93482527734SSukumar Swaminathan uint16_t nextRspOffset; 93582527734SSukumar Swaminathan #endif 93682527734SSukumar Swaminathan } READ_RCONF_VAR; 93782527734SSukumar Swaminathan 93882527734SSukumar Swaminathan 93982527734SSukumar Swaminathan /* Structure for MB Command READ_SPARM (13) */ 94082527734SSukumar Swaminathan /* Structure for MB Command READ_SPARM64 (0x8D) */ 94182527734SSukumar Swaminathan /* Good for SLI2/3 and SLI4 */ 94282527734SSukumar Swaminathan 94382527734SSukumar Swaminathan typedef struct 94482527734SSukumar Swaminathan { 94582527734SSukumar Swaminathan uint32_t rsvd1; 94682527734SSukumar Swaminathan uint32_t rsvd2; 94782527734SSukumar Swaminathan union 94882527734SSukumar Swaminathan { 94982527734SSukumar Swaminathan ULP_BDE sp; /* This BDE points to SERV_PARM */ 95082527734SSukumar Swaminathan /* structure */ 95182527734SSukumar Swaminathan ULP_BDE64 sp64; 95282527734SSukumar Swaminathan } un; 95382527734SSukumar Swaminathan uint32_t rsvd3; 95482527734SSukumar Swaminathan 95582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 95682527734SSukumar Swaminathan uint16_t portNameCnt; 95782527734SSukumar Swaminathan uint16_t portNameOffset; 95882527734SSukumar Swaminathan 95982527734SSukumar Swaminathan uint16_t fabricNameCnt; 96082527734SSukumar Swaminathan uint16_t fabricNameOffset; 96182527734SSukumar Swaminathan 96282527734SSukumar Swaminathan uint16_t lportNameCnt; 96382527734SSukumar Swaminathan uint16_t lportNameOffset; 96482527734SSukumar Swaminathan 96582527734SSukumar Swaminathan uint16_t lfabricNameCnt; 96682527734SSukumar Swaminathan uint16_t lfabricNameOffset; 96782527734SSukumar Swaminathan 96882527734SSukumar Swaminathan #endif 96982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 97082527734SSukumar Swaminathan uint16_t portNameOffset; 97182527734SSukumar Swaminathan uint16_t portNameCnt; 97282527734SSukumar Swaminathan 97382527734SSukumar Swaminathan uint16_t fabricNameOffset; 97482527734SSukumar Swaminathan uint16_t fabricNameCnt; 97582527734SSukumar Swaminathan 97682527734SSukumar Swaminathan uint16_t lportNameOffset; 97782527734SSukumar Swaminathan uint16_t lportNameCnt; 97882527734SSukumar Swaminathan 97982527734SSukumar Swaminathan uint16_t lfabricNameOffset; 98082527734SSukumar Swaminathan uint16_t lfabricNameCnt; 98182527734SSukumar Swaminathan 98282527734SSukumar Swaminathan #endif 98382527734SSukumar Swaminathan 98482527734SSukumar Swaminathan } READ_SPARM_VAR; 98582527734SSukumar Swaminathan 98682527734SSukumar Swaminathan 98782527734SSukumar Swaminathan /* Structure for MB Command READ_STATUS (14) */ 98882527734SSukumar Swaminathan /* Good for SLI2/3 and SLI4 */ 98982527734SSukumar Swaminathan 99082527734SSukumar Swaminathan typedef struct 99182527734SSukumar Swaminathan { 99282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 99382527734SSukumar Swaminathan uint32_t rsvd1:31; 99482527734SSukumar Swaminathan uint32_t clrCounters:1; 99582527734SSukumar Swaminathan 99682527734SSukumar Swaminathan uint16_t activeXriCnt; 99782527734SSukumar Swaminathan uint16_t activeRpiCnt; 99882527734SSukumar Swaminathan #endif 99982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 100082527734SSukumar Swaminathan uint32_t clrCounters:1; 100182527734SSukumar Swaminathan uint32_t rsvd1:31; 100282527734SSukumar Swaminathan 100382527734SSukumar Swaminathan uint16_t activeRpiCnt; 100482527734SSukumar Swaminathan uint16_t activeXriCnt; 100582527734SSukumar Swaminathan #endif 100682527734SSukumar Swaminathan uint32_t xmitByteCnt; 100782527734SSukumar Swaminathan uint32_t rcvByteCnt; 100882527734SSukumar Swaminathan uint32_t xmitFrameCnt; 100982527734SSukumar Swaminathan uint32_t rcvFrameCnt; 101082527734SSukumar Swaminathan uint32_t xmitSeqCnt; 101182527734SSukumar Swaminathan uint32_t rcvSeqCnt; 101282527734SSukumar Swaminathan uint32_t totalOrigExchanges; 101382527734SSukumar Swaminathan uint32_t totalRespExchanges; 101482527734SSukumar Swaminathan uint32_t rcvPbsyCnt; 101582527734SSukumar Swaminathan uint32_t rcvFbsyCnt; 101682527734SSukumar Swaminathan } READ_STATUS_VAR; 101782527734SSukumar Swaminathan 101882527734SSukumar Swaminathan 101982527734SSukumar Swaminathan /* Structure for MB Command READ_RPI (15) */ 102082527734SSukumar Swaminathan /* Structure for MB Command READ_RPI64 (0x8F) */ 102182527734SSukumar Swaminathan 102282527734SSukumar Swaminathan typedef struct 102382527734SSukumar Swaminathan { 102482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 102582527734SSukumar Swaminathan uint16_t nextRpi; 102682527734SSukumar Swaminathan uint16_t reqRpi; 102782527734SSukumar Swaminathan uint32_t rsvd2:8; 102882527734SSukumar Swaminathan uint32_t DID:24; 102982527734SSukumar Swaminathan #endif 103082527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 103182527734SSukumar Swaminathan uint16_t reqRpi; 103282527734SSukumar Swaminathan uint16_t nextRpi; 103382527734SSukumar Swaminathan uint32_t DID:24; 103482527734SSukumar Swaminathan uint32_t rsvd2:8; 103582527734SSukumar Swaminathan #endif 103682527734SSukumar Swaminathan union 103782527734SSukumar Swaminathan { 103882527734SSukumar Swaminathan ULP_BDE sp; 103982527734SSukumar Swaminathan ULP_BDE64 sp64; 104082527734SSukumar Swaminathan } un; 104182527734SSukumar Swaminathan } READ_RPI_VAR; 104282527734SSukumar Swaminathan 104382527734SSukumar Swaminathan 104482527734SSukumar Swaminathan /* Structure for MB Command READ_XRI (16) */ 104582527734SSukumar Swaminathan 104682527734SSukumar Swaminathan typedef struct 104782527734SSukumar Swaminathan { 104882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 104982527734SSukumar Swaminathan uint16_t nextXri; 105082527734SSukumar Swaminathan uint16_t reqXri; 105182527734SSukumar Swaminathan uint16_t rsvd1; 105282527734SSukumar Swaminathan uint16_t rpi; 105382527734SSukumar Swaminathan uint32_t rsvd2:8; 105482527734SSukumar Swaminathan uint32_t DID:24; 105582527734SSukumar Swaminathan uint32_t rsvd3:8; 105682527734SSukumar Swaminathan uint32_t SID:24; 105782527734SSukumar Swaminathan uint32_t rsvd4; 105882527734SSukumar Swaminathan uint8_t seqId; 105982527734SSukumar Swaminathan uint8_t rsvd5; 106082527734SSukumar Swaminathan uint16_t seqCount; 106182527734SSukumar Swaminathan uint16_t oxId; 106282527734SSukumar Swaminathan uint16_t rxId; 106382527734SSukumar Swaminathan uint32_t rsvd6:30; 106482527734SSukumar Swaminathan uint32_t si:1; 106582527734SSukumar Swaminathan uint32_t exchOrig:1; 106682527734SSukumar Swaminathan #endif 106782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 106882527734SSukumar Swaminathan uint16_t reqXri; 106982527734SSukumar Swaminathan uint16_t nextXri; 107082527734SSukumar Swaminathan uint16_t rpi; 107182527734SSukumar Swaminathan uint16_t rsvd1; 107282527734SSukumar Swaminathan uint32_t DID:24; 107382527734SSukumar Swaminathan uint32_t rsvd2:8; 107482527734SSukumar Swaminathan uint32_t SID:24; 107582527734SSukumar Swaminathan uint32_t rsvd3:8; 107682527734SSukumar Swaminathan uint32_t rsvd4; 107782527734SSukumar Swaminathan uint16_t seqCount; 107882527734SSukumar Swaminathan uint8_t rsvd5; 107982527734SSukumar Swaminathan uint8_t seqId; 108082527734SSukumar Swaminathan uint16_t rxId; 108182527734SSukumar Swaminathan uint16_t oxId; 108282527734SSukumar Swaminathan uint32_t exchOrig:1; 108382527734SSukumar Swaminathan uint32_t si:1; 108482527734SSukumar Swaminathan uint32_t rsvd6:30; 108582527734SSukumar Swaminathan #endif 108682527734SSukumar Swaminathan } READ_XRI_VAR; 108782527734SSukumar Swaminathan 108882527734SSukumar Swaminathan 108982527734SSukumar Swaminathan /* Structure for MB Command READ_REV (17) */ 109082527734SSukumar Swaminathan /* Good for SLI2/3 only */ 109182527734SSukumar Swaminathan 109282527734SSukumar Swaminathan typedef struct 109382527734SSukumar Swaminathan { 109482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 109582527734SSukumar Swaminathan uint32_t cv:1; 109682527734SSukumar Swaminathan uint32_t rr:1; 109782527734SSukumar Swaminathan uint32_t co:1; 109882527734SSukumar Swaminathan uint32_t rp:1; 109982527734SSukumar Swaminathan uint32_t cv3:1; 110082527734SSukumar Swaminathan uint32_t rf3:1; 110182527734SSukumar Swaminathan uint32_t rsvd1:10; 110282527734SSukumar Swaminathan uint32_t offset:14; 110382527734SSukumar Swaminathan uint32_t rv:2; 110482527734SSukumar Swaminathan #endif 110582527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 110682527734SSukumar Swaminathan uint32_t rv:2; 110782527734SSukumar Swaminathan uint32_t offset:14; 110882527734SSukumar Swaminathan uint32_t rsvd1:10; 110982527734SSukumar Swaminathan uint32_t rf3:1; 111082527734SSukumar Swaminathan uint32_t cv3:1; 111182527734SSukumar Swaminathan uint32_t rp:1; 111282527734SSukumar Swaminathan uint32_t co:1; 111382527734SSukumar Swaminathan uint32_t rr:1; 111482527734SSukumar Swaminathan uint32_t cv:1; 111582527734SSukumar Swaminathan #endif 111682527734SSukumar Swaminathan uint32_t biuRev; 111782527734SSukumar Swaminathan uint32_t smRev; 111882527734SSukumar Swaminathan union 111982527734SSukumar Swaminathan { 112082527734SSukumar Swaminathan uint32_t smFwRev; 112182527734SSukumar Swaminathan struct 112282527734SSukumar Swaminathan { 112382527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 112482527734SSukumar Swaminathan uint8_t ProgType; 112582527734SSukumar Swaminathan uint8_t ProgId; 112682527734SSukumar Swaminathan uint16_t ProgVer:4; 112782527734SSukumar Swaminathan uint16_t ProgRev:4; 112882527734SSukumar Swaminathan uint16_t ProgFixLvl:2; 112982527734SSukumar Swaminathan uint16_t ProgDistType:2; 113082527734SSukumar Swaminathan uint16_t DistCnt:4; 113182527734SSukumar Swaminathan #endif 113282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 113382527734SSukumar Swaminathan uint16_t DistCnt:4; 113482527734SSukumar Swaminathan uint16_t ProgDistType:2; 113582527734SSukumar Swaminathan uint16_t ProgFixLvl:2; 113682527734SSukumar Swaminathan uint16_t ProgRev:4; 113782527734SSukumar Swaminathan uint16_t ProgVer:4; 113882527734SSukumar Swaminathan uint8_t ProgId; 113982527734SSukumar Swaminathan uint8_t ProgType; 114082527734SSukumar Swaminathan #endif 114182527734SSukumar Swaminathan } b; 114282527734SSukumar Swaminathan } un; 114382527734SSukumar Swaminathan uint32_t endecRev; 114482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 114582527734SSukumar Swaminathan uint8_t feaLevelHigh; 114682527734SSukumar Swaminathan uint8_t feaLevelLow; 114782527734SSukumar Swaminathan uint8_t fcphHigh; 114882527734SSukumar Swaminathan uint8_t fcphLow; 114982527734SSukumar Swaminathan #endif 115082527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 115182527734SSukumar Swaminathan uint8_t fcphLow; 115282527734SSukumar Swaminathan uint8_t fcphHigh; 115382527734SSukumar Swaminathan uint8_t feaLevelLow; 115482527734SSukumar Swaminathan uint8_t feaLevelHigh; 115582527734SSukumar Swaminathan #endif 115682527734SSukumar Swaminathan uint32_t postKernRev; 115782527734SSukumar Swaminathan uint32_t opFwRev; 115882527734SSukumar Swaminathan uint8_t opFwName[16]; 115982527734SSukumar Swaminathan 116082527734SSukumar Swaminathan uint32_t sliFwRev1; 116182527734SSukumar Swaminathan uint8_t sliFwName1[16]; 116282527734SSukumar Swaminathan uint32_t sliFwRev2; 116382527734SSukumar Swaminathan uint8_t sliFwName2[16]; 116482527734SSukumar Swaminathan } READ_REV_VAR; 116582527734SSukumar Swaminathan 116682527734SSukumar Swaminathan /* Structure for MB Command READ_REV (17) */ 116782527734SSukumar Swaminathan /* Good for SLI4 only */ 116882527734SSukumar Swaminathan 116982527734SSukumar Swaminathan typedef struct 117082527734SSukumar Swaminathan { 117182527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 117282527734SSukumar Swaminathan uint32_t Rsvd3:2; 117382527734SSukumar Swaminathan uint32_t VPD:1; 117482527734SSukumar Swaminathan uint32_t rsvd2:6; 117582527734SSukumar Swaminathan uint32_t dcbxMode:2; 117682527734SSukumar Swaminathan uint32_t FCoE:1; 117782527734SSukumar Swaminathan uint32_t sliLevel:4; 117882527734SSukumar Swaminathan uint32_t rsvd1:16; 117982527734SSukumar Swaminathan #endif 118082527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 118182527734SSukumar Swaminathan uint32_t rsvd1:16; 118282527734SSukumar Swaminathan uint32_t sliLevel:4; 118382527734SSukumar Swaminathan uint32_t FCoE:1; 118482527734SSukumar Swaminathan uint32_t dcbxMode:2; 118582527734SSukumar Swaminathan uint32_t rsvd2:6; 118682527734SSukumar Swaminathan uint32_t VPD:1; 118782527734SSukumar Swaminathan uint32_t Rsvd3:2; 118882527734SSukumar Swaminathan #endif 118982527734SSukumar Swaminathan 119082527734SSukumar Swaminathan uint32_t HwRev1; 119182527734SSukumar Swaminathan uint32_t HwRev2; 119282527734SSukumar Swaminathan uint32_t Rsvd4; 119382527734SSukumar Swaminathan uint32_t HwRev3; 119482527734SSukumar Swaminathan 119582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 119682527734SSukumar Swaminathan uint8_t feaLevelHigh; 119782527734SSukumar Swaminathan uint8_t feaLevelLow; 119882527734SSukumar Swaminathan uint8_t fcphHigh; 119982527734SSukumar Swaminathan uint8_t fcphLow; 120082527734SSukumar Swaminathan #endif 120182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 120282527734SSukumar Swaminathan uint8_t fcphLow; 120382527734SSukumar Swaminathan uint8_t fcphHigh; 120482527734SSukumar Swaminathan uint8_t feaLevelLow; 120582527734SSukumar Swaminathan uint8_t feaLevelHigh; 120682527734SSukumar Swaminathan #endif 120782527734SSukumar Swaminathan 120882527734SSukumar Swaminathan uint32_t Redboot; 120982527734SSukumar Swaminathan 121082527734SSukumar Swaminathan uint32_t ARMFwId; 121182527734SSukumar Swaminathan uint8_t ARMFwName[16]; 121282527734SSukumar Swaminathan 121382527734SSukumar Swaminathan uint32_t ULPFwId; 121482527734SSukumar Swaminathan uint8_t ULPFwName[16]; 121582527734SSukumar Swaminathan 121682527734SSukumar Swaminathan uint32_t Rsvd6[30]; 121782527734SSukumar Swaminathan 121882527734SSukumar Swaminathan ULP_BDE64 VPDBde; 121982527734SSukumar Swaminathan 122082527734SSukumar Swaminathan uint32_t ReturnedVPDLength; 122182527734SSukumar Swaminathan 122282527734SSukumar Swaminathan } READ_REV4_VAR; 122382527734SSukumar Swaminathan 122482527734SSukumar Swaminathan #define EMLXS_DCBX_MODE_CIN 0 /* Mapped to nonFIP mode */ 122582527734SSukumar Swaminathan #define EMLXS_DCBX_MODE_CEE 1 /* Mapped to FIP mode */ 122682527734SSukumar Swaminathan 122782527734SSukumar Swaminathan /* Structure for MB Command READ_LINK_STAT (18) */ 122882527734SSukumar Swaminathan /* Good for SLI2/3 and SLI4 */ 122982527734SSukumar Swaminathan 123082527734SSukumar Swaminathan typedef struct 123182527734SSukumar Swaminathan { 1232*e2d1a434SCarsten Grzemba #ifdef EMLXS_BIG_ENDIAN 1233*e2d1a434SCarsten Grzemba uint32_t clof:1; /* clear_overflow_flags */ 1234*e2d1a434SCarsten Grzemba uint32_t clrc:1; /* clear_all_counters */ 1235*e2d1a434SCarsten Grzemba uint32_t resv0:8; 1236*e2d1a434SCarsten Grzemba uint32_t w21of:1; 1237*e2d1a434SCarsten Grzemba uint32_t w20of:1; 1238*e2d1a434SCarsten Grzemba uint32_t w19of:1; 1239*e2d1a434SCarsten Grzemba uint32_t w18of:1; 1240*e2d1a434SCarsten Grzemba uint32_t w17of:1; 1241*e2d1a434SCarsten Grzemba uint32_t w16of:1; 1242*e2d1a434SCarsten Grzemba uint32_t w15of:1; 1243*e2d1a434SCarsten Grzemba uint32_t w14of:1; 1244*e2d1a434SCarsten Grzemba uint32_t w13of:1; 1245*e2d1a434SCarsten Grzemba uint32_t w12of:1; 1246*e2d1a434SCarsten Grzemba uint32_t w11of:1; 1247*e2d1a434SCarsten Grzemba uint32_t w10of:1; 1248*e2d1a434SCarsten Grzemba uint32_t w09of:1; 1249*e2d1a434SCarsten Grzemba uint32_t w08of:1; 1250*e2d1a434SCarsten Grzemba uint32_t w07of:1; 1251*e2d1a434SCarsten Grzemba uint32_t w06of:1; 1252*e2d1a434SCarsten Grzemba uint32_t w05of:1; 1253*e2d1a434SCarsten Grzemba uint32_t w04of:1; 1254*e2d1a434SCarsten Grzemba uint32_t w03of:1; 1255*e2d1a434SCarsten Grzemba uint32_t w02of:1; /* counter overflow flags */ 1256*e2d1a434SCarsten Grzemba uint32_t gec:1; 1257*e2d1a434SCarsten Grzemba uint32_t rec:1; /* req_ext_counters */ 1258*e2d1a434SCarsten Grzemba #endif 1259*e2d1a434SCarsten Grzemba #ifdef EMLXS_LITTLE_ENDIAN 1260*e2d1a434SCarsten Grzemba uint32_t rec:1; /* req_ext_counters */ 1261*e2d1a434SCarsten Grzemba uint32_t gec:1; 1262*e2d1a434SCarsten Grzemba uint32_t w02of:1; /* counter overflow flags */ 1263*e2d1a434SCarsten Grzemba uint32_t w03of:1; 1264*e2d1a434SCarsten Grzemba uint32_t w04of:1; 1265*e2d1a434SCarsten Grzemba uint32_t w05of:1; 1266*e2d1a434SCarsten Grzemba uint32_t w06of:1; 1267*e2d1a434SCarsten Grzemba uint32_t w07of:1; 1268*e2d1a434SCarsten Grzemba uint32_t w08of:1; 1269*e2d1a434SCarsten Grzemba uint32_t w09of:1; 1270*e2d1a434SCarsten Grzemba uint32_t w10of:1; 1271*e2d1a434SCarsten Grzemba uint32_t w11of:1; 1272*e2d1a434SCarsten Grzemba uint32_t w12of:1; 1273*e2d1a434SCarsten Grzemba uint32_t w13of:1; 1274*e2d1a434SCarsten Grzemba uint32_t w14of:1; 1275*e2d1a434SCarsten Grzemba uint32_t w15of:1; 1276*e2d1a434SCarsten Grzemba uint32_t w16of:1; 1277*e2d1a434SCarsten Grzemba uint32_t w17of:1; 1278*e2d1a434SCarsten Grzemba uint32_t w18of:1; 1279*e2d1a434SCarsten Grzemba uint32_t w19of:1; 1280*e2d1a434SCarsten Grzemba uint32_t w20of:1; 1281*e2d1a434SCarsten Grzemba uint32_t w21of:1; 1282*e2d1a434SCarsten Grzemba uint32_t resv0:8; 1283*e2d1a434SCarsten Grzemba uint32_t clrc:1; /* clear_all_counters */ 1284*e2d1a434SCarsten Grzemba uint32_t clof:1; /* clear_overflow_flags */ 1285*e2d1a434SCarsten Grzemba #endif 1286*e2d1a434SCarsten Grzemba 128782527734SSukumar Swaminathan uint32_t linkFailureCnt; 128882527734SSukumar Swaminathan uint32_t lossSyncCnt; 128982527734SSukumar Swaminathan 129082527734SSukumar Swaminathan uint32_t lossSignalCnt; 129182527734SSukumar Swaminathan uint32_t primSeqErrCnt; 129282527734SSukumar Swaminathan uint32_t invalidXmitWord; 129382527734SSukumar Swaminathan uint32_t crcCnt; 129482527734SSukumar Swaminathan uint32_t primSeqTimeout; 129582527734SSukumar Swaminathan uint32_t elasticOverrun; 129682527734SSukumar Swaminathan uint32_t arbTimeout; 129782527734SSukumar Swaminathan 129882527734SSukumar Swaminathan uint32_t rxBufCredit; 129982527734SSukumar Swaminathan uint32_t rxBufCreditCur; 130082527734SSukumar Swaminathan 130182527734SSukumar Swaminathan uint32_t txBufCredit; 130282527734SSukumar Swaminathan uint32_t txBufCreditCur; 130382527734SSukumar Swaminathan 130482527734SSukumar Swaminathan uint32_t EOFaCnt; 130582527734SSukumar Swaminathan uint32_t EOFdtiCnt; 130682527734SSukumar Swaminathan uint32_t EOFniCnt; 130782527734SSukumar Swaminathan uint32_t SOFfCnt; 130882527734SSukumar Swaminathan uint32_t DropAERCnt; 130982527734SSukumar Swaminathan uint32_t DropRcv; 1310*e2d1a434SCarsten Grzemba uint32_t DropRcvXri; 131182527734SSukumar Swaminathan } READ_LNK_VAR; 131282527734SSukumar Swaminathan 131382527734SSukumar Swaminathan 131482527734SSukumar Swaminathan /* Structure for MB Command REG_LOGIN (19) */ 131582527734SSukumar Swaminathan /* Structure for MB Command REG_LOGIN64 (0x93) */ 131682527734SSukumar Swaminathan /* Structure for MB Command REG_RPI (0x93) */ 131782527734SSukumar Swaminathan /* Good for SLI2/3 and SLI4 */ 131882527734SSukumar Swaminathan 131982527734SSukumar Swaminathan typedef struct 132082527734SSukumar Swaminathan { 132182527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 132282527734SSukumar Swaminathan uint16_t rsvd1; 132382527734SSukumar Swaminathan uint16_t rpi; 132482527734SSukumar Swaminathan uint32_t CI:1; 13258f23e9faSHans Rosenfeld uint32_t rsvd2:1; 13268f23e9faSHans Rosenfeld uint32_t TERP:1; 13278f23e9faSHans Rosenfeld uint32_t rsvd3:4; 13288f23e9faSHans Rosenfeld uint32_t update:1; 132982527734SSukumar Swaminathan uint32_t did:24; 133082527734SSukumar Swaminathan #endif 133182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 133282527734SSukumar Swaminathan uint16_t rpi; 133382527734SSukumar Swaminathan uint16_t rsvd1; 133482527734SSukumar Swaminathan uint32_t did:24; 13358f23e9faSHans Rosenfeld uint32_t update:1; 13368f23e9faSHans Rosenfeld uint32_t rsvd3:4; 13378f23e9faSHans Rosenfeld uint32_t TERP:1; 13388f23e9faSHans Rosenfeld uint32_t rsvd2:1; 133982527734SSukumar Swaminathan uint32_t CI:1; 134082527734SSukumar Swaminathan #endif 134182527734SSukumar Swaminathan union 134282527734SSukumar Swaminathan { 134382527734SSukumar Swaminathan ULP_BDE sp; 134482527734SSukumar Swaminathan ULP_BDE64 sp64; 134582527734SSukumar Swaminathan } un; 134682527734SSukumar Swaminathan 134782527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 134882527734SSukumar Swaminathan uint16_t rsvd6; 134982527734SSukumar Swaminathan uint16_t vpi; 135082527734SSukumar Swaminathan #endif 135182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 135282527734SSukumar Swaminathan uint16_t vpi; 135382527734SSukumar Swaminathan uint16_t rsvd6; 135482527734SSukumar Swaminathan #endif 135582527734SSukumar Swaminathan } REG_LOGIN_VAR; 135682527734SSukumar Swaminathan 135782527734SSukumar Swaminathan /* Word 30 contents for REG_LOGIN */ 135882527734SSukumar Swaminathan typedef union 135982527734SSukumar Swaminathan { 136082527734SSukumar Swaminathan struct 136182527734SSukumar Swaminathan { 136282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 136382527734SSukumar Swaminathan uint16_t rsvd1:12; 136482527734SSukumar Swaminathan uint16_t class:4; 136582527734SSukumar Swaminathan uint16_t xri; 136682527734SSukumar Swaminathan #endif 136782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 136882527734SSukumar Swaminathan uint16_t xri; 136982527734SSukumar Swaminathan uint16_t class:4; 137082527734SSukumar Swaminathan uint16_t rsvd1:12; 137182527734SSukumar Swaminathan #endif 137282527734SSukumar Swaminathan } f; 137382527734SSukumar Swaminathan uint32_t word; 137482527734SSukumar Swaminathan } REG_WD30; 137582527734SSukumar Swaminathan 137682527734SSukumar Swaminathan 137782527734SSukumar Swaminathan /* Structure for MB Command UNREG_LOGIN (0x14) - SLI2/3 */ 137882527734SSukumar Swaminathan /* Structure for MB Command UNREG_RPI (0x14) - SLI4 */ 137982527734SSukumar Swaminathan 138082527734SSukumar Swaminathan typedef struct 138182527734SSukumar Swaminathan { 138282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 138382527734SSukumar Swaminathan uint16_t ll:2; /* SLI4 only */ 138482527734SSukumar Swaminathan uint16_t rsvd1:14; 138582527734SSukumar Swaminathan uint16_t rpi; 138682527734SSukumar Swaminathan #endif 138782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 138882527734SSukumar Swaminathan uint16_t rpi; 138982527734SSukumar Swaminathan uint16_t rsvd1:14; 139082527734SSukumar Swaminathan uint16_t ll:2; /* SLI4 only */ 139182527734SSukumar Swaminathan #endif 139282527734SSukumar Swaminathan 139382527734SSukumar Swaminathan uint32_t rsvd2; 139482527734SSukumar Swaminathan uint32_t rsvd3; 139582527734SSukumar Swaminathan uint32_t rsvd4; 139682527734SSukumar Swaminathan uint32_t rsvd5; 139782527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 139882527734SSukumar Swaminathan uint16_t rsvd6; 139982527734SSukumar Swaminathan uint16_t vpi; 140082527734SSukumar Swaminathan #endif 140182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 140282527734SSukumar Swaminathan uint16_t vpi; 140382527734SSukumar Swaminathan uint16_t rsvd6; 140482527734SSukumar Swaminathan #endif 140582527734SSukumar Swaminathan } UNREG_LOGIN_VAR; 140682527734SSukumar Swaminathan 140782527734SSukumar Swaminathan /* Structure for MB Command REG_FCFI (0xA0) */ 140882527734SSukumar Swaminathan /* Good for SLI4 only */ 140982527734SSukumar Swaminathan 141082527734SSukumar Swaminathan typedef struct 141182527734SSukumar Swaminathan { 141282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 141382527734SSukumar Swaminathan uint16_t FCFI; 141482527734SSukumar Swaminathan uint16_t InfoIndex; 141582527734SSukumar Swaminathan 141682527734SSukumar Swaminathan uint16_t RQId0; 141782527734SSukumar Swaminathan uint16_t RQId1; 141882527734SSukumar Swaminathan uint16_t RQId2; 141982527734SSukumar Swaminathan uint16_t RQId3; 142082527734SSukumar Swaminathan 142182527734SSukumar Swaminathan uint8_t Id0_type; 142282527734SSukumar Swaminathan uint8_t Id0_type_mask; 142382527734SSukumar Swaminathan uint8_t Id0_rctl; 142482527734SSukumar Swaminathan uint8_t Id0_rctl_mask; 142582527734SSukumar Swaminathan 142682527734SSukumar Swaminathan uint8_t Id1_type; 142782527734SSukumar Swaminathan uint8_t Id1_type_mask; 142882527734SSukumar Swaminathan uint8_t Id1_rctl; 142982527734SSukumar Swaminathan uint8_t Id1_rctl_mask; 143082527734SSukumar Swaminathan 143182527734SSukumar Swaminathan uint8_t Id2_type; 143282527734SSukumar Swaminathan uint8_t Id2_type_mask; 143382527734SSukumar Swaminathan uint8_t Id2_rctl; 143482527734SSukumar Swaminathan uint8_t Id2_rctl_mask; 143582527734SSukumar Swaminathan 143682527734SSukumar Swaminathan uint8_t Id3_type; 143782527734SSukumar Swaminathan uint8_t Id3_type_mask; 143882527734SSukumar Swaminathan uint8_t Id3_rctl; 143982527734SSukumar Swaminathan uint8_t Id3_rctl_mask; 144082527734SSukumar Swaminathan 144182527734SSukumar Swaminathan uint32_t Rsvd1: 17; 144282527734SSukumar Swaminathan uint32_t mam: 2; 144382527734SSukumar Swaminathan uint32_t vv: 1; 144482527734SSukumar Swaminathan uint32_t vlanTag: 12; 144582527734SSukumar Swaminathan #endif 144682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 144782527734SSukumar Swaminathan uint16_t InfoIndex; 144882527734SSukumar Swaminathan uint16_t FCFI; 144982527734SSukumar Swaminathan 145082527734SSukumar Swaminathan uint16_t RQId1; 145182527734SSukumar Swaminathan uint16_t RQId0; 145282527734SSukumar Swaminathan uint16_t RQId3; 145382527734SSukumar Swaminathan uint16_t RQId2; 145482527734SSukumar Swaminathan 145582527734SSukumar Swaminathan uint8_t Id0_rctl_mask; 145682527734SSukumar Swaminathan uint8_t Id0_rctl; 145782527734SSukumar Swaminathan uint8_t Id0_type_mask; 145882527734SSukumar Swaminathan uint8_t Id0_type; 145982527734SSukumar Swaminathan 146082527734SSukumar Swaminathan uint8_t Id1_rctl_mask; 146182527734SSukumar Swaminathan uint8_t Id1_rctl; 146282527734SSukumar Swaminathan uint8_t Id1_type_mask; 146382527734SSukumar Swaminathan uint8_t Id1_type; 146482527734SSukumar Swaminathan 146582527734SSukumar Swaminathan uint8_t Id2_rctl_mask; 146682527734SSukumar Swaminathan uint8_t Id2_rctl; 146782527734SSukumar Swaminathan uint8_t Id2_type_mask; 146882527734SSukumar Swaminathan uint8_t Id2_type; 146982527734SSukumar Swaminathan 147082527734SSukumar Swaminathan uint8_t Id3_rctl_mask; 147182527734SSukumar Swaminathan uint8_t Id3_rctl; 147282527734SSukumar Swaminathan uint8_t Id3_type_mask; 147382527734SSukumar Swaminathan uint8_t Id3_type; 147482527734SSukumar Swaminathan 147582527734SSukumar Swaminathan uint32_t vlanTag: 12; 147682527734SSukumar Swaminathan uint32_t vv: 1; 147782527734SSukumar Swaminathan uint32_t mam: 2; 147882527734SSukumar Swaminathan uint32_t Rsvd1: 17; 147982527734SSukumar Swaminathan #endif 148082527734SSukumar Swaminathan 148182527734SSukumar Swaminathan } REG_FCFI_VAR; 148282527734SSukumar Swaminathan 148382527734SSukumar Swaminathan /* Defines for mam */ 148482527734SSukumar Swaminathan #define EMLXS_REG_FCFI_MAM_SPMA 1 /* Server Provided MAC Address */ 148582527734SSukumar Swaminathan #define EMLXS_REG_FCFI_MAM_FPMA 2 /* Fabric Provided MAC Address */ 148682527734SSukumar Swaminathan 148782527734SSukumar Swaminathan /* Structure for MB Command UNREG_FCFI (0xA2) */ 148882527734SSukumar Swaminathan /* Good for SLI4 only */ 148982527734SSukumar Swaminathan 149082527734SSukumar Swaminathan typedef struct 149182527734SSukumar Swaminathan { 149282527734SSukumar Swaminathan uint32_t Rsvd1; 149382527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 149482527734SSukumar Swaminathan uint16_t Rsvd2; 149582527734SSukumar Swaminathan uint16_t FCFI; 149682527734SSukumar Swaminathan #endif 149782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 149882527734SSukumar Swaminathan uint16_t FCFI; 149982527734SSukumar Swaminathan uint16_t Rsvd2; 150082527734SSukumar Swaminathan #endif 150182527734SSukumar Swaminathan } UNREG_FCFI_VAR; 150282527734SSukumar Swaminathan 150382527734SSukumar Swaminathan /* Structure for MB Command RESUME_RPI (0x9E) */ 150482527734SSukumar Swaminathan /* Good for SLI4 only */ 150582527734SSukumar Swaminathan 150682527734SSukumar Swaminathan typedef struct 150782527734SSukumar Swaminathan { 150882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 150982527734SSukumar Swaminathan uint16_t Rsvd1; 151082527734SSukumar Swaminathan uint16_t RPI; 151182527734SSukumar Swaminathan 151282527734SSukumar Swaminathan uint32_t EventTag; 151382527734SSukumar Swaminathan uint32_t rsvd2[3]; 151482527734SSukumar Swaminathan 151582527734SSukumar Swaminathan uint16_t VFI; 151682527734SSukumar Swaminathan uint16_t VPI; 151782527734SSukumar Swaminathan #endif 151882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 151982527734SSukumar Swaminathan uint16_t RPI; 152082527734SSukumar Swaminathan uint16_t Rsvd1; 152182527734SSukumar Swaminathan 152282527734SSukumar Swaminathan uint32_t EventTag; 152382527734SSukumar Swaminathan uint32_t rsvd2[3]; 152482527734SSukumar Swaminathan 152582527734SSukumar Swaminathan uint16_t VPI; 152682527734SSukumar Swaminathan uint16_t VFI; 152782527734SSukumar Swaminathan #endif 152882527734SSukumar Swaminathan 152982527734SSukumar Swaminathan } RESUME_RPI_VAR; 153082527734SSukumar Swaminathan 153182527734SSukumar Swaminathan 153282527734SSukumar Swaminathan /* Structure for MB Command UNREG_D_ID (0x23) */ 153382527734SSukumar Swaminathan 153482527734SSukumar Swaminathan typedef struct 153582527734SSukumar Swaminathan { 153682527734SSukumar Swaminathan uint32_t did; 153782527734SSukumar Swaminathan 153882527734SSukumar Swaminathan uint32_t rsvd2; 153982527734SSukumar Swaminathan uint32_t rsvd3; 154082527734SSukumar Swaminathan uint32_t rsvd4; 154182527734SSukumar Swaminathan uint32_t rsvd5; 154282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 154382527734SSukumar Swaminathan uint16_t rsvd6; 154482527734SSukumar Swaminathan uint16_t vpi; 154582527734SSukumar Swaminathan #endif 154682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 154782527734SSukumar Swaminathan uint16_t vpi; 154882527734SSukumar Swaminathan uint16_t rsvd6; 154982527734SSukumar Swaminathan #endif 155082527734SSukumar Swaminathan } UNREG_D_ID_VAR; 155182527734SSukumar Swaminathan 155282527734SSukumar Swaminathan 155382527734SSukumar Swaminathan /* Structure for MB Command READ_LA (21) */ 155482527734SSukumar Swaminathan /* Structure for MB Command READ_LA64 (0x95) */ 155582527734SSukumar Swaminathan 155682527734SSukumar Swaminathan typedef struct 155782527734SSukumar Swaminathan { 155882527734SSukumar Swaminathan uint32_t eventTag; /* Event tag */ 155982527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 156082527734SSukumar Swaminathan uint32_t rsvd2:19; 156182527734SSukumar Swaminathan uint32_t fa:1; 156282527734SSukumar Swaminathan uint32_t mm:1; 156382527734SSukumar Swaminathan uint32_t tc:1; 156482527734SSukumar Swaminathan uint32_t pb:1; 156582527734SSukumar Swaminathan uint32_t il:1; 156682527734SSukumar Swaminathan uint32_t attType:8; 156782527734SSukumar Swaminathan #endif 156882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 156982527734SSukumar Swaminathan uint32_t attType:8; 157082527734SSukumar Swaminathan uint32_t il:1; 157182527734SSukumar Swaminathan uint32_t pb:1; 157282527734SSukumar Swaminathan uint32_t tc:1; 157382527734SSukumar Swaminathan uint32_t mm:1; 157482527734SSukumar Swaminathan uint32_t fa:1; 157582527734SSukumar Swaminathan uint32_t rsvd2:19; 157682527734SSukumar Swaminathan #endif 157782527734SSukumar Swaminathan #define AT_RESERVED 0x00 /* Reserved - attType */ 157882527734SSukumar Swaminathan #define AT_LINK_UP 0x01 /* Link is up */ 157982527734SSukumar Swaminathan #define AT_LINK_DOWN 0x02 /* Link is down */ 15808f23e9faSHans Rosenfeld #define AT_NO_HARD_ALPA 0x03 /* SLI4 */ 15818f23e9faSHans Rosenfeld 158282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 158382527734SSukumar Swaminathan uint8_t granted_AL_PA; 158482527734SSukumar Swaminathan uint8_t lipAlPs; 158582527734SSukumar Swaminathan uint8_t lipType; 158682527734SSukumar Swaminathan uint8_t topology; 158782527734SSukumar Swaminathan #endif 158882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 158982527734SSukumar Swaminathan uint8_t topology; 159082527734SSukumar Swaminathan uint8_t lipType; 159182527734SSukumar Swaminathan uint8_t lipAlPs; 159282527734SSukumar Swaminathan uint8_t granted_AL_PA; 159382527734SSukumar Swaminathan #endif 159482527734SSukumar Swaminathan 159582527734SSukumar Swaminathan /* lipType */ 159682527734SSukumar Swaminathan #define LT_PORT_INIT 0x00 /* An L_PORT initing (F7, AL_PS) - lipType */ 159782527734SSukumar Swaminathan #define LT_PORT_ERR 0x01 /* Err @L_PORT rcv'er (F8, AL_PS) */ 159882527734SSukumar Swaminathan #define LT_RESET_APORT 0x02 /* Lip Reset of some other port */ 159982527734SSukumar Swaminathan #define LT_RESET_MYPORT 0x03 /* Lip Reset of my port */ 160082527734SSukumar Swaminathan 160182527734SSukumar Swaminathan /* topology */ 160282527734SSukumar Swaminathan #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 160382527734SSukumar Swaminathan #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL (private) */ 160482527734SSukumar Swaminathan 160582527734SSukumar Swaminathan union 160682527734SSukumar Swaminathan { 160782527734SSukumar Swaminathan ULP_BDE lilpBde; /* This BDE points to a */ 160882527734SSukumar Swaminathan /* 128 byte buffer to store */ 160982527734SSukumar Swaminathan /* the LILP AL_PA position */ 161082527734SSukumar Swaminathan /* map into */ 161182527734SSukumar Swaminathan ULP_BDE64 lilpBde64; 161282527734SSukumar Swaminathan } un; 161382527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 161482527734SSukumar Swaminathan uint32_t Dlu:1; 161582527734SSukumar Swaminathan uint32_t Dtf:1; 161682527734SSukumar Swaminathan uint32_t Drsvd2:14; 161782527734SSukumar Swaminathan uint32_t DlnkSpeed:8; 161882527734SSukumar Swaminathan uint32_t DnlPort:4; 161982527734SSukumar Swaminathan uint32_t Dtx:2; 162082527734SSukumar Swaminathan uint32_t Drx:2; 162182527734SSukumar Swaminathan #endif 162282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 162382527734SSukumar Swaminathan uint32_t Drx:2; 162482527734SSukumar Swaminathan uint32_t Dtx:2; 162582527734SSukumar Swaminathan uint32_t DnlPort:4; 162682527734SSukumar Swaminathan uint32_t DlnkSpeed:8; 162782527734SSukumar Swaminathan uint32_t Drsvd2:14; 162882527734SSukumar Swaminathan uint32_t Dtf:1; 162982527734SSukumar Swaminathan uint32_t Dlu:1; 163082527734SSukumar Swaminathan #endif 163182527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 163282527734SSukumar Swaminathan uint32_t Ulu:1; 163382527734SSukumar Swaminathan uint32_t Utf:1; 163482527734SSukumar Swaminathan uint32_t Ursvd2:14; 163582527734SSukumar Swaminathan uint32_t UlnkSpeed:8; 163682527734SSukumar Swaminathan uint32_t UnlPort:4; 163782527734SSukumar Swaminathan uint32_t Utx:2; 163882527734SSukumar Swaminathan uint32_t Urx:2; 163982527734SSukumar Swaminathan #endif 164082527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 164182527734SSukumar Swaminathan uint32_t Urx:2; 164282527734SSukumar Swaminathan uint32_t Utx:2; 164382527734SSukumar Swaminathan uint32_t UnlPort:4; 164482527734SSukumar Swaminathan uint32_t UlnkSpeed:8; 164582527734SSukumar Swaminathan uint32_t Ursvd2:14; 164682527734SSukumar Swaminathan uint32_t Utf:1; 164782527734SSukumar Swaminathan uint32_t Ulu:1; 164882527734SSukumar Swaminathan #endif 164982527734SSukumar Swaminathan #define LA_1GHZ_LINK 0x04 /* lnkSpeed */ 165082527734SSukumar Swaminathan #define LA_2GHZ_LINK 0x08 /* lnkSpeed */ 165182527734SSukumar Swaminathan #define LA_4GHZ_LINK 0x10 /* lnkSpeed */ 165282527734SSukumar Swaminathan #define LA_8GHZ_LINK 0x20 /* lnkSpeed */ 165382527734SSukumar Swaminathan #define LA_10GHZ_LINK 0x40 /* lnkSpeed */ 16548f23e9faSHans Rosenfeld #define LA_16GHZ_LINK 0x80 /* lnkSpeed */ 1655a3170057SPaul Winder #define LA_32GHZ_LINK 0x90 /* lnkSpeed */ 165682527734SSukumar Swaminathan } READ_LA_VAR; 165782527734SSukumar Swaminathan 165882527734SSukumar Swaminathan 165982527734SSukumar Swaminathan /* Structure for MB Command CLEAR_LA (22) */ 166082527734SSukumar Swaminathan 166182527734SSukumar Swaminathan typedef struct 166282527734SSukumar Swaminathan { 166382527734SSukumar Swaminathan uint32_t eventTag; /* Event tag */ 166482527734SSukumar Swaminathan uint32_t rsvd1; 166582527734SSukumar Swaminathan } CLEAR_LA_VAR; 166682527734SSukumar Swaminathan 166782527734SSukumar Swaminathan /* Structure for MB Command DUMP */ 166882527734SSukumar Swaminathan /* Good for SLI2/3 only */ 166982527734SSukumar Swaminathan 167082527734SSukumar Swaminathan typedef struct 167182527734SSukumar Swaminathan { 167282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 167382527734SSukumar Swaminathan uint32_t rsvd:25; 167482527734SSukumar Swaminathan uint32_t ra:1; 167582527734SSukumar Swaminathan uint32_t co:1; 167682527734SSukumar Swaminathan uint32_t cv:1; 167782527734SSukumar Swaminathan uint32_t type:4; 167882527734SSukumar Swaminathan 167982527734SSukumar Swaminathan uint32_t entry_index:16; 168082527734SSukumar Swaminathan uint32_t region_id:16; 168182527734SSukumar Swaminathan #endif 168282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 168382527734SSukumar Swaminathan uint32_t type:4; 168482527734SSukumar Swaminathan uint32_t cv:1; 168582527734SSukumar Swaminathan uint32_t co:1; 168682527734SSukumar Swaminathan uint32_t ra:1; 168782527734SSukumar Swaminathan uint32_t rsvd:25; 168882527734SSukumar Swaminathan 168982527734SSukumar Swaminathan uint32_t region_id:16; 169082527734SSukumar Swaminathan uint32_t entry_index:16; 169182527734SSukumar Swaminathan #endif 169282527734SSukumar Swaminathan uint32_t base_adr; 169382527734SSukumar Swaminathan uint32_t word_cnt; 169482527734SSukumar Swaminathan uint32_t resp_offset; 169582527734SSukumar Swaminathan } DUMP_VAR; 169682527734SSukumar Swaminathan 169782527734SSukumar Swaminathan /* Structure for MB Command DUMP */ 169882527734SSukumar Swaminathan /* Good for SLI4 only */ 169982527734SSukumar Swaminathan 170082527734SSukumar Swaminathan typedef struct 170182527734SSukumar Swaminathan { 170282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 170382527734SSukumar Swaminathan uint32_t ppi:4; 170482527734SSukumar Swaminathan uint32_t phy_index:4; 170582527734SSukumar Swaminathan uint32_t rsvd:20; 170682527734SSukumar Swaminathan uint32_t type:4; 170782527734SSukumar Swaminathan 170882527734SSukumar Swaminathan uint32_t entry_index:16; 170982527734SSukumar Swaminathan uint32_t region_id:16; 171082527734SSukumar Swaminathan #endif 171182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 171282527734SSukumar Swaminathan uint32_t type:4; 171382527734SSukumar Swaminathan uint32_t rsvd:20; 171482527734SSukumar Swaminathan uint32_t phy_index:4; 171582527734SSukumar Swaminathan uint32_t ppi:4; 171682527734SSukumar Swaminathan 171782527734SSukumar Swaminathan uint32_t region_id:16; 171882527734SSukumar Swaminathan uint32_t entry_index:16; 171982527734SSukumar Swaminathan #endif 172082527734SSukumar Swaminathan uint32_t available_cnt; 172182527734SSukumar Swaminathan uint32_t addrLow; 172282527734SSukumar Swaminathan uint32_t addrHigh; 172382527734SSukumar Swaminathan uint32_t rsp_cnt; 172482527734SSukumar Swaminathan } DUMP4_VAR; 172582527734SSukumar Swaminathan 172682527734SSukumar Swaminathan /* 172782527734SSukumar Swaminathan * Dump type 172882527734SSukumar Swaminathan */ 172982527734SSukumar Swaminathan #define DMP_MEM_REG 0x1 173082527734SSukumar Swaminathan #define DMP_NV_PARAMS 0x2 173182527734SSukumar Swaminathan 173282527734SSukumar Swaminathan /* 173382527734SSukumar Swaminathan * Dump region ID 173482527734SSukumar Swaminathan */ 173582527734SSukumar Swaminathan #define NODE_CFG_A_REGION_ID 0 173682527734SSukumar Swaminathan #define NODE_CFG_B_REGION_ID 1 173782527734SSukumar Swaminathan #define NODE_CFG_C_REGION_ID 2 173882527734SSukumar Swaminathan #define NODE_CFG_D_REGION_ID 3 173982527734SSukumar Swaminathan #define WAKE_UP_PARMS_REGION_ID 4 174082527734SSukumar Swaminathan #define DEF_PCI_CFG_REGION_ID 5 174182527734SSukumar Swaminathan #define PCI_CFG_1_REGION_ID 6 174282527734SSukumar Swaminathan #define PCI_CFG_2_REGION_ID 7 174382527734SSukumar Swaminathan #define RSVD1_REGION_ID 8 174482527734SSukumar Swaminathan #define RSVD2_REGION_ID 9 174582527734SSukumar Swaminathan #define RSVD3_REGION_ID 10 174682527734SSukumar Swaminathan #define RSVD4_REGION_ID 11 174782527734SSukumar Swaminathan #define RSVD5_REGION_ID 12 174882527734SSukumar Swaminathan #define RSVD6_REGION_ID 13 174982527734SSukumar Swaminathan #define RSVD7_REGION_ID 14 175082527734SSukumar Swaminathan #define DIAG_TRACE_REGION_ID 15 175182527734SSukumar Swaminathan #define WWN_REGION_ID 16 175282527734SSukumar Swaminathan 175382527734SSukumar Swaminathan #define DMP_VPD_REGION 14 175482527734SSukumar Swaminathan #define DMP_VPD_SIZE 1024 175582527734SSukumar Swaminathan #define DMP_VPD_DUMP_WCOUNT 24 175682527734SSukumar Swaminathan 175782527734SSukumar Swaminathan #define DMP_FCOE_REGION 23 175882527734SSukumar Swaminathan #define DMP_FCOE_DUMP_WCOUNT 256 175982527734SSukumar Swaminathan 176082527734SSukumar Swaminathan 176182527734SSukumar Swaminathan /* Structure for MB Command UPDATE_CFG */ 176282527734SSukumar Swaminathan /* Good for SLI2/3 and SLI4 */ 176382527734SSukumar Swaminathan 176482527734SSukumar Swaminathan typedef struct 176582527734SSukumar Swaminathan { 176682527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 176782527734SSukumar Swaminathan uint32_t rsvd2:16; 176882527734SSukumar Swaminathan uint32_t proc_type:8; 176982527734SSukumar Swaminathan uint32_t rsvd1:1; 177082527734SSukumar Swaminathan uint32_t Abit:1; 177182527734SSukumar Swaminathan uint32_t Obit:1; 177282527734SSukumar Swaminathan uint32_t Vbit:1; 177382527734SSukumar Swaminathan uint32_t req_type:4; 177482527734SSukumar Swaminathan #define INIT_REGION 1 177582527734SSukumar Swaminathan #define UPDATE_DATA 2 177682527734SSukumar Swaminathan #define CLEAN_UP_CFG 3 177782527734SSukumar Swaminathan uint32_t entry_len:16; 177882527734SSukumar Swaminathan uint32_t region_id:16; 177982527734SSukumar Swaminathan #endif 178082527734SSukumar Swaminathan 178182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 178282527734SSukumar Swaminathan uint32_t req_type:4; 178382527734SSukumar Swaminathan #define INIT_REGION 1 178482527734SSukumar Swaminathan #define UPDATE_DATA 2 178582527734SSukumar Swaminathan #define CLEAN_UP_CFG 3 178682527734SSukumar Swaminathan uint32_t Vbit:1; 178782527734SSukumar Swaminathan uint32_t Obit:1; 178882527734SSukumar Swaminathan uint32_t Abit:1; 178982527734SSukumar Swaminathan uint32_t rsvd1:1; 179082527734SSukumar Swaminathan uint32_t proc_type:8; 179182527734SSukumar Swaminathan uint32_t rsvd2:16; 179282527734SSukumar Swaminathan 179382527734SSukumar Swaminathan uint32_t region_id:16; 179482527734SSukumar Swaminathan uint32_t entry_len:16; 179582527734SSukumar Swaminathan #endif 179682527734SSukumar Swaminathan 179782527734SSukumar Swaminathan uint32_t rsp_info; 179882527734SSukumar Swaminathan uint32_t byte_len; 179982527734SSukumar Swaminathan uint32_t cfg_data; 180082527734SSukumar Swaminathan } UPDATE_CFG_VAR; 180182527734SSukumar Swaminathan 180282527734SSukumar Swaminathan /* Structure for MB Command DEL_LD_ENTRY (29) */ 180382527734SSukumar Swaminathan 180482527734SSukumar Swaminathan typedef struct 180582527734SSukumar Swaminathan { 180682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 180782527734SSukumar Swaminathan uint32_t list_req:2; 180882527734SSukumar Swaminathan uint32_t list_rsp:2; 180982527734SSukumar Swaminathan uint32_t rsvd:28; 181082527734SSukumar Swaminathan #else 181182527734SSukumar Swaminathan uint32_t rsvd:28; 181282527734SSukumar Swaminathan uint32_t list_rsp:2; 181382527734SSukumar Swaminathan uint32_t list_req:2; 181482527734SSukumar Swaminathan #endif 181582527734SSukumar Swaminathan 181682527734SSukumar Swaminathan #define FLASH_LOAD_LIST 1 181782527734SSukumar Swaminathan #define RAM_LOAD_LIST 2 181882527734SSukumar Swaminathan #define BOTH_LISTS 3 181982527734SSukumar Swaminathan 182082527734SSukumar Swaminathan PROG_ID prog_id; 182182527734SSukumar Swaminathan } DEL_LD_ENTRY_VAR; 182282527734SSukumar Swaminathan 182382527734SSukumar Swaminathan /* Structure for MB Command LOAD_AREA (81) */ 182482527734SSukumar Swaminathan typedef struct 182582527734SSukumar Swaminathan { 182682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 182782527734SSukumar Swaminathan uint32_t load_cmplt:1; 182882527734SSukumar Swaminathan uint32_t method:1; 182982527734SSukumar Swaminathan uint32_t rsvd1:1; 183082527734SSukumar Swaminathan uint32_t update_flash:1; 183182527734SSukumar Swaminathan uint32_t erase_or_prog:1; 183282527734SSukumar Swaminathan uint32_t version:1; 183382527734SSukumar Swaminathan uint32_t rsvd2:2; 183482527734SSukumar Swaminathan uint32_t progress:8; 183582527734SSukumar Swaminathan uint32_t step:8; 183682527734SSukumar Swaminathan uint32_t area_id:8; 183782527734SSukumar Swaminathan #else 183882527734SSukumar Swaminathan uint32_t area_id:8; 183982527734SSukumar Swaminathan uint32_t step:8; 184082527734SSukumar Swaminathan uint32_t progress:8; 184182527734SSukumar Swaminathan uint32_t rsvd2:2; 184282527734SSukumar Swaminathan uint32_t version:1; 184382527734SSukumar Swaminathan uint32_t erase_or_prog:1; 184482527734SSukumar Swaminathan uint32_t update_flash:1; 184582527734SSukumar Swaminathan uint32_t rsvd1:1; 184682527734SSukumar Swaminathan uint32_t method:1; 184782527734SSukumar Swaminathan uint32_t load_cmplt:1; 184882527734SSukumar Swaminathan #endif 184982527734SSukumar Swaminathan uint32_t dl_to_adr; 185082527734SSukumar Swaminathan uint32_t dl_len; 185182527734SSukumar Swaminathan union 185282527734SSukumar Swaminathan { 185382527734SSukumar Swaminathan uint32_t dl_from_slim_offset; 185482527734SSukumar Swaminathan ULP_BDE dl_from_bde; 185582527734SSukumar Swaminathan ULP_BDE64 dl_from_bde64; 185682527734SSukumar Swaminathan PROG_ID prog_id; 185782527734SSukumar Swaminathan } un; 185882527734SSukumar Swaminathan } LOAD_AREA_VAR; 185982527734SSukumar Swaminathan 186082527734SSukumar Swaminathan /* Structure for MB Command LOAD_EXP_ROM (9C) */ 186182527734SSukumar Swaminathan typedef struct 186282527734SSukumar Swaminathan { 186382527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 186482527734SSukumar Swaminathan uint32_t rsvd1:8; 186582527734SSukumar Swaminathan uint32_t progress:8; 186682527734SSukumar Swaminathan uint32_t step:8; 186782527734SSukumar Swaminathan uint32_t rsvd2:8; 186882527734SSukumar Swaminathan #else 186982527734SSukumar Swaminathan uint32_t rsvd2:8; 187082527734SSukumar Swaminathan uint32_t step:8; 187182527734SSukumar Swaminathan uint32_t progress:8; 187282527734SSukumar Swaminathan uint32_t rsvd1:8; 187382527734SSukumar Swaminathan #endif 187482527734SSukumar Swaminathan uint32_t dl_to_adr; 187582527734SSukumar Swaminathan uint32_t rsvd3; 187682527734SSukumar Swaminathan union 187782527734SSukumar Swaminathan { 187882527734SSukumar Swaminathan uint32_t word[2]; 187982527734SSukumar Swaminathan PROG_ID prog_id; 188082527734SSukumar Swaminathan } un; 188182527734SSukumar Swaminathan } LOAD_EXP_ROM_VAR; 188282527734SSukumar Swaminathan 188382527734SSukumar Swaminathan 188482527734SSukumar Swaminathan /* Structure for MB Command CONFIG_HBQ (7C) */ 188582527734SSukumar Swaminathan 188682527734SSukumar Swaminathan typedef struct 188782527734SSukumar Swaminathan { 188882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 188982527734SSukumar Swaminathan uint32_t rsvd1:7; 189082527734SSukumar Swaminathan uint32_t recvNotify:1; /* Receive Notification */ 189182527734SSukumar Swaminathan uint32_t numMask:8; /* # Mask Entries */ 189282527734SSukumar Swaminathan uint32_t profile:8; /* Selection Profile */ 189382527734SSukumar Swaminathan uint32_t rsvd2:8; 189482527734SSukumar Swaminathan #endif 189582527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 189682527734SSukumar Swaminathan uint32_t rsvd2:8; 189782527734SSukumar Swaminathan uint32_t profile:8; /* Selection Profile */ 189882527734SSukumar Swaminathan uint32_t numMask:8; /* # Mask Entries */ 189982527734SSukumar Swaminathan uint32_t recvNotify:1; /* Receive Notification */ 190082527734SSukumar Swaminathan uint32_t rsvd1:7; 190182527734SSukumar Swaminathan #endif 190282527734SSukumar Swaminathan 190382527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 190482527734SSukumar Swaminathan uint32_t hbqId:16; 190582527734SSukumar Swaminathan uint32_t rsvd3:12; 190682527734SSukumar Swaminathan uint32_t ringMask:4; 190782527734SSukumar Swaminathan #endif 190882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 190982527734SSukumar Swaminathan uint32_t ringMask:4; 191082527734SSukumar Swaminathan uint32_t rsvd3:12; 191182527734SSukumar Swaminathan uint32_t hbqId:16; 191282527734SSukumar Swaminathan #endif 191382527734SSukumar Swaminathan 191482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 191582527734SSukumar Swaminathan uint32_t numEntries:16; 191682527734SSukumar Swaminathan uint32_t rsvd4:8; 191782527734SSukumar Swaminathan uint32_t headerLen:8; 191882527734SSukumar Swaminathan #endif 191982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 192082527734SSukumar Swaminathan uint32_t headerLen:8; 192182527734SSukumar Swaminathan uint32_t rsvd4:8; 192282527734SSukumar Swaminathan uint32_t numEntries:16; 192382527734SSukumar Swaminathan #endif 192482527734SSukumar Swaminathan 192582527734SSukumar Swaminathan uint32_t hbqaddrLow; 192682527734SSukumar Swaminathan uint32_t hbqaddrHigh; 192782527734SSukumar Swaminathan 192882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 192982527734SSukumar Swaminathan uint32_t rsvd5:31; 193082527734SSukumar Swaminathan uint32_t logEntry:1; 193182527734SSukumar Swaminathan #endif 193282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 193382527734SSukumar Swaminathan uint32_t logEntry:1; 193482527734SSukumar Swaminathan uint32_t rsvd5:31; 193582527734SSukumar Swaminathan #endif 193682527734SSukumar Swaminathan 193782527734SSukumar Swaminathan uint32_t rsvd6; /* w7 */ 193882527734SSukumar Swaminathan uint32_t rsvd7; /* w8 */ 193982527734SSukumar Swaminathan uint32_t rsvd8; /* w9 */ 194082527734SSukumar Swaminathan 194182527734SSukumar Swaminathan HBQ_MASK hbqMasks[6]; 194282527734SSukumar Swaminathan 194382527734SSukumar Swaminathan union 194482527734SSukumar Swaminathan { 194582527734SSukumar Swaminathan uint32_t allprofiles[12]; 194682527734SSukumar Swaminathan 194782527734SSukumar Swaminathan struct 194882527734SSukumar Swaminathan { 194982527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 195082527734SSukumar Swaminathan uint32_t seqlenoff:16; 195182527734SSukumar Swaminathan uint32_t maxlen:16; 195282527734SSukumar Swaminathan #endif 195382527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 195482527734SSukumar Swaminathan uint32_t maxlen:16; 195582527734SSukumar Swaminathan uint32_t seqlenoff:16; 195682527734SSukumar Swaminathan #endif 195782527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 195882527734SSukumar Swaminathan uint32_t rsvd1:28; 195982527734SSukumar Swaminathan uint32_t seqlenbcnt:4; 196082527734SSukumar Swaminathan #endif 196182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 196282527734SSukumar Swaminathan uint32_t seqlenbcnt:4; 196382527734SSukumar Swaminathan uint32_t rsvd1:28; 196482527734SSukumar Swaminathan #endif 196582527734SSukumar Swaminathan uint32_t rsvd[10]; 196682527734SSukumar Swaminathan } profile2; 196782527734SSukumar Swaminathan 196882527734SSukumar Swaminathan struct 196982527734SSukumar Swaminathan { 197082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 197182527734SSukumar Swaminathan uint32_t seqlenoff:16; 197282527734SSukumar Swaminathan uint32_t maxlen:16; 197382527734SSukumar Swaminathan #endif 197482527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 197582527734SSukumar Swaminathan uint32_t maxlen:16; 197682527734SSukumar Swaminathan uint32_t seqlenoff:16; 197782527734SSukumar Swaminathan #endif 197882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 197982527734SSukumar Swaminathan uint32_t cmdcodeoff:28; 198082527734SSukumar Swaminathan uint32_t rsvd1:12; 198182527734SSukumar Swaminathan uint32_t seqlenbcnt:4; 198282527734SSukumar Swaminathan #endif 198382527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 198482527734SSukumar Swaminathan uint32_t seqlenbcnt:4; 198582527734SSukumar Swaminathan uint32_t rsvd1:12; 198682527734SSukumar Swaminathan uint32_t cmdcodeoff:28; 198782527734SSukumar Swaminathan #endif 198882527734SSukumar Swaminathan uint32_t cmdmatch[8]; 198982527734SSukumar Swaminathan 199082527734SSukumar Swaminathan uint32_t rsvd[2]; 199182527734SSukumar Swaminathan } profile3; 199282527734SSukumar Swaminathan 199382527734SSukumar Swaminathan struct 199482527734SSukumar Swaminathan { 199582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 199682527734SSukumar Swaminathan uint32_t seqlenoff:16; 199782527734SSukumar Swaminathan uint32_t maxlen:16; 199882527734SSukumar Swaminathan #endif 199982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 200082527734SSukumar Swaminathan uint32_t maxlen:16; 200182527734SSukumar Swaminathan uint32_t seqlenoff:16; 200282527734SSukumar Swaminathan #endif 200382527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 200482527734SSukumar Swaminathan uint32_t cmdcodeoff:28; 200582527734SSukumar Swaminathan uint32_t rsvd1:12; 200682527734SSukumar Swaminathan uint32_t seqlenbcnt:4; 200782527734SSukumar Swaminathan #endif 200882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 200982527734SSukumar Swaminathan uint32_t seqlenbcnt:4; 201082527734SSukumar Swaminathan uint32_t rsvd1:12; 201182527734SSukumar Swaminathan uint32_t cmdcodeoff:28; 201282527734SSukumar Swaminathan #endif 201382527734SSukumar Swaminathan uint32_t cmdmatch[8]; 201482527734SSukumar Swaminathan 201582527734SSukumar Swaminathan uint32_t rsvd[2]; 201682527734SSukumar Swaminathan } profile5; 201782527734SSukumar Swaminathan } profiles; 201882527734SSukumar Swaminathan } CONFIG_HBQ_VAR; 201982527734SSukumar Swaminathan 202082527734SSukumar Swaminathan 202182527734SSukumar Swaminathan /* Structure for MB Command REG_VPI(0x96) */ 202282527734SSukumar Swaminathan /* Good for SLI2/3 and SLI4 */ 202382527734SSukumar Swaminathan 202482527734SSukumar Swaminathan typedef struct 202582527734SSukumar Swaminathan { 202682527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 202782527734SSukumar Swaminathan uint32_t rsvd1; 2028a9800bebSGarrett D'Amore uint32_t rsvd2:7; 2029a9800bebSGarrett D'Amore uint32_t upd:1; 203082527734SSukumar Swaminathan uint32_t sid:24; 2031b3660a96SSukumar Swaminathan uint32_t portname[2]; /* N_PORT name */ 203282527734SSukumar Swaminathan uint32_t rsvd5; 203382527734SSukumar Swaminathan uint16_t vfi; 203482527734SSukumar Swaminathan uint16_t vpi; 203582527734SSukumar Swaminathan #endif 203682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 203782527734SSukumar Swaminathan uint32_t rsvd1; 203882527734SSukumar Swaminathan uint32_t sid:24; 2039a9800bebSGarrett D'Amore uint32_t upd:1; 2040a9800bebSGarrett D'Amore uint32_t rsvd2:7; 2041b3660a96SSukumar Swaminathan uint32_t portname[2]; /* N_PORT name */ 204282527734SSukumar Swaminathan uint32_t rsvd5; 204382527734SSukumar Swaminathan uint16_t vpi; 204482527734SSukumar Swaminathan uint16_t vfi; 204582527734SSukumar Swaminathan #endif 204682527734SSukumar Swaminathan } REG_VPI_VAR; 204782527734SSukumar Swaminathan 204882527734SSukumar Swaminathan /* Structure for MB Command INIT_VPI(0xA3) */ 204982527734SSukumar Swaminathan /* Good for SLI4 only */ 205082527734SSukumar Swaminathan 205182527734SSukumar Swaminathan typedef struct 205282527734SSukumar Swaminathan { 205382527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 205482527734SSukumar Swaminathan uint16_t vfi; 205582527734SSukumar Swaminathan uint16_t vpi; 205682527734SSukumar Swaminathan #endif 205782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 205882527734SSukumar Swaminathan uint16_t vpi; 205982527734SSukumar Swaminathan uint16_t vfi; 206082527734SSukumar Swaminathan #endif 206182527734SSukumar Swaminathan } INIT_VPI_VAR; 206282527734SSukumar Swaminathan 206382527734SSukumar Swaminathan /* Structure for MB Command UNREG_VPI (0x97) */ 2064e2ca2865SSukumar Swaminathan /* Good for SLI2/3 */ 206582527734SSukumar Swaminathan 206682527734SSukumar Swaminathan typedef struct 206782527734SSukumar Swaminathan { 206882527734SSukumar Swaminathan uint32_t rsvd1; 2069e2ca2865SSukumar Swaminathan uint32_t rsvd2; 2070e2ca2865SSukumar Swaminathan uint32_t rsvd3; 2071e2ca2865SSukumar Swaminathan uint32_t rsvd4; 2072e2ca2865SSukumar Swaminathan uint32_t rsvd5; 207382527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 2074e2ca2865SSukumar Swaminathan uint16_t rsvd6; 207582527734SSukumar Swaminathan uint16_t vpi; 207682527734SSukumar Swaminathan #endif 207782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 207882527734SSukumar Swaminathan uint16_t vpi; 2079e2ca2865SSukumar Swaminathan uint16_t rsvd6; 208082527734SSukumar Swaminathan #endif 208182527734SSukumar Swaminathan } UNREG_VPI_VAR; 208282527734SSukumar Swaminathan 2083e2ca2865SSukumar Swaminathan /* Structure for MB Command UNREG_VPI (0x97) */ 2084e2ca2865SSukumar Swaminathan /* Good for SLI4 */ 2085e2ca2865SSukumar Swaminathan 2086e2ca2865SSukumar Swaminathan typedef struct 2087e2ca2865SSukumar Swaminathan { 2088e2ca2865SSukumar Swaminathan uint32_t rsvd1; 2089e2ca2865SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 2090e2ca2865SSukumar Swaminathan uint8_t ii:2; 2091e2ca2865SSukumar Swaminathan uint16_t rsvd2:14; 2092e2ca2865SSukumar Swaminathan uint16_t index; 2093e2ca2865SSukumar Swaminathan #endif 2094e2ca2865SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 2095e2ca2865SSukumar Swaminathan uint16_t index; 2096e2ca2865SSukumar Swaminathan uint16_t rsvd2:14; 2097e2ca2865SSukumar Swaminathan uint8_t ii:2; 2098e2ca2865SSukumar Swaminathan #endif 2099e2ca2865SSukumar Swaminathan } UNREG_VPI_VAR4; 2100e2ca2865SSukumar Swaminathan 210182527734SSukumar Swaminathan /* Structure for MB Command REG_VFI(0x9F) */ 210282527734SSukumar Swaminathan /* Good for SLI4 only */ 210382527734SSukumar Swaminathan 210482527734SSukumar Swaminathan typedef struct 210582527734SSukumar Swaminathan { 210682527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 2107*e2d1a434SCarsten Grzemba uint16_t rsvd1:2; /* Word 1 */ 21088f23e9faSHans Rosenfeld uint16_t upd:1; 21098f23e9faSHans Rosenfeld uint16_t vp:1; 21108f23e9faSHans Rosenfeld uint16_t rsvd2:12; 211182527734SSukumar Swaminathan uint16_t vfi; 2112*e2d1a434SCarsten Grzemba uint16_t vpi; /* Word 2 */ 211382527734SSukumar Swaminathan uint16_t fcfi; 211482527734SSukumar Swaminathan 2115b3660a96SSukumar Swaminathan uint32_t portname[2]; /* N_PORT name */ 211682527734SSukumar Swaminathan 211782527734SSukumar Swaminathan ULP_BDE64 bde; 211882527734SSukumar Swaminathan 211982527734SSukumar Swaminathan /* CHANGE with next firmware drop */ 212082527734SSukumar Swaminathan uint32_t edtov; 212182527734SSukumar Swaminathan uint32_t ratov; 212282527734SSukumar Swaminathan 2123*e2d1a434SCarsten Grzemba uint32_t vfi_bbscn:4; 2124*e2d1a434SCarsten Grzemba uint32_t vfi_bbcr:1; 2125*e2d1a434SCarsten Grzemba uint32_t rsvd5:3; /* Word 10 */ 212682527734SSukumar Swaminathan uint32_t sid:24; 212782527734SSukumar Swaminathan #endif 212882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 212982527734SSukumar Swaminathan uint16_t vfi; 21308f23e9faSHans Rosenfeld uint16_t rsvd2:12; 21318f23e9faSHans Rosenfeld uint16_t vp:1; 21328f23e9faSHans Rosenfeld uint16_t upd:1; 21338f23e9faSHans Rosenfeld uint16_t rsvd1:2; 213482527734SSukumar Swaminathan uint16_t fcfi; 213582527734SSukumar Swaminathan uint16_t vpi; 213682527734SSukumar Swaminathan 2137b3660a96SSukumar Swaminathan uint32_t portname[2]; /* N_PORT name */ 213882527734SSukumar Swaminathan 213982527734SSukumar Swaminathan ULP_BDE64 bde; 214082527734SSukumar Swaminathan 214182527734SSukumar Swaminathan /* CHANGE with next firmware drop */ 214282527734SSukumar Swaminathan uint32_t edtov; 214382527734SSukumar Swaminathan uint32_t ratov; 214482527734SSukumar Swaminathan 2145*e2d1a434SCarsten Grzemba uint32_t sid:24; /* nport_id */ 2146*e2d1a434SCarsten Grzemba uint32_t rsvd5:3; 2147*e2d1a434SCarsten Grzemba uint32_t vfi_bbcr:1; 2148*e2d1a434SCarsten Grzemba uint32_t vfi_bbscn:4; 214982527734SSukumar Swaminathan #endif 215082527734SSukumar Swaminathan } REG_VFI_VAR; 215182527734SSukumar Swaminathan 215282527734SSukumar Swaminathan /* Structure for MB Command INIT_VFI(0xA4) */ 215382527734SSukumar Swaminathan /* Good for SLI4 only */ 215482527734SSukumar Swaminathan 215582527734SSukumar Swaminathan typedef struct 215682527734SSukumar Swaminathan { 215782527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 215882527734SSukumar Swaminathan uint32_t vr:1; 215982527734SSukumar Swaminathan uint32_t vt:1; 216082527734SSukumar Swaminathan uint32_t vf:1; 216182527734SSukumar Swaminathan uint32_t rsvd1:13; 216282527734SSukumar Swaminathan uint32_t vfi:16; 216382527734SSukumar Swaminathan 216482527734SSukumar Swaminathan uint16_t rsvd2; 216582527734SSukumar Swaminathan uint16_t fcfi; 216682527734SSukumar Swaminathan 216782527734SSukumar Swaminathan uint32_t rsvd3:16; 216882527734SSukumar Swaminathan uint32_t pri:3; 216982527734SSukumar Swaminathan uint32_t vf_id:12; 217082527734SSukumar Swaminathan uint32_t rsvd4:1; 217182527734SSukumar Swaminathan 217282527734SSukumar Swaminathan uint32_t hop_count:8; 217382527734SSukumar Swaminathan uint32_t rsvd5:24; 217482527734SSukumar Swaminathan #endif 217582527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 217682527734SSukumar Swaminathan uint32_t vfi:16; 217782527734SSukumar Swaminathan uint32_t rsvd1:13; 217882527734SSukumar Swaminathan uint32_t vf:1; 217982527734SSukumar Swaminathan uint32_t vt:1; 218082527734SSukumar Swaminathan uint32_t vr:1; 218182527734SSukumar Swaminathan 218282527734SSukumar Swaminathan uint16_t fcfi; 218382527734SSukumar Swaminathan uint16_t rsvd2; 218482527734SSukumar Swaminathan 218582527734SSukumar Swaminathan uint32_t rsvd4:1; 218682527734SSukumar Swaminathan uint32_t vf_id:12; 218782527734SSukumar Swaminathan uint32_t pri:3; 218882527734SSukumar Swaminathan uint32_t rsvd3:16; 218982527734SSukumar Swaminathan 219082527734SSukumar Swaminathan uint32_t rsvd5:24; 219182527734SSukumar Swaminathan uint32_t hop_count:8; 219282527734SSukumar Swaminathan #endif 219382527734SSukumar Swaminathan } INIT_VFI_VAR; 219482527734SSukumar Swaminathan 219582527734SSukumar Swaminathan /* Structure for MB Command UNREG_VFI (0xA1) */ 219682527734SSukumar Swaminathan /* Good for SLI4 only */ 219782527734SSukumar Swaminathan 219882527734SSukumar Swaminathan typedef struct 219982527734SSukumar Swaminathan { 220082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 220182527734SSukumar Swaminathan uint32_t rsvd1:3; 220282527734SSukumar Swaminathan uint32_t vp:1; 220382527734SSukumar Swaminathan uint32_t rsvd2:28; 220482527734SSukumar Swaminathan 220582527734SSukumar Swaminathan uint16_t vpi; 220682527734SSukumar Swaminathan uint16_t vfi; 220782527734SSukumar Swaminathan #endif 220882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 220982527734SSukumar Swaminathan uint32_t rsvd2:28; 221082527734SSukumar Swaminathan uint32_t vp:1; 221182527734SSukumar Swaminathan uint32_t rsvd1:3; 221282527734SSukumar Swaminathan 221382527734SSukumar Swaminathan uint16_t vfi; 221482527734SSukumar Swaminathan uint16_t vpi; 221582527734SSukumar Swaminathan #endif 221682527734SSukumar Swaminathan } UNREG_VFI_VAR; 221782527734SSukumar Swaminathan 221882527734SSukumar Swaminathan 221982527734SSukumar Swaminathan 222082527734SSukumar Swaminathan typedef struct 222182527734SSukumar Swaminathan { 222282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 222382527734SSukumar Swaminathan uint32_t read_log:1; 222482527734SSukumar Swaminathan uint32_t clear_log:1; 222582527734SSukumar Swaminathan uint32_t mbox_rsp:1; 222682527734SSukumar Swaminathan uint32_t resv:28; 222782527734SSukumar Swaminathan #endif 222882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 222982527734SSukumar Swaminathan uint32_t resv:28; 223082527734SSukumar Swaminathan uint32_t mbox_rsp:1; 223182527734SSukumar Swaminathan uint32_t clear_log:1; 223282527734SSukumar Swaminathan uint32_t read_log:1; 223382527734SSukumar Swaminathan #endif 223482527734SSukumar Swaminathan 223582527734SSukumar Swaminathan uint32_t offset; 223682527734SSukumar Swaminathan 223782527734SSukumar Swaminathan union 223882527734SSukumar Swaminathan { 223982527734SSukumar Swaminathan ULP_BDE sp; 224082527734SSukumar Swaminathan ULP_BDE64 sp64; 224182527734SSukumar Swaminathan } un; 224282527734SSukumar Swaminathan } READ_EVT_LOG_VAR; 224382527734SSukumar Swaminathan 224482527734SSukumar Swaminathan typedef struct 224582527734SSukumar Swaminathan { 224682527734SSukumar Swaminathan 224782527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 224882527734SSukumar Swaminathan uint16_t split_log_next; 224982527734SSukumar Swaminathan uint16_t log_next; 225082527734SSukumar Swaminathan 225182527734SSukumar Swaminathan uint32_t size; 225282527734SSukumar Swaminathan 225382527734SSukumar Swaminathan uint32_t format:8; 225482527734SSukumar Swaminathan uint32_t resv2:22; 225582527734SSukumar Swaminathan uint32_t log_level:1; 225682527734SSukumar Swaminathan uint32_t split_log:1; 225782527734SSukumar Swaminathan #endif 225882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 225982527734SSukumar Swaminathan uint16_t log_next; 226082527734SSukumar Swaminathan uint16_t split_log_next; 226182527734SSukumar Swaminathan 226282527734SSukumar Swaminathan uint32_t size; 226382527734SSukumar Swaminathan 226482527734SSukumar Swaminathan uint32_t split_log:1; 226582527734SSukumar Swaminathan uint32_t log_level:1; 226682527734SSukumar Swaminathan uint32_t resv2:22; 226782527734SSukumar Swaminathan uint32_t format:8; 226882527734SSukumar Swaminathan #endif 226982527734SSukumar Swaminathan 227082527734SSukumar Swaminathan uint32_t offset; 227182527734SSukumar Swaminathan } LOG_STATUS_VAR; 227282527734SSukumar Swaminathan 227382527734SSukumar Swaminathan 227482527734SSukumar Swaminathan /* Structure for MB Command CONFIG_PORT (0x88) */ 227582527734SSukumar Swaminathan typedef struct 227682527734SSukumar Swaminathan { 227782527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 227882527734SSukumar Swaminathan uint32_t cBE:1; 227982527734SSukumar Swaminathan uint32_t cET:1; 228082527734SSukumar Swaminathan uint32_t cHpcb:1; 228182527734SSukumar Swaminathan uint32_t rMA:1; 228282527734SSukumar Swaminathan uint32_t sli_mode:4; 228382527734SSukumar Swaminathan uint32_t pcbLen:24; /* bit 23:0 of memory based port */ 228482527734SSukumar Swaminathan /* config block */ 228582527734SSukumar Swaminathan #endif 228682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 228782527734SSukumar Swaminathan uint32_t pcbLen:24; /* bit 23:0 of memory based port */ 228882527734SSukumar Swaminathan /* config block */ 228982527734SSukumar Swaminathan uint32_t sli_mode:4; 229082527734SSukumar Swaminathan uint32_t rMA:1; 229182527734SSukumar Swaminathan uint32_t cHpcb:1; 229282527734SSukumar Swaminathan uint32_t cET:1; 229382527734SSukumar Swaminathan uint32_t cBE:1; 229482527734SSukumar Swaminathan #endif 229582527734SSukumar Swaminathan 229682527734SSukumar Swaminathan uint32_t pcbLow; /* bit 31:0 of memory based port */ 229782527734SSukumar Swaminathan /* config block */ 229882527734SSukumar Swaminathan uint32_t pcbHigh; /* bit 63:32 of memory based port */ 229982527734SSukumar Swaminathan /* config block */ 230082527734SSukumar Swaminathan uint32_t hbainit[5]; 230182527734SSukumar Swaminathan 230282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 230382527734SSukumar Swaminathan uint32_t hps:1; /* Host pointers in SLIM */ 230482527734SSukumar Swaminathan uint32_t rsvd:31; 230582527734SSukumar Swaminathan #endif 230682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 230782527734SSukumar Swaminathan uint32_t rsvd:31; 230882527734SSukumar Swaminathan uint32_t hps:1; /* Host pointers in SLIM */ 230982527734SSukumar Swaminathan #endif 231082527734SSukumar Swaminathan 231182527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 231282527734SSukumar Swaminathan uint32_t rsvd1:24; 231382527734SSukumar Swaminathan uint32_t cmv:1; /* Configure Max VPIs */ 231482527734SSukumar Swaminathan uint32_t ccrp:1; /* Config Command Ring Polling */ 231582527734SSukumar Swaminathan uint32_t csah:1; /* Configure Synchronous Abort */ 231682527734SSukumar Swaminathan /* Handling */ 231782527734SSukumar Swaminathan uint32_t chbs:1; /* Cofigure Host Backing store */ 231882527734SSukumar Swaminathan uint32_t cinb:1; /* Enable Interrupt Notification */ 231982527734SSukumar Swaminathan /* Block */ 232082527734SSukumar Swaminathan uint32_t cerbm:1; /* Configure Enhanced Receive */ 232182527734SSukumar Swaminathan /* Buffer Management */ 232282527734SSukumar Swaminathan uint32_t cmx:1; /* Configure Max XRIs */ 232382527734SSukumar Swaminathan uint32_t cmr:1; /* Configure Max RPIs */ 232482527734SSukumar Swaminathan #endif 232582527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 232682527734SSukumar Swaminathan uint32_t cmr:1; /* Configure Max RPIs */ 232782527734SSukumar Swaminathan uint32_t cmx:1; /* Configure Max XRIs */ 232882527734SSukumar Swaminathan uint32_t cerbm:1; /* Configure Enhanced Receive */ 232982527734SSukumar Swaminathan /* Buffer Management */ 233082527734SSukumar Swaminathan uint32_t cinb:1; /* Enable Interrupt Notification */ 233182527734SSukumar Swaminathan /* Block */ 233282527734SSukumar Swaminathan uint32_t chbs:1; /* Cofigure Host Backing store */ 233382527734SSukumar Swaminathan uint32_t csah:1; /* Configure Synchronous Abort */ 233482527734SSukumar Swaminathan /* Handling */ 233582527734SSukumar Swaminathan uint32_t ccrp:1; /* Config Command Ring Polling */ 233682527734SSukumar Swaminathan uint32_t cmv:1; /* Configure Max VPIs */ 233782527734SSukumar Swaminathan uint32_t rsvd1:24; 233882527734SSukumar Swaminathan #endif 233982527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 23408f23e9faSHans Rosenfeld uint32_t rsvd2:19; /* Reserved */ 23418f23e9faSHans Rosenfeld uint32_t gdss:1; /* Configure Data Security SLI */ 23428f23e9faSHans Rosenfeld uint32_t rsvd3:3; /* Reserved */ 23438f23e9faSHans Rosenfeld uint32_t gbg:1; /* Grant BlockGuard */ 234482527734SSukumar Swaminathan uint32_t gmv:1; /* Grant Max VPIs */ 234582527734SSukumar Swaminathan uint32_t gcrp:1; /* Grant Command Ring Polling */ 234682527734SSukumar Swaminathan uint32_t gsah:1; /* Grant Synchronous Abort Handling */ 234782527734SSukumar Swaminathan uint32_t ghbs:1; /* Grant Host Backing Store */ 234882527734SSukumar Swaminathan uint32_t ginb:1; /* Grant Interrupt Notification Block */ 234982527734SSukumar Swaminathan uint32_t gerbm:1; /* Grant ERBM Request */ 235082527734SSukumar Swaminathan uint32_t gmx:1; /* Grant Max XRIs */ 235182527734SSukumar Swaminathan uint32_t gmr:1; /* Grant Max RPIs */ 235282527734SSukumar Swaminathan #endif 235382527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 235482527734SSukumar Swaminathan uint32_t gmr:1; /* Grant Max RPIs */ 235582527734SSukumar Swaminathan uint32_t gmx:1; /* Grant Max XRIs */ 235682527734SSukumar Swaminathan uint32_t gerbm:1; /* Grant ERBM Request */ 235782527734SSukumar Swaminathan uint32_t ginb:1; /* Grant Interrupt Notification Block */ 235882527734SSukumar Swaminathan uint32_t ghbs:1; /* Grant Host Backing Store */ 235982527734SSukumar Swaminathan uint32_t gsah:1; /* Grant Synchronous Abort Handling */ 236082527734SSukumar Swaminathan uint32_t gcrp:1; /* Grant Command Ring Polling */ 236182527734SSukumar Swaminathan uint32_t gmv:1; /* Grant Max VPIs */ 23628f23e9faSHans Rosenfeld uint32_t gbg:1; /* Grant BlockGuard */ 23638f23e9faSHans Rosenfeld uint32_t rsvd3:3; /* Reserved */ 23648f23e9faSHans Rosenfeld uint32_t gdss:1; /* Configure Data Security SLI */ 23658f23e9faSHans Rosenfeld uint32_t rsvd2:19; /* Reserved */ 236682527734SSukumar Swaminathan #endif 236782527734SSukumar Swaminathan 236882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 236982527734SSukumar Swaminathan uint32_t max_rpi:16; /* Max RPIs Port should configure */ 237082527734SSukumar Swaminathan uint32_t max_xri:16; /* Max XRIs Port should configure */ 237182527734SSukumar Swaminathan #endif 237282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 237382527734SSukumar Swaminathan uint32_t max_xri:16; /* Max XRIs Port should configure */ 237482527734SSukumar Swaminathan uint32_t max_rpi:16; /* Max RPIs Port should configure */ 237582527734SSukumar Swaminathan #endif 237682527734SSukumar Swaminathan 237782527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 237882527734SSukumar Swaminathan uint32_t max_hbq:16; /* Max HBQs Host expect to configure */ 23798f23e9faSHans Rosenfeld uint32_t rsvd4:16; /* Max HBQs Host expect to configure */ 238082527734SSukumar Swaminathan #endif 238182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 23828f23e9faSHans Rosenfeld uint32_t rsvd4:16; /* Max HBQs Host expect to configure */ 238382527734SSukumar Swaminathan uint32_t max_hbq:16; /* Max HBQs Host expect to configure */ 238482527734SSukumar Swaminathan #endif 238582527734SSukumar Swaminathan 23868f23e9faSHans Rosenfeld uint32_t rsvd5; /* Reserved */ 238782527734SSukumar Swaminathan 238882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 23898f23e9faSHans Rosenfeld uint32_t rsvd6:16; /* Reserved */ 239082527734SSukumar Swaminathan uint32_t vpi_max:16; /* Max number of virt N-Ports */ 239182527734SSukumar Swaminathan #endif 239282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 239382527734SSukumar Swaminathan uint32_t vpi_max:16; /* Max number of virt N-Ports */ 23948f23e9faSHans Rosenfeld uint32_t rsvd6:16; /* Reserved */ 239582527734SSukumar Swaminathan #endif 239682527734SSukumar Swaminathan } CONFIG_PORT_VAR; 239782527734SSukumar Swaminathan 239882527734SSukumar Swaminathan /* Structure for MB Command REQUEST_FEATURES (0x9D) */ 239982527734SSukumar Swaminathan /* Good for SLI4 only */ 240082527734SSukumar Swaminathan 240182527734SSukumar Swaminathan typedef struct 240282527734SSukumar Swaminathan { 240382527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 240482527734SSukumar Swaminathan uint32_t rsvd1:31; 240582527734SSukumar Swaminathan uint32_t QueryMode:1; 240682527734SSukumar Swaminathan #endif 240782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 240882527734SSukumar Swaminathan uint32_t QueryMode:1; 240982527734SSukumar Swaminathan uint32_t rsvd1:31; 241082527734SSukumar Swaminathan #endif 241182527734SSukumar Swaminathan 241282527734SSukumar Swaminathan uint32_t featuresRequested; 241382527734SSukumar Swaminathan uint32_t featuresEnabled; 241482527734SSukumar Swaminathan 241582527734SSukumar Swaminathan } REQUEST_FEATURES_VAR; 241682527734SSukumar Swaminathan 24178f23e9faSHans Rosenfeld #define SLI4_FEATURE_INHIBIT_AUTO_ABTS 0x0001 24188f23e9faSHans Rosenfeld #define SLI4_FEATURE_NPIV 0x0002 24198f23e9faSHans Rosenfeld #define SLI4_FEATURE_DIF 0x0004 24208f23e9faSHans Rosenfeld #define SLI4_FEATURE_VIRTUAL_FABRICS 0x0008 24218f23e9faSHans Rosenfeld #define SLI4_FEATURE_FCP_INITIATOR 0x0010 24228f23e9faSHans Rosenfeld #define SLI4_FEATURE_FCP_TARGET 0x0020 24238f23e9faSHans Rosenfeld #define SLI4_FEATURE_FCP_COMBO 0x0040 24248f23e9faSHans Rosenfeld #define SLI4_FEATURE_RSVD1 0x0080 24258f23e9faSHans Rosenfeld #define SLI4_FEATURE_RQD 0x0100 24268f23e9faSHans Rosenfeld #define SLI4_FEATURE_INHIBIT_AUTO_ABTS_R 0x0200 24278f23e9faSHans Rosenfeld #define SLI4_FEATURE_HIGH_LOGIN_MODE 0x0400 24288f23e9faSHans Rosenfeld #define SLI4_FEATURE_PERF_HINT 0x0800 242982527734SSukumar Swaminathan 243082527734SSukumar Swaminathan 243182527734SSukumar Swaminathan /* SLI-2 Port Control Block */ 243282527734SSukumar Swaminathan 243382527734SSukumar Swaminathan /* SLIM POINTER */ 243482527734SSukumar Swaminathan #define SLIMOFF 0x30 /* WORD */ 243582527734SSukumar Swaminathan 243682527734SSukumar Swaminathan typedef struct _SLI2_RDSC 243782527734SSukumar Swaminathan { 243882527734SSukumar Swaminathan uint32_t cmdEntries; 243982527734SSukumar Swaminathan uint32_t cmdAddrLow; 244082527734SSukumar Swaminathan uint32_t cmdAddrHigh; 244182527734SSukumar Swaminathan 244282527734SSukumar Swaminathan uint32_t rspEntries; 244382527734SSukumar Swaminathan uint32_t rspAddrLow; 244482527734SSukumar Swaminathan uint32_t rspAddrHigh; 244582527734SSukumar Swaminathan } SLI2_RDSC; 244682527734SSukumar Swaminathan 244782527734SSukumar Swaminathan typedef struct _PCB 244882527734SSukumar Swaminathan { 244982527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 245082527734SSukumar Swaminathan uint32_t type:8; 245182527734SSukumar Swaminathan #define TYPE_NATIVE_SLI2 0x01; 245282527734SSukumar Swaminathan uint32_t feature:8; 245382527734SSukumar Swaminathan #define FEATURE_INITIAL_SLI2 0x01; 245482527734SSukumar Swaminathan uint32_t rsvd:12; 245582527734SSukumar Swaminathan uint32_t maxRing:4; 245682527734SSukumar Swaminathan #endif 245782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 245882527734SSukumar Swaminathan uint32_t maxRing:4; 245982527734SSukumar Swaminathan uint32_t rsvd:12; 246082527734SSukumar Swaminathan uint32_t feature:8; 246182527734SSukumar Swaminathan #define FEATURE_INITIAL_SLI2 0x01; 246282527734SSukumar Swaminathan uint32_t type:8; 246382527734SSukumar Swaminathan #define TYPE_NATIVE_SLI2 0x01; 246482527734SSukumar Swaminathan #endif 246582527734SSukumar Swaminathan 246682527734SSukumar Swaminathan uint32_t mailBoxSize; 246782527734SSukumar Swaminathan uint32_t mbAddrLow; 246882527734SSukumar Swaminathan uint32_t mbAddrHigh; 246982527734SSukumar Swaminathan 247082527734SSukumar Swaminathan uint32_t hgpAddrLow; 247182527734SSukumar Swaminathan uint32_t hgpAddrHigh; 247282527734SSukumar Swaminathan 247382527734SSukumar Swaminathan uint32_t pgpAddrLow; 247482527734SSukumar Swaminathan uint32_t pgpAddrHigh; 247582527734SSukumar Swaminathan SLI2_RDSC rdsc[MAX_RINGS_AVAILABLE]; 247682527734SSukumar Swaminathan } PCB; 247782527734SSukumar Swaminathan 247882527734SSukumar Swaminathan /* NEW_FEATURE */ 247982527734SSukumar Swaminathan typedef struct 248082527734SSukumar Swaminathan { 248182527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 248282527734SSukumar Swaminathan uint32_t rsvd0:27; 248382527734SSukumar Swaminathan uint32_t discardFarp:1; 248482527734SSukumar Swaminathan uint32_t IPEnable:1; 248582527734SSukumar Swaminathan uint32_t nodeName:1; 248682527734SSukumar Swaminathan uint32_t portName:1; 248782527734SSukumar Swaminathan uint32_t filterEnable:1; 248882527734SSukumar Swaminathan #endif 248982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 249082527734SSukumar Swaminathan uint32_t filterEnable:1; 249182527734SSukumar Swaminathan uint32_t portName:1; 249282527734SSukumar Swaminathan uint32_t nodeName:1; 249382527734SSukumar Swaminathan uint32_t IPEnable:1; 249482527734SSukumar Swaminathan uint32_t discardFarp:1; 249582527734SSukumar Swaminathan uint32_t rsvd:27; 249682527734SSukumar Swaminathan #endif 249782527734SSukumar Swaminathan NAME_TYPE portname; 249882527734SSukumar Swaminathan NAME_TYPE nodename; 249982527734SSukumar Swaminathan uint32_t rsvd1; 250082527734SSukumar Swaminathan uint32_t rsvd2; 250182527734SSukumar Swaminathan uint32_t rsvd3; 250282527734SSukumar Swaminathan uint32_t IPAddress; 250382527734SSukumar Swaminathan } CONFIG_FARP_VAR; 250482527734SSukumar Swaminathan 250582527734SSukumar Swaminathan 250682527734SSukumar Swaminathan /* NEW_FEATURE */ 250782527734SSukumar Swaminathan typedef struct 250882527734SSukumar Swaminathan { 250982527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 251082527734SSukumar Swaminathan uint32_t defaultMessageNumber:16; 251182527734SSukumar Swaminathan uint32_t rsvd1:3; 251282527734SSukumar Swaminathan uint32_t nid:5; 251382527734SSukumar Swaminathan uint32_t rsvd2:5; 251482527734SSukumar Swaminathan uint32_t defaultPresent:1; 251582527734SSukumar Swaminathan uint32_t addAssociations:1; 251682527734SSukumar Swaminathan uint32_t reportAssociations:1; 251782527734SSukumar Swaminathan #endif 251882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 251982527734SSukumar Swaminathan uint32_t reportAssociations:1; 252082527734SSukumar Swaminathan uint32_t addAssociations:1; 252182527734SSukumar Swaminathan uint32_t defaultPresent:1; 252282527734SSukumar Swaminathan uint32_t rsvd2:5; 252382527734SSukumar Swaminathan uint32_t nid:5; 252482527734SSukumar Swaminathan uint32_t rsvd1:3; 252582527734SSukumar Swaminathan uint32_t defaultMessageNumber:16; 252682527734SSukumar Swaminathan #endif 252782527734SSukumar Swaminathan uint32_t attConditions; 252882527734SSukumar Swaminathan uint8_t attentionId[16]; 252982527734SSukumar Swaminathan uint16_t messageNumberByHA[32]; 253082527734SSukumar Swaminathan uint16_t messageNumberByID[16]; 253182527734SSukumar Swaminathan uint32_t rsvd3; 253282527734SSukumar Swaminathan } CONFIG_MSI_VAR; 253382527734SSukumar Swaminathan 253482527734SSukumar Swaminathan 253582527734SSukumar Swaminathan /* NEW_FEATURE */ 253682527734SSukumar Swaminathan typedef struct 253782527734SSukumar Swaminathan { 253882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 253982527734SSukumar Swaminathan uint32_t defaultMessageNumber:8; 254082527734SSukumar Swaminathan uint32_t rsvd1:11; 254182527734SSukumar Swaminathan uint32_t nid:5; 254282527734SSukumar Swaminathan uint32_t rsvd2:5; 254382527734SSukumar Swaminathan uint32_t defaultPresent:1; 254482527734SSukumar Swaminathan uint32_t addAssociations:1; 254582527734SSukumar Swaminathan uint32_t reportAssociations:1; 254682527734SSukumar Swaminathan #endif 254782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 254882527734SSukumar Swaminathan uint32_t reportAssociations:1; 254982527734SSukumar Swaminathan uint32_t addAssociations:1; 255082527734SSukumar Swaminathan uint32_t defaultPresent:1; 255182527734SSukumar Swaminathan uint32_t rsvd2:5; 255282527734SSukumar Swaminathan uint32_t nid:5; 255382527734SSukumar Swaminathan uint32_t rsvd1:11; 255482527734SSukumar Swaminathan uint32_t defaultMessageNumber:8; 255582527734SSukumar Swaminathan #endif 255682527734SSukumar Swaminathan uint32_t attConditions1; 255782527734SSukumar Swaminathan uint32_t attConditions2; 255882527734SSukumar Swaminathan uint8_t attentionId[16]; 255982527734SSukumar Swaminathan uint8_t messageNumberByHA[64]; 256082527734SSukumar Swaminathan uint8_t messageNumberByID[16]; 256182527734SSukumar Swaminathan uint32_t autoClearByHA1; 256282527734SSukumar Swaminathan uint32_t autoClearByHA2; 256382527734SSukumar Swaminathan uint32_t autoClearByID; 256482527734SSukumar Swaminathan uint32_t resv3; 256582527734SSukumar Swaminathan } CONFIG_MSIX_VAR; 256682527734SSukumar Swaminathan 256782527734SSukumar Swaminathan 256882527734SSukumar Swaminathan /* Union of all Mailbox Command types */ 256982527734SSukumar Swaminathan 257082527734SSukumar Swaminathan typedef union 257182527734SSukumar Swaminathan { 257282527734SSukumar Swaminathan uint32_t varWords[31]; 257382527734SSukumar Swaminathan LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 257482527734SSukumar Swaminathan READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 257582527734SSukumar Swaminathan WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 257682527734SSukumar Swaminathan BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 257782527734SSukumar Swaminathan INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 257882527734SSukumar Swaminathan DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 257982527734SSukumar Swaminathan CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 258082527734SSukumar Swaminathan PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 258182527734SSukumar Swaminathan CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 258282527734SSukumar Swaminathan RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 258382527734SSukumar Swaminathan READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 258482527734SSukumar Swaminathan READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 258582527734SSukumar Swaminathan READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 258682527734SSukumar Swaminathan READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 258782527734SSukumar Swaminathan READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 258882527734SSukumar Swaminathan READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 258982527734SSukumar Swaminathan READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 259082527734SSukumar Swaminathan READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 259182527734SSukumar Swaminathan REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 259282527734SSukumar Swaminathan UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 259382527734SSukumar Swaminathan READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 259482527734SSukumar Swaminathan CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 259582527734SSukumar Swaminathan DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 259682527734SSukumar Swaminathan UPDATE_CFG_VAR varUpdateCfg; /* cmd = 0x1b Warm Start */ 259782527734SSukumar Swaminathan /* UPDATE_CFG cmd */ 259882527734SSukumar Swaminathan DEL_LD_ENTRY_VAR varDelLdEntry; /* cmd = 0x1d (DEL_LD_ENTRY) */ 259982527734SSukumar Swaminathan UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 260082527734SSukumar Swaminathan CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) */ 260182527734SSukumar Swaminathan CONFIG_MSI_VAR varCfgMSI; /* cmd = 0x90 (CONFIG_MSI) */ 260282527734SSukumar Swaminathan CONFIG_MSIX_VAR varCfgMSIX; /* cmd = 0x30 (CONFIG_MSIX) */ 260382527734SSukumar Swaminathan CONFIG_HBQ_VAR varCfgHbq; /* cmd = 0x7C (CONFIG_HBQ) */ 260482527734SSukumar Swaminathan LOAD_AREA_VAR varLdArea; /* cmd = 0x81 (LOAD_AREA) */ 260582527734SSukumar Swaminathan CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 260682527734SSukumar Swaminathan LOAD_EXP_ROM_VAR varLdExpRom; /* cmd = 0x9C (LOAD_XP_ROM) */ 260782527734SSukumar Swaminathan REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 260882527734SSukumar Swaminathan UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 260982527734SSukumar Swaminathan READ_EVT_LOG_VAR varRdEvtLog; /* cmd = 0x38 (READ_EVT_LOG) */ 261082527734SSukumar Swaminathan LOG_STATUS_VAR varLogStat; /* cmd = 0x37 */ 261182527734SSukumar Swaminathan 261282527734SSukumar Swaminathan } MAILVARIANTS; 261382527734SSukumar Swaminathan 261482527734SSukumar Swaminathan #define MAILBOX_CMD_BSIZE 128 261582527734SSukumar Swaminathan #define MAILBOX_CMD_WSIZE 32 261682527734SSukumar Swaminathan 261782527734SSukumar Swaminathan /* 261882527734SSukumar Swaminathan * SLI-2 specific structures 261982527734SSukumar Swaminathan */ 262082527734SSukumar Swaminathan 262182527734SSukumar Swaminathan typedef struct _SLI1_DESC 262282527734SSukumar Swaminathan { 262382527734SSukumar Swaminathan emlxs_rings_t mbxCring[4]; 262482527734SSukumar Swaminathan uint32_t mbxUnused[24]; 262582527734SSukumar Swaminathan } SLI1_DESC; /* 128 bytes */ 262682527734SSukumar Swaminathan 262782527734SSukumar Swaminathan typedef struct 262882527734SSukumar Swaminathan { 262982527734SSukumar Swaminathan uint32_t cmdPutInx; 263082527734SSukumar Swaminathan uint32_t rspGetInx; 263182527734SSukumar Swaminathan } HGP; 263282527734SSukumar Swaminathan 263382527734SSukumar Swaminathan typedef struct 263482527734SSukumar Swaminathan { 263582527734SSukumar Swaminathan uint32_t cmdGetInx; 263682527734SSukumar Swaminathan uint32_t rspPutInx; 263782527734SSukumar Swaminathan } PGP; 263882527734SSukumar Swaminathan 263982527734SSukumar Swaminathan typedef struct _SLI2_DESC 264082527734SSukumar Swaminathan { 264182527734SSukumar Swaminathan HGP host[4]; 264282527734SSukumar Swaminathan PGP port[4]; 264382527734SSukumar Swaminathan uint32_t HBQ_PortGetIdx[16]; 264482527734SSukumar Swaminathan } SLI2_DESC; /* 128 bytes */ 264582527734SSukumar Swaminathan 264682527734SSukumar Swaminathan typedef union 264782527734SSukumar Swaminathan { 264882527734SSukumar Swaminathan SLI1_DESC s1; /* 32 words, 128 bytes */ 264982527734SSukumar Swaminathan SLI2_DESC s2; /* 32 words, 128 bytes */ 265082527734SSukumar Swaminathan } SLI_VAR; 265182527734SSukumar Swaminathan 265282527734SSukumar Swaminathan typedef volatile struct 265382527734SSukumar Swaminathan { 265482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 265582527734SSukumar Swaminathan uint16_t mbxStatus; 265682527734SSukumar Swaminathan uint8_t mbxCommand; 265782527734SSukumar Swaminathan uint8_t mbxReserved:6; 265882527734SSukumar Swaminathan uint8_t mbxHc:1; 265982527734SSukumar Swaminathan uint8_t mbxOwner:1; /* Low order bit first word */ 266082527734SSukumar Swaminathan #endif 266182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 266282527734SSukumar Swaminathan uint8_t mbxOwner:1; /* Low order bit first word */ 266382527734SSukumar Swaminathan uint8_t mbxHc:1; 266482527734SSukumar Swaminathan uint8_t mbxReserved:6; 266582527734SSukumar Swaminathan uint8_t mbxCommand; 266682527734SSukumar Swaminathan uint16_t mbxStatus; 266782527734SSukumar Swaminathan #endif 266882527734SSukumar Swaminathan MAILVARIANTS un; /* 124 bytes */ 266982527734SSukumar Swaminathan SLI_VAR us; /* 128 bytes */ 267082527734SSukumar Swaminathan } MAILBOX; /* 256 bytes */ 267182527734SSukumar Swaminathan 267282527734SSukumar Swaminathan 267382527734SSukumar Swaminathan 267482527734SSukumar Swaminathan /* SLI4 IOCTL Mailbox */ 267582527734SSukumar Swaminathan /* ALL SLI4 specific mbox commands have a standard request /response header */ 267682527734SSukumar Swaminathan /* Word 0 is just like SLI 3 */ 267782527734SSukumar Swaminathan 267882527734SSukumar Swaminathan typedef struct mbox_req_hdr 267982527734SSukumar Swaminathan { 268082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 268182527734SSukumar Swaminathan uint32_t domain:8; /* word 6 */ 268282527734SSukumar Swaminathan uint32_t port:8; 268382527734SSukumar Swaminathan uint32_t subsystem:8; 268482527734SSukumar Swaminathan uint32_t opcode:8; 26858f23e9faSHans Rosenfeld 26868f23e9faSHans Rosenfeld uint32_t timeout; /* word 7 */ 26878f23e9faSHans Rosenfeld 26888f23e9faSHans Rosenfeld uint32_t req_length; /* word 8 */ 26898f23e9faSHans Rosenfeld 26908f23e9faSHans Rosenfeld uint32_t reserved1:24; /* word 9 */ 26918f23e9faSHans Rosenfeld uint32_t version:8; /* word 9 */ 269282527734SSukumar Swaminathan #endif 269382527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 269482527734SSukumar Swaminathan uint32_t opcode:8; 269582527734SSukumar Swaminathan uint32_t subsystem:8; 269682527734SSukumar Swaminathan uint32_t port:8; 269782527734SSukumar Swaminathan uint32_t domain:8; /* word 6 */ 26988f23e9faSHans Rosenfeld 269982527734SSukumar Swaminathan uint32_t timeout; /* word 7 */ 27008f23e9faSHans Rosenfeld 270182527734SSukumar Swaminathan uint32_t req_length; /* word 8 */ 27028f23e9faSHans Rosenfeld 27038f23e9faSHans Rosenfeld uint32_t version:8; /* word 9 */ 27048f23e9faSHans Rosenfeld uint32_t reserved1:24; /* word 9 */ 27058f23e9faSHans Rosenfeld #endif 27068f23e9faSHans Rosenfeld 270782527734SSukumar Swaminathan } mbox_req_hdr_t; 270882527734SSukumar Swaminathan 27098f23e9faSHans Rosenfeld 27108f23e9faSHans Rosenfeld typedef struct mbox_req_hdr2 27118f23e9faSHans Rosenfeld { 27128f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 27138f23e9faSHans Rosenfeld uint32_t vf_number:16; /* word 6 */ 27148f23e9faSHans Rosenfeld uint32_t subsystem:8; 27158f23e9faSHans Rosenfeld uint32_t opcode:8; 27168f23e9faSHans Rosenfeld 27178f23e9faSHans Rosenfeld uint32_t timeout; /* word 7 */ 27188f23e9faSHans Rosenfeld 27198f23e9faSHans Rosenfeld uint32_t req_length; /* word 8 */ 27208f23e9faSHans Rosenfeld 27218f23e9faSHans Rosenfeld uint32_t vh_number:6; /* word 9 */ 27228f23e9faSHans Rosenfeld uint32_t pf_number:10; 27238f23e9faSHans Rosenfeld uint32_t reserved1:8; 27248f23e9faSHans Rosenfeld uint32_t version:8; 27258f23e9faSHans Rosenfeld #endif 27268f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 27278f23e9faSHans Rosenfeld uint32_t opcode:8; 27288f23e9faSHans Rosenfeld uint32_t subsystem:8; 27298f23e9faSHans Rosenfeld uint32_t vf_number:16; /* word 6 */ 27308f23e9faSHans Rosenfeld 27318f23e9faSHans Rosenfeld uint32_t timeout; /* word 7 */ 27328f23e9faSHans Rosenfeld 27338f23e9faSHans Rosenfeld uint32_t req_length; /* word 8 */ 27348f23e9faSHans Rosenfeld 27358f23e9faSHans Rosenfeld uint32_t version:8; 27368f23e9faSHans Rosenfeld uint32_t reserved1:8; 27378f23e9faSHans Rosenfeld uint32_t pf_number:10; 27388f23e9faSHans Rosenfeld uint32_t vh_number:6; /* word 9 */ 27398f23e9faSHans Rosenfeld #endif 27408f23e9faSHans Rosenfeld 27418f23e9faSHans Rosenfeld } mbox_req_hdr2_t; 27428f23e9faSHans Rosenfeld 274382527734SSukumar Swaminathan typedef struct mbox_rsp_hdr 274482527734SSukumar Swaminathan { 274582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 274682527734SSukumar Swaminathan uint32_t domain:8; /* word 6 */ 274782527734SSukumar Swaminathan uint32_t reserved1:8; 274882527734SSukumar Swaminathan uint32_t subsystem:8; 274982527734SSukumar Swaminathan uint32_t opcode:8; 275082527734SSukumar Swaminathan 275182527734SSukumar Swaminathan uint32_t reserved2:16; /* word 7 */ 275282527734SSukumar Swaminathan uint32_t extra_status:8; 275382527734SSukumar Swaminathan uint32_t status:8; 275482527734SSukumar Swaminathan #endif 275582527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 275682527734SSukumar Swaminathan uint32_t opcode:8; 275782527734SSukumar Swaminathan uint32_t subsystem:8; 275882527734SSukumar Swaminathan uint32_t reserved1:8; 275982527734SSukumar Swaminathan uint32_t domain:8; /* word 6 */ 276082527734SSukumar Swaminathan 276182527734SSukumar Swaminathan uint32_t status:8; 276282527734SSukumar Swaminathan uint32_t extra_status:8; 276382527734SSukumar Swaminathan uint32_t reserved2:16; /* word 7 */ 276482527734SSukumar Swaminathan #endif 276582527734SSukumar Swaminathan uint32_t rsp_length; /* word 8 */ 276682527734SSukumar Swaminathan uint32_t allocated_length; /* word 9 */ 276782527734SSukumar Swaminathan } mbox_rsp_hdr_t; 276882527734SSukumar Swaminathan 2769a9800bebSGarrett D'Amore #define MBX_RSP_STATUS_SUCCESS 0x00 2770a9800bebSGarrett D'Amore #define MBX_RSP_STATUS_FAILED 0x01 2771a9800bebSGarrett D'Amore #define MBX_RSP_STATUS_ILLEGAL_REQ 0x02 2772a9800bebSGarrett D'Amore #define MBX_RSP_STATUS_ILLEGAL_FIELD 0x03 2773a9800bebSGarrett D'Amore #define MBX_RSP_STATUS_FCF_IN_USE 0x3A 2774a9800bebSGarrett D'Amore #define MBX_RSP_STATUS_NO_FCF 0x43 2775a9800bebSGarrett D'Amore 27768f23e9faSHans Rosenfeld #define MGMT_ADDI_STATUS_INCOMPATIBLE 0xA2 27778f23e9faSHans Rosenfeld 277882527734SSukumar Swaminathan typedef struct be_req_hdr 277982527734SSukumar Swaminathan { 278082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 278182527734SSukumar Swaminathan uint32_t special:8; /* word 1 */ 278282527734SSukumar Swaminathan uint32_t reserved2:16; /* word 1 */ 278382527734SSukumar Swaminathan uint32_t sge_cnt:5; /* word 1 */ 278482527734SSukumar Swaminathan uint32_t reserved1:2; /* word 1 */ 278582527734SSukumar Swaminathan uint32_t embedded:1; /* word 1 */ 278682527734SSukumar Swaminathan #endif 278782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 278882527734SSukumar Swaminathan uint32_t embedded:1; /* word 1 */ 278982527734SSukumar Swaminathan uint32_t reserved1:2; /* word 1 */ 279082527734SSukumar Swaminathan uint32_t sge_cnt:5; /* word 1 */ 279182527734SSukumar Swaminathan uint32_t reserved2:16; /* word 1 */ 279282527734SSukumar Swaminathan uint32_t special:8; /* word 1 */ 279382527734SSukumar Swaminathan #endif 279482527734SSukumar Swaminathan uint32_t payload_length; /* word 2 */ 279582527734SSukumar Swaminathan uint32_t tag_low; /* word 3 */ 279682527734SSukumar Swaminathan uint32_t tag_hi; /* word 4 */ 279782527734SSukumar Swaminathan uint32_t reserved3; /* word 5 */ 279882527734SSukumar Swaminathan union 279982527734SSukumar Swaminathan { 280082527734SSukumar Swaminathan mbox_req_hdr_t hdr_req; 28018f23e9faSHans Rosenfeld mbox_req_hdr2_t hdr_req2; 280282527734SSukumar Swaminathan mbox_rsp_hdr_t hdr_rsp; 280382527734SSukumar Swaminathan } un_hdr; 280482527734SSukumar Swaminathan } be_req_hdr_t; 280582527734SSukumar Swaminathan 280682527734SSukumar Swaminathan #define EMLXS_MAX_NONEMBED_SIZE (1024 * 64) 280782527734SSukumar Swaminathan 280882527734SSukumar Swaminathan /* SLI_CONFIG Mailbox commands */ 280982527734SSukumar Swaminathan 281082527734SSukumar Swaminathan #define IOCTL_SUBSYSTEM_COMMON 0x01 2811088c6f3fSHans Rosenfeld #define IOCTL_SUBSYSTEM_LOWLEVEL 0x0B 281282527734SSukumar Swaminathan #define IOCTL_SUBSYSTEM_FCOE 0x0C 281382527734SSukumar Swaminathan #define IOCTL_SUBSYSTEM_DCBX 0x10 281482527734SSukumar Swaminathan 281582527734SSukumar Swaminathan #define COMMON_OPCODE_READ_FLASHROM 0x06 281682527734SSukumar Swaminathan #define COMMON_OPCODE_WRITE_FLASHROM 0x07 281782527734SSukumar Swaminathan #define COMMON_OPCODE_CQ_CREATE 0x0C 281882527734SSukumar Swaminathan #define COMMON_OPCODE_EQ_CREATE 0x0D 281982527734SSukumar Swaminathan #define COMMON_OPCODE_MQ_CREATE 0x15 282082527734SSukumar Swaminathan #define COMMON_OPCODE_GET_CNTL_ATTRIB 0x20 282182527734SSukumar Swaminathan #define COMMON_OPCODE_NOP 0x21 282282527734SSukumar Swaminathan #define COMMON_OPCODE_QUERY_FIRMWARE_CONFIG 0x3A 282382527734SSukumar Swaminathan #define COMMON_OPCODE_RESET 0x3D 28248f23e9faSHans Rosenfeld #define COMMON_OPCODE_SET_PHYSICAL_LINK_CFG_V1 0x3E 28258f23e9faSHans Rosenfeld 28268f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_BOOT_CFG 0x42 28278f23e9faSHans Rosenfeld #define COMMON_OPCODE_SET_BOOT_CFG 0x43 282882527734SSukumar Swaminathan #define COMMON_OPCODE_MANAGE_FAT 0x44 28298f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_PHYSICAL_LINK_CFG_V1 0x47 28308f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_PORT_NAME 0x4D 28318f23e9faSHans Rosenfeld 28328f23e9faSHans Rosenfeld #define COMMON_OPCODE_MQ_CREATE_EXT 0x5A 28338f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_VPD_DATA 0x5B 28348f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_PHY_DETAILS 0x66 28358f23e9faSHans Rosenfeld #define COMMON_OPCODE_SEND_ACTIVATION 0x73 28368f23e9faSHans Rosenfeld #define COMMON_OPCODE_RESET_LICENSES 0x74 28378f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_CNTL_ADDL_ATTRIB 0x79 28388f23e9faSHans Rosenfeld 28398f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_EXTENTS_INFO 0x9A 28408f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_EXTENTS 0x9B 28418f23e9faSHans Rosenfeld #define COMMON_OPCODE_ALLOC_EXTENTS 0x9C 28428f23e9faSHans Rosenfeld #define COMMON_OPCODE_DEALLOC_EXTENTS 0x9D 28438f23e9faSHans Rosenfeld 28448f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_PROFILE_CAPS 0xA1 28458f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_MR_PROFILE_CAPS 0xA2 28468f23e9faSHans Rosenfeld #define COMMON_OPCODE_SET_MR_PROFILE_CAPS 0xA3 28478f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_PROFILE_CFG 0xA4 28488f23e9faSHans Rosenfeld #define COMMON_OPCODE_SET_PROFILE_CFG 0xA5 28498f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_PROFILE_LIST 0xA6 28508f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_ACTIVE_PROFILE 0xA7 28518f23e9faSHans Rosenfeld #define COMMON_OPCODE_SET_ACTIVE_PROFILE 0xA8 28528f23e9faSHans Rosenfeld #define COMMON_OPCODE_SET_FACTORY_PROFILE_CFG 0xA9 28538f23e9faSHans Rosenfeld 28548f23e9faSHans Rosenfeld #define COMMON_OPCODE_READ_OBJ 0xAB 28558f23e9faSHans Rosenfeld #define COMMON_OPCODE_WRITE_OBJ 0xAC 28568f23e9faSHans Rosenfeld #define COMMON_OPCODE_READ_OBJ_LIST 0xAD 28578f23e9faSHans Rosenfeld #define COMMON_OPCODE_DELETE_OBJ 0xAE 28588f23e9faSHans Rosenfeld #define COMMON_OPCODE_GET_SLI4_PARAMS 0xB5 2859*e2d1a434SCarsten Grzemba #define COMMON_OPCODE_SET_FEATURES 0xBF 2860*e2d1a434SCarsten Grzemba #define COMMON_OPCODE_GET_RECONFIG_LINK_INFO 0xC9 2861*e2d1a434SCarsten Grzemba #define COMMON_OPCODE_SET_RECONFIG_LINK_ID 0xCA 286282527734SSukumar Swaminathan 2863088c6f3fSHans Rosenfeld #define LOWLEVEL_OPCODE_GPIO_RDWR 0x30 2864088c6f3fSHans Rosenfeld 286582527734SSukumar Swaminathan #define FCOE_OPCODE_WQ_CREATE 0x01 286682527734SSukumar Swaminathan #define FCOE_OPCODE_CFG_POST_SGL_PAGES 0x03 286782527734SSukumar Swaminathan #define FCOE_OPCODE_RQ_CREATE 0x05 286882527734SSukumar Swaminathan #define FCOE_OPCODE_READ_FCF_TABLE 0x08 286982527734SSukumar Swaminathan #define FCOE_OPCODE_ADD_FCF_TABLE 0x09 2870a9800bebSGarrett D'Amore #define FCOE_OPCODE_DELETE_FCF_TABLE 0x0A 287182527734SSukumar Swaminathan #define FCOE_OPCODE_POST_HDR_TEMPLATES 0x0B 2872a9800bebSGarrett D'Amore #define FCOE_OPCODE_REDISCOVER_FCF_TABLE 0x10 28738f23e9faSHans Rosenfeld #define FCOE_OPCODE_SET_FCLINK_SETTINGS 0x21 287482527734SSukumar Swaminathan 287582527734SSukumar Swaminathan #define DCBX_OPCODE_GET_DCBX_MODE 0x04 287682527734SSukumar Swaminathan #define DCBX_OPCODE_SET_DCBX_MODE 0x05 287782527734SSukumar Swaminathan 287882527734SSukumar Swaminathan typedef struct 287982527734SSukumar Swaminathan { 288082527734SSukumar Swaminathan struct 288182527734SSukumar Swaminathan { 288282527734SSukumar Swaminathan uint32_t opcode; 288382527734SSukumar Swaminathan #define MGMT_FLASHROM_OPCODE_FLASH 1 288482527734SSukumar Swaminathan #define MGMT_FLASHROM_OPCODE_SAVE 2 288582527734SSukumar Swaminathan #define MGMT_FLASHROM_OPCODE_CLEAR 3 288682527734SSukumar Swaminathan #define MGMT_FLASHROM_OPCODE_REPORT 4 288782527734SSukumar Swaminathan #define MGMT_FLASHROM_OPCODE_INFO 5 288882527734SSukumar Swaminathan #define MGMT_FLASHROM_OPCODE_CRC 6 28898f23e9faSHans Rosenfeld #define MGMT_FLASHROM_OPCODE_OFFSET_FLASH 7 28908f23e9faSHans Rosenfeld #define MGMT_FLASHROM_OPCODE_OFFSET_SAVE 8 28918f23e9faSHans Rosenfeld #define MGMT_PHY_FLASHROM_OPCODE_FLASH 9 28928f23e9faSHans Rosenfeld #define MGMT_PHY_FLASHROM_OPCODE_SAVE 10 289382527734SSukumar Swaminathan 289482527734SSukumar Swaminathan uint32_t optype; 289582527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_ISCSI_FIRMWARE 0 289682527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_REDBOOT 1 289782527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_ISCSI_BIOS 2 289882527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_PXE_BIOS 3 289982527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_CTRLS 4 290082527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_CFG_IPSEC 5 290182527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_CFG_INI 6 290282527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_ROM_OFFSET 7 290382527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_FCOE_BIOS 8 290482527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_ISCSI_BACKUP 9 290582527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_FCOE_FIRMWARE 10 290682527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_FCOE_BACKUP 11 290782527734SSukumar Swaminathan #define MGMT_FLASHROM_OPTYPE_CTRLP 12 2908a9800bebSGarrett D'Amore #define MGMT_FLASHROM_OPTYPE_NCSI_FIRMWARE 13 29098f23e9faSHans Rosenfeld #define MGMT_FLASHROM_OPTYPE_CFG_NIC 14 29108f23e9faSHans Rosenfeld #define MGMT_FLASHROM_OPTYPE_CFG_DCBX 15 29118f23e9faSHans Rosenfeld #define MGMT_FLASHROM_OPTYPE_CFG_PXE_BIOS 16 29128f23e9faSHans Rosenfeld #define MGMT_FLASHROM_OPTYPE_CFG_ALL 17 29138f23e9faSHans Rosenfeld #define MGMT_FLASHROM_OPTYPE_PHY_FIRMWARE 0xff /* Driver defined */ 291482527734SSukumar Swaminathan 291582527734SSukumar Swaminathan uint32_t data_buffer_size; /* Align to 4KB */ 291682527734SSukumar Swaminathan uint32_t offset; 291782527734SSukumar Swaminathan uint32_t data_buffer; /* image starts here */ 291882527734SSukumar Swaminathan 291982527734SSukumar Swaminathan } params; 292082527734SSukumar Swaminathan 292182527734SSukumar Swaminathan } IOCTL_COMMON_FLASHROM; 292282527734SSukumar Swaminathan 292382527734SSukumar Swaminathan 29248f23e9faSHans Rosenfeld typedef struct 29258f23e9faSHans Rosenfeld { 29268f23e9faSHans Rosenfeld union 29278f23e9faSHans Rosenfeld { 29288f23e9faSHans Rosenfeld struct 29298f23e9faSHans Rosenfeld { 29308f23e9faSHans Rosenfeld uint32_t rsvd; 29318f23e9faSHans Rosenfeld } request; 29328f23e9faSHans Rosenfeld 29338f23e9faSHans Rosenfeld 29348f23e9faSHans Rosenfeld struct 29358f23e9faSHans Rosenfeld { 29368f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 29378f23e9faSHans Rosenfeld uint16_t interface_type; 29388f23e9faSHans Rosenfeld uint16_t phy_type; 29398f23e9faSHans Rosenfeld #endif 29408f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 29418f23e9faSHans Rosenfeld uint16_t phy_type; 29428f23e9faSHans Rosenfeld uint16_t interface_type; 29438f23e9faSHans Rosenfeld #endif 29448f23e9faSHans Rosenfeld 29458f23e9faSHans Rosenfeld /* phy_type */ 29468f23e9faSHans Rosenfeld #define PHY_XAUI 0x0 29478f23e9faSHans Rosenfeld #define PHY_AEL_2020 0x1 /* eluris/Netlogic */ 29488f23e9faSHans Rosenfeld #define PHY_LSI_BRCM1 0x2 /* Peak pre-production board */ 29498f23e9faSHans Rosenfeld #define PHY_LSI_BRCM2 0x3 /* Peak production board */ 29508f23e9faSHans Rosenfeld #define PHY_SOLARFLARE 0x4 /* Dell recommended */ 29518f23e9faSHans Rosenfeld #define PHY_AMCC_QT2025 0x5 /* AMCC PHY */ 29528f23e9faSHans Rosenfeld #define PHY_AMCC_QT2225 0x6 /* AMCC PHY */ 29538f23e9faSHans Rosenfeld #define PHY_BRCM_5931 0x7 /* Broadcom Phy used by HP LOM */ 29548f23e9faSHans Rosenfeld #define PHY_BE3_INTERNAL_10GB 0x8 /* Internal 10GbPHY in BE3 */ 29558f23e9faSHans Rosenfeld #define PHY_BE3_INTERNAL_1GB 0x9 /* Internal 1Gb PHY in BE3 */ 29568f23e9faSHans Rosenfeld #define PHY_TN_2022 0xa /* Teranetics dual port 65nm PHY */ 29578f23e9faSHans Rosenfeld #define PHY_MARVELL_88E1340 0xb /* Marvel 1G PHY */ 29588f23e9faSHans Rosenfeld #define PHY_MARVELL_88E1322 0xc /* Marvel 1G PHY */ 29598f23e9faSHans Rosenfeld #define PHY_TN_8022 0xd /* Teranetics dual port 40nm PHY */ 29608f23e9faSHans Rosenfeld #define PHY_TYPE_NOT_SUPPORTED 29618f23e9faSHans Rosenfeld 29628f23e9faSHans Rosenfeld /* interface_type */ 29638f23e9faSHans Rosenfeld #define CX4_10GB_TYPE 0x0 29648f23e9faSHans Rosenfeld #define XFP_10GB_TYPE 0x1 29658f23e9faSHans Rosenfeld #define SFP_1GB_TYPE 0x2 29668f23e9faSHans Rosenfeld #define SFP_PLUS_10GB_TYPE 0x3 29678f23e9faSHans Rosenfeld #define KR_10GB_TYPE 0x4 29688f23e9faSHans Rosenfeld #define KX4_10GB_TYPE 0x5 29698f23e9faSHans Rosenfeld #define BASET_10GB_TYPE 0x6 /* 10G BaseT */ 29708f23e9faSHans Rosenfeld #define BASET_1000_TYPE 0x7 /* 1000 BaseT */ 29718f23e9faSHans Rosenfeld #define BASEX_1000_TYPE 0x8 /* 1000 BaseX */ 29728f23e9faSHans Rosenfeld #define SGMII_TYPE 0x9 29738f23e9faSHans Rosenfeld #define INTERFACE_10GB_DISABLED 0xff /* Interface type not supported */ 29748f23e9faSHans Rosenfeld 29758f23e9faSHans Rosenfeld uint32_t misc_params; 29768f23e9faSHans Rosenfeld uint32_t rsvd[4]; 29778f23e9faSHans Rosenfeld } response; 29788f23e9faSHans Rosenfeld 29798f23e9faSHans Rosenfeld } params; 29808f23e9faSHans Rosenfeld 29818f23e9faSHans Rosenfeld } IOCTL_COMMON_GET_PHY_DETAILS; 29828f23e9faSHans Rosenfeld 29838f23e9faSHans Rosenfeld 29848f23e9faSHans Rosenfeld typedef struct 29858f23e9faSHans Rosenfeld { 29868f23e9faSHans Rosenfeld union 29878f23e9faSHans Rosenfeld { 29888f23e9faSHans Rosenfeld struct 29898f23e9faSHans Rosenfeld { 29908f23e9faSHans Rosenfeld uint32_t rsvd; 29918f23e9faSHans Rosenfeld } request; 29928f23e9faSHans Rosenfeld 29938f23e9faSHans Rosenfeld 29948f23e9faSHans Rosenfeld struct 29958f23e9faSHans Rosenfeld { 29968f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 29978f23e9faSHans Rosenfeld uint8_t port3_name; 29988f23e9faSHans Rosenfeld uint8_t port2_name; 29998f23e9faSHans Rosenfeld uint8_t port1_name; 30008f23e9faSHans Rosenfeld uint8_t port0_name; 30018f23e9faSHans Rosenfeld #endif 30028f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 30038f23e9faSHans Rosenfeld uint8_t port0_name; 30048f23e9faSHans Rosenfeld uint8_t port1_name; 30058f23e9faSHans Rosenfeld uint8_t port2_name; 30068f23e9faSHans Rosenfeld uint8_t port3_name; 30078f23e9faSHans Rosenfeld #endif 30088f23e9faSHans Rosenfeld } response; 30098f23e9faSHans Rosenfeld 30108f23e9faSHans Rosenfeld } params; 30118f23e9faSHans Rosenfeld 30128f23e9faSHans Rosenfeld } IOCTL_COMMON_GET_PORT_NAME; 30138f23e9faSHans Rosenfeld 30148f23e9faSHans Rosenfeld 30158f23e9faSHans Rosenfeld typedef struct 30168f23e9faSHans Rosenfeld { 30178f23e9faSHans Rosenfeld union 30188f23e9faSHans Rosenfeld { 30198f23e9faSHans Rosenfeld struct 30208f23e9faSHans Rosenfeld { 30218f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 30228f23e9faSHans Rosenfeld uint32_t rsvd:30; 30238f23e9faSHans Rosenfeld uint32_t pt:2; 30248f23e9faSHans Rosenfeld #endif 30258f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 30268f23e9faSHans Rosenfeld uint32_t pt:2; 30278f23e9faSHans Rosenfeld uint32_t rsvd:30; 30288f23e9faSHans Rosenfeld #endif 30298f23e9faSHans Rosenfeld #define PORT_TYPE_GIGE 0 30308f23e9faSHans Rosenfeld #define PORT_TYPE_FC 1 30318f23e9faSHans Rosenfeld } request; 30328f23e9faSHans Rosenfeld 30338f23e9faSHans Rosenfeld 30348f23e9faSHans Rosenfeld struct 30358f23e9faSHans Rosenfeld { 30368f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 30378f23e9faSHans Rosenfeld uint8_t port3_name; 30388f23e9faSHans Rosenfeld uint8_t port2_name; 30398f23e9faSHans Rosenfeld uint8_t port1_name; 30408f23e9faSHans Rosenfeld uint8_t port0_name; 30418f23e9faSHans Rosenfeld #endif 30428f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 30438f23e9faSHans Rosenfeld uint8_t port0_name; 30448f23e9faSHans Rosenfeld uint8_t port1_name; 30458f23e9faSHans Rosenfeld uint8_t port2_name; 30468f23e9faSHans Rosenfeld uint8_t port3_name; 30478f23e9faSHans Rosenfeld #endif 30488f23e9faSHans Rosenfeld } response; 30498f23e9faSHans Rosenfeld 30508f23e9faSHans Rosenfeld } params; 30518f23e9faSHans Rosenfeld 30528f23e9faSHans Rosenfeld } IOCTL_COMMON_GET_PORT_NAME_V1; 30538f23e9faSHans Rosenfeld 30548f23e9faSHans Rosenfeld 305582527734SSukumar Swaminathan typedef struct 305682527734SSukumar Swaminathan { 305782527734SSukumar Swaminathan union 305882527734SSukumar Swaminathan { 305982527734SSukumar Swaminathan struct 306082527734SSukumar Swaminathan { 306182527734SSukumar Swaminathan uint32_t fat_operation; 306282527734SSukumar Swaminathan #define RETRIEVE_FAT 0 306382527734SSukumar Swaminathan #define QUERY_FAT 1 306482527734SSukumar Swaminathan #define CLEAR_FAT 2 306582527734SSukumar Swaminathan 306682527734SSukumar Swaminathan uint32_t read_log_offset; 306782527734SSukumar Swaminathan uint32_t read_log_length; 306882527734SSukumar Swaminathan uint32_t data_buffer_size; 306982527734SSukumar Swaminathan uint32_t data_buffer; 307082527734SSukumar Swaminathan } request; 307182527734SSukumar Swaminathan 307282527734SSukumar Swaminathan struct 307382527734SSukumar Swaminathan { 307482527734SSukumar Swaminathan uint32_t log_size; 307582527734SSukumar Swaminathan uint32_t read_log_length; 307682527734SSukumar Swaminathan uint32_t rsvd0; 307782527734SSukumar Swaminathan uint32_t rsvd1; 307882527734SSukumar Swaminathan uint32_t data_buffer; 307982527734SSukumar Swaminathan } response; 308082527734SSukumar Swaminathan 308182527734SSukumar Swaminathan } params; 308282527734SSukumar Swaminathan 308382527734SSukumar Swaminathan } IOCTL_COMMON_MANAGE_FAT; 308482527734SSukumar Swaminathan 308582527734SSukumar Swaminathan 30868f23e9faSHans Rosenfeld typedef struct 30878f23e9faSHans Rosenfeld { 30888f23e9faSHans Rosenfeld union 30898f23e9faSHans Rosenfeld { 30908f23e9faSHans Rosenfeld struct 30918f23e9faSHans Rosenfeld { 30928f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 30938f23e9faSHans Rosenfeld uint32_t EOF:1; /* word 4 */ 30948f23e9faSHans Rosenfeld uint32_t rsvd0:7; 30958f23e9faSHans Rosenfeld uint32_t desired_write_length:24; 30968f23e9faSHans Rosenfeld #endif 30978f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 30988f23e9faSHans Rosenfeld uint32_t desired_write_length:24; 30998f23e9faSHans Rosenfeld uint32_t rsvd0:7; 31008f23e9faSHans Rosenfeld uint32_t EOF:1; /* word 4 */ 31018f23e9faSHans Rosenfeld #endif 31028f23e9faSHans Rosenfeld uint32_t write_offset; /* word 5 */ 31038f23e9faSHans Rosenfeld char object_name[(4 * 26)]; /* word 6 - 31 */ 31048f23e9faSHans Rosenfeld uint32_t buffer_desc_count; /* word 32 */ 31058f23e9faSHans Rosenfeld 31068f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 31078f23e9faSHans Rosenfeld uint32_t rsvd:8; /* word 33 */ 31088f23e9faSHans Rosenfeld uint32_t buffer_length:24; 31098f23e9faSHans Rosenfeld #endif 31108f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 31118f23e9faSHans Rosenfeld uint32_t buffer_length:24; 31128f23e9faSHans Rosenfeld uint32_t rsvd:8; /* word 33 */ 31138f23e9faSHans Rosenfeld #endif 31148f23e9faSHans Rosenfeld uint32_t buffer_addrlo; /* word 34 */ 31158f23e9faSHans Rosenfeld uint32_t buffer_addrhi; /* word 35 */ 31168f23e9faSHans Rosenfeld } request; 31178f23e9faSHans Rosenfeld 31188f23e9faSHans Rosenfeld struct 31198f23e9faSHans Rosenfeld { 31208f23e9faSHans Rosenfeld uint32_t actual_write_length; 31218f23e9faSHans Rosenfeld 31228f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 31238f23e9faSHans Rosenfeld uint32_t rsvd:24; 31248f23e9faSHans Rosenfeld uint32_t change_status:8; 31258f23e9faSHans Rosenfeld #endif 31268f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 31278f23e9faSHans Rosenfeld uint32_t change_status:8; 31288f23e9faSHans Rosenfeld uint32_t rsvd:24; 31298f23e9faSHans Rosenfeld #endif 31308f23e9faSHans Rosenfeld #define CS_NO_RESET 0 31318f23e9faSHans Rosenfeld #define CS_REBOOT_RQD 1 31328f23e9faSHans Rosenfeld #define CS_FW_RESET_RQD 2 31338f23e9faSHans Rosenfeld #define CS_PROTO_RESET_RQD 3 31348f23e9faSHans Rosenfeld } response; 31358f23e9faSHans Rosenfeld 31368f23e9faSHans Rosenfeld } params; 31378f23e9faSHans Rosenfeld 31388f23e9faSHans Rosenfeld } IOCTL_COMMON_WRITE_OBJECT; 31398f23e9faSHans Rosenfeld 31408f23e9faSHans Rosenfeld 31418f23e9faSHans Rosenfeld typedef struct 31428f23e9faSHans Rosenfeld { 31438f23e9faSHans Rosenfeld union 31448f23e9faSHans Rosenfeld { 31458f23e9faSHans Rosenfeld struct 31468f23e9faSHans Rosenfeld { 31478f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 31488f23e9faSHans Rosenfeld uint32_t descriptor_offset:16; /* word 4 */ 31498f23e9faSHans Rosenfeld uint32_t descriptor_count:16; 31508f23e9faSHans Rosenfeld #endif 31518f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 31528f23e9faSHans Rosenfeld uint32_t descriptor_count:16; 31538f23e9faSHans Rosenfeld uint32_t descriptor_offset:16; /* word 4 */ 31548f23e9faSHans Rosenfeld #endif 31558f23e9faSHans Rosenfeld uint32_t reserved; /* word 5 */ 31568f23e9faSHans Rosenfeld char object_name[(4 * 26)]; /* word 6 - 31 */ 31578f23e9faSHans Rosenfeld uint32_t buffer_desc_count; /* word 32 */ 31588f23e9faSHans Rosenfeld 31598f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 31608f23e9faSHans Rosenfeld uint32_t rsvd:8; /* word 33 */ 31618f23e9faSHans Rosenfeld uint32_t buffer_length:24; 31628f23e9faSHans Rosenfeld #endif 31638f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 31648f23e9faSHans Rosenfeld uint32_t buffer_length:24; 31658f23e9faSHans Rosenfeld uint32_t rsvd:8; /* word 33 */ 31668f23e9faSHans Rosenfeld #endif 31678f23e9faSHans Rosenfeld uint32_t buffer_addrlo; /* word 34 */ 31688f23e9faSHans Rosenfeld uint32_t buffer_addrhi; /* word 35 */ 31698f23e9faSHans Rosenfeld } request; 31708f23e9faSHans Rosenfeld 31718f23e9faSHans Rosenfeld struct 31728f23e9faSHans Rosenfeld { 31738f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 31748f23e9faSHans Rosenfeld uint32_t reserved:16; 31758f23e9faSHans Rosenfeld uint32_t actual_descriptor_count:16; 31768f23e9faSHans Rosenfeld #endif 31778f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 31788f23e9faSHans Rosenfeld uint32_t actual_descriptor_count:16; 31798f23e9faSHans Rosenfeld uint32_t reserved:16; 31808f23e9faSHans Rosenfeld #endif 31818f23e9faSHans Rosenfeld } response; 31828f23e9faSHans Rosenfeld 31838f23e9faSHans Rosenfeld } params; 31848f23e9faSHans Rosenfeld 31858f23e9faSHans Rosenfeld } IOCTL_COMMON_READ_OBJECT_LIST; 31868f23e9faSHans Rosenfeld 31878f23e9faSHans Rosenfeld 31888f23e9faSHans Rosenfeld typedef struct 31898f23e9faSHans Rosenfeld { 31908f23e9faSHans Rosenfeld union 31918f23e9faSHans Rosenfeld { 31928f23e9faSHans Rosenfeld struct 31938f23e9faSHans Rosenfeld { 31948f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 31958f23e9faSHans Rosenfeld uint32_t reserved:16; /* word 4 */ 31968f23e9faSHans Rosenfeld uint32_t boot_instance:8; 31978f23e9faSHans Rosenfeld uint32_t boot_status:8; 31988f23e9faSHans Rosenfeld #endif 31998f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 32008f23e9faSHans Rosenfeld uint32_t boot_status:8; 32018f23e9faSHans Rosenfeld uint32_t boot_instance:8; 32028f23e9faSHans Rosenfeld uint32_t reserved:16; /* word 4 */ 32038f23e9faSHans Rosenfeld #endif 32048f23e9faSHans Rosenfeld } request; 32058f23e9faSHans Rosenfeld 32068f23e9faSHans Rosenfeld struct 32078f23e9faSHans Rosenfeld { 32088f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 32098f23e9faSHans Rosenfeld uint32_t reserved:16; /* word 4 */ 32108f23e9faSHans Rosenfeld uint32_t boot_instance:8; 32118f23e9faSHans Rosenfeld uint32_t boot_status:8; 32128f23e9faSHans Rosenfeld #endif 32138f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 32148f23e9faSHans Rosenfeld uint32_t boot_status:8; 32158f23e9faSHans Rosenfeld uint32_t boot_instance:8; 32168f23e9faSHans Rosenfeld uint32_t reserved:16; /* word 4 */ 32178f23e9faSHans Rosenfeld #endif 32188f23e9faSHans Rosenfeld } response; 32198f23e9faSHans Rosenfeld 32208f23e9faSHans Rosenfeld } params; 32218f23e9faSHans Rosenfeld 32228f23e9faSHans Rosenfeld } IOCTL_COMMON_BOOT_CFG; 32238f23e9faSHans Rosenfeld 32248f23e9faSHans Rosenfeld 322582527734SSukumar Swaminathan /* IOCTL_COMMON_QUERY_FIRMWARE_CONFIG */ 322682527734SSukumar Swaminathan typedef struct _BE_FW_CFG 322782527734SSukumar Swaminathan { 322882527734SSukumar Swaminathan uint32_t BEConfigNumber; 322982527734SSukumar Swaminathan uint32_t ASICRevision; 323082527734SSukumar Swaminathan uint32_t PhysicalPort; 323182527734SSukumar Swaminathan uint32_t FunctionMode; 323282527734SSukumar Swaminathan uint32_t ULPMode; 323382527734SSukumar Swaminathan 323482527734SSukumar Swaminathan } BE_FW_CFG; 323582527734SSukumar Swaminathan 323682527734SSukumar Swaminathan typedef struct _IOCTL_COMMON_QUERY_FIRMWARE_CONFIG 323782527734SSukumar Swaminathan { 323882527734SSukumar Swaminathan union 323982527734SSukumar Swaminathan { 324082527734SSukumar Swaminathan struct 324182527734SSukumar Swaminathan { 324282527734SSukumar Swaminathan uint32_t rsvd0; 324382527734SSukumar Swaminathan } request; 324482527734SSukumar Swaminathan 324582527734SSukumar Swaminathan BE_FW_CFG response; 324682527734SSukumar Swaminathan 324782527734SSukumar Swaminathan } params; 324882527734SSukumar Swaminathan 324982527734SSukumar Swaminathan } IOCTL_COMMON_QUERY_FIRMWARE_CONFIG; 325082527734SSukumar Swaminathan 3251088c6f3fSHans Rosenfeld /* IOCTL_LOWLEVEL_GPIO_RDWR */ 3252088c6f3fSHans Rosenfeld typedef struct _IOCTL_LOWLEVEL_GPIO_RDWR 3253088c6f3fSHans Rosenfeld { 3254088c6f3fSHans Rosenfeld union 3255088c6f3fSHans Rosenfeld { 3256088c6f3fSHans Rosenfeld struct 3257088c6f3fSHans Rosenfeld { 3258088c6f3fSHans Rosenfeld uint32_t GpioAction; 3259088c6f3fSHans Rosenfeld #define LOWLEVEL_GPIO_ACT_READ 0 3260088c6f3fSHans Rosenfeld #define LOWLEVEL_GPIO_ACT_WRITE 1 3261088c6f3fSHans Rosenfeld #define LOWLEVEL_GPIO_ACT_RDSENSE 2 3262088c6f3fSHans Rosenfeld #define LOWLEVEL_GPIO_ACT_STSENSE 3 3263088c6f3fSHans Rosenfeld 3264088c6f3fSHans Rosenfeld uint32_t LogicalPin; 3265088c6f3fSHans Rosenfeld uint32_t PinValue; 3266088c6f3fSHans Rosenfeld #define LOWLEVEL_GPIO_STSENSE_IN 0 3267088c6f3fSHans Rosenfeld #define LOWLEVEL_GPIO_STSENSE_OUT 1 3268088c6f3fSHans Rosenfeld 3269088c6f3fSHans Rosenfeld uint32_t OutputValue; 3270088c6f3fSHans Rosenfeld } request; 327182527734SSukumar Swaminathan 3272088c6f3fSHans Rosenfeld struct 3273088c6f3fSHans Rosenfeld { 3274088c6f3fSHans Rosenfeld uint32_t PinValue; 3275088c6f3fSHans Rosenfeld } response; 3276088c6f3fSHans Rosenfeld } params; 3277088c6f3fSHans Rosenfeld } IOCTL_LOWLEVEL_GPIO_RDWR; 327882527734SSukumar Swaminathan 327982527734SSukumar Swaminathan /* IOCTL_FCOE_READ_FCF_TABLE */ 328082527734SSukumar Swaminathan typedef struct 328182527734SSukumar Swaminathan { 328282527734SSukumar Swaminathan uint32_t max_recv_size; 328382527734SSukumar Swaminathan uint32_t fka_adv_period; 328482527734SSukumar Swaminathan uint32_t fip_priority; 328582527734SSukumar Swaminathan 328682527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 328782527734SSukumar Swaminathan uint8_t fcf_mac_address_hi[4]; 328882527734SSukumar Swaminathan 328982527734SSukumar Swaminathan uint8_t mac_address_provider; 329082527734SSukumar Swaminathan uint8_t fcf_available; 329182527734SSukumar Swaminathan uint8_t fcf_mac_address_low[2]; 329282527734SSukumar Swaminathan 329382527734SSukumar Swaminathan uint8_t fabric_name_identifier[8]; 329482527734SSukumar Swaminathan 32958f23e9faSHans Rosenfeld uint8_t fcf_sol:1; 32968f23e9faSHans Rosenfeld uint8_t rsvd0:5; 32978f23e9faSHans Rosenfeld uint8_t fcf_fc:1; 32988f23e9faSHans Rosenfeld uint8_t fcf_valid:1; 329982527734SSukumar Swaminathan uint8_t fc_map[3]; 330082527734SSukumar Swaminathan 330182527734SSukumar Swaminathan uint16_t fcf_state; 330282527734SSukumar Swaminathan uint16_t fcf_index; 330382527734SSukumar Swaminathan #endif 330482527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 330582527734SSukumar Swaminathan uint8_t fcf_mac_address_hi[4]; 330682527734SSukumar Swaminathan 330782527734SSukumar Swaminathan uint8_t fcf_mac_address_low[2]; 330882527734SSukumar Swaminathan uint8_t fcf_available; 330982527734SSukumar Swaminathan uint8_t mac_address_provider; 331082527734SSukumar Swaminathan 331182527734SSukumar Swaminathan uint8_t fabric_name_identifier[8]; 331282527734SSukumar Swaminathan 331382527734SSukumar Swaminathan uint8_t fc_map[3]; 33148f23e9faSHans Rosenfeld uint8_t fcf_valid:1; 33158f23e9faSHans Rosenfeld uint8_t fcf_fc:1; 33168f23e9faSHans Rosenfeld uint8_t rsvd0:5; 33178f23e9faSHans Rosenfeld uint8_t fcf_sol:1; 331882527734SSukumar Swaminathan 331982527734SSukumar Swaminathan uint16_t fcf_index; 332082527734SSukumar Swaminathan uint16_t fcf_state; 332182527734SSukumar Swaminathan #endif 332282527734SSukumar Swaminathan 332382527734SSukumar Swaminathan uint8_t vlan_bitmap[512]; 332482527734SSukumar Swaminathan uint8_t switch_name_identifier[8]; 332582527734SSukumar Swaminathan 332682527734SSukumar Swaminathan } FCF_RECORD_t; 332782527734SSukumar Swaminathan 332882527734SSukumar Swaminathan #define EMLXS_FCOE_MAX_RCV_SZ 0x800 332982527734SSukumar Swaminathan 333082527734SSukumar Swaminathan /* defines for mac_address_provider */ 333182527734SSukumar Swaminathan #define EMLXS_MAM_BOTH 0 /* Both SPMA and FPMA */ 333282527734SSukumar Swaminathan #define EMLXS_MAM_FPMA 1 /* Fabric Provided MAC Address */ 333382527734SSukumar Swaminathan #define EMLXS_MAM_SPMA 2 /* Server Provided MAC Address */ 333482527734SSukumar Swaminathan 333582527734SSukumar Swaminathan typedef struct 333682527734SSukumar Swaminathan { 333782527734SSukumar Swaminathan union 333882527734SSukumar Swaminathan { 333982527734SSukumar Swaminathan struct 334082527734SSukumar Swaminathan { 334182527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 334282527734SSukumar Swaminathan uint16_t rsvd0; 334382527734SSukumar Swaminathan uint16_t fcf_index; 334482527734SSukumar Swaminathan #endif 334582527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 334682527734SSukumar Swaminathan uint16_t fcf_index; 334782527734SSukumar Swaminathan uint16_t rsvd0; 334882527734SSukumar Swaminathan #endif 334982527734SSukumar Swaminathan 335082527734SSukumar Swaminathan } request; 335182527734SSukumar Swaminathan 335282527734SSukumar Swaminathan struct 335382527734SSukumar Swaminathan { 335482527734SSukumar Swaminathan uint32_t event_tag; 335582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 335682527734SSukumar Swaminathan uint16_t rsvd0; 335782527734SSukumar Swaminathan uint16_t next_valid_fcf_index; 335882527734SSukumar Swaminathan #endif 335982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 336082527734SSukumar Swaminathan uint16_t next_valid_fcf_index; 336182527734SSukumar Swaminathan uint16_t rsvd0; 336282527734SSukumar Swaminathan #endif 336382527734SSukumar Swaminathan FCF_RECORD_t fcf_entry[1]; 336482527734SSukumar Swaminathan 336582527734SSukumar Swaminathan } response; 336682527734SSukumar Swaminathan 336782527734SSukumar Swaminathan } params; 336882527734SSukumar Swaminathan 336982527734SSukumar Swaminathan } IOCTL_FCOE_READ_FCF_TABLE; 337082527734SSukumar Swaminathan 337182527734SSukumar Swaminathan 337282527734SSukumar Swaminathan /* IOCTL_FCOE_ADD_FCF_TABLE */ 337382527734SSukumar Swaminathan typedef struct 337482527734SSukumar Swaminathan { 337582527734SSukumar Swaminathan union 337682527734SSukumar Swaminathan { 337782527734SSukumar Swaminathan struct 337882527734SSukumar Swaminathan { 337982527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 338082527734SSukumar Swaminathan uint16_t rsvd0; 338182527734SSukumar Swaminathan uint16_t fcf_index; 338282527734SSukumar Swaminathan #endif 338382527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 338482527734SSukumar Swaminathan uint16_t fcf_index; 338582527734SSukumar Swaminathan uint16_t rsvd0; 338682527734SSukumar Swaminathan #endif 338782527734SSukumar Swaminathan FCF_RECORD_t fcf_entry; 338882527734SSukumar Swaminathan 338982527734SSukumar Swaminathan } request; 3390a9800bebSGarrett D'Amore } params; 3391a9800bebSGarrett D'Amore 3392a9800bebSGarrett D'Amore } IOCTL_FCOE_ADD_FCF_TABLE; 3393a9800bebSGarrett D'Amore 339482527734SSukumar Swaminathan 3395a9800bebSGarrett D'Amore /* IOCTL_FCOE_DELETE_FCF_TABLE */ 3396a9800bebSGarrett D'Amore typedef struct 3397a9800bebSGarrett D'Amore { 3398a9800bebSGarrett D'Amore union 3399a9800bebSGarrett D'Amore { 3400a9800bebSGarrett D'Amore struct 3401a9800bebSGarrett D'Amore { 3402a9800bebSGarrett D'Amore #ifdef EMLXS_BIG_ENDIAN 3403a9800bebSGarrett D'Amore uint16_t fcf_indexes[1]; 3404a9800bebSGarrett D'Amore uint16_t fcf_count; 3405a9800bebSGarrett D'Amore #endif 3406a9800bebSGarrett D'Amore #ifdef EMLXS_LITTLE_ENDIAN 3407a9800bebSGarrett D'Amore uint16_t fcf_count; 3408a9800bebSGarrett D'Amore uint16_t fcf_indexes[1]; 3409a9800bebSGarrett D'Amore #endif 3410a9800bebSGarrett D'Amore 3411a9800bebSGarrett D'Amore } request; 3412a9800bebSGarrett D'Amore } params; 3413a9800bebSGarrett D'Amore 3414a9800bebSGarrett D'Amore } IOCTL_FCOE_DELETE_FCF_TABLE; 3415a9800bebSGarrett D'Amore 3416a9800bebSGarrett D'Amore 3417a9800bebSGarrett D'Amore /* IOCTL_FCOE_REDISCOVER_FCF_TABLE */ 3418a9800bebSGarrett D'Amore typedef struct 3419a9800bebSGarrett D'Amore { 3420a9800bebSGarrett D'Amore union 3421a9800bebSGarrett D'Amore { 342282527734SSukumar Swaminathan struct 342382527734SSukumar Swaminathan { 342482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 342582527734SSukumar Swaminathan uint16_t rsvd0; 3426a9800bebSGarrett D'Amore uint16_t fcf_count; 342782527734SSukumar Swaminathan #endif 342882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 3429a9800bebSGarrett D'Amore uint16_t fcf_count; 343082527734SSukumar Swaminathan uint16_t rsvd0; 343182527734SSukumar Swaminathan #endif 3432a9800bebSGarrett D'Amore uint32_t rsvd1; 3433a9800bebSGarrett D'Amore uint16_t fcf_index[1]; 3434a9800bebSGarrett D'Amore 3435a9800bebSGarrett D'Amore } request; 343682527734SSukumar Swaminathan } params; 343782527734SSukumar Swaminathan 3438a9800bebSGarrett D'Amore } IOCTL_FCOE_REDISCOVER_FCF_TABLE; 3439a9800bebSGarrett D'Amore 344082527734SSukumar Swaminathan 344182527734SSukumar Swaminathan #define FCOE_FCF_MAC0 0x0E 344282527734SSukumar Swaminathan #define FCOE_FCF_MAC1 0xFC 344382527734SSukumar Swaminathan #define FCOE_FCF_MAC2 0x00 344482527734SSukumar Swaminathan #define FCOE_FCF_MAC3 0xFF 344582527734SSukumar Swaminathan #define FCOE_FCF_MAC4 0xFF 344682527734SSukumar Swaminathan #define FCOE_FCF_MAC5 0xFE 344782527734SSukumar Swaminathan 344882527734SSukumar Swaminathan #define FCOE_FCF_MAP0 0x0E 344982527734SSukumar Swaminathan #define FCOE_FCF_MAP1 0xFC 345082527734SSukumar Swaminathan #define FCOE_FCF_MAP2 0x00 345182527734SSukumar Swaminathan 345282527734SSukumar Swaminathan #define MGMT_STATUS_FCF_IN_USE 0x3a 345382527734SSukumar Swaminathan 345482527734SSukumar Swaminathan /* IOCTL_COMMON_NOP */ 345582527734SSukumar Swaminathan typedef struct _IOCTL_COMMON_NOP 345682527734SSukumar Swaminathan { 345782527734SSukumar Swaminathan union 345882527734SSukumar Swaminathan { 345982527734SSukumar Swaminathan struct 346082527734SSukumar Swaminathan { 346182527734SSukumar Swaminathan uint64_t context; 346282527734SSukumar Swaminathan } request; 346382527734SSukumar Swaminathan 346482527734SSukumar Swaminathan struct 346582527734SSukumar Swaminathan { 346682527734SSukumar Swaminathan uint64_t context; 346782527734SSukumar Swaminathan } response; 346882527734SSukumar Swaminathan 346982527734SSukumar Swaminathan } params; 347082527734SSukumar Swaminathan 347182527734SSukumar Swaminathan } IOCTL_COMMON_NOP; 347282527734SSukumar Swaminathan 347382527734SSukumar Swaminathan 347482527734SSukumar Swaminathan /* Context for EQ create */ 347582527734SSukumar Swaminathan typedef struct _EQ_CONTEXT 347682527734SSukumar Swaminathan { 347782527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 347882527734SSukumar Swaminathan uint32_t Size:1; 347982527734SSukumar Swaminathan uint32_t Rsvd2:1; 348082527734SSukumar Swaminathan uint32_t Valid:1; 3481*e2d1a434SCarsten Grzemba uint32_t AutoValid:1; 3482*e2d1a434SCarsten Grzemba uint32_t Rsvd1:28; 348382527734SSukumar Swaminathan 348482527734SSukumar Swaminathan uint32_t Armed:1; 34858f23e9faSHans Rosenfeld uint32_t Rsvd4:2; 348682527734SSukumar Swaminathan uint32_t Count:3; 34878f23e9faSHans Rosenfeld uint32_t Rsvd3:26; 348882527734SSukumar Swaminathan 34898f23e9faSHans Rosenfeld uint32_t Rsvd6:9; 349082527734SSukumar Swaminathan uint32_t DelayMult:10; 34918f23e9faSHans Rosenfeld uint32_t Rsvd5:13; 349282527734SSukumar Swaminathan #endif 349382527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 3494*e2d1a434SCarsten Grzemba uint32_t Rsvd1:28; 3495*e2d1a434SCarsten Grzemba uint32_t AutoValid:1; 349682527734SSukumar Swaminathan uint32_t Valid:1; 349782527734SSukumar Swaminathan uint32_t Rsvd2:1; 349882527734SSukumar Swaminathan uint32_t Size:1; 349982527734SSukumar Swaminathan 35008f23e9faSHans Rosenfeld uint32_t Rsvd3:26; 350182527734SSukumar Swaminathan uint32_t Count:3; 35028f23e9faSHans Rosenfeld uint32_t Rsvd4:2; 350382527734SSukumar Swaminathan uint32_t Armed:1; 350482527734SSukumar Swaminathan 35058f23e9faSHans Rosenfeld uint32_t Rsvd5:13; 350682527734SSukumar Swaminathan uint32_t DelayMult:10; 35078f23e9faSHans Rosenfeld uint32_t Rsvd6:9; 350882527734SSukumar Swaminathan #endif 350982527734SSukumar Swaminathan 35108f23e9faSHans Rosenfeld uint32_t Rsvd7; 35118f23e9faSHans Rosenfeld 35128f23e9faSHans Rosenfeld } EQ_CONTEXT; 351382527734SSukumar Swaminathan 351482527734SSukumar Swaminathan 351582527734SSukumar Swaminathan /* define for Count field */ 351682527734SSukumar Swaminathan #define EQ_ELEMENT_COUNT_1024 2 351782527734SSukumar Swaminathan #define EQ_ELEMENT_COUNT_2048 3 351882527734SSukumar Swaminathan #define EQ_ELEMENT_COUNT_4096 4 351982527734SSukumar Swaminathan 352082527734SSukumar Swaminathan /* define for Size field */ 352182527734SSukumar Swaminathan #define EQ_ELEMENT_SIZE_4 0 3522*e2d1a434SCarsten Grzemba #define EQ_ELEMENT_SIZE_16 1 352382527734SSukumar Swaminathan 352482527734SSukumar Swaminathan /* define for DelayMullt - used for interrupt coalescing */ 3525a9800bebSGarrett D'Amore #define EQ_DELAY_MULT 64 352682527734SSukumar Swaminathan 352782527734SSukumar Swaminathan /* Context for CQ create */ 352882527734SSukumar Swaminathan typedef struct _CQ_CONTEXT 352982527734SSukumar Swaminathan { 353082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 353182527734SSukumar Swaminathan uint32_t Eventable:1; 35328f23e9faSHans Rosenfeld uint32_t Rsvd3:1; 353382527734SSukumar Swaminathan uint32_t Valid:1; 353482527734SSukumar Swaminathan uint32_t Count:2; 35358f23e9faSHans Rosenfeld uint32_t Rsvd2:12; 353682527734SSukumar Swaminathan uint32_t NoDelay:1; 353782527734SSukumar Swaminathan uint32_t CoalesceWM:2; 35388f23e9faSHans Rosenfeld uint32_t Rsvd1:12; 353982527734SSukumar Swaminathan 354082527734SSukumar Swaminathan uint32_t Armed:1; 35418f23e9faSHans Rosenfeld uint32_t Rsvd5:1; 354282527734SSukumar Swaminathan uint32_t EQId:8; 35438f23e9faSHans Rosenfeld uint32_t Rsvd4:22; 354482527734SSukumar Swaminathan 35458f23e9faSHans Rosenfeld uint32_t Rsvd6; 354682527734SSukumar Swaminathan #endif 354782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 35488f23e9faSHans Rosenfeld uint32_t Rsvd1:12; 354982527734SSukumar Swaminathan uint32_t CoalesceWM:2; 355082527734SSukumar Swaminathan uint32_t NoDelay:1; 35518f23e9faSHans Rosenfeld uint32_t Rsvd2:12; 355282527734SSukumar Swaminathan uint32_t Count:2; 355382527734SSukumar Swaminathan uint32_t Valid:1; 35548f23e9faSHans Rosenfeld uint32_t Rsvd3:1; 355582527734SSukumar Swaminathan uint32_t Eventable:1; 355682527734SSukumar Swaminathan 35578f23e9faSHans Rosenfeld uint32_t Rsvd4:22; 355882527734SSukumar Swaminathan uint32_t EQId:8; 35598f23e9faSHans Rosenfeld uint32_t Rsvd5:1; 356082527734SSukumar Swaminathan uint32_t Armed:1; 356182527734SSukumar Swaminathan 35628f23e9faSHans Rosenfeld uint32_t Rsvd6; 356382527734SSukumar Swaminathan #endif 356482527734SSukumar Swaminathan 35658f23e9faSHans Rosenfeld uint32_t Rsvd7; 356682527734SSukumar Swaminathan 356782527734SSukumar Swaminathan } CQ_CONTEXT; 356882527734SSukumar Swaminathan 35698f23e9faSHans Rosenfeld typedef struct _CQ_CONTEXT_V2 35708f23e9faSHans Rosenfeld { 35718f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 35728f23e9faSHans Rosenfeld uint32_t Eventable:1; 35738f23e9faSHans Rosenfeld uint32_t Rsvd3:1; 35748f23e9faSHans Rosenfeld uint32_t Valid:1; 35758f23e9faSHans Rosenfeld uint32_t CqeCnt:2; 35768f23e9faSHans Rosenfeld uint32_t CqeSize:2; 35778f23e9faSHans Rosenfeld uint32_t Rsvd2:9; 35788f23e9faSHans Rosenfeld uint32_t AutoValid:1; 35798f23e9faSHans Rosenfeld uint32_t NoDelay:1; 35808f23e9faSHans Rosenfeld uint32_t CoalesceWM:2; 35818f23e9faSHans Rosenfeld uint32_t Rsvd1:12; 35828f23e9faSHans Rosenfeld 35838f23e9faSHans Rosenfeld uint32_t Armed:1; 35848f23e9faSHans Rosenfeld uint32_t Rsvd4:15; 35858f23e9faSHans Rosenfeld uint32_t EQId:16; 35868f23e9faSHans Rosenfeld 35878f23e9faSHans Rosenfeld uint32_t Rsvd5:16; 35888f23e9faSHans Rosenfeld uint32_t Count1:16; 35898f23e9faSHans Rosenfeld #endif 35908f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 35918f23e9faSHans Rosenfeld uint32_t Rsvd1:12; 35928f23e9faSHans Rosenfeld uint32_t CoalesceWM:2; 35938f23e9faSHans Rosenfeld uint32_t NoDelay:1; 35948f23e9faSHans Rosenfeld uint32_t AutoValid:1; 35958f23e9faSHans Rosenfeld uint32_t Rsvd2:9; 35968f23e9faSHans Rosenfeld uint32_t CqeSize:2; 35978f23e9faSHans Rosenfeld uint32_t CqeCnt:2; 35988f23e9faSHans Rosenfeld uint32_t Valid:1; 35998f23e9faSHans Rosenfeld uint32_t Rsvd3:1; 36008f23e9faSHans Rosenfeld uint32_t Eventable:1; 36018f23e9faSHans Rosenfeld 36028f23e9faSHans Rosenfeld uint32_t EQId:16; 36038f23e9faSHans Rosenfeld uint32_t Rsvd4:15; 36048f23e9faSHans Rosenfeld uint32_t Armed:1; 36058f23e9faSHans Rosenfeld 36068f23e9faSHans Rosenfeld uint32_t Count1:16; 36078f23e9faSHans Rosenfeld uint32_t Rsvd5:16; 36088f23e9faSHans Rosenfeld #endif 36098f23e9faSHans Rosenfeld 36108f23e9faSHans Rosenfeld uint32_t Rsvd7; 36118f23e9faSHans Rosenfeld 36128f23e9faSHans Rosenfeld } CQ_CONTEXT_V2; 36138f23e9faSHans Rosenfeld 36148f23e9faSHans Rosenfeld /* CqeSize */ 36158f23e9faSHans Rosenfeld #define CQE_SIZE_16_BYTES 0 36168f23e9faSHans Rosenfeld #define CQE_SIZE_32_BYTES 1 36178f23e9faSHans Rosenfeld 361882527734SSukumar Swaminathan /* define for Count field */ 361982527734SSukumar Swaminathan #define CQ_ELEMENT_COUNT_256 0 362082527734SSukumar Swaminathan #define CQ_ELEMENT_COUNT_512 1 362182527734SSukumar Swaminathan #define CQ_ELEMENT_COUNT_1024 2 36228f23e9faSHans Rosenfeld #define CQ_ELEMENT_COUNT_SPECIFIED 3 362382527734SSukumar Swaminathan 362482527734SSukumar Swaminathan /* Context for MQ create */ 362582527734SSukumar Swaminathan typedef struct _MQ_CONTEXT 362682527734SSukumar Swaminathan { 362782527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 362882527734SSukumar Swaminathan uint32_t CQId:10; 362982527734SSukumar Swaminathan uint32_t Rsvd2:2; 363082527734SSukumar Swaminathan uint32_t Size:4; 36318f23e9faSHans Rosenfeld uint32_t Rsvd1:16; 363282527734SSukumar Swaminathan 363382527734SSukumar Swaminathan uint32_t Valid:1; 36348f23e9faSHans Rosenfeld uint32_t Rsvd3:31; 36358f23e9faSHans Rosenfeld 36368f23e9faSHans Rosenfeld uint32_t Rsvd4:21; 36378f23e9faSHans Rosenfeld uint32_t ACQId:10; 36388f23e9faSHans Rosenfeld uint32_t ACQV:1; 363982527734SSukumar Swaminathan #endif 364082527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 36418f23e9faSHans Rosenfeld uint32_t Rsvd1:16; 364282527734SSukumar Swaminathan uint32_t Size:4; 364382527734SSukumar Swaminathan uint32_t Rsvd2:2; 364482527734SSukumar Swaminathan uint32_t CQId:10; 364582527734SSukumar Swaminathan 36468f23e9faSHans Rosenfeld uint32_t Rsvd3:31; 364782527734SSukumar Swaminathan uint32_t Valid:1; 36488f23e9faSHans Rosenfeld 36498f23e9faSHans Rosenfeld uint32_t ACQV:1; 36508f23e9faSHans Rosenfeld uint32_t ACQId:10; 36518f23e9faSHans Rosenfeld uint32_t Rsvd4:21; 365282527734SSukumar Swaminathan #endif 365382527734SSukumar Swaminathan 36548f23e9faSHans Rosenfeld uint32_t Rsvd5; 365582527734SSukumar Swaminathan 365682527734SSukumar Swaminathan } MQ_CONTEXT; 365782527734SSukumar Swaminathan 36588f23e9faSHans Rosenfeld 36598f23e9faSHans Rosenfeld typedef struct _MQ_CONTEXT_V1 36608f23e9faSHans Rosenfeld { 36618f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 36628f23e9faSHans Rosenfeld uint32_t Rsvd2:12; 36638f23e9faSHans Rosenfeld uint32_t Size:4; 36648f23e9faSHans Rosenfeld uint32_t ACQId:16; 36658f23e9faSHans Rosenfeld 36668f23e9faSHans Rosenfeld uint32_t Valid:1; 36678f23e9faSHans Rosenfeld uint32_t Rsvd3:31; 36688f23e9faSHans Rosenfeld 36698f23e9faSHans Rosenfeld uint32_t Rsvd4:31; 36708f23e9faSHans Rosenfeld uint32_t ACQV:1; 36718f23e9faSHans Rosenfeld #endif 36728f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 36738f23e9faSHans Rosenfeld uint32_t ACQId:16; 36748f23e9faSHans Rosenfeld uint32_t Size:4; 36758f23e9faSHans Rosenfeld uint32_t Rsvd2:12; 36768f23e9faSHans Rosenfeld 36778f23e9faSHans Rosenfeld uint32_t Rsvd3:31; 36788f23e9faSHans Rosenfeld uint32_t Valid:1; 36798f23e9faSHans Rosenfeld 36808f23e9faSHans Rosenfeld uint32_t ACQV:1; 36818f23e9faSHans Rosenfeld uint32_t Rsvd4:31; 36828f23e9faSHans Rosenfeld #endif 36838f23e9faSHans Rosenfeld 36848f23e9faSHans Rosenfeld uint32_t Rsvd5; 36858f23e9faSHans Rosenfeld 36868f23e9faSHans Rosenfeld } MQ_CONTEXT_V1; 36878f23e9faSHans Rosenfeld 36888f23e9faSHans Rosenfeld 368982527734SSukumar Swaminathan /* define for Size field */ 369082527734SSukumar Swaminathan #define MQ_ELEMENT_COUNT_16 0x05 369182527734SSukumar Swaminathan 369282527734SSukumar Swaminathan /* Context for RQ create */ 369382527734SSukumar Swaminathan typedef struct _RQ_CONTEXT 369482527734SSukumar Swaminathan { 369582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 36968f23e9faSHans Rosenfeld uint32_t Rsvd2:12; 36978f23e9faSHans Rosenfeld uint32_t RqeCnt:4; 369882527734SSukumar Swaminathan uint32_t Rsvd1:16; 369982527734SSukumar Swaminathan 370082527734SSukumar Swaminathan uint32_t Rsvd3; 370182527734SSukumar Swaminathan 37028f23e9faSHans Rosenfeld uint32_t CQId:16; 370382527734SSukumar Swaminathan uint32_t BufferSize:16; 370482527734SSukumar Swaminathan #endif 370582527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 370682527734SSukumar Swaminathan uint32_t Rsvd1:16; 37078f23e9faSHans Rosenfeld uint32_t RqeCnt:4; 37088f23e9faSHans Rosenfeld uint32_t Rsvd2:12; 370982527734SSukumar Swaminathan 371082527734SSukumar Swaminathan uint32_t Rsvd3; 371182527734SSukumar Swaminathan 371282527734SSukumar Swaminathan uint32_t BufferSize:16; 37138f23e9faSHans Rosenfeld uint32_t CQId:16; 371482527734SSukumar Swaminathan #endif 371582527734SSukumar Swaminathan 371682527734SSukumar Swaminathan uint32_t Rsvd5; 371782527734SSukumar Swaminathan 371882527734SSukumar Swaminathan } RQ_CONTEXT; 371982527734SSukumar Swaminathan 37208f23e9faSHans Rosenfeld typedef struct _RQ_CONTEXT_V1 37218f23e9faSHans Rosenfeld { 37228f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 37238f23e9faSHans Rosenfeld uint32_t RqeCnt:16; 37248f23e9faSHans Rosenfeld uint32_t Rsvd1:4; 37258f23e9faSHans Rosenfeld uint32_t RqeSize:4; 37268f23e9faSHans Rosenfeld uint32_t PageSize:8; 37278f23e9faSHans Rosenfeld 37288f23e9faSHans Rosenfeld uint32_t Rsvd2; 37298f23e9faSHans Rosenfeld 37308f23e9faSHans Rosenfeld uint32_t CQId:16; 37318f23e9faSHans Rosenfeld uint32_t Rsvd:16; 37328f23e9faSHans Rosenfeld #endif 37338f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 37348f23e9faSHans Rosenfeld uint32_t PageSize:8; 37358f23e9faSHans Rosenfeld uint32_t RqeSize:4; 37368f23e9faSHans Rosenfeld uint32_t Rsvd1:4; 37378f23e9faSHans Rosenfeld uint32_t RqeCnt:16; 37388f23e9faSHans Rosenfeld 37398f23e9faSHans Rosenfeld uint32_t Rsvd2; 37408f23e9faSHans Rosenfeld 37418f23e9faSHans Rosenfeld uint32_t Rsvd:16; 37428f23e9faSHans Rosenfeld uint32_t CQId:16; 37438f23e9faSHans Rosenfeld #endif 37448f23e9faSHans Rosenfeld 37458f23e9faSHans Rosenfeld uint32_t BufferSize; 37468f23e9faSHans Rosenfeld 37478f23e9faSHans Rosenfeld } RQ_CONTEXT_V1; 37488f23e9faSHans Rosenfeld 37498f23e9faSHans Rosenfeld /* RqeSize */ 37508f23e9faSHans Rosenfeld #define RQE_SIZE_8_BYTES 0x02 37518f23e9faSHans Rosenfeld #define RQE_SIZE_16_BYTES 0x03 37528f23e9faSHans Rosenfeld #define RQE_SIZE_32_BYTES 0x04 37538f23e9faSHans Rosenfeld #define RQE_SIZE_64_BYTES 0x05 37548f23e9faSHans Rosenfeld #define RQE_SIZE_128_BYTES 0x06 37558f23e9faSHans Rosenfeld 37568f23e9faSHans Rosenfeld /* RQ PageSize */ 37578f23e9faSHans Rosenfeld #define RQ_PAGE_SIZE_4K 0x01 37588f23e9faSHans Rosenfeld #define RQ_PAGE_SIZE_8K 0x02 37598f23e9faSHans Rosenfeld #define RQ_PAGE_SIZE_16K 0x04 37608f23e9faSHans Rosenfeld #define RQ_PAGE_SIZE_32K 0x08 37618f23e9faSHans Rosenfeld #define RQ_PAGE_SIZE_64K 0x10 37628f23e9faSHans Rosenfeld 376382527734SSukumar Swaminathan 376482527734SSukumar Swaminathan /* IOCTL_COMMON_EQ_CREATE */ 376582527734SSukumar Swaminathan typedef struct 376682527734SSukumar Swaminathan { 376782527734SSukumar Swaminathan union 376882527734SSukumar Swaminathan { 376982527734SSukumar Swaminathan struct 377082527734SSukumar Swaminathan { 377182527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 377282527734SSukumar Swaminathan uint16_t Rsvd1; 377382527734SSukumar Swaminathan uint16_t NumPages; 377482527734SSukumar Swaminathan #endif 377582527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 377682527734SSukumar Swaminathan uint16_t NumPages; 377782527734SSukumar Swaminathan uint16_t Rsvd1; 377882527734SSukumar Swaminathan #endif 377982527734SSukumar Swaminathan EQ_CONTEXT EQContext; 378082527734SSukumar Swaminathan BE_PHYS_ADDR Pages[8]; 378182527734SSukumar Swaminathan } request; 378282527734SSukumar Swaminathan 378382527734SSukumar Swaminathan struct 378482527734SSukumar Swaminathan { 378582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 37868f23e9faSHans Rosenfeld uint16_t MsiIndex; /* V1 only */ 378782527734SSukumar Swaminathan uint16_t EQId; 378882527734SSukumar Swaminathan #endif 378982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 379082527734SSukumar Swaminathan uint16_t EQId; 37918f23e9faSHans Rosenfeld uint16_t MsiIndex; /* V1 only */ 379282527734SSukumar Swaminathan #endif 379382527734SSukumar Swaminathan } response; 379482527734SSukumar Swaminathan } params; 379582527734SSukumar Swaminathan 379682527734SSukumar Swaminathan } IOCTL_COMMON_EQ_CREATE; 379782527734SSukumar Swaminathan 379882527734SSukumar Swaminathan 37998f23e9faSHans Rosenfeld typedef struct 38008f23e9faSHans Rosenfeld { 38018f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 38028f23e9faSHans Rosenfeld uint32_t Rsvd1:24; /* Word 0 */ 38038f23e9faSHans Rosenfeld uint32_t ProtocolType:8; 38048f23e9faSHans Rosenfeld 38058f23e9faSHans Rosenfeld uint32_t Rsvd3:3; /* Word 1 */ 38068f23e9faSHans Rosenfeld uint32_t SliHint2:5; 38078f23e9faSHans Rosenfeld uint32_t SliHint1:8; 38088f23e9faSHans Rosenfeld uint32_t IfType:4; 38098f23e9faSHans Rosenfeld uint32_t SliFamily:4; 38108f23e9faSHans Rosenfeld uint32_t Revision:4; 38118f23e9faSHans Rosenfeld uint32_t Rsvd2:3; 38128f23e9faSHans Rosenfeld uint32_t FT:1; 38138f23e9faSHans Rosenfeld 3814*e2d1a434SCarsten Grzemba uint32_t EqAV:1; /* Word 2 */ 3815*e2d1a434SCarsten Grzemba uint32_t EqRsvd3:3; 38168f23e9faSHans Rosenfeld uint32_t EqeCntMethod:4; 38178f23e9faSHans Rosenfeld uint32_t EqPageSize:8; 38188f23e9faSHans Rosenfeld uint32_t EqRsvd2:4; 38198f23e9faSHans Rosenfeld uint32_t EqeSize:4; 38208f23e9faSHans Rosenfeld uint32_t EqRsvd1:4; 38218f23e9faSHans Rosenfeld uint32_t EqPageCnt:4; 38228f23e9faSHans Rosenfeld 38238f23e9faSHans Rosenfeld uint32_t EqRsvd4:16; /* Word 3 */ 38248f23e9faSHans Rosenfeld uint32_t EqeCntMask:16; 38258f23e9faSHans Rosenfeld 3826*e2d1a434SCarsten Grzemba uint32_t CqAV:1; /* Word 4 */ 3827*e2d1a434SCarsten Grzemba uint32_t CqRsvd3:3; 38288f23e9faSHans Rosenfeld uint32_t CqeCntMethod:4; 38298f23e9faSHans Rosenfeld uint32_t CqPageSize:8; 38308f23e9faSHans Rosenfeld uint32_t CQV:2; 38318f23e9faSHans Rosenfeld uint32_t CqRsvd2:2; 38328f23e9faSHans Rosenfeld uint32_t CqeSize:4; 38338f23e9faSHans Rosenfeld uint32_t CqRsvd1:4; 38348f23e9faSHans Rosenfeld uint32_t CqPageCnt:4; 38358f23e9faSHans Rosenfeld 38368f23e9faSHans Rosenfeld uint32_t CqRsvd4:16; /* Word 5 */ 38378f23e9faSHans Rosenfeld uint32_t CqeCntMask:16; 38388f23e9faSHans Rosenfeld 38398f23e9faSHans Rosenfeld uint32_t MqRsvd2:4; /* Word 6 */ 38408f23e9faSHans Rosenfeld uint32_t MqeCntMethod:4; 38418f23e9faSHans Rosenfeld uint32_t MqPageSize:8; 38428f23e9faSHans Rosenfeld uint32_t MQV:2; 38438f23e9faSHans Rosenfeld uint32_t MqRsvd1:10; 38448f23e9faSHans Rosenfeld uint32_t MqPageCnt:4; 38458f23e9faSHans Rosenfeld 38468f23e9faSHans Rosenfeld uint32_t MqRsvd3:16; /* Word 7 */ 38478f23e9faSHans Rosenfeld uint32_t MqeCntMask:16; 38488f23e9faSHans Rosenfeld 38498f23e9faSHans Rosenfeld uint32_t WqRsvd3:4; /* Word 8 */ 38508f23e9faSHans Rosenfeld uint32_t WqeCntMethod:4; 38518f23e9faSHans Rosenfeld uint32_t WqPageSize:8; 38528f23e9faSHans Rosenfeld uint32_t WQV:2; 38538f23e9faSHans Rosenfeld uint32_t WqeRsvd2:2; 38548f23e9faSHans Rosenfeld uint32_t WqeSize:4; 38558f23e9faSHans Rosenfeld uint32_t WqRsvd1:4; 38568f23e9faSHans Rosenfeld uint32_t WqPageCnt:4; 38578f23e9faSHans Rosenfeld 38588f23e9faSHans Rosenfeld uint32_t WqRsvd4:16; /* Word 9 */ 38598f23e9faSHans Rosenfeld uint32_t WqeCntMask:16; 38608f23e9faSHans Rosenfeld 38618f23e9faSHans Rosenfeld uint32_t RqRsvd3:4; /* Word 10 */ 38628f23e9faSHans Rosenfeld uint32_t RqeCntMethod:4; 38638f23e9faSHans Rosenfeld uint32_t RqPageSize:8; 38648f23e9faSHans Rosenfeld uint32_t RQV:2; 38658f23e9faSHans Rosenfeld uint32_t RqeRsvd2:2; 38668f23e9faSHans Rosenfeld uint32_t RqeSize:4; 38678f23e9faSHans Rosenfeld uint32_t RqRsvd1:4; 38688f23e9faSHans Rosenfeld uint32_t RqPageCnt:4; 38698f23e9faSHans Rosenfeld 38708f23e9faSHans Rosenfeld uint32_t RqDbWin:4; /* Word 11 */ 38718f23e9faSHans Rosenfeld uint32_t RqRsvd4:12; 38728f23e9faSHans Rosenfeld uint32_t RqeCntMask:16; 38738f23e9faSHans Rosenfeld 38748f23e9faSHans Rosenfeld uint32_t Loopback:4; /* Word 12 */ 3875*e2d1a434SCarsten Grzemba uint32_t agxf :1; 3876*e2d1a434SCarsten Grzemba uint32_t lc :1; 3877*e2d1a434SCarsten Grzemba uint32_t oas :1; 3878*e2d1a434SCarsten Grzemba uint32_t :1; 3879*e2d1a434SCarsten Grzemba uint32_t tsmm :1; 3880*e2d1a434SCarsten Grzemba uint32_t timm :1; 3881*e2d1a434SCarsten Grzemba uint32_t sglc :1; 3882*e2d1a434SCarsten Grzemba uint32_t rxri :1; 3883*e2d1a434SCarsten Grzemba uint32_t ipr :1; 3884*e2d1a434SCarsten Grzemba uint32_t hlm :1; 3885*e2d1a434SCarsten Grzemba uint32_t rxc :1; 3886*e2d1a434SCarsten Grzemba uint32_t boundary_4ga:1; 38878f23e9faSHans Rosenfeld uint32_t PHWQ:1; 38888f23e9faSHans Rosenfeld uint32_t PHON:1; 38898f23e9faSHans Rosenfeld uint32_t PHOFF:1; 38908f23e9faSHans Rosenfeld uint32_t TRIR:1; 38918f23e9faSHans Rosenfeld uint32_t TRTY:1; 38928f23e9faSHans Rosenfeld uint32_t TCCA:1; 38938f23e9faSHans Rosenfeld uint32_t MWQE:1; 38948f23e9faSHans Rosenfeld uint32_t ASSI:1; 38958f23e9faSHans Rosenfeld uint32_t TERP:1; 38968f23e9faSHans Rosenfeld uint32_t TGT:1; 38978f23e9faSHans Rosenfeld uint32_t AREG:1; 38988f23e9faSHans Rosenfeld uint32_t FBRR:1; 38998f23e9faSHans Rosenfeld uint32_t SGLR:1; 39008f23e9faSHans Rosenfeld uint32_t HDRR:1; 39018f23e9faSHans Rosenfeld uint32_t EXT:1; 39028f23e9faSHans Rosenfeld uint32_t FCOE:1; 39038f23e9faSHans Rosenfeld 39048f23e9faSHans Rosenfeld uint32_t SgeLength; /* Word 13 */ 39058f23e9faSHans Rosenfeld 39068f23e9faSHans Rosenfeld uint32_t SglRsvd2:8; /* Word 14 */ 39078f23e9faSHans Rosenfeld uint32_t SglAlign:8; 39088f23e9faSHans Rosenfeld uint32_t SglPageSize:8; 39098f23e9faSHans Rosenfeld uint32_t SglRsvd1:4; 39108f23e9faSHans Rosenfeld uint32_t SglPageCnt:4; 39118f23e9faSHans Rosenfeld 39128f23e9faSHans Rosenfeld uint32_t Rsvd5:16; /* Word 15 */ 39138f23e9faSHans Rosenfeld uint32_t MinRqSize:16; 39148f23e9faSHans Rosenfeld 39158f23e9faSHans Rosenfeld uint32_t MaxRqSize; /* Word 16 */ 39168f23e9faSHans Rosenfeld 39178f23e9faSHans Rosenfeld uint32_t RPIMax:16; 39188f23e9faSHans Rosenfeld uint32_t XRIMax:16; /* Word 17 */ 39198f23e9faSHans Rosenfeld 39208f23e9faSHans Rosenfeld uint32_t VFIMax:16; 39218f23e9faSHans Rosenfeld uint32_t VPIMax:16; /* Word 18 */ 3922*e2d1a434SCarsten Grzemba 3923*e2d1a434SCarsten Grzemba uint32_t :11; 3924*e2d1a434SCarsten Grzemba uint32_t pbde :1; /* Word 19 */ 3925*e2d1a434SCarsten Grzemba uint32_t :6; 3926*e2d1a434SCarsten Grzemba uint32_t pvl:1; 3927*e2d1a434SCarsten Grzemba uint32_t nsler :1; 3928*e2d1a434SCarsten Grzemba uint32_t :1; 3929*e2d1a434SCarsten Grzemba uint32_t bv1s :1; 3930*e2d1a434SCarsten Grzemba uint32_t nosr :1; 3931*e2d1a434SCarsten Grzemba uint32_t eqdr :1; 3932*e2d1a434SCarsten Grzemba uint32_t :1; 3933*e2d1a434SCarsten Grzemba uint32_t xpsgl :1; 3934*e2d1a434SCarsten Grzemba uint32_t :1; 3935*e2d1a434SCarsten Grzemba uint32_t xibi :1; 3936*e2d1a434SCarsten Grzemba uint32_t nvme :1; 3937*e2d1a434SCarsten Grzemba uint32_t :1; 3938*e2d1a434SCarsten Grzemba uint32_t mds_diags :1; 3939*e2d1a434SCarsten Grzemba uint32_t ext_embed_cb :1; 3940*e2d1a434SCarsten Grzemba 3941*e2d1a434SCarsten Grzemba uint32_t frag_num_field_size:16; 3942*e2d1a434SCarsten Grzemba uint32_t frag_num_field_offset:16; 3943*e2d1a434SCarsten Grzemba uint32_t sgl_index_field_size:16; 3944*e2d1a434SCarsten Grzemba uint32_t sgl_index_field_offset:16; 39458f23e9faSHans Rosenfeld #endif 39468f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 39478f23e9faSHans Rosenfeld uint32_t ProtocolType:8; /* Word 0 */ 39488f23e9faSHans Rosenfeld uint32_t Rsvd1:24; 39498f23e9faSHans Rosenfeld 39508f23e9faSHans Rosenfeld uint32_t FT:1; /* Word 1 */ 39518f23e9faSHans Rosenfeld uint32_t Rsvd2:3; 39528f23e9faSHans Rosenfeld uint32_t Revision:4; 39538f23e9faSHans Rosenfeld uint32_t SliFamily:4; 39548f23e9faSHans Rosenfeld uint32_t IfType:4; 39558f23e9faSHans Rosenfeld uint32_t SliHint1:8; 39568f23e9faSHans Rosenfeld uint32_t SliHint2:5; 39578f23e9faSHans Rosenfeld uint32_t Rsvd3:3; 39588f23e9faSHans Rosenfeld 39598f23e9faSHans Rosenfeld uint32_t EqPageCnt:4; /* Word 2 */ 39608f23e9faSHans Rosenfeld uint32_t EqRsvd1:4; 39618f23e9faSHans Rosenfeld uint32_t EqeSize:4; 39628f23e9faSHans Rosenfeld uint32_t EqRsvd2:4; 39638f23e9faSHans Rosenfeld uint32_t EqPageSize:8; 39648f23e9faSHans Rosenfeld uint32_t EqeCntMethod:4; 3965*e2d1a434SCarsten Grzemba uint32_t EqRsvd3:3; 3966*e2d1a434SCarsten Grzemba uint32_t EqAV:1; /* auto valid */ 39678f23e9faSHans Rosenfeld 39688f23e9faSHans Rosenfeld uint32_t EqeCntMask:16; /* Word 3 */ 39698f23e9faSHans Rosenfeld uint32_t EqRsvd4:16; 39708f23e9faSHans Rosenfeld 39718f23e9faSHans Rosenfeld uint32_t CqPageCnt:4; /* Word 4 */ 39728f23e9faSHans Rosenfeld uint32_t CqRsvd1:4; 39738f23e9faSHans Rosenfeld uint32_t CqeSize:4; 39748f23e9faSHans Rosenfeld uint32_t CqRsvd2:2; 3975*e2d1a434SCarsten Grzemba uint32_t CQV:2; /* queue version */ 39768f23e9faSHans Rosenfeld uint32_t CqPageSize:8; 39778f23e9faSHans Rosenfeld uint32_t CqeCntMethod:4; 3978*e2d1a434SCarsten Grzemba uint32_t CqRsvd3:3; 3979*e2d1a434SCarsten Grzemba uint32_t CqAV:1; /* auto valid */ 39808f23e9faSHans Rosenfeld 39818f23e9faSHans Rosenfeld uint32_t CqeCntMask:16; /* Word 5 */ 39828f23e9faSHans Rosenfeld uint32_t CqRsvd4:16; 39838f23e9faSHans Rosenfeld 39848f23e9faSHans Rosenfeld uint32_t MqPageCnt:4; /* Word 6 */ 39858f23e9faSHans Rosenfeld uint32_t MqRsvd1:10; 3986*e2d1a434SCarsten Grzemba uint32_t MQV:2; /* queue version */ 39878f23e9faSHans Rosenfeld uint32_t MqPageSize:8; 39888f23e9faSHans Rosenfeld uint32_t MqeCntMethod:4; 39898f23e9faSHans Rosenfeld uint32_t MqRsvd2:4; 39908f23e9faSHans Rosenfeld 39918f23e9faSHans Rosenfeld uint32_t MqeCntMask:16; /* Word 7 */ 39928f23e9faSHans Rosenfeld uint32_t MqRsvd3:16; 39938f23e9faSHans Rosenfeld 39948f23e9faSHans Rosenfeld uint32_t WqPageCnt:4; /* Word 8 */ 39958f23e9faSHans Rosenfeld uint32_t WqRsvd1:4; 39968f23e9faSHans Rosenfeld uint32_t WqeSize:4; 39978f23e9faSHans Rosenfeld uint32_t WqeRsvd2:2; 39988f23e9faSHans Rosenfeld uint32_t WQV:2; 39998f23e9faSHans Rosenfeld uint32_t WqPageSize:8; 40008f23e9faSHans Rosenfeld uint32_t WqeCntMethod:4; 40018f23e9faSHans Rosenfeld uint32_t WqRsvd3:4; 40028f23e9faSHans Rosenfeld 40038f23e9faSHans Rosenfeld uint32_t WqeCntMask:16; /* Word 9 */ 40048f23e9faSHans Rosenfeld uint32_t WqRsvd4:16; 40058f23e9faSHans Rosenfeld 40068f23e9faSHans Rosenfeld uint32_t RqPageCnt:4; /* Word 10 */ 40078f23e9faSHans Rosenfeld uint32_t RqRsvd1:4; 40088f23e9faSHans Rosenfeld uint32_t RqeSize:4; 40098f23e9faSHans Rosenfeld uint32_t RqeRsvd2:2; 4010*e2d1a434SCarsten Grzemba uint32_t RQV:2; /* queue version */ 40118f23e9faSHans Rosenfeld uint32_t RqPageSize:8; 40128f23e9faSHans Rosenfeld uint32_t RqeCntMethod:4; 40138f23e9faSHans Rosenfeld uint32_t RqRsvd3:4; 40148f23e9faSHans Rosenfeld 40158f23e9faSHans Rosenfeld uint32_t RqeCntMask:16; /* Word 11 */ 40168f23e9faSHans Rosenfeld uint32_t RqRsvd4:12; 40178f23e9faSHans Rosenfeld uint32_t RqDbWin:4; 40188f23e9faSHans Rosenfeld 40198f23e9faSHans Rosenfeld uint32_t FCOE:1; /* Word 12 */ 40208f23e9faSHans Rosenfeld uint32_t EXT:1; 4021*e2d1a434SCarsten Grzemba uint32_t HDRR:1; /* hdr_template_req */ 4022*e2d1a434SCarsten Grzemba uint32_t SGLR:1; /* sgl_pre_reg_requi */ 40238f23e9faSHans Rosenfeld uint32_t FBRR:1; 4024*e2d1a434SCarsten Grzemba uint32_t AREG:1; /* auto_reg */ 40258f23e9faSHans Rosenfeld uint32_t TGT:1; 40268f23e9faSHans Rosenfeld uint32_t TERP:1; 40278f23e9faSHans Rosenfeld uint32_t ASSI:1; 40288f23e9faSHans Rosenfeld uint32_t MWQE:1; 40298f23e9faSHans Rosenfeld uint32_t TCCA:1; 40308f23e9faSHans Rosenfeld uint32_t TRTY:1; 40318f23e9faSHans Rosenfeld uint32_t TRIR:1; 40328f23e9faSHans Rosenfeld uint32_t PHOFF:1; 4033*e2d1a434SCarsten Grzemba uint32_t PHON:1; /* perf_hint */ 4034*e2d1a434SCarsten Grzemba uint32_t PHWQ:1; /* perf_wq_id_assoc */ 4035*e2d1a434SCarsten Grzemba 4036*e2d1a434SCarsten Grzemba uint32_t boundary_4ga:1; 4037*e2d1a434SCarsten Grzemba uint32_t rxc:1; 4038*e2d1a434SCarsten Grzemba uint32_t hlm:1; 4039*e2d1a434SCarsten Grzemba uint32_t ipr:1; 4040*e2d1a434SCarsten Grzemba uint32_t rxri:1; 4041*e2d1a434SCarsten Grzemba uint32_t sglc:1; /* skyhawk SGL chaining_capable */ 4042*e2d1a434SCarsten Grzemba uint32_t timm:1; /* t10_dif_inline_capable */ 4043*e2d1a434SCarsten Grzemba uint32_t tsmm:1; /* t10_dif_separate_capable */ 4044*e2d1a434SCarsten Grzemba uint32_t :1; 4045*e2d1a434SCarsten Grzemba uint32_t oas:1; /* OAS is supported */ 4046*e2d1a434SCarsten Grzemba uint32_t lc:1; 4047*e2d1a434SCarsten Grzemba uint32_t agxf:1; /* auto_xfer_rdy */ 4048*e2d1a434SCarsten Grzemba 40498f23e9faSHans Rosenfeld uint32_t Loopback:4; 40508f23e9faSHans Rosenfeld 40518f23e9faSHans Rosenfeld uint32_t SgeLength; /* Word 13 */ 40528f23e9faSHans Rosenfeld 40538f23e9faSHans Rosenfeld uint32_t SglPageCnt:4; /* Word 14 */ 40548f23e9faSHans Rosenfeld uint32_t SglRsvd1:4; 40558f23e9faSHans Rosenfeld uint32_t SglPageSize:8; 40568f23e9faSHans Rosenfeld uint32_t SglAlign:8; 40578f23e9faSHans Rosenfeld uint32_t SglRsvd2:8; 40588f23e9faSHans Rosenfeld 40598f23e9faSHans Rosenfeld uint32_t MinRqSize:16; /* Word 15 */ 40608f23e9faSHans Rosenfeld uint32_t Rsvd5:16; 40618f23e9faSHans Rosenfeld 40628f23e9faSHans Rosenfeld uint32_t MaxRqSize; /* Word 16 */ 40638f23e9faSHans Rosenfeld 40648f23e9faSHans Rosenfeld uint32_t XRIMax:16; /* Word 17 */ 40658f23e9faSHans Rosenfeld uint32_t RPIMax:16; 40668f23e9faSHans Rosenfeld 40678f23e9faSHans Rosenfeld uint32_t VPIMax:16; /* Word 18 */ 40688f23e9faSHans Rosenfeld uint32_t VFIMax:16; 40698f23e9faSHans Rosenfeld 4070*e2d1a434SCarsten Grzemba uint32_t ext_embed_cb:1; /* Word 19 */ 4071*e2d1a434SCarsten Grzemba uint32_t mds_diags:1; 4072*e2d1a434SCarsten Grzemba uint32_t :1; 4073*e2d1a434SCarsten Grzemba uint32_t nvme:1; 4074*e2d1a434SCarsten Grzemba uint32_t xibi:1; 4075*e2d1a434SCarsten Grzemba uint32_t :1; 4076*e2d1a434SCarsten Grzemba uint32_t xpsgl:1; 4077*e2d1a434SCarsten Grzemba uint32_t :1; 4078*e2d1a434SCarsten Grzemba uint32_t eqdr:1; 4079*e2d1a434SCarsten Grzemba uint32_t nosr:1; 4080*e2d1a434SCarsten Grzemba uint32_t bv1s:1; 4081*e2d1a434SCarsten Grzemba uint32_t :1; 4082*e2d1a434SCarsten Grzemba uint32_t nsler:1; 4083*e2d1a434SCarsten Grzemba uint32_t pvl:1; 4084*e2d1a434SCarsten Grzemba uint32_t :6; 4085*e2d1a434SCarsten Grzemba uint32_t pbde:1; 4086*e2d1a434SCarsten Grzemba uint32_t :11; 4087*e2d1a434SCarsten Grzemba 4088*e2d1a434SCarsten Grzemba uint32_t frag_num_field_offset:16, /* Word 20 */ 4089*e2d1a434SCarsten Grzemba frag_num_field_size:16; 4090*e2d1a434SCarsten Grzemba uint32_t sgl_index_field_offset:16, /* Word 21 */ 4091*e2d1a434SCarsten Grzemba sgl_index_field_size:16; 4092*e2d1a434SCarsten Grzemba #endif 4093*e2d1a434SCarsten Grzemba uint32_t chain_sge_initial_value_lo; /* Word 22 */ 4094*e2d1a434SCarsten Grzemba uint32_t chain_sge_initial_value_hi; /* Word 23 */ 4095*e2d1a434SCarsten Grzemba 4096*e2d1a434SCarsten Grzemba /* frag_field_offset, frag_field_size */ 4097*e2d1a434SCarsten Grzemba uint32_t word24; 4098*e2d1a434SCarsten Grzemba 4099*e2d1a434SCarsten Grzemba /* sgl_field_offset, sgl_field_size */ 4100*e2d1a434SCarsten Grzemba uint32_t word25; 4101*e2d1a434SCarsten Grzemba uint32_t word26; /* Chain SGE initial value LOW */ 4102*e2d1a434SCarsten Grzemba uint32_t word27; /* Chain SGE initial value HIGH */ 41038f23e9faSHans Rosenfeld } sli_params_t; 41048f23e9faSHans Rosenfeld 41058f23e9faSHans Rosenfeld /* SliFamily values */ 41068f23e9faSHans Rosenfeld #define SLI_FAMILY_BE2 0x0 41078f23e9faSHans Rosenfeld #define SLI_FAMILY_BE3 0x1 41088f23e9faSHans Rosenfeld #define SLI_FAMILY_LANCER_A 0xA 41098f23e9faSHans Rosenfeld #define SLI_FAMILY_LANCER_B 0xB 41108f23e9faSHans Rosenfeld 41118f23e9faSHans Rosenfeld 41128f23e9faSHans Rosenfeld 41138f23e9faSHans Rosenfeld /* IOCTL_COMMON_SLI4_PARAMS */ 41148f23e9faSHans Rosenfeld typedef struct 41158f23e9faSHans Rosenfeld { 41168f23e9faSHans Rosenfeld union 41178f23e9faSHans Rosenfeld { 41188f23e9faSHans Rosenfeld struct 41198f23e9faSHans Rosenfeld { 41208f23e9faSHans Rosenfeld uint32_t Rsvd1; 41218f23e9faSHans Rosenfeld } request; 41228f23e9faSHans Rosenfeld 41238f23e9faSHans Rosenfeld struct 41248f23e9faSHans Rosenfeld { 41258f23e9faSHans Rosenfeld sli_params_t param; 41268f23e9faSHans Rosenfeld } response; 41278f23e9faSHans Rosenfeld } params; 41288f23e9faSHans Rosenfeld 41298f23e9faSHans Rosenfeld } IOCTL_COMMON_SLI4_PARAMS; 41308f23e9faSHans Rosenfeld 41318f23e9faSHans Rosenfeld 41328f23e9faSHans Rosenfeld #define MAX_EXTENTS 16 /* 1 to 104 */ 41338f23e9faSHans Rosenfeld 41348f23e9faSHans Rosenfeld /* IOCTL_COMMON_EXTENTS */ 41358f23e9faSHans Rosenfeld typedef struct 41368f23e9faSHans Rosenfeld { 41378f23e9faSHans Rosenfeld union 41388f23e9faSHans Rosenfeld { 41398f23e9faSHans Rosenfeld struct 41408f23e9faSHans Rosenfeld { 41418f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 41428f23e9faSHans Rosenfeld uint16_t RscCnt; 41438f23e9faSHans Rosenfeld uint16_t RscType; 41448f23e9faSHans Rosenfeld #endif 41458f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 41468f23e9faSHans Rosenfeld uint16_t RscType; 41478f23e9faSHans Rosenfeld uint16_t RscCnt; 41488f23e9faSHans Rosenfeld #endif 41498f23e9faSHans Rosenfeld } request; 41508f23e9faSHans Rosenfeld 41518f23e9faSHans Rosenfeld struct 41528f23e9faSHans Rosenfeld { 41538f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 41548f23e9faSHans Rosenfeld uint16_t ExtentSize; 41558f23e9faSHans Rosenfeld uint16_t ExtentCnt; 41568f23e9faSHans Rosenfeld #endif 41578f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 41588f23e9faSHans Rosenfeld uint16_t ExtentCnt; 41598f23e9faSHans Rosenfeld uint16_t ExtentSize; 41608f23e9faSHans Rosenfeld #endif 41618f23e9faSHans Rosenfeld 41628f23e9faSHans Rosenfeld uint16_t RscId[MAX_EXTENTS]; 41638f23e9faSHans Rosenfeld 41648f23e9faSHans Rosenfeld } response; 41658f23e9faSHans Rosenfeld } params; 41668f23e9faSHans Rosenfeld 41678f23e9faSHans Rosenfeld } IOCTL_COMMON_EXTENTS; 41688f23e9faSHans Rosenfeld 41698f23e9faSHans Rosenfeld /* RscType */ 41708f23e9faSHans Rosenfeld #define RSC_TYPE_FCOE_VFI 0x20 41718f23e9faSHans Rosenfeld #define RSC_TYPE_FCOE_VPI 0x21 41728f23e9faSHans Rosenfeld #define RSC_TYPE_FCOE_RPI 0x22 41738f23e9faSHans Rosenfeld #define RSC_TYPE_FCOE_XRI 0x23 41748f23e9faSHans Rosenfeld 41758f23e9faSHans Rosenfeld 41768f23e9faSHans Rosenfeld 417782527734SSukumar Swaminathan /* IOCTL_COMMON_CQ_CREATE */ 417882527734SSukumar Swaminathan typedef struct 417982527734SSukumar Swaminathan { 418082527734SSukumar Swaminathan union 418182527734SSukumar Swaminathan { 418282527734SSukumar Swaminathan struct 418382527734SSukumar Swaminathan { 418482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 418582527734SSukumar Swaminathan uint16_t Rsvd1; 418682527734SSukumar Swaminathan uint16_t NumPages; 418782527734SSukumar Swaminathan #endif 418882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 418982527734SSukumar Swaminathan uint16_t NumPages; 419082527734SSukumar Swaminathan uint16_t Rsvd1; 419182527734SSukumar Swaminathan #endif 419282527734SSukumar Swaminathan CQ_CONTEXT CQContext; 419382527734SSukumar Swaminathan BE_PHYS_ADDR Pages[4]; 419482527734SSukumar Swaminathan } request; 419582527734SSukumar Swaminathan 419682527734SSukumar Swaminathan struct 419782527734SSukumar Swaminathan { 419882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 419982527734SSukumar Swaminathan uint16_t Rsvd1; 420082527734SSukumar Swaminathan uint16_t CQId; 420182527734SSukumar Swaminathan #endif 420282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 420382527734SSukumar Swaminathan uint16_t CQId; 420482527734SSukumar Swaminathan uint16_t Rsvd1; 420582527734SSukumar Swaminathan #endif 420682527734SSukumar Swaminathan } response; 420782527734SSukumar Swaminathan } params; 420882527734SSukumar Swaminathan 420982527734SSukumar Swaminathan } IOCTL_COMMON_CQ_CREATE; 421082527734SSukumar Swaminathan 421182527734SSukumar Swaminathan 42128f23e9faSHans Rosenfeld /* IOCTL_COMMON_CQ_CREATE_V2 */ 42138f23e9faSHans Rosenfeld typedef struct 42148f23e9faSHans Rosenfeld { 42158f23e9faSHans Rosenfeld union 42168f23e9faSHans Rosenfeld { 42178f23e9faSHans Rosenfeld struct 42188f23e9faSHans Rosenfeld { 42198f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 42208f23e9faSHans Rosenfeld uint8_t Rsvd1; 42218f23e9faSHans Rosenfeld uint8_t PageSize; 42228f23e9faSHans Rosenfeld uint16_t NumPages; 42238f23e9faSHans Rosenfeld #endif 42248f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 42258f23e9faSHans Rosenfeld uint16_t NumPages; 42268f23e9faSHans Rosenfeld uint8_t PageSize; 42278f23e9faSHans Rosenfeld uint8_t Rsvd1; 42288f23e9faSHans Rosenfeld #endif 42298f23e9faSHans Rosenfeld CQ_CONTEXT_V2 CQContext; 42308f23e9faSHans Rosenfeld BE_PHYS_ADDR Pages[8]; 42318f23e9faSHans Rosenfeld } request; 42328f23e9faSHans Rosenfeld 42338f23e9faSHans Rosenfeld struct 42348f23e9faSHans Rosenfeld { 42358f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 42368f23e9faSHans Rosenfeld uint16_t Rsvd1; 42378f23e9faSHans Rosenfeld uint16_t CQId; 42388f23e9faSHans Rosenfeld #endif 42398f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 42408f23e9faSHans Rosenfeld uint16_t CQId; 42418f23e9faSHans Rosenfeld uint16_t Rsvd1; 42428f23e9faSHans Rosenfeld #endif 42438f23e9faSHans Rosenfeld } response; 42448f23e9faSHans Rosenfeld } params; 42458f23e9faSHans Rosenfeld 42468f23e9faSHans Rosenfeld } IOCTL_COMMON_CQ_CREATE_V2; 42478f23e9faSHans Rosenfeld 42488f23e9faSHans Rosenfeld #define CQ_PAGE_SIZE_4K 0x01 42498f23e9faSHans Rosenfeld #define CQ_PAGE_SIZE_8K 0x02 42508f23e9faSHans Rosenfeld #define CQ_PAGE_SIZE_16K 0x04 42518f23e9faSHans Rosenfeld #define CQ_PAGE_SIZE_32K 0x08 42528f23e9faSHans Rosenfeld #define CQ_PAGE_SIZE_64K 0x10 42538f23e9faSHans Rosenfeld 42548f23e9faSHans Rosenfeld 42558f23e9faSHans Rosenfeld 425682527734SSukumar Swaminathan /* IOCTL_COMMON_MQ_CREATE */ 425782527734SSukumar Swaminathan typedef struct 425882527734SSukumar Swaminathan { 425982527734SSukumar Swaminathan union 426082527734SSukumar Swaminathan { 426182527734SSukumar Swaminathan struct 426282527734SSukumar Swaminathan { 426382527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 426482527734SSukumar Swaminathan uint16_t Rsvd1; 426582527734SSukumar Swaminathan uint16_t NumPages; 426682527734SSukumar Swaminathan #endif 426782527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 426882527734SSukumar Swaminathan uint16_t NumPages; 426982527734SSukumar Swaminathan uint16_t Rsvd1; 427082527734SSukumar Swaminathan #endif 427182527734SSukumar Swaminathan MQ_CONTEXT MQContext; 427282527734SSukumar Swaminathan BE_PHYS_ADDR Pages[8]; 427382527734SSukumar Swaminathan } request; 427482527734SSukumar Swaminathan 427582527734SSukumar Swaminathan struct 427682527734SSukumar Swaminathan { 427782527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 427882527734SSukumar Swaminathan uint16_t Rsvd1; 427982527734SSukumar Swaminathan uint16_t MQId; 428082527734SSukumar Swaminathan #endif 428182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 428282527734SSukumar Swaminathan uint16_t MQId; 428382527734SSukumar Swaminathan uint16_t Rsvd1; 428482527734SSukumar Swaminathan #endif 428582527734SSukumar Swaminathan } response; 428682527734SSukumar Swaminathan } params; 428782527734SSukumar Swaminathan 428882527734SSukumar Swaminathan } IOCTL_COMMON_MQ_CREATE; 428982527734SSukumar Swaminathan 429082527734SSukumar Swaminathan 42918f23e9faSHans Rosenfeld /* IOCTL_COMMON_MQ_CREATE_EXT */ 4292a9800bebSGarrett D'Amore typedef struct 4293a9800bebSGarrett D'Amore { 4294a9800bebSGarrett D'Amore union 4295a9800bebSGarrett D'Amore { 4296a9800bebSGarrett D'Amore struct 4297a9800bebSGarrett D'Amore { 4298a9800bebSGarrett D'Amore #ifdef EMLXS_BIG_ENDIAN 4299a9800bebSGarrett D'Amore uint16_t rsvd0; 4300a9800bebSGarrett D'Amore uint16_t num_pages; 4301a9800bebSGarrett D'Amore #endif 4302a9800bebSGarrett D'Amore #ifdef EMLXS_LITTLE_ENDIAN 4303a9800bebSGarrett D'Amore uint16_t num_pages; 4304a9800bebSGarrett D'Amore uint16_t rsvd0; 4305a9800bebSGarrett D'Amore #endif 4306a9800bebSGarrett D'Amore uint32_t async_event_bitmap; 4307a9800bebSGarrett D'Amore 43088f23e9faSHans Rosenfeld #define ASYNC_LINK_EVENT 0x00000002 43098f23e9faSHans Rosenfeld #define ASYNC_FCF_EVENT 0x00000004 43108f23e9faSHans Rosenfeld #define ASYNC_DCBX_EVENT 0x00000008 43118f23e9faSHans Rosenfeld #define ASYNC_iSCSI_EVENT 0x00000010 43128f23e9faSHans Rosenfeld #define ASYNC_GROUP5_EVENT 0x00000020 43138f23e9faSHans Rosenfeld #define ASYNC_FC_EVENT 0x00010000 43148f23e9faSHans Rosenfeld #define ASYNC_PORT_EVENT 0x00020000 43158f23e9faSHans Rosenfeld #define ASYNC_VF_EVENT 0x00040000 43168f23e9faSHans Rosenfeld #define ASYNC_MR_EVENT 0x00080000 4317a9800bebSGarrett D'Amore 4318a9800bebSGarrett D'Amore MQ_CONTEXT context; 4319a9800bebSGarrett D'Amore BE_PHYS_ADDR pages[8]; 4320a9800bebSGarrett D'Amore } request; 4321a9800bebSGarrett D'Amore 4322a9800bebSGarrett D'Amore struct 4323a9800bebSGarrett D'Amore { 4324a9800bebSGarrett D'Amore #ifdef EMLXS_BIG_ENDIAN 4325a9800bebSGarrett D'Amore uint16_t rsvd0; 43268f23e9faSHans Rosenfeld uint16_t MQId; 4327a9800bebSGarrett D'Amore #endif 4328a9800bebSGarrett D'Amore #ifdef EMLXS_LITTLE_ENDIAN 43298f23e9faSHans Rosenfeld uint16_t MQId; 4330a9800bebSGarrett D'Amore uint16_t rsvd0; 4331a9800bebSGarrett D'Amore #endif 4332a9800bebSGarrett D'Amore } response; 4333a9800bebSGarrett D'Amore 4334a9800bebSGarrett D'Amore } params; 4335a9800bebSGarrett D'Amore 43368f23e9faSHans Rosenfeld } IOCTL_COMMON_MQ_CREATE_EXT; 43378f23e9faSHans Rosenfeld 43388f23e9faSHans Rosenfeld 43398f23e9faSHans Rosenfeld /* IOCTL_COMMON_MQ_CREATE_EXT_V1 */ 43408f23e9faSHans Rosenfeld typedef struct 43418f23e9faSHans Rosenfeld { 43428f23e9faSHans Rosenfeld union 43438f23e9faSHans Rosenfeld { 43448f23e9faSHans Rosenfeld struct 43458f23e9faSHans Rosenfeld { 43468f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 43478f23e9faSHans Rosenfeld uint16_t CQId; 43488f23e9faSHans Rosenfeld uint16_t num_pages; 43498f23e9faSHans Rosenfeld #endif 43508f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 43518f23e9faSHans Rosenfeld uint16_t num_pages; 43528f23e9faSHans Rosenfeld uint16_t CQId; 43538f23e9faSHans Rosenfeld #endif 43548f23e9faSHans Rosenfeld uint32_t async_event_bitmap; 43558f23e9faSHans Rosenfeld 43568f23e9faSHans Rosenfeld MQ_CONTEXT_V1 context; 43578f23e9faSHans Rosenfeld BE_PHYS_ADDR pages[8]; 43588f23e9faSHans Rosenfeld } request; 43598f23e9faSHans Rosenfeld 43608f23e9faSHans Rosenfeld struct 43618f23e9faSHans Rosenfeld { 43628f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 43638f23e9faSHans Rosenfeld uint16_t rsvd0; 43648f23e9faSHans Rosenfeld uint16_t MQId; 43658f23e9faSHans Rosenfeld #endif 43668f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 43678f23e9faSHans Rosenfeld uint16_t MQId; 43688f23e9faSHans Rosenfeld uint16_t rsvd0; 43698f23e9faSHans Rosenfeld #endif 43708f23e9faSHans Rosenfeld } response; 43718f23e9faSHans Rosenfeld 43728f23e9faSHans Rosenfeld } params; 43738f23e9faSHans Rosenfeld 43748f23e9faSHans Rosenfeld } IOCTL_COMMON_MQ_CREATE_EXT_V1; 4375a9800bebSGarrett D'Amore 4376a9800bebSGarrett D'Amore 437782527734SSukumar Swaminathan /* IOCTL_FCOE_RQ_CREATE */ 437882527734SSukumar Swaminathan typedef struct 437982527734SSukumar Swaminathan { 438082527734SSukumar Swaminathan union 438182527734SSukumar Swaminathan { 438282527734SSukumar Swaminathan struct 438382527734SSukumar Swaminathan { 438482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 43858f23e9faSHans Rosenfeld uint16_t Rsvd0; 438682527734SSukumar Swaminathan uint16_t NumPages; 438782527734SSukumar Swaminathan #endif 438882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 438982527734SSukumar Swaminathan uint16_t NumPages; 43908f23e9faSHans Rosenfeld uint16_t Rsvd0; 439182527734SSukumar Swaminathan #endif 439282527734SSukumar Swaminathan RQ_CONTEXT RQContext; 439382527734SSukumar Swaminathan BE_PHYS_ADDR Pages[8]; 439482527734SSukumar Swaminathan } request; 439582527734SSukumar Swaminathan 439682527734SSukumar Swaminathan struct 439782527734SSukumar Swaminathan { 439882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 439982527734SSukumar Swaminathan uint16_t Rsvd1; 440082527734SSukumar Swaminathan uint16_t RQId; 440182527734SSukumar Swaminathan #endif 440282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 440382527734SSukumar Swaminathan uint16_t RQId; 440482527734SSukumar Swaminathan uint16_t Rsvd1; 440582527734SSukumar Swaminathan #endif 440682527734SSukumar Swaminathan } response; 440782527734SSukumar Swaminathan 440882527734SSukumar Swaminathan } params; 440982527734SSukumar Swaminathan 441082527734SSukumar Swaminathan } IOCTL_FCOE_RQ_CREATE; 441182527734SSukumar Swaminathan 441282527734SSukumar Swaminathan 44138f23e9faSHans Rosenfeld /* IOCTL_FCOE_RQ_CREATE_V1 */ 44148f23e9faSHans Rosenfeld typedef struct 44158f23e9faSHans Rosenfeld { 44168f23e9faSHans Rosenfeld union 44178f23e9faSHans Rosenfeld { 44188f23e9faSHans Rosenfeld struct 44198f23e9faSHans Rosenfeld { 44208f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 44218f23e9faSHans Rosenfeld uint32_t DNB:1; 44228f23e9faSHans Rosenfeld uint32_t DFD:1; 44238f23e9faSHans Rosenfeld uint32_t DIM:1; 44248f23e9faSHans Rosenfeld uint32_t Rsvd0:13; 44258f23e9faSHans Rosenfeld uint32_t NumPages:16; 44268f23e9faSHans Rosenfeld #endif 44278f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 44288f23e9faSHans Rosenfeld uint32_t NumPages:16; 44298f23e9faSHans Rosenfeld uint32_t Rsvd0:13; 44308f23e9faSHans Rosenfeld uint32_t DIM:1; 44318f23e9faSHans Rosenfeld uint32_t DFD:1; 44328f23e9faSHans Rosenfeld uint32_t DNB:1; 44338f23e9faSHans Rosenfeld #endif 44348f23e9faSHans Rosenfeld RQ_CONTEXT_V1 RQContext; 44358f23e9faSHans Rosenfeld BE_PHYS_ADDR Pages[8]; 44368f23e9faSHans Rosenfeld } request; 44378f23e9faSHans Rosenfeld 44388f23e9faSHans Rosenfeld struct 44398f23e9faSHans Rosenfeld { 44408f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 44418f23e9faSHans Rosenfeld uint16_t Rsvd1; 44428f23e9faSHans Rosenfeld uint16_t RQId; 44438f23e9faSHans Rosenfeld #endif 44448f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 44458f23e9faSHans Rosenfeld uint16_t RQId; 44468f23e9faSHans Rosenfeld uint16_t Rsvd1; 44478f23e9faSHans Rosenfeld #endif 44488f23e9faSHans Rosenfeld } response; 44498f23e9faSHans Rosenfeld 44508f23e9faSHans Rosenfeld } params; 44518f23e9faSHans Rosenfeld 44528f23e9faSHans Rosenfeld } IOCTL_FCOE_RQ_CREATE_V1; 44538f23e9faSHans Rosenfeld 44548f23e9faSHans Rosenfeld 445582527734SSukumar Swaminathan /* IOCTL_FCOE_WQ_CREATE */ 445682527734SSukumar Swaminathan typedef struct 445782527734SSukumar Swaminathan { 445882527734SSukumar Swaminathan union 445982527734SSukumar Swaminathan { 446082527734SSukumar Swaminathan struct 446182527734SSukumar Swaminathan { 446282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 446382527734SSukumar Swaminathan uint16_t CQId; 446482527734SSukumar Swaminathan uint16_t NumPages; 446582527734SSukumar Swaminathan #endif 446682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 446782527734SSukumar Swaminathan uint16_t NumPages; 446882527734SSukumar Swaminathan uint16_t CQId; 446982527734SSukumar Swaminathan #endif 447082527734SSukumar Swaminathan BE_PHYS_ADDR Pages[4]; 447182527734SSukumar Swaminathan } request; 447282527734SSukumar Swaminathan 447382527734SSukumar Swaminathan struct 447482527734SSukumar Swaminathan { 447582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 447682527734SSukumar Swaminathan uint16_t Rsvd0; 447782527734SSukumar Swaminathan uint16_t WQId; 447882527734SSukumar Swaminathan #endif 447982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 448082527734SSukumar Swaminathan uint16_t WQId; 448182527734SSukumar Swaminathan uint16_t Rsvd0; 448282527734SSukumar Swaminathan #endif 448382527734SSukumar Swaminathan } response; 448482527734SSukumar Swaminathan 448582527734SSukumar Swaminathan } params; 448682527734SSukumar Swaminathan 448782527734SSukumar Swaminathan } IOCTL_FCOE_WQ_CREATE; 448882527734SSukumar Swaminathan 448982527734SSukumar Swaminathan 44908f23e9faSHans Rosenfeld /* IOCTL_FCOE_WQ_CREATE_V1 */ 44918f23e9faSHans Rosenfeld typedef struct 44928f23e9faSHans Rosenfeld { 44938f23e9faSHans Rosenfeld union 44948f23e9faSHans Rosenfeld { 44958f23e9faSHans Rosenfeld struct 44968f23e9faSHans Rosenfeld { 44978f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 44988f23e9faSHans Rosenfeld uint16_t CQId; 44998f23e9faSHans Rosenfeld uint16_t NumPages; 45008f23e9faSHans Rosenfeld 45018f23e9faSHans Rosenfeld uint32_t WqeCnt:16; 45028f23e9faSHans Rosenfeld uint32_t Rsvd1:4; 45038f23e9faSHans Rosenfeld uint32_t WqeSize:4; 45048f23e9faSHans Rosenfeld uint32_t PageSize:8; 45058f23e9faSHans Rosenfeld #endif 45068f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 45078f23e9faSHans Rosenfeld uint16_t NumPages; 45088f23e9faSHans Rosenfeld uint16_t CQId; 45098f23e9faSHans Rosenfeld 45108f23e9faSHans Rosenfeld uint32_t PageSize:8; 45118f23e9faSHans Rosenfeld uint32_t WqeSize:4; 45128f23e9faSHans Rosenfeld uint32_t Rsvd1:4; 45138f23e9faSHans Rosenfeld uint32_t WqeCnt:16; 45148f23e9faSHans Rosenfeld #endif 45158f23e9faSHans Rosenfeld uint32_t Rsvd:2; 45168f23e9faSHans Rosenfeld BE_PHYS_ADDR Pages[4]; 45178f23e9faSHans Rosenfeld } request; 45188f23e9faSHans Rosenfeld 45198f23e9faSHans Rosenfeld struct 45208f23e9faSHans Rosenfeld { 45218f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 45228f23e9faSHans Rosenfeld uint16_t Rsvd0; 45238f23e9faSHans Rosenfeld uint16_t WQId; 45248f23e9faSHans Rosenfeld #endif 45258f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 45268f23e9faSHans Rosenfeld uint16_t WQId; 45278f23e9faSHans Rosenfeld uint16_t Rsvd0; 45288f23e9faSHans Rosenfeld #endif 45298f23e9faSHans Rosenfeld } response; 45308f23e9faSHans Rosenfeld 45318f23e9faSHans Rosenfeld } params; 45328f23e9faSHans Rosenfeld 45338f23e9faSHans Rosenfeld } IOCTL_FCOE_WQ_CREATE_V1; 45348f23e9faSHans Rosenfeld 45358f23e9faSHans Rosenfeld /* WqeSize */ 45368f23e9faSHans Rosenfeld #define WQE_SIZE_64_BYTES 0x05 45378f23e9faSHans Rosenfeld #define WQE_SIZE_128_BYTES 0x06 45388f23e9faSHans Rosenfeld 45398f23e9faSHans Rosenfeld /* PageSize */ 45408f23e9faSHans Rosenfeld #define WQ_PAGE_SIZE_4K 0x01 45418f23e9faSHans Rosenfeld #define WQ_PAGE_SIZE_8K 0x02 45428f23e9faSHans Rosenfeld #define WQ_PAGE_SIZE_16K 0x04 45438f23e9faSHans Rosenfeld #define WQ_PAGE_SIZE_32K 0x08 45448f23e9faSHans Rosenfeld #define WQ_PAGE_SIZE_64K 0x10 45458f23e9faSHans Rosenfeld 45468f23e9faSHans Rosenfeld 45478f23e9faSHans Rosenfeld 454882527734SSukumar Swaminathan /* IOCTL_FCOE_CFG_POST_SGL_PAGES */ 454982527734SSukumar Swaminathan typedef struct _FCOE_SGL_PAGES 455082527734SSukumar Swaminathan { 455182527734SSukumar Swaminathan BE_PHYS_ADDR sgl_page0; /* 1st page per XRI */ 455282527734SSukumar Swaminathan BE_PHYS_ADDR sgl_page1; /* 2nd page per XRI */ 455382527734SSukumar Swaminathan 455482527734SSukumar Swaminathan } FCOE_SGL_PAGES; 455582527734SSukumar Swaminathan 455682527734SSukumar Swaminathan typedef struct 455782527734SSukumar Swaminathan { 455882527734SSukumar Swaminathan union 455982527734SSukumar Swaminathan { 456082527734SSukumar Swaminathan struct 456182527734SSukumar Swaminathan { 456282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 456382527734SSukumar Swaminathan uint16_t xri_count; 456482527734SSukumar Swaminathan uint16_t xri_start; 456582527734SSukumar Swaminathan #endif 456682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 456782527734SSukumar Swaminathan uint16_t xri_start; 456882527734SSukumar Swaminathan uint16_t xri_count; 456982527734SSukumar Swaminathan #endif 457082527734SSukumar Swaminathan FCOE_SGL_PAGES pages[1]; 457182527734SSukumar Swaminathan } request; 457282527734SSukumar Swaminathan 457382527734SSukumar Swaminathan struct 457482527734SSukumar Swaminathan { 457582527734SSukumar Swaminathan uint32_t rsvd0; 457682527734SSukumar Swaminathan } response; 457782527734SSukumar Swaminathan 457882527734SSukumar Swaminathan } params; 457982527734SSukumar Swaminathan 458082527734SSukumar Swaminathan uint32_t rsvd0[2]; 458182527734SSukumar Swaminathan 458282527734SSukumar Swaminathan } IOCTL_FCOE_CFG_POST_SGL_PAGES; 458382527734SSukumar Swaminathan 458482527734SSukumar Swaminathan 458582527734SSukumar Swaminathan /* IOCTL_FCOE_POST_HDR_TEMPLATES */ 458682527734SSukumar Swaminathan typedef struct _IOCTL_FCOE_POST_HDR_TEMPLATES 458782527734SSukumar Swaminathan { 458882527734SSukumar Swaminathan union 458982527734SSukumar Swaminathan { 459082527734SSukumar Swaminathan struct 459182527734SSukumar Swaminathan { 459282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 459382527734SSukumar Swaminathan uint16_t num_pages; 45948f23e9faSHans Rosenfeld uint16_t rpi_offset; 459582527734SSukumar Swaminathan #endif 459682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 45978f23e9faSHans Rosenfeld uint16_t rpi_offset; 459882527734SSukumar Swaminathan uint16_t num_pages; 459982527734SSukumar Swaminathan #endif 460082527734SSukumar Swaminathan BE_PHYS_ADDR pages[32]; 460182527734SSukumar Swaminathan 460282527734SSukumar Swaminathan }request; 460382527734SSukumar Swaminathan 460482527734SSukumar Swaminathan }params; 460582527734SSukumar Swaminathan 460682527734SSukumar Swaminathan } IOCTL_FCOE_POST_HDR_TEMPLATES; 460782527734SSukumar Swaminathan 460882527734SSukumar Swaminathan 460982527734SSukumar Swaminathan 461082527734SSukumar Swaminathan #define EMLXS_IOCTL_DCBX_MODE_CEE 0 /* Mapped to FIP mode */ 461182527734SSukumar Swaminathan #define EMLXS_IOCTL_DCBX_MODE_CIN 1 /* Mapped to nonFIP mode */ 461282527734SSukumar Swaminathan 461382527734SSukumar Swaminathan /* IOCTL_DCBX_GET_DCBX_MODE */ 461482527734SSukumar Swaminathan typedef struct _IOCTL_DCBX_GET_DCBX_MODE 461582527734SSukumar Swaminathan { 461682527734SSukumar Swaminathan union 461782527734SSukumar Swaminathan { 461882527734SSukumar Swaminathan struct 461982527734SSukumar Swaminathan { 462082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 462182527734SSukumar Swaminathan uint8_t rsvd0[3]; 462282527734SSukumar Swaminathan uint8_t port_num; 462382527734SSukumar Swaminathan #endif 462482527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 462582527734SSukumar Swaminathan uint8_t port_num; 462682527734SSukumar Swaminathan uint8_t rsvd0[3]; 462782527734SSukumar Swaminathan #endif 462882527734SSukumar Swaminathan } request; 462982527734SSukumar Swaminathan 463082527734SSukumar Swaminathan struct 463182527734SSukumar Swaminathan { 463282527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 463382527734SSukumar Swaminathan uint8_t rsvd1[3]; 463482527734SSukumar Swaminathan uint8_t dcbx_mode; 463582527734SSukumar Swaminathan #endif 463682527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 463782527734SSukumar Swaminathan uint8_t dcbx_mode; 463882527734SSukumar Swaminathan uint8_t rsvd1[3]; 463982527734SSukumar Swaminathan #endif 464082527734SSukumar Swaminathan } response; 464182527734SSukumar Swaminathan 464282527734SSukumar Swaminathan } params; 464382527734SSukumar Swaminathan 464482527734SSukumar Swaminathan } IOCTL_DCBX_GET_DCBX_MODE; 464582527734SSukumar Swaminathan 464682527734SSukumar Swaminathan 464782527734SSukumar Swaminathan /* IOCTL_DCBX_SET_DCBX_MODE */ 464882527734SSukumar Swaminathan typedef struct _IOCTL_DCBX_SET_DCBX_MODE 464982527734SSukumar Swaminathan { 465082527734SSukumar Swaminathan union 465182527734SSukumar Swaminathan { 465282527734SSukumar Swaminathan struct 465382527734SSukumar Swaminathan { 465482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 465582527734SSukumar Swaminathan uint8_t rsvd0[2]; 465682527734SSukumar Swaminathan uint8_t dcbx_mode; 465782527734SSukumar Swaminathan uint8_t port_num; 465882527734SSukumar Swaminathan #endif 465982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 466082527734SSukumar Swaminathan uint8_t port_num; 466182527734SSukumar Swaminathan uint8_t dcbx_mode; 466282527734SSukumar Swaminathan uint8_t rsvd0[2]; 466382527734SSukumar Swaminathan #endif 466482527734SSukumar Swaminathan } request; 466582527734SSukumar Swaminathan 466682527734SSukumar Swaminathan struct 466782527734SSukumar Swaminathan { 466882527734SSukumar Swaminathan uint32_t rsvd1; 466982527734SSukumar Swaminathan } response; 467082527734SSukumar Swaminathan 467182527734SSukumar Swaminathan } params; 467282527734SSukumar Swaminathan 467382527734SSukumar Swaminathan } IOCTL_DCBX_SET_DCBX_MODE; 467482527734SSukumar Swaminathan 467582527734SSukumar Swaminathan 467682527734SSukumar Swaminathan /* IOCTL_COMMON_GET_CNTL_ATTRIB */ 467782527734SSukumar Swaminathan typedef struct 467882527734SSukumar Swaminathan { 467982527734SSukumar Swaminathan char flashrom_version_string[32]; 468082527734SSukumar Swaminathan char manufacturer_name[32]; 468182527734SSukumar Swaminathan char rsvd0[28]; 468282527734SSukumar Swaminathan uint32_t default_extended_timeout; 468382527734SSukumar Swaminathan char controller_model_number[32]; 468482527734SSukumar Swaminathan char controller_description[64]; 468582527734SSukumar Swaminathan char controller_serial_number[32]; 468682527734SSukumar Swaminathan char ip_version_string[32]; 468782527734SSukumar Swaminathan char firmware_version_string[32]; 468882527734SSukumar Swaminathan char bios_version_string[32]; 468982527734SSukumar Swaminathan char redboot_version_string[32]; 469082527734SSukumar Swaminathan char driver_version_string[32]; 469182527734SSukumar Swaminathan char fw_on_flash_version_string[32]; 469282527734SSukumar Swaminathan uint32_t functionalities_supported; 469382527734SSukumar Swaminathan uint16_t max_cdblength; 469482527734SSukumar Swaminathan uint8_t asic_revision; 469582527734SSukumar Swaminathan uint8_t generational_guid[16]; 469682527734SSukumar Swaminathan uint8_t hba_port_count; 469782527734SSukumar Swaminathan uint16_t default_link_down_timeout; 469882527734SSukumar Swaminathan uint8_t iscsi_ver_min_max; 469982527734SSukumar Swaminathan uint8_t multifunction_device; 470082527734SSukumar Swaminathan uint8_t cache_valid; 470182527734SSukumar Swaminathan uint8_t hba_status; 470282527734SSukumar Swaminathan uint8_t max_domains_supported; 470382527734SSukumar Swaminathan uint8_t phy_port; 470482527734SSukumar Swaminathan uint32_t firmware_post_status; 470582527734SSukumar Swaminathan uint32_t hba_mtu[2]; 470682527734SSukumar Swaminathan 470782527734SSukumar Swaminathan } MGMT_HBA_ATTRIB; 470882527734SSukumar Swaminathan 470982527734SSukumar Swaminathan typedef struct 471082527734SSukumar Swaminathan { 471182527734SSukumar Swaminathan MGMT_HBA_ATTRIB hba_attribs; 471282527734SSukumar Swaminathan uint16_t pci_vendor_id; 471382527734SSukumar Swaminathan uint16_t pci_device_id; 471482527734SSukumar Swaminathan uint16_t pci_sub_vendor_id; 471582527734SSukumar Swaminathan uint16_t pci_sub_system_id; 471682527734SSukumar Swaminathan uint8_t pci_bus_number; 471782527734SSukumar Swaminathan uint8_t pci_device_number; 471882527734SSukumar Swaminathan uint8_t pci_function_number; 471982527734SSukumar Swaminathan uint8_t interface_type; 472082527734SSukumar Swaminathan uint64_t unique_identifier; 472182527734SSukumar Swaminathan 472282527734SSukumar Swaminathan } MGMT_CONTROLLER_ATTRIB; 472382527734SSukumar Swaminathan 472482527734SSukumar Swaminathan typedef struct 472582527734SSukumar Swaminathan { 472682527734SSukumar Swaminathan union 472782527734SSukumar Swaminathan { 472882527734SSukumar Swaminathan struct 472982527734SSukumar Swaminathan { 473082527734SSukumar Swaminathan uint32_t rsvd0; 473182527734SSukumar Swaminathan } request; 473282527734SSukumar Swaminathan 473382527734SSukumar Swaminathan struct 473482527734SSukumar Swaminathan { 473582527734SSukumar Swaminathan MGMT_CONTROLLER_ATTRIB cntl_attributes_info; 473682527734SSukumar Swaminathan } response; 473782527734SSukumar Swaminathan 473882527734SSukumar Swaminathan } params; 473982527734SSukumar Swaminathan 474082527734SSukumar Swaminathan } IOCTL_COMMON_GET_CNTL_ATTRIB; 474182527734SSukumar Swaminathan 474282527734SSukumar Swaminathan 474382527734SSukumar Swaminathan typedef union 474482527734SSukumar Swaminathan { 474582527734SSukumar Swaminathan IOCTL_COMMON_NOP NOPVar; 474682527734SSukumar Swaminathan IOCTL_FCOE_WQ_CREATE WQCreateVar; 47478f23e9faSHans Rosenfeld IOCTL_FCOE_WQ_CREATE_V1 WQCreateVar1; 47488f23e9faSHans Rosenfeld IOCTL_FCOE_RQ_CREATE RQCreateVar; 47498f23e9faSHans Rosenfeld IOCTL_FCOE_RQ_CREATE_V1 RQCreateVar1; 475082527734SSukumar Swaminathan IOCTL_COMMON_EQ_CREATE EQCreateVar; 475182527734SSukumar Swaminathan IOCTL_COMMON_CQ_CREATE CQCreateVar; 47528f23e9faSHans Rosenfeld IOCTL_COMMON_CQ_CREATE_V2 CQCreateVar2; 475382527734SSukumar Swaminathan IOCTL_COMMON_MQ_CREATE MQCreateVar; 47548f23e9faSHans Rosenfeld IOCTL_COMMON_MQ_CREATE_EXT MQCreateExtVar; 47558f23e9faSHans Rosenfeld IOCTL_COMMON_MQ_CREATE_EXT_V1 MQCreateExtVar1; 475682527734SSukumar Swaminathan IOCTL_FCOE_CFG_POST_SGL_PAGES PostSGLVar; 475782527734SSukumar Swaminathan IOCTL_COMMON_GET_CNTL_ATTRIB GetCntlAttributesVar; 475882527734SSukumar Swaminathan IOCTL_FCOE_READ_FCF_TABLE ReadFCFTableVar; 475982527734SSukumar Swaminathan IOCTL_FCOE_ADD_FCF_TABLE AddFCFTableVar; 4760a9800bebSGarrett D'Amore IOCTL_FCOE_REDISCOVER_FCF_TABLE RediscoverFCFTableVar; 476182527734SSukumar Swaminathan IOCTL_COMMON_FLASHROM FlashRomVar; 476282527734SSukumar Swaminathan IOCTL_COMMON_MANAGE_FAT FATVar; 476382527734SSukumar Swaminathan IOCTL_DCBX_GET_DCBX_MODE GetDCBX; 476482527734SSukumar Swaminathan IOCTL_DCBX_SET_DCBX_MODE SetDCBX; 47658f23e9faSHans Rosenfeld IOCTL_COMMON_SLI4_PARAMS Sli4ParamVar; 47668f23e9faSHans Rosenfeld IOCTL_COMMON_EXTENTS ExtentsVar; 47678f23e9faSHans Rosenfeld IOCTL_COMMON_GET_PHY_DETAILS PHYDetailsVar; 47688f23e9faSHans Rosenfeld IOCTL_COMMON_GET_PORT_NAME PortNameVar; 47698f23e9faSHans Rosenfeld IOCTL_COMMON_GET_PORT_NAME_V1 PortNameVar1; 47708f23e9faSHans Rosenfeld IOCTL_COMMON_WRITE_OBJECT WriteObjVar; 47718f23e9faSHans Rosenfeld IOCTL_COMMON_BOOT_CFG BootCfgVar; 477282527734SSukumar Swaminathan 477382527734SSukumar Swaminathan } IOCTL_VARIANTS; 477482527734SSukumar Swaminathan 477582527734SSukumar Swaminathan /* Structure for MB Command SLI_CONFIG(0x9b) */ 477682527734SSukumar Swaminathan /* Good for SLI4 only */ 477782527734SSukumar Swaminathan 477882527734SSukumar Swaminathan typedef struct 477982527734SSukumar Swaminathan { 478082527734SSukumar Swaminathan be_req_hdr_t be; 478182527734SSukumar Swaminathan BE_PHYS_ADDR payload; 478282527734SSukumar Swaminathan } SLI_CONFIG_VAR; 478382527734SSukumar Swaminathan 478482527734SSukumar Swaminathan #define IOCTL_HEADER_SZ (4 * sizeof (uint32_t)) 478582527734SSukumar Swaminathan 478682527734SSukumar Swaminathan 478782527734SSukumar Swaminathan typedef union 478882527734SSukumar Swaminathan { 478982527734SSukumar Swaminathan uint32_t varWords[63]; 479082527734SSukumar Swaminathan READ_NV_VAR varRDnvp; /* cmd = x02 (READ_NVPARMS) */ 479182527734SSukumar Swaminathan INIT_LINK_VAR varInitLnk; /* cmd = x05 (INIT_LINK) */ 479282527734SSukumar Swaminathan CONFIG_LINK varCfgLnk; /* cmd = x07 (CONFIG_LINK) */ 479382527734SSukumar Swaminathan READ_REV4_VAR varRdRev4; /* cmd = x11 (READ_REV) */ 479482527734SSukumar Swaminathan READ_LNK_VAR varRdLnk; /* cmd = x12 (READ_LNK_STAT) */ 479582527734SSukumar Swaminathan DUMP4_VAR varDmp4; /* cmd = x17 (DUMP) */ 47968f23e9faSHans Rosenfeld UPDATE_CFG_VAR varUpdateCfg; /* cmd = x1b (update Cfg) */ 47978f23e9faSHans Rosenfeld BIU_DIAG_VAR varBIUdiag; /* cmd = x84 (RUN_BIU_DIAG64) */ 479882527734SSukumar Swaminathan READ_SPARM_VAR varRdSparm; /* cmd = x8D (READ_SPARM64) */ 479982527734SSukumar Swaminathan REG_FCFI_VAR varRegFCFI; /* cmd = xA0 (REG_FCFI) */ 480082527734SSukumar Swaminathan UNREG_FCFI_VAR varUnRegFCFI; /* cmd = xA2 (UNREG_FCFI) */ 480182527734SSukumar Swaminathan READ_LA_VAR varReadLA; /* cmd = x95 (READ_LA64) */ 480282527734SSukumar Swaminathan READ_CONFIG4_VAR varRdConfig4; /* cmd = x0B (READ_CONFIG) */ 480382527734SSukumar Swaminathan RESUME_RPI_VAR varResumeRPI; /* cmd = x9E (RESUME_RPI) */ 480482527734SSukumar Swaminathan REG_LOGIN_VAR varRegLogin; /* cmd = x93 (REG_RPI) */ 480582527734SSukumar Swaminathan UNREG_LOGIN_VAR varUnregLogin; /* cmd = x14 (UNREG_RPI) */ 480682527734SSukumar Swaminathan REG_VPI_VAR varRegVPI4; /* cmd = x96 (REG_VPI) */ 4807e2ca2865SSukumar Swaminathan UNREG_VPI_VAR4 varUnRegVPI4; /* cmd = x97 (UNREG_VPI) */ 480882527734SSukumar Swaminathan REG_VFI_VAR varRegVFI4; /* cmd = x9F (REG_VFI) */ 480982527734SSukumar Swaminathan UNREG_VFI_VAR varUnRegVFI4; /* cmd = xA1 (UNREG_VFI) */ 481082527734SSukumar Swaminathan REQUEST_FEATURES_VAR varReqFeatures; /* cmd = x9D (REQ_FEATURES) */ 481182527734SSukumar Swaminathan SLI_CONFIG_VAR varSLIConfig; /* cmd = x9B (SLI_CONFIG) */ 481282527734SSukumar Swaminathan INIT_VPI_VAR varInitVPI4; /* cmd = xA3 (INIT_VPI) */ 481382527734SSukumar Swaminathan INIT_VFI_VAR varInitVFI4; /* cmd = xA4 (INIT_VFI) */ 481482527734SSukumar Swaminathan 481582527734SSukumar Swaminathan } MAILVARIANTS4; /* Used for SLI-4 */ 481682527734SSukumar Swaminathan 481782527734SSukumar Swaminathan #define MAILBOX_CMD_SLI4_BSIZE 256 481882527734SSukumar Swaminathan #define MAILBOX_CMD_SLI4_WSIZE 64 481982527734SSukumar Swaminathan 482082527734SSukumar Swaminathan #define MAILBOX_CMD_MAX_BSIZE 256 482182527734SSukumar Swaminathan #define MAILBOX_CMD_MAX_WSIZE 64 482282527734SSukumar Swaminathan 482382527734SSukumar Swaminathan 482482527734SSukumar Swaminathan typedef volatile struct 482582527734SSukumar Swaminathan { 482682527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 482782527734SSukumar Swaminathan uint16_t mbxStatus; 482882527734SSukumar Swaminathan uint8_t mbxCommand; 482982527734SSukumar Swaminathan uint8_t mbxReserved:6; 483082527734SSukumar Swaminathan uint8_t mbxHc:1; 483182527734SSukumar Swaminathan uint8_t mbxOwner:1; /* Low order bit first word */ 483282527734SSukumar Swaminathan #endif 483382527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 483482527734SSukumar Swaminathan uint8_t mbxOwner:1; /* Low order bit first word */ 483582527734SSukumar Swaminathan uint8_t mbxHc:1; 483682527734SSukumar Swaminathan uint8_t mbxReserved:6; 483782527734SSukumar Swaminathan uint8_t mbxCommand; 483882527734SSukumar Swaminathan uint16_t mbxStatus; 483982527734SSukumar Swaminathan #endif 48408f23e9faSHans Rosenfeld MAILVARIANTS4 un; /* 252 bytes */ 484182527734SSukumar Swaminathan } MAILBOX4; /* Used for SLI-4 */ 484282527734SSukumar Swaminathan 484382527734SSukumar Swaminathan /* 484482527734SSukumar Swaminathan * End Structure Definitions for Mailbox Commands 484582527734SSukumar Swaminathan */ 484682527734SSukumar Swaminathan 484782527734SSukumar Swaminathan 484882527734SSukumar Swaminathan typedef struct emlxs_mbq 484982527734SSukumar Swaminathan { 485082527734SSukumar Swaminathan volatile uint32_t mbox[MAILBOX_CMD_MAX_WSIZE]; 485182527734SSukumar Swaminathan struct emlxs_mbq *next; 485282527734SSukumar Swaminathan 485382527734SSukumar Swaminathan /* Defferred handling pointers */ 4854a9800bebSGarrett D'Amore void *nonembed; /* ptr to data buffer */ 485582527734SSukumar Swaminathan /* structure */ 4856a9800bebSGarrett D'Amore void *bp; /* ptr to data buffer */ 485782527734SSukumar Swaminathan /* structure */ 4858a9800bebSGarrett D'Amore void *sbp; /* ptr to emlxs_buf_t */ 485982527734SSukumar Swaminathan /* structure */ 4860a9800bebSGarrett D'Amore void *ubp; /* ptr to fc_unsol_buf_t */ 486182527734SSukumar Swaminathan /* structure */ 4862a9800bebSGarrett D'Amore void *iocbq; /* ptr to IOCBQ structure */ 4863a9800bebSGarrett D'Amore void *context; /* ptr to mbox context data */ 4864a9800bebSGarrett D'Amore void *port; /* Sending port */ 486582527734SSukumar Swaminathan uint32_t flag; 486682527734SSukumar Swaminathan 486782527734SSukumar Swaminathan #define MBQ_POOL_ALLOCATED 0x00000001 486882527734SSukumar Swaminathan #define MBQ_PASSTHRU 0x00000002 486982527734SSukumar Swaminathan #define MBQ_EMBEDDED 0x00000004 487082527734SSukumar Swaminathan #define MBQ_BOOTSTRAP 0x00000008 487182527734SSukumar Swaminathan #define MBQ_COMPLETED 0x00010000 /* Used for MBX_SLEEP */ 487282527734SSukumar Swaminathan #define MBQ_INIT_MASK 0x0000ffff 487382527734SSukumar Swaminathan 487482527734SSukumar Swaminathan #ifdef MBOX_EXT_SUPPORT 487582527734SSukumar Swaminathan uint8_t *extbuf; /* ptr to mailbox ext buffer */ 487682527734SSukumar Swaminathan uint32_t extsize; /* size of mailbox ext buffer */ 487782527734SSukumar Swaminathan #endif /* MBOX_EXT_SUPPORT */ 4878a9800bebSGarrett D'Amore uint32_t (*mbox_cmpl)(); 487982527734SSukumar Swaminathan } emlxs_mbq_t; 488082527734SSukumar Swaminathan typedef emlxs_mbq_t MAILBOXQ; 488182527734SSukumar Swaminathan 488282527734SSukumar Swaminathan 488382527734SSukumar Swaminathan /* We currently do not support IOCBs in SLI1 mode */ 488482527734SSukumar Swaminathan typedef struct 488582527734SSukumar Swaminathan { 488682527734SSukumar Swaminathan MAILBOX mbx; 488782527734SSukumar Swaminathan #ifdef MBOX_EXT_SUPPORT 488882527734SSukumar Swaminathan uint8_t mbxExt[MBOX_EXTENSION_SIZE]; 488982527734SSukumar Swaminathan #endif /* MBOX_EXT_SUPPORT */ 489082527734SSukumar Swaminathan uint8_t pad[(SLI_SLIM1_SIZE - 489182527734SSukumar Swaminathan (sizeof (MAILBOX) + MBOX_EXTENSION_SIZE))]; 489282527734SSukumar Swaminathan } SLIM1; 489382527734SSukumar Swaminathan 489482527734SSukumar Swaminathan 489582527734SSukumar Swaminathan typedef struct 489682527734SSukumar Swaminathan { 489782527734SSukumar Swaminathan MAILBOX mbx; 489882527734SSukumar Swaminathan #ifdef MBOX_EXT_SUPPORT 489982527734SSukumar Swaminathan uint8_t mbxExt[MBOX_EXTENSION_SIZE]; 490082527734SSukumar Swaminathan #endif /* MBOX_EXT_SUPPORT */ 490182527734SSukumar Swaminathan PCB pcb; 490282527734SSukumar Swaminathan uint8_t IOCBs[SLI_IOCB_MAX_SIZE]; 490382527734SSukumar Swaminathan } SLIM2; 490482527734SSukumar Swaminathan 490582527734SSukumar Swaminathan 490682527734SSukumar Swaminathan /* def for new 2MB Flash (Pegasus ...) */ 490782527734SSukumar Swaminathan #define MBX_LOAD_AREA 0x81 490882527734SSukumar Swaminathan #define MBX_LOAD_EXP_ROM 0x9C 490982527734SSukumar Swaminathan 491082527734SSukumar Swaminathan #define FILE_TYPE_AWC 0xE1A01001 491182527734SSukumar Swaminathan #define FILE_TYPE_DWC 0xE1A02002 491282527734SSukumar Swaminathan #define FILE_TYPE_BWC 0xE1A03003 491382527734SSukumar Swaminathan 491482527734SSukumar Swaminathan #define AREA_ID_MASK 0xFFFFFF0F 491582527734SSukumar Swaminathan #define AREA_ID_AWC 0x00000001 491682527734SSukumar Swaminathan #define AREA_ID_DWC 0x00000002 491782527734SSukumar Swaminathan #define AREA_ID_BWC 0x00000003 491882527734SSukumar Swaminathan 491982527734SSukumar Swaminathan #define CMD_START_ERASE 1 492082527734SSukumar Swaminathan #define CMD_CONTINUE_ERASE 2 492182527734SSukumar Swaminathan #define CMD_DOWNLOAD 3 492282527734SSukumar Swaminathan #define CMD_END_DOWNLOAD 4 492382527734SSukumar Swaminathan 492482527734SSukumar Swaminathan #define RSP_ERASE_STARTED 1 492582527734SSukumar Swaminathan #define RSP_ERASE_COMPLETE 2 492682527734SSukumar Swaminathan #define RSP_DOWNLOAD_MORE 3 492782527734SSukumar Swaminathan #define RSP_DOWNLOAD_DONE 4 492882527734SSukumar Swaminathan 492982527734SSukumar Swaminathan #define EROM_CMD_FIND_IMAGE 8 493082527734SSukumar Swaminathan #define EROM_CMD_CONTINUE_ERASE 9 493182527734SSukumar Swaminathan #define EROM_CMD_COPY 10 493282527734SSukumar Swaminathan 493382527734SSukumar Swaminathan #define EROM_RSP_ERASE_STARTED 8 493482527734SSukumar Swaminathan #define EROM_RSP_ERASE_COMPLETE 9 493582527734SSukumar Swaminathan #define EROM_RSP_COPY_MORE 10 493682527734SSukumar Swaminathan #define EROM_RSP_COPY_DONE 11 493782527734SSukumar Swaminathan 493882527734SSukumar Swaminathan #define ALLext 1 493982527734SSukumar Swaminathan #define DWCext 2 494082527734SSukumar Swaminathan #define BWCext 3 494182527734SSukumar Swaminathan 494282527734SSukumar Swaminathan #define NO_ALL 0 494382527734SSukumar Swaminathan #define ALL_WITHOUT_BWC 1 494482527734SSukumar Swaminathan #define ALL_WITH_BWC 2 494582527734SSukumar Swaminathan 494682527734SSukumar Swaminathan #define KERNEL_START_ADDRESS 0x000000 494782527734SSukumar Swaminathan #define DOWNLOAD_START_ADDRESS 0x040000 494882527734SSukumar Swaminathan #define EXP_ROM_START_ADDRESS 0x180000 494982527734SSukumar Swaminathan #define SCRATCH_START_ADDRESS 0x1C0000 495082527734SSukumar Swaminathan #define CONFIG_START_ADDRESS 0x1E0000 495182527734SSukumar Swaminathan 495282527734SSukumar Swaminathan 495382527734SSukumar Swaminathan typedef struct SliAifHdr 495482527734SSukumar Swaminathan { 495582527734SSukumar Swaminathan uint32_t CompressBr; 495682527734SSukumar Swaminathan uint32_t RelocBr; 495782527734SSukumar Swaminathan uint32_t ZinitBr; 495882527734SSukumar Swaminathan uint32_t EntryBr; 495982527734SSukumar Swaminathan uint32_t Area_ID; 496082527734SSukumar Swaminathan uint32_t RoSize; 496182527734SSukumar Swaminathan uint32_t RwSize; 496282527734SSukumar Swaminathan uint32_t DbgSize; 496382527734SSukumar Swaminathan uint32_t ZinitSize; 496482527734SSukumar Swaminathan uint32_t DbgType; 496582527734SSukumar Swaminathan uint32_t ImageBase; 496682527734SSukumar Swaminathan uint32_t Area_Size; 496782527734SSukumar Swaminathan uint32_t AddressMode; 496882527734SSukumar Swaminathan uint32_t DataBase; 496982527734SSukumar Swaminathan uint32_t AVersion; 497082527734SSukumar Swaminathan uint32_t Spare2; 497182527734SSukumar Swaminathan uint32_t DebugSwi; 497282527734SSukumar Swaminathan uint32_t ZinitCode[15]; 497382527734SSukumar Swaminathan } AIF_HDR, *PAIF_HDR; 497482527734SSukumar Swaminathan 497582527734SSukumar Swaminathan typedef struct ImageHdr 497682527734SSukumar Swaminathan { 497782527734SSukumar Swaminathan uint32_t BlockSize; 497882527734SSukumar Swaminathan PROG_ID Id; 497982527734SSukumar Swaminathan uint32_t Flags; 498082527734SSukumar Swaminathan uint32_t EntryAdr; 498182527734SSukumar Swaminathan uint32_t InitAdr; 498282527734SSukumar Swaminathan uint32_t ExitAdr; 498382527734SSukumar Swaminathan uint32_t ImageBase; 498482527734SSukumar Swaminathan uint32_t ImageSize; 498582527734SSukumar Swaminathan uint32_t ZinitSize; 498682527734SSukumar Swaminathan uint32_t RelocSize; 498782527734SSukumar Swaminathan uint32_t HdrCks; 498882527734SSukumar Swaminathan } IMAGE_HDR, *PIMAGE_HDR; 498982527734SSukumar Swaminathan 499082527734SSukumar Swaminathan 499182527734SSukumar Swaminathan 499282527734SSukumar Swaminathan typedef struct 499382527734SSukumar Swaminathan { 499482527734SSukumar Swaminathan PROG_ID prog_id; 499582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 499682527734SSukumar Swaminathan uint32_t pci_cfg_rsvd:27; 499782527734SSukumar Swaminathan uint32_t use_hdw_def:1; 499882527734SSukumar Swaminathan uint32_t pci_cfg_sel:3; 499982527734SSukumar Swaminathan uint32_t pci_cfg_lookup_sel:1; 500082527734SSukumar Swaminathan #endif 500182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 500282527734SSukumar Swaminathan uint32_t pci_cfg_lookup_sel:1; 500382527734SSukumar Swaminathan uint32_t pci_cfg_sel:3; 500482527734SSukumar Swaminathan uint32_t use_hdw_def:1; 500582527734SSukumar Swaminathan uint32_t pci_cfg_rsvd:27; 500682527734SSukumar Swaminathan #endif 500782527734SSukumar Swaminathan union 500882527734SSukumar Swaminathan { 500982527734SSukumar Swaminathan PROG_ID boot_bios_id; 501082527734SSukumar Swaminathan uint32_t boot_bios_wd[2]; 501182527734SSukumar Swaminathan } u0; 501282527734SSukumar Swaminathan PROG_ID sli1_prog_id; 501382527734SSukumar Swaminathan PROG_ID sli2_prog_id; 501482527734SSukumar Swaminathan PROG_ID sli3_prog_id; 501582527734SSukumar Swaminathan PROG_ID sli4_prog_id; 501682527734SSukumar Swaminathan union 501782527734SSukumar Swaminathan { 501882527734SSukumar Swaminathan PROG_ID EROM_prog_id; 501982527734SSukumar Swaminathan uint32_t EROM_prog_wd[2]; 502082527734SSukumar Swaminathan } u1; 502182527734SSukumar Swaminathan } WAKE_UP_PARMS, *PWAKE_UP_PARMS; 502282527734SSukumar Swaminathan 502382527734SSukumar Swaminathan 502482527734SSukumar Swaminathan #define PROG_DESCR_STR_LEN 24 50256a573d82SSukumar Swaminathan #define MAX_LOAD_ENTRY 32 502682527734SSukumar Swaminathan 502782527734SSukumar Swaminathan typedef struct 502882527734SSukumar Swaminathan { 502982527734SSukumar Swaminathan uint32_t next; 503082527734SSukumar Swaminathan uint32_t prev; 503182527734SSukumar Swaminathan uint32_t start_adr; 503282527734SSukumar Swaminathan uint32_t len; 503382527734SSukumar Swaminathan union 503482527734SSukumar Swaminathan { 503582527734SSukumar Swaminathan PROG_ID id; 503682527734SSukumar Swaminathan uint32_t wd[2]; 503782527734SSukumar Swaminathan } un; 503882527734SSukumar Swaminathan uint8_t prog_descr[PROG_DESCR_STR_LEN]; 503982527734SSukumar Swaminathan } LOAD_ENTRY; 504082527734SSukumar Swaminathan 504182527734SSukumar Swaminathan typedef struct 504282527734SSukumar Swaminathan { 504382527734SSukumar Swaminathan uint32_t head; 504482527734SSukumar Swaminathan uint32_t tail; 504582527734SSukumar Swaminathan uint32_t entry_cnt; 504682527734SSukumar Swaminathan LOAD_ENTRY load_entry[MAX_LOAD_ENTRY]; 504782527734SSukumar Swaminathan } LOAD_LIST; 504882527734SSukumar Swaminathan 504982527734SSukumar Swaminathan #ifdef __cplusplus 505082527734SSukumar Swaminathan } 505182527734SSukumar Swaminathan #endif 505282527734SSukumar Swaminathan 505382527734SSukumar Swaminathan #endif /* _EMLXS_MBOX_H */ 5054