1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _EMLXS_HW_H 28 #define _EMLXS_HW_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #define MAX_VPORTS 256 /* Max virtual ports per HBA */ 35 /* (includes physical port) */ 36 #define MAX_VPORTS_LIMITED 101 37 38 #define FC_MAX_TRANSFER 0x40000 /* Max transfer size per */ 39 /* operation */ 40 41 #define MAX_RINGS_AVAILABLE 4 /* # rings available */ 42 #define MAX_RINGS 4 /* Max # rings used */ 43 44 #define PCB_SIZE 128 45 46 #define SLIM_IOCB_CMD_R0_ENTRIES 128 /* SLI FCP cmd ring entries */ 47 #define SLIM_IOCB_RSP_R0_ENTRIES 128 /* SLI FCP rsp ring entries */ 48 #define SLIM_IOCB_CMD_R1_ENTRIES 128 /* SLI IP cmd ring entries */ 49 #define SLIM_IOCB_RSP_R1_ENTRIES 128 /* SLI IP rsp ring entries */ 50 #define SLIM_IOCB_CMD_R2_ENTRIES 128 /* SLI ELS cmd ring entries */ 51 #define SLIM_IOCB_RSP_R2_ENTRIES 128 /* SLI ELS rspe ring entries */ 52 #define SLIM_IOCB_CMD_R3_ENTRIES 128 /* SLI CT cmd ring entries */ 53 #define SLIM_IOCB_RSP_R3_ENTRIES 128 /* SLI CT rsp ring entries */ 54 55 /* 56 * Total: 184 Cmd's + 184 Rsp's = 368 57 * Command and response entry counts are not required to be equal 58 */ 59 60 #define SLIM_IOCB_CMD_ENTRIES (SLIM_IOCB_CMD_R0_ENTRIES + \ 61 SLIM_IOCB_CMD_R1_ENTRIES + \ 62 SLIM_IOCB_CMD_R2_ENTRIES + \ 63 SLIM_IOCB_CMD_R3_ENTRIES) 64 65 #define SLIM_IOCB_RSP_ENTRIES (SLIM_IOCB_RSP_R0_ENTRIES + \ 66 SLIM_IOCB_RSP_R1_ENTRIES + \ 67 SLIM_IOCB_RSP_R2_ENTRIES + \ 68 SLIM_IOCB_RSP_R3_ENTRIES) 69 70 #define SLIM_IOCB_ENTRIES (SLIM_IOCB_CMD_ENTRIES + \ 71 SLIM_IOCB_RSP_ENTRIES) 72 73 74 /* SLI1 Definitions */ 75 #define SLI_SLIM1_SIZE 4096 /* Fixed size memory */ 76 77 78 /* SLI2 Definitions */ 79 #define SLI2_IOCB_CMD_SIZE 32 80 #define SLI2_IOCB_RSP_SIZE 32 81 #define SLI2_IOCB_MAX_SIZE ((SLI2_IOCB_CMD_SIZE * \ 82 SLIM_IOCB_CMD_ENTRIES) + \ 83 (SLI2_IOCB_RSP_SIZE * \ 84 SLIM_IOCB_RSP_ENTRIES)) 85 #define SLI2_SLIM2_SIZE (MBOX_SIZE + MBOX_EXTENSION_SIZE + \ 86 PCB_SIZE + SLI2_IOCB_MAX_SIZE) 87 88 89 /* SLI3 Definitions */ 90 #define SLI3_MAX_BDE 7 91 #define SLI3_IOCB_CMD_SIZE 128 92 #define SLI3_IOCB_RSP_SIZE 64 93 #define SLI3_IOCB_MAX_SIZE ((SLI3_IOCB_CMD_SIZE * \ 94 SLIM_IOCB_CMD_ENTRIES) + \ 95 (SLI3_IOCB_RSP_SIZE * \ 96 SLIM_IOCB_RSP_ENTRIES)) 97 #define SLI3_SLIM2_SIZE (MBOX_SIZE + MBOX_EXTENSION_SIZE + \ 98 PCB_SIZE + SLI3_IOCB_MAX_SIZE) 99 100 #define SLI_SLIM2_SIZE SLI3_SLIM2_SIZE 101 #define SLI_IOCB_MAX_SIZE SLI3_IOCB_MAX_SIZE 102 103 104 /* These two are defined to indicate FCP cmd or non FCP cmd */ 105 #define FC_FCP_CMD 0 106 #define FC_FCT_CMD 0 107 #define FC_IP_CMD 1 108 #define FC_ELS_CMD 2 109 #define FC_CT_CMD 3 110 111 #define FC_NFCP_CMD 1 /* could be a bit mask */ 112 113 #define FC_MAXRETRY 3 /* max retries for ELS commands */ 114 #define FC_FCP_RING 0 /* use ring 0 for FCP initiator cmds */ 115 #define FC_FCT_RING 0 /* use ring 0 for FCP target cmds */ 116 117 #define FC_IP_RING 1 /* use ring 1 for IP commands */ 118 #define FC_ELS_RING 2 /* use ring 2 for ELS commands */ 119 #define FC_CT_RING 3 /* use ring 3 for CT commands */ 120 121 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 122 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 123 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 124 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 125 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG */ 126 /* iocb */ 127 #define FF_REG_AREA_SIZE 256 /* size, in bytes, of i/o register */ 128 /* area */ 129 130 /* 131 * Miscellaneous stuff.... 132 */ 133 /* HBA Mgmt */ 134 #define FDMI_DID ((uint32_t)0xfffffa) 135 #define NAMESERVER_DID ((uint32_t)0xfffffc) 136 #define SCR_DID ((uint32_t)0xfffffd) 137 #define FABRIC_DID ((uint32_t)0xfffffe) 138 #define BCAST_DID ((uint32_t)0xffffff) 139 #define MASK_DID ((uint32_t)0xffffff) 140 #define CT_DID_MASK ((uint32_t)0xffff00) 141 #define FABRIC_DID_MASK ((uint32_t)0xfff000) 142 #define WELL_KNOWN_DID_MASK ((uint32_t)0xfffff0) 143 144 #define EMLXS_MENLO_DID ((uint32_t)0x00fc0e) 145 146 #define OWN_CHIP 1 /* IOCB / Mailbox is owned by FireFly */ 147 #define OWN_HOST 0 /* IOCB / Mailbox is owned by Host */ 148 #define END_OF_CHAIN 0 149 150 151 /* defines for type field in fc header */ 152 #define FC_ELS_DATA 0x01 153 #define FC_LLC_SNAP 0x05 154 #define FC_FCP_DATA 0x08 155 #define FC_CT_TYPE 0x20 156 #define EMLXS_MENLO_TYPE 0xFE 157 158 /* defines for rctl field in fc header */ 159 #define FC_DEV_DATA 0x0 160 #define FC_UNSOL_CTL 0x2 161 #define FC_SOL_CTL 0x3 162 #define FC_UNSOL_DATA 0x4 163 #define FC_FCP_CMND 0x6 164 #define FC_ELS_REQ 0x22 165 #define FC_ELS_RSP 0x23 166 #define FC_NET_HDR 0x20 /* network headers for Dfctl field */ 167 168 /* 169 * Common Transport structures and definitions 170 * 171 */ 172 #define EMLXS_COMMAND 0 173 #define EMLXS_RESPONSE 1 174 175 typedef union CtRevisionId 176 { 177 /* Structure is in Big Endian format */ 178 struct 179 { 180 uint32_t Revision:8; 181 uint32_t InId:24; 182 } bits; 183 uint32_t word; 184 } CtRevisionId_t; 185 186 typedef union CtCommandResponse 187 { 188 /* Structure is in Big Endian format */ 189 struct 190 { 191 uint32_t CmdRsp:16; 192 uint32_t Size:16; 193 } bits; 194 uint32_t word; 195 } CtCommandResponse_t; 196 197 typedef struct SliCtRequest 198 { 199 /* Structure is in Big Endian format */ 200 CtRevisionId_t RevisionId; 201 uint8_t FsType; 202 uint8_t FsSubType; 203 uint8_t Options; 204 uint8_t Rsrvd1; 205 CtCommandResponse_t CommandResponse; 206 uint8_t Rsrvd2; 207 uint8_t ReasonCode; 208 uint8_t Explanation; 209 uint8_t VendorUnique; 210 211 union 212 { 213 uint32_t data; 214 uint32_t PortID; 215 216 struct gid 217 { 218 uint8_t PortType; /* for GID_PT requests */ 219 uint8_t DomainScope; 220 uint8_t AreaScope; 221 uint8_t Fc4Type; /* for GID_FT requests */ 222 } gid; 223 struct rft 224 { 225 uint32_t PortId; /* For RFT_ID requests */ 226 #ifdef EMLXS_BIG_ENDIAN 227 uint32_t rsvd0:16; 228 uint32_t rsvd1:7; 229 uint32_t fcpReg:1; /* Type 8 */ 230 uint32_t rsvd2:2; 231 uint32_t ipReg:1; /* Type 5 */ 232 uint32_t rsvd3:5; 233 #endif 234 #ifdef EMLXS_LITTLE_ENDIAN 235 uint32_t rsvd0:16; 236 uint32_t fcpReg:1; /* Type 8 */ 237 uint32_t rsvd1:7; 238 uint32_t rsvd3:5; 239 uint32_t ipReg:1; /* Type 5 */ 240 uint32_t rsvd2:2; 241 #endif 242 uint32_t rsvd[7]; 243 } rft; 244 245 struct rsnn 246 { 247 uint8_t wwnn[8]; 248 uint8_t snn_len; 249 char snn[256]; 250 } rsnn; 251 252 struct rspn 253 { 254 uint32_t PortId; 255 uint8_t spn_len; 256 char spn[256]; 257 } rspn; 258 } un; 259 } SliCtRequest_t; 260 typedef SliCtRequest_t SLI_CT_REQUEST; 261 262 #define SLI_CT_REVISION 1 263 264 265 /* 266 * FsType Definitions 267 */ 268 269 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 270 #define SLI_CT_TIME_SERVICE 0xFB 271 #define SLI_CT_DIRECTORY_SERVICE 0xFC 272 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 273 274 /* 275 * Directory Service Subtypes 276 */ 277 278 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 279 280 /* 281 * Response Codes 282 */ 283 284 #define SLI_CT_RESPONSE_FS_RJT 0x8001 285 #define SLI_CT_RESPONSE_FS_ACC 0x8002 286 287 /* 288 * Reason Codes 289 */ 290 291 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 292 #define SLI_CT_INVALID_COMMAND 0x01 293 #define SLI_CT_INVALID_VERSION 0x02 294 #define SLI_CT_LOGICAL_ERROR 0x03 295 #define SLI_CT_INVALID_IU_SIZE 0x04 296 #define SLI_CT_LOGICAL_BUSY 0x05 297 #define SLI_CT_PROTOCOL_ERROR 0x07 298 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 299 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 300 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 301 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 302 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 303 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 304 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 305 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 306 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 307 #define SLI_CT_VENDOR_UNIQUE 0xff 308 309 /* 310 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 311 */ 312 313 #define SLI_CT_NO_PORT_ID 0x01 314 #define SLI_CT_NO_PORT_NAME 0x02 315 #define SLI_CT_NO_NODE_NAME 0x03 316 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 317 #define SLI_CT_NO_IP_ADDRESS 0x05 318 #define SLI_CT_NO_IPA 0x06 319 #define SLI_CT_NO_FC4_TYPES 0x07 320 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 321 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 322 #define SLI_CT_NO_PORT_TYPE 0x0A 323 #define SLI_CT_ACCESS_DENIED 0x10 324 #define SLI_CT_INVALID_PORT_ID 0x11 325 #define SLI_CT_DATABASE_EMPTY 0x12 326 327 #ifdef EMLXS_BIG_ENDIAN 328 #define CT_CMD_MASK 0xffff0000 329 #endif 330 331 #ifdef EMLXS_LITTLE_ENDIAN 332 #define CT_CMD_MASK 0xffff 333 #endif 334 335 /* 336 * Management Server Interface Command Codes 337 */ 338 339 #define MS_GTIN 0x0100 340 #define MS_GIEL 0x0101 341 #define MS_GIET 0x0111 342 #define MS_GDID 0x0112 343 #define MS_GMID 0x0113 344 #define MS_GFN 0x0114 345 #define MS_GIELN 0x0115 346 #define MS_GMAL 0x0116 347 #define MS_GIEIL 0x0117 348 #define MS_GPL 0x0118 349 #define MS_GPT 0x0121 350 #define MS_GPPN 0x0122 351 #define MS_GAPNL 0x0124 352 #define MS_GPS 0x0126 353 #define MS_GPSC 0x0127 354 #define MS_GATIN 0x0128 355 #define MS_GSES 0x0130 356 #define MS_GPLNL 0x0191 357 #define MS_GPLT 0x0192 358 #define MS_GPLML 0x0193 359 #define MS_GPAB 0x0197 360 #define MS_GNPL 0x01A1 361 #define MS_GPNL 0x01A2 362 #define MS_GPFCP 0x01A4 363 #define MS_GPLI 0x01A5 364 #define MS_GNID 0x01B1 365 #define MS_RIELN 0x0215 366 #define MS_RPL 0x0280 367 #define MS_RPLN 0x0291 368 #define MS_RPLT 0x0292 369 #define MS_RPLM 0x0293 370 #define MS_RPAB 0x0298 371 #define MS_RPFCP 0x029A 372 #define MS_RPLI 0x029B 373 #define MS_DPL 0x0380 374 #define MS_DPLN 0x0391 375 #define MS_DPLM 0x0392 376 #define MS_DPLML 0x0393 377 #define MS_DPLI 0x0394 378 #define MS_DPAB 0x0395 379 #define MS_DPALL 0x039F 380 381 /* 382 * Name Server Command Codes 383 */ 384 #define SLI_CTNS_GA_NXT 0x0100 385 #define SLI_CTNS_GPN_ID 0x0112 386 #define SLI_CTNS_GNN_ID 0x0113 387 #define SLI_CTNS_GCS_ID 0x0114 388 #define SLI_CTNS_GFT_ID 0x0117 389 #define SLI_CTNS_GSPN_ID 0x0118 390 #define SLI_CTNS_GPT_ID 0x011A 391 #define SLI_CTNS_GID_PN 0x0121 392 #define SLI_CTNS_GID_NN 0x0131 393 #define SLI_CTNS_GIP_NN 0x0135 394 #define SLI_CTNS_GIPA_NN 0x0136 395 #define SLI_CTNS_GSNN_NN 0x0139 396 #define SLI_CTNS_GNN_IP 0x0153 397 #define SLI_CTNS_GIPA_IP 0x0156 398 #define SLI_CTNS_GID_FT 0x0171 399 #define SLI_CTNS_GID_PT 0x01A1 400 #define SLI_CTNS_RPN_ID 0x0212 401 #define SLI_CTNS_RNN_ID 0x0213 402 #define SLI_CTNS_RCS_ID 0x0214 403 #define SLI_CTNS_RFT_ID 0x0217 404 #define SLI_CTNS_RSPN_ID 0x0218 405 #define SLI_CTNS_RPT_ID 0x021A 406 #define SLI_CTNS_RIP_NN 0x0235 407 #define SLI_CTNS_RIPA_NN 0x0236 408 #define SLI_CTNS_RSNN_NN 0x0239 409 #define SLI_CTNS_DA_ID 0x0300 410 411 #define SLI_CT_LOOPBACK 0xFCFC 412 413 414 /* 415 * Port Types 416 */ 417 418 #define SLI_CTPT_N_PORT 0x01 419 #define SLI_CTPT_NL_PORT 0x02 420 #define SLI_CTPT_FNL_PORT 0x03 421 #define SLI_CTPT_IP 0x04 422 #define SLI_CTPT_FCP 0x08 423 #define SLI_CTPT_NX_PORT 0x7F 424 #define SLI_CTPT_F_PORT 0x81 425 #define SLI_CTPT_FL_PORT 0x82 426 #define SLI_CTPT_E_PORT 0x84 427 428 #define SLI_CT_LAST_ENTRY 0x80000000 429 430 /* ===================================================================== */ 431 432 /* 433 * Start FireFly Register definitions 434 */ 435 436 /* PCI register offsets */ 437 #define MEM_ADDR_OFFSET 0x10 /* SLIM base memory address */ 438 #define MEMH_OFFSET 0x14 /* SLIM base memory high address */ 439 #define REG_ADDR_OFFSET 0x18 /* REGISTER base memory address */ 440 #define REGH_OFFSET 0x1c /* REGISTER base memory high address */ 441 #define IO_ADDR_OFFSET 0x20 /* BIU I/O registers */ 442 #define REGIOH_OFFSET 0x24 /* REGISTER base io high address */ 443 444 #define CMD_REG_OFFSET 0x4 /* PCI command configuration */ 445 446 /* General PCI Register Definitions */ 447 /* Refer To The PCI Specification For Detailed Explanations */ 448 449 /* Register Offsets in little endian format */ 450 #define PCI_VENDOR_ID_REGISTER 0x00 /* PCI Vendor ID Reg */ 451 #define PCI_DEVICE_ID_REGISTER 0x02 /* PCI Device ID Reg */ 452 #define PCI_CONFIG_ID_REGISTER 0x00 /* PCI Configuration ID Reg */ 453 #define PCI_COMMAND_REGISTER 0x04 /* PCI Command Reg */ 454 #define PCI_STATUS_REGISTER 0x06 /* PCI Status Reg */ 455 #define PCI_REV_ID_REGISTER 0x08 /* PCI Revision ID Reg */ 456 #define PCI_CLASS_CODE_REGISTER 0x09 /* PCI Class Code Reg */ 457 #define PCI_CACHE_LINE_REGISTER 0x0C /* PCI Cache Line Reg */ 458 #define PCI_LATENCY_TMR_REGISTER 0x0D /* PCI Latency Timer Reg */ 459 #define PCI_HEADER_TYPE_REGISTER 0x0E /* PCI Header Type Reg */ 460 #define PCI_BIST_REGISTER 0x0F /* PCI Built-In SelfTest Reg */ 461 #define PCI_BAR_0_REGISTER 0x10 /* PCI Base Address Reg 0 */ 462 #define PCI_BAR_1_REGISTER 0x14 /* PCI Base Address Reg 1 */ 463 #define PCI_BAR_2_REGISTER 0x18 /* PCI Base Address Reg 2 */ 464 #define PCI_BAR_3_REGISTER 0x1C /* PCI Base Address Reg 3 */ 465 #define PCI_BAR_4_REGISTER 0x20 /* PCI Base Address Reg 4 */ 466 #define PCI_BAR_5_REGISTER 0x24 /* PCI Base Address Reg 5 */ 467 #define PCI_SSID_REGISTER 0x2C 468 #define PCI_SSVID_REGISTER 0x2C 469 #define PCI_SSDID_REGISTER 0x2E 470 #define PCI_EXPANSION_ROM 0x30 /* PCI Expansion ROM Base Reg */ 471 #define PCI_CAP_POINTER 0x34 472 #define PCI_INTR_LINE_REGISTER 0x3C /* PCI Interrupt Line Reg */ 473 #define PCI_INTR_PIN_REGISTER 0x3D /* PCI Interrupt Pin Reg */ 474 #define PCI_MIN_GNT_REGISTER 0x3E /* PCI Min-Gnt Reg */ 475 #define PCI_MAX_LAT_REGISTER 0x3F /* PCI Max_Lat Reg */ 476 #define PCI_NODE_ADDR_REGISTER 0x40 /* PCI Node Address Reg */ 477 478 #define PCI_PM_CONTROL_REGISTER 0x50 /* PCI Power Mgmt Control Reg */ 479 480 /* PCIe adapters only */ 481 #define PCIe_MSI_CONTROL_REG0 0x60 /* MSI Control */ 482 #define PCIe_MSI_CONTROL_REG1 0x62 /* MSI Control */ 483 484 /* Power management command states */ 485 #define PCI_PM_D0_STATE 0x00 /* Power up state */ 486 #define PCI_PM_D3_STATE 0x03 /* Power down state */ 487 488 489 /* PCI access methods */ 490 #define P_CONF_T1 1 491 #define P_CONF_T2 2 492 493 /* max number of pci buses */ 494 #define MAX_PCI_BUSES 0xFF 495 496 /* number of PCI config bytes to access */ 497 #define PCI_BYTE 1 498 #define PCI_WORD 2 499 #define PCI_DWORD 4 500 501 /* PCI related constants */ 502 #define CMD_IO_ENBL 0x0001 503 #define CMD_MEM_ENBL 0x0002 504 #define CMD_BUS_MASTER 0x0004 505 #define CMD_MWI 0x0010 506 #define CMD_PARITY_CHK 0x0040 507 #define CMD_SERR_ENBL 0x0100 508 509 #define CMD_CFG_VALUE 0x156 /* mem enable, master, MWI, SERR, PERR */ 510 511 /* PCI addresses */ 512 #define PCI_SPACE_ENABLE 0x0CF8 513 #define CF1_CONFIG_ADDR_REGISTER 0x0CF8 514 #define CF1_CONFIG_DATA_REGISTER 0x0CFC 515 #define CF2_FORWARD_REGISTER 0x0CFA 516 #define CF2_BASE_ADDRESS 0xC000 517 518 519 #define DEFAULT_PCI_LATENCY_CLOCKS 0xf8 /* 0xF8 is a special value */ 520 /* for FF11.1N6 firmware. */ 521 /* Use 0x80 for pre-FF11.1N6 */ 522 /* &N7, etc */ 523 #define PCI_LATENCY_VALUE 0xf8 524 525 526 527 /* ==== Register Bit Definitions ==== */ 528 529 /* Used by SBUS adapter */ 530 /* SBUS Control Register */ 531 #define SBUS_CTRL_REG_OFFSET 0 /* Word offset from reg base addr */ 532 533 #define SBUS_CTRL_SBRST 0x00000001 /* Bit 0 */ 534 #define SBUS_CTRL_BKOFF 0x00000002 /* Bit 1 */ 535 #define SBUS_CTRL_ENP 0x00000004 /* Bit 2 */ 536 #define SBUS_CTRL_EN64 0x00000008 /* Bit 3 */ 537 #define SBUS_CTRL_SIR_1 0x00000010 /* Bit [6:4] IRL 1, */ 538 /* lowset priority */ 539 #define SBUS_CTRL_SIR_2 0x00000020 540 #define SBUS_CTRL_SIR_3 0x00000030 541 #define SBUS_CTRL_SIR_4 0x00000040 542 #define SBUS_CTRL_SIR_5 0x00000050 543 #define SBUS_CTRL_SIR_6 0x00000060 544 #define SBUS_CTRL_SIR_7 0x00000070 /* IRL 7, highest priority */ 545 546 /* SBUS Status Register */ 547 #define SBUS_STAT_REG_OFFSET 1 /* Word offset from reg base addr */ 548 #define SBUS_STAT_IP 0x00000001 /* Bit 0 */ 549 #define SBUS_STAT_LERR 0x00000002 /* Bit 1 */ 550 #define SBUS_STAT_SBPE 0x00000004 /* Bit 2 */ 551 #define SBUS_STAT_TE 0x00000008 /* Bit 3 */ 552 #define SBUS_STAT_WPE 0x00000010 /* Bit 4 */ 553 #define SBUS_STAT_PERR 0x00000020 /* Bit 5 */ 554 #define SBUS_STAT_SERR 0x00000040 /* Bit 6 */ 555 #define SBUS_STAT_PTA 0x00000080 /* Bit 7 */ 556 557 /* SBUS Update Register */ 558 #define SBUS_UPDATE_REG_OFFSET 2 /* Word offfset from reg base addr */ 559 560 #define SBUS_UPDATE_DATA 0x00000001 /* Bit 0 */ 561 #define SBUS_UPDATE_SPCLK 0x00000002 /* Bit 1 */ 562 #define SBUS_UPDATE_SPCE 0x00000004 /* Bit 2 */ 563 #define SBUS_UPDATE_SPRST 0x00000008 /* Bit 3 */ 564 #define SBUS_UPDATE_SPWE 0x00000010 /* Bit 4 */ 565 #define SBUS_UPDATE_LDFPGA 0x00000080 /* Bit 7 */ 566 567 /* Host Attention Register */ 568 569 #define HA_REG_OFFSET 0 /* Word offset from register base address */ 570 571 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 572 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 573 #define HA_R0ATT 0x00000008 /* Bit 3 */ 574 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 575 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 576 #define HA_R1ATT 0x00000080 /* Bit 7 */ 577 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 578 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 579 #define HA_R2ATT 0x00000800 /* Bit 11 */ 580 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 581 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 582 #define HA_R3ATT 0x00008000 /* Bit 15 */ 583 #define HA_LATT 0x20000000 /* Bit 29 */ 584 #define HA_MBATT 0x40000000 /* Bit 30 */ 585 #define HA_ERATT 0x80000000 /* Bit 31 */ 586 587 588 #ifdef MSI_SUPPORT 589 590 591 /* Host attention interrupt map */ 592 #define EMLXS_MSI_MAP8 {0, HA_R0ATT, HA_R1ATT, HA_R2ATT, \ 593 HA_R3ATT, HA_LATT, HA_MBATT, HA_ERATT} 594 #define EMLXS_MSI_MAP4 {0, HA_R0ATT, HA_R1ATT, HA_R2ATT, 0, 0, 0, 0} 595 #define EMLXS_MSI_MAP2 {0, HA_R0ATT, 0, 0, 0, 0, 0, 0} 596 #define EMLXS_MSI_MAP1 {0, 0, 0, 0, 0, 0, 0, 0} 597 598 /* MSI 0 interrupt mask */ 599 #define EMLXS_MSI0_MASK8 0 600 #define EMLXS_MSI0_MASK4 (HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \ 601 HC_ERINT_ENA) 602 #define EMLXS_MSI0_MASK2 (HC_R1INT_ENA|HC_R2INT_ENA|HC_R3INT_ENA| \ 603 HC_MBINT_ENA|HC_LAINT_ENA|HC_ERINT_ENA) 604 #define EMLXS_MSI0_MASK1 (HC_R0INT_ENA|HC_R1INT_ENA|HC_R2INT_ENA| \ 605 HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \ 606 HC_ERINT_ENA) 607 608 609 #define EMLXS_MSI_MAX_INTRS 8 610 611 #define EMLXS_MSI_MODE1 0 612 #define EMLXS_MSI_MODE2 1 613 #define EMLXS_MSI_MODE4 2 614 #define EMLXS_MSI_MODE8 3 615 #define EMLXS_MSI_MODES 4 616 617 #endif /* MSI_SUPPORT */ 618 619 620 #define IO_THROTTLE_RESERVE 12 621 622 623 624 625 /* Chip Attention Register */ 626 627 #define CA_REG_OFFSET 1 /* Word offset from register base address */ 628 629 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 630 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 631 #define CA_R0ATT 0x00000008 /* Bit 3 */ 632 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 633 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 634 #define CA_R1ATT 0x00000080 /* Bit 7 */ 635 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 636 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 637 #define CA_R2ATT 0x00000800 /* Bit 11 */ 638 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 639 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 640 #define CA_R3ATT 0x00008000 /* Bit 15 */ 641 #define CA_MBATT 0x40000000 /* Bit 30 */ 642 643 /* Host Status Register */ 644 645 #define HS_REG_OFFSET 2 /* Word offset from register base address */ 646 647 #define HS_OVERTEMP 0x00000100 /* Bit 8 */ 648 #define HS_MBRDY 0x00400000 /* Bit 22 */ 649 #define HS_FFRDY 0x00800000 /* Bit 23 */ 650 #define HS_FFER8 0x01000000 /* Bit 24 */ 651 #define HS_FFER7 0x02000000 /* Bit 25 */ 652 #define HS_FFER6 0x04000000 /* Bit 26 */ 653 #define HS_FFER5 0x08000000 /* Bit 27 */ 654 #define HS_FFER4 0x10000000 /* Bit 28 */ 655 #define HS_FFER3 0x20000000 /* Bit 29 */ 656 #define HS_FFER2 0x40000000 /* Bit 30 */ 657 #define HS_FFER1 0x80000000 /* Bit 31 */ 658 #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */ 659 660 /* Host Control Register */ 661 662 #define HC_REG_OFFSET 3 /* Word offset from register base address */ 663 664 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 665 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 666 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 667 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 668 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 669 #define HC_INITHBI 0x02000000 /* Bit 25 */ 670 #define HC_INITMB 0x04000000 /* Bit 26 */ 671 #define HC_INITFF 0x08000000 /* Bit 27 */ 672 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 673 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 674 675 /* BIU Configuration Register */ 676 677 #define BC_REG_OFFSET 4 /* Word offset from register base address */ 678 679 #define BC_BSE 0x00000001 /* Bit 0 */ 680 #define BC_BSE_SWAP 0x01000000 /* Bit 0 - swapped */ 681 682 /* 683 * End FireFly Register definitions 684 */ 685 686 /* 687 * Start SLI 4 section. 688 */ 689 690 /* PCI Config Register offsets */ 691 #define PCICFG_UE_STATUS_LO_OFFSET 0xA0 /* Error Indication - low */ 692 #define PCICFG_UE_STATUS_HI_OFFSET 0xA4 /* Error Indication - high */ 693 #define PCICFG_UE_STATUS_ONLINE1 0xB0 /* Error status1 */ 694 #define PCICFG_UE_STATUS_ONLINE2 0xB4 /* Error status2 */ 695 696 /* BAR1 and BAR2 register offsets */ 697 698 /* BAR1 offsets for principal registers */ 699 #define CSR_ISR0_OFFSET 0x0C18 /* CSR for EQ interrupt indications */ 700 #define CSR_IMR0_OFFSET 0x0C48 /* CSR for EQ interrupt masking */ 701 #define CSR_ISCR0_OFFSET 0x0C78 /* CSR for EQ interrupt clearing */ 702 703 #define ISR0_EQ0_INDC 0x00000001 /* Indication bit for EQ0 */ 704 #define ISR0_EQ1_INDC 0x00000002 /* Indication bit for EQ1 */ 705 #define ISR0_EQ2_INDC 0x00000004 /* Indication bit for EQ2 */ 706 #define ISR0_EQ3_INDC 0x00000008 /* Indication bit for EQ3 */ 707 #define ISR0_EQ4_INDC 0x00000010 /* Indication bit for EQ4 */ 708 #define ISR0_EQ5_INDC 0x00000020 /* Indication bit for EQ5 */ 709 #define ISR0_EQ6_INDC 0x00000040 /* Indication bit for EQ6 */ 710 #define ISR0_EQ7_INDC 0x00000080 /* Indication bit for EQ7 */ 711 712 /* MPU EP Semaphore register (ARM POST) */ 713 #define CSR_MPU_EP_SEMAPHORE_OFFSET 0x00AC 714 715 /* POST Stages of interest */ 716 #define ARM_POST_FATAL 0x80000000 717 #define ARM_POST_READY 0xc000 718 #define ARM_POST_MASK 0xffff 719 720 #define MPU_EP_DL 0x04000000 /* Driverloadedbitmask */ 721 #define MPU_EP_ORI 0x08000000 /* OptionROMinstalledbitmask */ 722 #define MPU_EP_IPC 0x10000000 /* IPaddressconflictmask */ 723 #define MPU_EP_NIP 0x20000000 /* NoIPaddressmask */ 724 #define MPU_EP_BFW 0x40000000 /* BackupFWinusemask */ 725 #define MPU_EP_ERR 0x80000000 /* POSTfatalerrormask */ 726 727 /* BAR2 offsets for principal doorbell registers */ 728 729 #define PD_RQ_DB_OFFSET 0x00A0 /* Doorbell notify of posted RQEs */ 730 731 #define PD_WQ_DB_OFFSET 0x0040 /* Doorbell notify of posted WQEs */ 732 733 #define PD_CQ_DB_OFFSET 0x0120 /* Doorbell notify of processed CQEs or EQEs */ 734 735 #define PD_MQ_DB_OFFSET 0x0140 /* Doorbell notify of posted MQEs */ 736 737 #define PD_MB_DB_OFFSET 0x0160 /* Doorbell Bootstrap Mailbox */ 738 739 /* Doorbell definitions */ 740 741 /* Defines for MQ doorbell */ 742 #define MQ_DB_POP_SHIFT 16 /* shift for entries popped */ 743 #define MQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ 744 745 /* Defines for CQ doorbell */ 746 #define CQ_DB_POP_SHIFT 16 /* shift for entries popped */ 747 #define CQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ 748 #define CQ_DB_REARM 0x20000000 /* Bit 29, rearm */ 749 750 /* Defines for EQ doorbell */ 751 #define EQ_DB_CLEAR 0x00000200 /* Bit 9, designates clear EQ ISR */ 752 #define EQ_DB_EVENT 0x00000400 /* Bit 10, designates EQ */ 753 #define EQ_DB_POP_SHIFT 16 /* shift for entries popped */ 754 #define EQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ 755 #define EQ_DB_REARM 0x20000000 /* Bit 29, rearm */ 756 757 /* bootstrap mailbox doorbell defines */ 758 #define BMBX_READY 0x00000001 /* Mask for Port Ready bit */ 759 #define BMBX_ADDR_HI 0x00000002 /* Mask for Addr Hi bit */ 760 #define BMBX_ADDR 0xFFFFFFFA /* Mask for Addr bits */ 761 762 /* Sizeof bootstrap mailbox */ 763 #define EMLXS_BOOTSTRAP_MB_SIZE 256 764 765 #define MQE_SPECIAL_WORD0 0xFF1234FF /* Initialize bootstrap wd 0 */ 766 #define MQE_SPECIAL_WORD1 0xFF5678FF /* Initialize bootstrap wd 1 */ 767 768 769 /* ===================================================================== */ 770 771 /* 772 * Start of FCP specific structures 773 */ 774 775 typedef struct emlxs_fcp_rsp 776 { 777 uint32_t rspRsvd1; /* FC Word 0, byte 0:3 */ 778 uint32_t rspRsvd2; /* FC Word 1, byte 0:3 */ 779 780 uint8_t rspStatus0; /* FCP_STATUS byte 0 (reserved) */ 781 uint8_t rspStatus1; /* FCP_STATUS byte 1 (reserved) */ 782 uint8_t rspStatus2; /* FCP_STATUS byte 2 field validity */ 783 #define RSP_LEN_VALID 0x01 /* bit 0 */ 784 #define SNS_LEN_VALID 0x02 /* bit 1 */ 785 #define RESID_OVER 0x04 /* bit 2 */ 786 #define RESID_UNDER 0x08 /* bit 3 */ 787 788 uint8_t rspStatus3; /* FCP_STATUS byte 3 SCSI status byte */ 789 #define SCSI_STAT_GOOD 0x00 790 #define SCSI_STAT_CHECK_COND 0x02 791 #define SCSI_STAT_COND_MET 0x04 792 #define SCSI_STAT_BUSY 0x08 793 #define SCSI_STAT_INTERMED 0x10 794 #define SCSI_STAT_INTERMED_CM 0x14 795 #define SCSI_STAT_RES_CNFLCT 0x18 796 #define SCSI_STAT_CMD_TERM 0x22 797 #define SCSI_STAT_QUE_FULL 0x28 798 #define SCSI_STAT_ACA_ACTIVE 0x30 799 #define SCSI_STAT_TASK_ABORT 0x40 800 801 uint32_t rspResId; /* Residual xfer if RESID_xxxx set */ 802 /* in fcpStatus2. */ 803 /* Received in Big Endian format */ 804 uint32_t rspSnsLen; /* Length of sense data in fcpSnsInfo */ 805 /* Received in Big Endian format */ 806 uint32_t rspRspLen; /* Length of FCP response data */ 807 /* in fcpRspInfo */ 808 /* Received in Big Endian format */ 809 810 uint8_t rspInfo0; /* FCP_RSP_INFO byte 0 (reserved) */ 811 uint8_t rspInfo1; /* FCP_RSP_INFO byte 1 (reserved) */ 812 uint8_t rspInfo2; /* FCP_RSP_INFO byte 2 (reserved) */ 813 uint8_t rspInfo3; /* FCP_RSP_INFO RSP_CODE byte 3 */ 814 815 #define RSP_NO_FAILURE 0x00 816 #define RSP_DATA_BURST_ERR 0x01 817 #define RSP_CMD_FIELD_ERR 0x02 818 #define RSP_RO_MISMATCH_ERR 0x03 819 #define RSP_TM_NOT_SUPPORTED 0x04 /* Task mgmt function not supported */ 820 #define RSP_TM_NOT_COMPLETED 0x05 /* Task mgmt function not performed */ 821 822 uint32_t rspInfoRsvd; /* FCP_RSP_INFO bytes 4-7 (reserved) */ 823 824 /* 825 * Define maximum size of SCSI Sense buffer. 826 * Seagate never issues more than 18 bytes of Sense data 827 */ 828 #define MAX_FCP_SNS 128 829 uint8_t rspSnsInfo[MAX_FCP_SNS]; 830 } emlxs_fcp_rsp; 831 typedef emlxs_fcp_rsp FCP_RSP; 832 833 834 typedef struct emlxs_fcp_cmd 835 { 836 uint32_t fcpLunMsl; /* most significant lun word */ 837 uint32_t fcpLunLsl; /* least significant lun word */ 838 839 /* 840 * # of bits to shift lun id to end up in right payload word, 841 * little endian = 8, big = 16. 842 */ 843 #ifdef EMLXS_LITTLE_ENDIAN 844 #define FC_LUN_SHIFT 8 845 #define FC_ADDR_MODE_SHIFT 0 846 #endif 847 #ifdef EMLXS_BIG_ENDIAN 848 #define FC_LUN_SHIFT 16 849 #define FC_ADDR_MODE_SHIFT 24 850 #endif 851 852 uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */ 853 uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */ 854 #define SIMPLE_Q 0x00 855 #define HEAD_OF_Q 0x01 856 #define ORDERED_Q 0x02 857 #define ACA_Q 0x04 858 #define UNTAGGED 0x05 859 860 uint8_t fcpCntl2; /* FCP_CTL byte 2 task management */ 861 /* codes */ 862 #define ABORT_TASK_SET 0x02 /* Bit 1 */ 863 #define CLEAR_TASK_SET 0x04 /* bit 2 */ 864 #define LUN_RESET 0x10 /* bit 4 */ 865 #define TARGET_RESET 0x20 /* bit 5 */ 866 #define CLEAR_ACA 0x40 /* bit 6 */ 867 #define TERMINATE_TASK 0x80 /* bit 7 */ 868 869 uint8_t fcpCntl3; 870 #define WRITE_DATA 0x01 /* Bit 0 */ 871 #define READ_DATA 0x02 /* Bit 1 */ 872 873 uint8_t fcpCdb[16]; /* SRB cdb field is copied here */ 874 uint32_t fcpDl; /* Total transfer length */ 875 } emlxs_fcp_cmd_t; 876 typedef emlxs_fcp_cmd_t FCP_CMND; 877 878 879 880 881 /* SCSI INQUIRY Command Structure */ 882 883 typedef struct emlxs_inquiryDataType 884 { 885 uint8_t DeviceType:5; 886 uint8_t DeviceTypeQualifier:3; 887 888 uint8_t DeviceTypeModifier:7; 889 uint8_t RemovableMedia:1; 890 891 uint8_t Versions; 892 uint8_t ResponseDataFormat; 893 uint8_t AdditionalLength; 894 uint8_t Reserved[2]; 895 896 uint8_t SoftReset:1; 897 uint8_t CommandQueue:1; 898 uint8_t Reserved2:1; 899 uint8_t LinkedCommands:1; 900 uint8_t Synchronous:1; 901 uint8_t Wide16Bit:1; 902 uint8_t Wide32Bit:1; 903 uint8_t RelativeAddressing:1; 904 905 uint8_t VendorId[8]; 906 uint8_t ProductId[16]; 907 uint8_t ProductRevisionLevel[4]; 908 uint8_t VendorSpecific[20]; 909 uint8_t Reserved3[40]; 910 } emlxs_inquiry_data_type_t; 911 typedef emlxs_inquiry_data_type_t INQUIRY_DATA_DEF; 912 913 914 typedef struct emlxs_read_capacity_data 915 { 916 uint32_t LogicalBlockAddress; 917 uint32_t BytesPerBlock; 918 } emlxs_read_capacity_data_t; 919 typedef emlxs_read_capacity_data_t READ_CAPACITY_DATA_DEF; 920 921 922 /* SCSI CDB command codes */ 923 #define FCP_SCSI_FORMAT_UNIT 0x04 924 #define FCP_SCSI_INQUIRY 0x12 925 #define FCP_SCSI_MODE_SELECT 0x15 926 #define FCP_SCSI_MODE_SENSE 0x1A 927 #define FCP_SCSI_PAUSE_RESUME 0x4B 928 #define FCP_SCSI_PLAY_AUDIO 0x45 929 #define FCP_SCSI_PLAY_AUDIO_EXT 0xA5 930 #define FCP_SCSI_PLAY_AUDIO_MSF 0x47 931 #define FCP_SCSI_PLAY_AUDIO_TRK_INDX 0x48 932 #define FCP_SCSI_PREVENT_ALLOW_REMOVAL 0x1E 933 #define FCP_SCSI_READ_CMD 0x08 934 #define FCP_SCSI_READ_BUFFER 0x3C 935 #define FCP_SCSI_READ_CAPACITY 0x25 936 #define FCP_SCSI_READ_DEFECT_LIST 0x37 937 #define FCP_SCSI_READ_EXTENDED 0x28 938 #define FCP_SCSI_READ_HEADER 0x44 939 #define FCP_SCSI_READ_LONG 0xE8 940 #define FCP_SCSI_READ_SUB_CHANNEL 0x42 941 #define FCP_SCSI_READ_TOC 0x43 942 #define FCP_SCSI_REASSIGN_BLOCK 0x07 943 #define FCP_SCSI_RECEIVE_DIAGNOSTIC_RESULTS 0x1C 944 #define FCP_SCSI_RELEASE_UNIT 0x17 945 #define FCP_SCSI_REPORT_LUNS 0xa0 946 #define FCP_SCSI_REQUEST_SENSE 0x03 947 #define FCP_SCSI_RESERVE_UNIT 0x16 948 #define FCP_SCSI_REZERO_UNIT 0x01 949 #define FCP_SCSI_SEEK 0x0B 950 #define FCP_SCSI_SEEK_EXTENDED 0x2B 951 #define FCP_SCSI_SEND_DIAGNOSTIC 0x1D 952 #define FCP_SCSI_START_STOP_UNIT 0x1B 953 #define FCP_SCSI_TEST_UNIT_READY 0x00 954 #define FCP_SCSI_VERIFY 0x2F 955 #define FCP_SCSI_WRITE_CMD 0x0A 956 #define FCP_SCSI_WRITE_AND_VERIFY 0x2E 957 #define FCP_SCSI_WRITE_BUFFER 0x3B 958 #define FCP_SCSI_WRITE_EXTENDED 0x2A 959 #define FCP_SCSI_WRITE_LONG 0xEA 960 #define FCP_SCSI_RELEASE_LUNR 0xBB 961 #define FCP_SCSI_RELEASE_LUNV 0xBF 962 963 #define HPVA_SETPASSTHROUGHMODE 0x27 964 #define HPVA_EXECUTEPASSTHROUGH 0x29 965 #define HPVA_CREATELUN 0xE2 966 #define HPVA_SETLUNSECURITYLIST 0xED 967 #define HPVA_SETCLOCK 0xF9 968 #define HPVA_RECOVER 0xFA 969 #define HPVA_GENERICSERVICEOUT 0xFD 970 971 #define DMEP_EXPORT_IN 0x85 972 #define DMEP_EXPORT_OUT 0x89 973 974 #define MDACIOCTL_DIRECT_CMD 0x22 975 #define MDACIOCTL_STOREIMAGE 0x2C 976 #define MDACIOCTL_WRITESIGNATURE 0xA6 977 #define MDACIOCTL_SETREALTIMECLOCK 0xAC 978 #define MDACIOCTL_PASS_THRU_CDB 0xAD 979 #define MDACIOCTL_PASS_THRU_INITIATE 0xAE 980 #define MDACIOCTL_CREATENEWCONF 0xC0 981 #define MDACIOCTL_ADDNEWCONF 0xC4 982 #define MDACIOCTL_MORE 0xC6 983 #define MDACIOCTL_SETPHYSDEVPARAMETER 0xC8 984 #define MDACIOCTL_SETLOGDEVPARAMETER 0xCF 985 #define MDACIOCTL_SETCONTROLLERPARAMETER 0xD1 986 #define MDACIOCTL_WRITESANMAP 0xD4 987 #define MDACIOCTL_SETMACADDRESS 0xD5 988 989 /* 990 * End of FCP specific structures 991 */ 992 993 #define FL_ALPA 0x00 /* AL_PA of FL_Port */ 994 995 /* Fibre Channel Service Parameter definitions */ 996 997 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 998 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 999 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 1000 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 1001 1002 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 1003 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 1004 #define FC_PH3 0x20 /* FC-PH-3 version */ 1005 1006 #define FF_FRAME_SIZE 2048 1007 1008 1009 typedef struct emlxs_rings 1010 { 1011 #ifdef EMLXS_BIG_ENDIAN 1012 uint32_t crReserved:16; 1013 uint32_t crBegin:8; 1014 uint32_t crEnd:8; /* Low order bit first word */ 1015 uint32_t rrReserved:16; 1016 uint32_t rrBegin:8; 1017 uint32_t rrEnd:8; /* Low order bit second word */ 1018 #endif 1019 #ifdef EMLXS_LITTLE_ENDIAN 1020 uint32_t crEnd:8; /* Low order bit first word */ 1021 uint32_t crBegin:8; 1022 uint32_t crReserved:16; 1023 uint32_t rrEnd:8; /* Low order bit second word */ 1024 uint32_t rrBegin:8; 1025 uint32_t rrReserved:16; 1026 #endif 1027 } emlxs_rings_t; 1028 typedef emlxs_rings_t RINGS; 1029 1030 1031 typedef struct emlxs_ring_def 1032 { 1033 #ifdef EMLXS_BIG_ENDIAN 1034 uint16_t offCiocb; 1035 uint16_t numCiocb; 1036 uint16_t offRiocb; 1037 uint16_t numRiocb; 1038 #endif 1039 #ifdef EMLXS_LITTLE_ENDIAN 1040 uint16_t numCiocb; 1041 uint16_t offCiocb; 1042 uint16_t numRiocb; 1043 uint16_t offRiocb; 1044 #endif 1045 } emlxs_ring_def_t; 1046 typedef emlxs_ring_def_t RING_DEF; 1047 1048 /* 1049 * The following F.C. frame stuctures are defined in Big Endian format. 1050 */ 1051 1052 typedef struct emlxs_name_type 1053 { 1054 #ifdef EMLXS_BIG_ENDIAN 1055 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 1056 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 */ 1057 /* of IEEE ext */ 1058 #endif 1059 #ifdef EMLXS_LITTLE_ENDIAN 1060 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 */ 1061 /* of IEEE ext */ 1062 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 1063 #endif 1064 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 1065 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 1066 #define NAME_FC_TYPE 0x3 /* FC native name type */ 1067 #define NAME_IP_TYPE 0x4 /* IP address */ 1068 #define NAME_CCITT_TYPE 0xC 1069 #define NAME_CCITT_GR_TYPE 0xE 1070 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, */ 1071 /* IEEE extended Lsb */ 1072 uint8_t IEEE[6]; /* FC IEEE address */ 1073 } emlxs_name_type_t; 1074 typedef emlxs_name_type_t NAME_TYPE; 1075 1076 1077 typedef struct emlxs_csp 1078 { 1079 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 1080 uint8_t fcphLow; 1081 uint8_t bbCreditMsb; 1082 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 1083 #ifdef EMLXS_BIG_ENDIAN 1084 uint16_t reqMultipleNPort:1; /* FC Word 1, bit 31 */ 1085 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 1086 uint16_t rspMultipleNPort:1; /* FC Word 1, bit 29 */ 1087 uint16_t fPort:1; /* FC Word 1, bit 28 */ 1088 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 1089 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 1090 uint16_t multicast:1; /* FC Word 1, bit 25 */ 1091 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 1092 1093 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 1094 uint16_t simplex:1; /* FC Word 1, bit 22 */ 1095 1096 uint16_t fcsp_support:1; /* FC Word 1, bit 21 */ 1097 uint16_t word1Reserved20:1; /* FC Word 1, bit 20 */ 1098 uint16_t word1Reserved19:1; /* FC Word 1, bit 19 */ 1099 1100 uint16_t dhd:1; /* FC Word 1, bit 18 */ 1101 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 1102 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 1103 #endif 1104 #ifdef EMLXS_LITTLE_ENDIAN 1105 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 1106 uint16_t multicast:1; /* FC Word 1, bit 25 */ 1107 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 1108 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 1109 uint16_t fPort:1; /* FC Word 1, bit 28 */ 1110 uint16_t rspMultipleNPort:1; /* FC Word 1, bit 29 */ 1111 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 1112 uint16_t reqMultipleNPort:1; /* FC Word 1, bit 31 */ 1113 1114 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 1115 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 1116 uint16_t dhd:1; /* FC Word 1, bit 18 */ 1117 1118 uint16_t word1Reserved19:1; /* FC Word 1, bit 19 */ 1119 uint16_t word1Reserved20:1; /* FC Word 1, bit 20 */ 1120 uint16_t fcsp_support:1; /* FC Word 1, bit 21 */ 1121 1122 uint16_t simplex:1; /* FC Word 1, bit 22 */ 1123 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 1124 #endif 1125 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 1126 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 1127 union 1128 { 1129 struct 1130 { 1131 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 1132 1133 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 1134 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 1135 1136 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 1137 } nPort; 1138 uint32_t r_a_tov; /* R_A_TOV must be in Big */ 1139 /* Endian format */ 1140 } w2; 1141 1142 uint32_t e_d_tov; /* E_D_TOV must be in Big */ 1143 /* Endian format */ 1144 } emlxs_csp_t; 1145 typedef emlxs_csp_t CSP; 1146 1147 1148 typedef struct emlxs_class_parms 1149 { 1150 #ifdef EMLXS_BIG_ENDIAN 1151 uint8_t classValid:1; /* FC Word 0, bit 31 */ 1152 uint8_t intermix:1; /* FC Word 0, bit 30 */ 1153 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 1154 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 1155 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 1156 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 1157 #endif 1158 #ifdef EMLXS_LITTLE_ENDIAN 1159 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 1160 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 1161 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 1162 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 1163 uint8_t intermix:1; /* FC Word 0, bit 30 */ 1164 uint8_t classValid:1; /* FC Word 0, bit 31 */ 1165 1166 #endif 1167 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 1168 #ifdef EMLXS_BIG_ENDIAN 1169 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 1170 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 1171 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 1172 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 1173 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 1174 #endif 1175 #ifdef EMLXS_LITTLE_ENDIAN 1176 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 1177 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 1178 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 1179 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 1180 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 1181 #endif 1182 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 1183 #ifdef EMLXS_BIG_ENDIAN 1184 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 1185 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 1186 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 1187 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 1188 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 1189 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 1190 #endif 1191 #ifdef EMLXS_LITTLE_ENDIAN 1192 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 1193 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 1194 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 1195 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 1196 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 1197 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 1198 #endif 1199 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 1200 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 1201 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 1202 1203 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 1204 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 1205 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 1206 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 1207 1208 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 1209 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 1210 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 1211 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 1212 } emlxs_class_parms_t; 1213 typedef emlxs_class_parms_t CLASS_PARMS; 1214 1215 1216 typedef struct emlxs_serv_parms 1217 { /* Structure is in Big Endian format */ 1218 CSP cmn; 1219 NAME_TYPE portName; 1220 NAME_TYPE nodeName; 1221 CLASS_PARMS cls1; 1222 CLASS_PARMS cls2; 1223 CLASS_PARMS cls3; 1224 CLASS_PARMS cls4; 1225 uint8_t vendorVersion[16]; 1226 } emlxs_serv_parms_t; 1227 typedef emlxs_serv_parms_t SERV_PARM; 1228 1229 typedef struct 1230 { 1231 union 1232 { 1233 uint32_t word0; 1234 struct 1235 { 1236 #ifdef EMLXS_BIG_ENDIAN 1237 uint32_t rsvd0:8; /* Word 0, Byte 3 */ 1238 uint32_t oui:24; /* Elx Organization */ 1239 /* Unique ID (0000C9) */ 1240 #endif 1241 #ifdef EMLXS_LITTLE_ENDIAN 1242 uint32_t oui:24; /* Elx Organization */ 1243 /* Unique ID (0000C9) */ 1244 uint32_t rsvd0:8; /* Word 0, Byte 3 */ 1245 #endif 1246 } w0; 1247 } un0; 1248 union 1249 { 1250 uint32_t word1; 1251 struct 1252 { 1253 #ifdef EMLXS_BIG_ENDIAN 1254 uint32_t vport:1; /* Word 1, Bit 31 */ 1255 uint32_t rsvd1:31; /* Word 1, Bit 0-30 */ 1256 #endif 1257 #ifdef EMLXS_LITTLE_ENDIAN 1258 uint32_t rsvd1:31; /* Word 1, Bit 0-30 */ 1259 uint32_t vport:1; /* Word 1, Bit 31 */ 1260 #endif 1261 } w1; 1262 } un1; 1263 uint8_t rsvd2[8]; 1264 } emlxs_vvl_fmt_t; 1265 1266 #define VALID_VENDOR_VERSION cmn.rspMultipleNPort 1267 1268 1269 1270 /* 1271 * Extended Link Service LS_COMMAND codes (Payload BYTE 0) 1272 */ 1273 #ifdef EMLXS_BIG_ENDIAN 1274 #define ELS_CMD_SHIFT 24 1275 #define ELS_CMD_MASK 0xff000000 1276 #define ELS_RSP_MASK 0xff000000 1277 #define ELS_CMD_LS_RJT 0x01000000 1278 #define ELS_CMD_ACC 0x02000000 1279 #define ELS_CMD_PLOGI 0x03000000 1280 #define ELS_CMD_FLOGI 0x04000000 1281 #define ELS_CMD_LOGO 0x05000000 1282 #define ELS_CMD_ABTX 0x06000000 1283 #define ELS_CMD_RCS 0x07000000 1284 #define ELS_CMD_RES 0x08000000 1285 #define ELS_CMD_RSS 0x09000000 1286 #define ELS_CMD_RSI 0x0A000000 1287 #define ELS_CMD_ESTS 0x0B000000 1288 #define ELS_CMD_ESTC 0x0C000000 1289 #define ELS_CMD_ADVC 0x0D000000 1290 #define ELS_CMD_RTV 0x0E000000 1291 #define ELS_CMD_RLS 0x0F000000 1292 #define ELS_CMD_ECHO 0x10000000 1293 #define ELS_CMD_TEST 0x11000000 1294 #define ELS_CMD_RRQ 0x12000000 1295 #define ELS_CMD_PRLI 0x20000000 1296 #define ELS_CMD_PRLO 0x21000000 1297 #define ELS_CMD_SCN 0x22000000 1298 #define ELS_CMD_TPLS 0x23000000 1299 #define ELS_CMD_GPRLO 0x24000000 1300 #define ELS_CMD_GAID 0x30000000 1301 #define ELS_CMD_FACT 0x31000000 1302 #define ELS_CMD_FDACT 0x32000000 1303 #define ELS_CMD_NACT 0x33000000 1304 #define ELS_CMD_NDACT 0x34000000 1305 #define ELS_CMD_QoSR 0x40000000 1306 #define ELS_CMD_RVCS 0x41000000 1307 #define ELS_CMD_PDISC 0x50000000 1308 #define ELS_CMD_FDISC 0x51000000 1309 #define ELS_CMD_ADISC 0x52000000 1310 #define ELS_CMD_FARP 0x54000000 1311 #define ELS_CMD_FARPR 0x55000000 1312 #define ELS_CMD_FAN 0x60000000 1313 #define ELS_CMD_RSCN 0x61000000 1314 #define ELS_CMD_SCR 0x62000000 1315 #define ELS_CMD_LINIT 0x70000000 1316 #define ELS_CMD_RNID 0x78000000 1317 #define ELS_CMD_AUTH 0x90000000 1318 #endif 1319 1320 #ifdef EMLXS_LITTLE_ENDIAN 1321 #define ELS_CMD_SHIFT 0 1322 #define ELS_CMD_MASK 0xff 1323 #define ELS_RSP_MASK 0xff 1324 #define ELS_CMD_LS_RJT 0x01 1325 #define ELS_CMD_ACC 0x02 1326 #define ELS_CMD_PLOGI 0x03 1327 #define ELS_CMD_FLOGI 0x04 1328 #define ELS_CMD_LOGO 0x05 1329 #define ELS_CMD_ABTX 0x06 1330 #define ELS_CMD_RCS 0x07 1331 #define ELS_CMD_RES 0x08 1332 #define ELS_CMD_RSS 0x09 1333 #define ELS_CMD_RSI 0x0A 1334 #define ELS_CMD_ESTS 0x0B 1335 #define ELS_CMD_ESTC 0x0C 1336 #define ELS_CMD_ADVC 0x0D 1337 #define ELS_CMD_RTV 0x0E 1338 #define ELS_CMD_RLS 0x0F 1339 #define ELS_CMD_ECHO 0x10 1340 #define ELS_CMD_TEST 0x11 1341 #define ELS_CMD_RRQ 0x12 1342 #define ELS_CMD_PRLI 0x20 1343 #define ELS_CMD_PRLO 0x21 1344 #define ELS_CMD_SCN 0x22 1345 #define ELS_CMD_TPLS 0x23 1346 #define ELS_CMD_GPRLO 0x24 1347 #define ELS_CMD_GAID 0x30 1348 #define ELS_CMD_FACT 0x31 1349 #define ELS_CMD_FDACT 0x32 1350 #define ELS_CMD_NACT 0x33 1351 #define ELS_CMD_NDACT 0x34 1352 #define ELS_CMD_QoSR 0x40 1353 #define ELS_CMD_RVCS 0x41 1354 #define ELS_CMD_PDISC 0x50 1355 #define ELS_CMD_FDISC 0x51 1356 #define ELS_CMD_ADISC 0x52 1357 #define ELS_CMD_FARP 0x54 1358 #define ELS_CMD_FARPR 0x55 1359 #define ELS_CMD_FAN 0x60 1360 #define ELS_CMD_RSCN 0x61 1361 #define ELS_CMD_SCR 0x62 1362 #define ELS_CMD_LINIT 0x70 1363 #define ELS_CMD_RNID 0x78 1364 #define ELS_CMD_AUTH 0x90 1365 #endif 1366 1367 1368 /* 1369 * LS_RJT Payload Definition 1370 */ 1371 1372 typedef struct _LS_RJT 1373 { /* Structure is in Big Endian format */ 1374 union 1375 { 1376 uint32_t lsRjtError; 1377 struct 1378 { 1379 uint8_t lsRjtRsvd0; /* FC Word 0, */ 1380 /* bit 24:31 */ 1381 1382 uint8_t lsRjtRsnCode; /* FC Word 0, */ 1383 /* bit 16:23 */ 1384 /* LS_RJT reason codes */ 1385 #define LSRJT_INVALID_CMD 0x01 1386 #define LSRJT_LOGICAL_ERR 0x03 1387 #define LSRJT_LOGICAL_BSY 0x05 1388 #define LSRJT_PROTOCOL_ERR 0x07 1389 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 1390 #define LSRJT_CMD_UNSUPPORTED 0x0B 1391 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 1392 1393 uint8_t lsRjtRsnCodeExp; /* FC Word 0, */ 1394 /* bit 8:15 */ 1395 /* LS_RJT reason explanation */ 1396 #define LSEXP_NOTHING_MORE 0x00 1397 #define LSEXP_SPARM_OPTIONS 0x01 1398 #define LSEXP_SPARM_ICTL 0x03 1399 #define LSEXP_SPARM_RCTL 0x05 1400 #define LSEXP_SPARM_RCV_SIZE 0x07 1401 #define LSEXP_SPARM_CONCUR_SEQ 0x09 1402 #define LSEXP_SPARM_CREDIT 0x0B 1403 #define LSEXP_INVALID_PNAME 0x0D 1404 #define LSEXP_INVALID_NNAME 0x0E 1405 #define LSEXP_INVALID_CSP 0x0F 1406 #define LSEXP_INVALID_ASSOC_HDR 0x11 1407 #define LSEXP_ASSOC_HDR_REQ 0x13 1408 #define LSEXP_INVALID_O_SID 0x15 1409 #define LSEXP_INVALID_OX_RX 0x17 1410 #define LSEXP_CMD_IN_PROGRESS 0x19 1411 #define LSEXP_INVALID_NPORT_ID 0x1F 1412 #define LSEXP_INVALID_SEQ_ID 0x21 1413 #define LSEXP_INVALID_XCHG 0x23 1414 #define LSEXP_INACTIVE_XCHG 0x25 1415 #define LSEXP_RQ_REQUIRED 0x27 1416 #define LSEXP_OUT_OF_RESOURCE 0x29 1417 #define LSEXP_CANT_GIVE_DATA 0x2A 1418 #define LSEXP_REQ_UNSUPPORTED 0x2C 1419 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 1420 } b; 1421 } un; 1422 } LS_RJT; 1423 1424 1425 /* 1426 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 1427 */ 1428 1429 typedef struct _LOGO 1430 { /* Structure is in Big Endian format */ 1431 union 1432 { 1433 uint32_t nPortId32; /* Access nPortId as a word */ 1434 struct 1435 { 1436 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 1437 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 1438 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 1439 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 1440 } b; 1441 } un; 1442 NAME_TYPE portName; /* N_port name field */ 1443 } LOGO; 1444 1445 1446 /* 1447 * FCP Login (PRLI Request / ACC) Payload Definition 1448 */ 1449 1450 #define PRLX_PAGE_LEN 0x10 1451 #define TPRLO_PAGE_LEN 0x14 1452 1453 typedef struct _PRLI 1454 { /* Structure is in Big Endian format */ 1455 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 1456 1457 #define PRLI_FCP_TYPE 0x08 1458 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 1459 1460 #ifdef EMLXS_BIG_ENDIAN 1461 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1462 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1463 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 1464 1465 /* ACC = imagePairEstablished */ 1466 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 1467 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1468 /* ACC ONLY */ 1469 #endif 1470 #ifdef EMLXS_LITTLE_ENDIAN 1471 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1472 /* ACC ONLY */ 1473 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 1474 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 1475 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1476 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1477 /* ACC = imagePairEstablished */ 1478 #endif 1479 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 1480 #define PRLI_NO_RESOURCES 0x2 1481 #define PRLI_INIT_INCOMPLETE 0x3 1482 #define PRLI_NO_SUCH_PA 0x4 1483 #define PRLI_PREDEF_CONFIG 0x5 1484 #define PRLI_PARTIAL_SUCCESS 0x6 1485 #define PRLI_INVALID_PAGE_CNT 0x7 1486 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 1487 1488 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 1489 1490 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 1491 1492 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 1493 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 1494 #ifdef EMLXS_BIG_ENDIAN 1495 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 1496 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 1497 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 1498 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 1499 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 1500 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 1501 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 1502 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 1503 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 1504 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 1505 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 1506 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 1507 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 1508 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 1509 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 1510 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 1511 #endif 1512 #ifdef EMLXS_LITTLE_ENDIAN 1513 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 1514 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 1515 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 1516 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 1517 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 1518 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 1519 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 1520 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 1521 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 1522 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 1523 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 1524 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 1525 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 1526 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 1527 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 1528 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 1529 #endif 1530 } PRLI; 1531 1532 /* 1533 * FCP Logout (PRLO Request / ACC) Payload Definition 1534 */ 1535 1536 typedef struct _PRLO 1537 { /* Structure is in Big Endian format */ 1538 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 1539 1540 #define PRLO_FCP_TYPE 0x08 1541 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 1542 1543 #ifdef EMLXS_BIG_ENDIAN 1544 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1545 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1546 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 1547 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1548 /* ACC ONLY */ 1549 #endif 1550 #ifdef EMLXS_LITTLE_ENDIAN 1551 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1552 /* ACC ONLY */ 1553 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 1554 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1555 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1556 #endif 1557 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 1558 #define PRLO_NO_SUCH_IMAGE 0x4 1559 #define PRLO_INVALID_PAGE_CNT 0x7 1560 1561 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 1562 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 1563 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 1564 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 1565 } PRLO; 1566 1567 1568 typedef struct _ADISC 1569 { /* Structure is in Big Endian format */ 1570 uint32_t hardAL_PA; 1571 NAME_TYPE portName; 1572 NAME_TYPE nodeName; 1573 uint32_t DID; 1574 } ADISC; 1575 1576 1577 typedef struct _FARP 1578 { /* Structure is in Big Endian format */ 1579 uint32_t Mflags:8; 1580 uint32_t Odid:24; 1581 #define FARP_NO_ACTION 0 /* FARP information enclosed, no action */ 1582 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 1583 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 1584 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 1585 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not supported */ 1586 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not supported */ 1587 uint32_t Rflags:8; 1588 uint32_t Rdid:24; 1589 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 1590 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 1591 NAME_TYPE OportName; 1592 NAME_TYPE OnodeName; 1593 NAME_TYPE RportName; 1594 NAME_TYPE RnodeName; 1595 uint8_t Oipaddr[16]; 1596 uint8_t Ripaddr[16]; 1597 } FARP; 1598 1599 typedef struct _FAN 1600 { /* Structure is in Big Endian format */ 1601 uint32_t Fdid; 1602 NAME_TYPE FportName; 1603 NAME_TYPE FnodeName; 1604 } FAN; 1605 1606 typedef struct _SCR 1607 { /* Structure is in Big Endian format */ 1608 uint8_t resvd1; 1609 uint8_t resvd2; 1610 uint8_t resvd3; 1611 uint8_t Function; 1612 #define SCR_FUNC_FABRIC 0x01 1613 #define SCR_FUNC_NPORT 0x02 1614 #define SCR_FUNC_FULL 0x03 1615 #define SCR_CLEAR 0xff 1616 } SCR; 1617 1618 typedef struct _RNID_TOP_DISC 1619 { 1620 NAME_TYPE portName; 1621 uint8_t resvd[8]; 1622 uint32_t unitType; 1623 #define RNID_HBA 0x7 1624 #define RNID_HOST 0xa 1625 #define RNID_DRIVER 0xd 1626 uint32_t physPort; 1627 uint32_t attachedNodes; 1628 uint16_t ipVersion; 1629 #define RNID_IPV4 0x1 1630 #define RNID_IPV6 0x2 1631 uint16_t UDPport; 1632 uint8_t ipAddr[16]; 1633 uint16_t resvd1; 1634 uint16_t flags; 1635 #define RNID_TD_SUPPORT 0x1 1636 #define RNID_LP_VALID 0x2 1637 } RNID_TOP_DISC; 1638 1639 typedef struct _RNID 1640 { /* Structure is in Big Endian format */ 1641 uint8_t Format; 1642 #define RNID_TOPOLOGY_DISC 0xdf 1643 uint8_t CommonLen; 1644 uint8_t resvd1; 1645 uint8_t SpecificLen; 1646 NAME_TYPE portName; 1647 NAME_TYPE nodeName; 1648 union 1649 { 1650 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 1651 } un; 1652 } RNID; 1653 1654 typedef struct _RRQ 1655 { /* Structure is in Big Endian format */ 1656 uint32_t SID; 1657 uint16_t Oxid; 1658 uint16_t Rxid; 1659 uint8_t resv[32]; /* optional association hdr */ 1660 } RRQ; 1661 1662 1663 /* This is used for RSCN command */ 1664 typedef struct _D_ID 1665 { /* Structure is in Big Endian format */ 1666 union 1667 { 1668 uint32_t word; 1669 struct 1670 { 1671 #ifdef EMLXS_BIG_ENDIAN 1672 uint8_t resv; 1673 uint8_t domain; 1674 uint8_t area; 1675 uint8_t id; 1676 #endif 1677 #ifdef EMLXS_LITTLE_ENDIAN 1678 uint8_t id; 1679 uint8_t area; 1680 uint8_t domain; 1681 uint8_t resv; 1682 #endif 1683 } b; 1684 } un; 1685 } D_ID; 1686 1687 /* 1688 * Structure to define all ELS Payload types 1689 */ 1690 1691 typedef struct _ELS_PKT 1692 { /* Structure is in Big Endian format */ 1693 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 1694 uint8_t elsByte1; 1695 uint8_t elsByte2; 1696 uint8_t elsByte3; 1697 union 1698 { 1699 LS_RJT lsRjt; /* Payload for LS_RJT */ 1700 SERV_PARM logi; /* Payload for PLOGI, FLOGI */ 1701 /* PDISC, ACC */ 1702 LOGO logo; /* Payload for PLOGO, FLOGO */ 1703 /* ACC */ 1704 PRLI prli; /* Payload for PRLI/ACC */ 1705 PRLO prlo; /* Payload for PRLO/ACC */ 1706 ADISC adisc; /* Payload for ADISC/ACC */ 1707 FARP farp; /* Payload for FARP/ACC */ 1708 FAN fan; /* Payload for FAN */ 1709 SCR scr; /* Payload for SCR/ACC */ 1710 RRQ rrq; /* Payload for RRQ */ 1711 RNID rnid; /* Payload for RNID */ 1712 uint8_t pad[128 - 4]; /* Pad out to payload of */ 1713 /* 128 bytes */ 1714 } un; 1715 } ELS_PKT; 1716 1717 1718 typedef struct 1719 { 1720 uint32_t bdeAddress; 1721 #ifdef EMLXS_BIG_ENDIAN 1722 uint32_t bdeReserved:4; 1723 uint32_t bdeAddrHigh:4; 1724 uint32_t bdeSize:24; 1725 #endif 1726 #ifdef EMLXS_LITTLE_ENDIAN 1727 uint32_t bdeSize:24; 1728 uint32_t bdeAddrHigh:4; 1729 uint32_t bdeReserved:4; 1730 #endif 1731 } ULP_BDE; 1732 1733 typedef struct ULP_BDE_64 1734 { /* SLI-2 */ 1735 union ULP_BDE_TUS 1736 { 1737 uint32_t w; 1738 struct 1739 { 1740 #ifdef EMLXS_BIG_ENDIAN 1741 uint32_t bdeFlags:8; /* BDE Flags 0 IS A */ 1742 /* SUPPORTED VALUE !! */ 1743 uint32_t bdeSize:24; /* buff size in bytes */ 1744 #endif 1745 #ifdef EMLXS_LITTLE_ENDIAN 1746 uint32_t bdeSize:24; /* buff size in bytes */ 1747 uint32_t bdeFlags:8; /* BDE Flags 0 IS A */ 1748 /* SUPPORTED VALUE !! */ 1749 #endif 1750 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 1751 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 1752 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 1753 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, */ 1754 /* 0=xmit buffer */ 1755 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr */ 1756 /* 0=64 bit addr */ 1757 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 1758 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 1759 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 1760 } f; 1761 } tus; 1762 uint32_t addrLow; 1763 uint32_t addrHigh; 1764 } ULP_BDE64; 1765 1766 #define BDE64_SIZE_WORD 0 1767 #define BPL64_SIZE_WORD 0x40 1768 1769 /* ULP */ 1770 typedef struct ULP_BPL_64 1771 { 1772 ULP_BDE64 fccmd_payload; 1773 ULP_BDE64 fcrsp_payload; 1774 ULP_BDE64 fcdat_payload; 1775 ULP_BDE64 pat0; 1776 } ULP_BPL64; 1777 1778 typedef struct ULP_BDL 1779 { /* SLI-2 */ 1780 #ifdef EMLXS_BIG_ENDIAN 1781 uint32_t bdeFlags:8; /* BDL Flags */ 1782 uint32_t bdeSize:24; /* Size of BDL array in host */ 1783 /* memory (bytes) */ 1784 #endif 1785 #ifdef EMLXS_LITTLE_ENDIAN 1786 uint32_t bdeSize:24; /* Size of BDL array in host */ 1787 /* memory (bytes) */ 1788 uint32_t bdeFlags:8; /* BDL Flags */ 1789 #endif 1790 uint32_t addrLow; /* Address 0:31 */ 1791 uint32_t addrHigh; /* Address 32:63 */ 1792 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1793 } ULP_BDL; 1794 1795 typedef struct ULP_SGE_64 1796 { /* SLI-4 */ 1797 uint32_t addrHigh; /* Address 32:63 */ 1798 uint32_t addrLow; /* Address 0:31 */ 1799 #ifdef EMLXS_BIG_ENDIAN 1800 uint32_t last:1; /* Last entry in SGL */ 1801 uint32_t reserved:11; 1802 uint32_t offset:20; 1803 #endif 1804 #ifdef EMLXS_LITTLE_ENDIAN 1805 uint32_t offset:20; 1806 uint32_t reserved:11; 1807 uint32_t last:1; /* Last entry in SGL */ 1808 #endif 1809 uint32_t length; 1810 #define EMLXS_MAX_SGE_SIZE 0x10000 /* 64K max length */ 1811 } ULP_SGE64; 1812 1813 1814 typedef struct _BE_PHYS_ADDR 1815 { 1816 uint32_t addrLow; 1817 uint32_t addrHigh; 1818 } BE_PHYS_ADDR; 1819 1820 1821 typedef struct 1822 { 1823 uint8_t *fc_mptr; 1824 struct emlxs_memseg *segment; /* Parent segment */ 1825 1826 uint8_t *virt; /* virtual address ptr */ 1827 uint64_t phys; /* mapped address */ 1828 uint32_t size; 1829 1830 void *data_handle; 1831 void *dma_handle; 1832 uint32_t tag; 1833 uint32_t flag; 1834 #define MAP_POOL_ALLOCATED 0x00000001 1835 #define MAP_BUF_ALLOCATED 0x00000002 1836 #define MAP_TABLE_ALLOCATED 0x00000004 1837 } MATCHMAP; 1838 1839 1840 /* 1841 * This file defines the Header File for the FDMI HBA Management Service 1842 */ 1843 1844 /* 1845 * FDMI HBA MAnagement Operations Command Codes 1846 */ 1847 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1848 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1849 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1850 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1851 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1852 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 1853 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1854 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1855 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1856 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1857 1858 /* 1859 * Management Service Subtypes 1860 */ 1861 #define SLI_CT_FDMI_SUBTYPES 0x10 1862 1863 1864 /* 1865 * HBA Management Service Reject Code 1866 */ 1867 #define REJECT_CODE 0x9 /* Unable to perform command request */ 1868 1869 /* 1870 * HBA Management Service Reject Reason Code 1871 * Please refer to the Reason Codes above 1872 */ 1873 1874 /* 1875 * HBA Attribute Types 1876 */ 1877 #define NODE_NAME 0x1 1878 #define MANUFACTURER 0x2 1879 #define SERIAL_NUMBER 0x3 1880 #define MODEL 0x4 1881 #define MODEL_DESCRIPTION 0x5 1882 #define HARDWARE_VERSION 0x6 1883 #define DRIVER_VERSION 0x7 1884 #define OPTION_ROM_VERSION 0x8 1885 #define FIRMWARE_VERSION 0x9 1886 #define VENDOR_SPECIFIC 0xa 1887 #define DRV_NAME 0xb 1888 #define OS_NAME_VERSION 0xc 1889 #define MAX_CT_PAYLOAD_LEN 0xd 1890 1891 /* 1892 * Port Attrubute Types 1893 */ 1894 #define SUPPORTED_FC4_TYPES 0x1 1895 #define SUPPORTED_SPEED 0x2 1896 #define PORT_SPEED 0x3 1897 #define MAX_FRAME_SIZE 0x4 1898 #define OS_DEVICE_NAME 0x5 1899 1900 union AttributesDef 1901 { 1902 /* Structure is in Big Endian format */ 1903 struct 1904 { 1905 uint32_t AttrType:16; 1906 uint32_t AttrLen:16; 1907 } bits; 1908 uint32_t word; 1909 }; 1910 1911 /* 1912 * HBA Attribute Entry (8 - 260 bytes) 1913 */ 1914 typedef struct 1915 { 1916 union AttributesDef ad; 1917 union 1918 { 1919 uint32_t VendorSpecific; 1920 uint32_t SupportSpeed; 1921 uint32_t PortSpeed; 1922 uint32_t MaxFrameSize; 1923 uint32_t MaxCTPayloadLen; 1924 uint8_t SupportFC4Types[32]; 1925 uint8_t OsDeviceName[256]; 1926 uint8_t Manufacturer[64]; 1927 uint8_t SerialNumber[64]; 1928 uint8_t Model[256]; 1929 uint8_t ModelDescription[256]; 1930 uint8_t HardwareVersion[256]; 1931 uint8_t DriverVersion[256]; 1932 uint8_t OptionROMVersion[256]; 1933 uint8_t FirmwareVersion[256]; 1934 uint8_t DriverName[256]; 1935 NAME_TYPE NodeName; 1936 } un; 1937 } ATTRIBUTE_ENTRY, *PATTRIBUTE_ENTRY; 1938 1939 1940 /* 1941 * HBA Attribute Block 1942 */ 1943 typedef struct 1944 { 1945 uint32_t EntryCnt; /* Number of HBA attribute entries */ 1946 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 1947 } ATTRIBUTE_BLOCK, *PATTRIBUTE_BLOCK; 1948 1949 1950 /* 1951 * Port Entry 1952 */ 1953 typedef struct 1954 { 1955 NAME_TYPE PortName; 1956 } PORT_ENTRY, *PPORT_ENTRY; 1957 1958 /* 1959 * HBA Identifier 1960 */ 1961 typedef struct 1962 { 1963 NAME_TYPE PortName; 1964 } HBA_IDENTIFIER, *PHBA_IDENTIFIER; 1965 1966 /* 1967 * Registered Port List Format 1968 */ 1969 typedef struct 1970 { 1971 uint32_t EntryCnt; 1972 PORT_ENTRY pe; /* Variable-length array */ 1973 } REG_PORT_LIST, *PREG_PORT_LIST; 1974 1975 /* 1976 * Register HBA(RHBA) 1977 */ 1978 typedef struct 1979 { 1980 HBA_IDENTIFIER hi; 1981 REG_PORT_LIST rpl; /* variable-length array */ 1982 } REG_HBA, *PREG_HBA; 1983 1984 /* 1985 * Register HBA Attributes (RHAT) 1986 */ 1987 typedef struct 1988 { 1989 NAME_TYPE HBA_PortName; 1990 ATTRIBUTE_BLOCK ab; 1991 } REG_HBA_ATTRIBUTE, *PREG_HBA_ATTRIBUTE; 1992 1993 /* 1994 * Register Port Attributes (RPA) 1995 */ 1996 typedef struct 1997 { 1998 NAME_TYPE HBA_PortName; 1999 NAME_TYPE PortName; 2000 ATTRIBUTE_BLOCK ab; 2001 } REG_PORT_ATTRIBUTE, *PREG_PORT_ATTRIBUTE; 2002 2003 /* 2004 * Get Registered HBA List (GRHL) Accept Payload Format 2005 */ 2006 typedef struct 2007 { 2008 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Ids */ 2009 NAME_TYPE HBA_PortName; /* Variable-length array */ 2010 } GRHL_ACC_PAYLOAD, *PGRHL_ACC_PAYLOAD; 2011 2012 /* 2013 * Get Registered Port List (GRPL) Accept Payload Format 2014 */ 2015 typedef struct 2016 { 2017 uint32_t RPL_Entry_Cnt; /* No of Reg Port Entries */ 2018 PORT_ENTRY eg_Port_Entry[1]; /* Variable-length array */ 2019 } GRPL_ACC_PAYLOAD, *PGRPL_ACC_PAYLOAD; 2020 2021 /* 2022 * Get Port Attributes (GPAT) Accept Payload Format 2023 */ 2024 2025 typedef struct 2026 { 2027 ATTRIBUTE_BLOCK pab; 2028 } GPAT_ACC_PAYLOAD, *PGPAT_ACC_PAYLOAD; 2029 2030 /* 2031 * Use for Firmware DownLoad 2032 */ 2033 2034 /* download.h */ 2035 2036 #define REDUCED_SRAM_CFG 0x7FFFC /* 9802DC */ 2037 #define FULL_SRAM_CFG 0x13FFFC /* 9802 */ 2038 2039 #define SLI_FW_TYPE_SHIFT(x) ((x << 20)) 2040 #define SLI_FW_ADAPTER_TYPE_MASK 0x00f00000 2041 #define SLI_FW_TYPE_6000 SLI_FW_TYPE_SHIFT(0) 2042 #define SLI_FW_TYPE_7000 SLI_FW_TYPE_SHIFT(1) 2043 #define SLI_FW_TYPE_8000 SLI_FW_TYPE_SHIFT(2) 2044 #define SLI_FW_TYPE_850 SLI_FW_TYPE_SHIFT(3) 2045 #define SLI_FW_TYPE_9000 SLI_FW_TYPE_SHIFT(4) 2046 #define SLI_FW_TYPE_950 SLI_FW_TYPE_SHIFT(5) 2047 #define SLI_FW_TYPE_9802 SLI_FW_TYPE_SHIFT(6) /* [022702] */ 2048 #define SLI_FW_TYPE_982 SLI_FW_TYPE_SHIFT(7) 2049 #define SLI_FW_TYPE_10000 SLI_FW_TYPE_SHIFT(8) 2050 #define SLI_FW_TYPE_1050 SLI_FW_TYPE_SHIFT(9) 2051 #define SLI_FW_TYPE_X1000 SLI_FW_TYPE_SHIFT(0xa) 2052 #define SLI_FW_TYPE_101 SLI_FW_TYPE_SHIFT(0xb) /* LP101 */ 2053 2054 2055 enum emlxs_prog_type 2056 { 2057 TEST_PROGRAM, /* 0 */ 2058 UTIL_PROGRAM, /* 1 */ 2059 FUNC_FIRMWARE, /* 2 */ 2060 BOOT_BIOS, /* 3 */ 2061 CONFIG_DATA, /* 4 */ 2062 SEQUENCER_CODE, /* 5 */ 2063 SLI1_OVERLAY, /* 6 */ 2064 SLI2_OVERLAY, /* 7 */ 2065 GASKET, /* 8 */ 2066 HARDWARE_IMAGE, /* 9 */ 2067 SBUS_FCODE, /* A */ 2068 SLI3_OVERLAY, /* B */ 2069 RESERVED_C, 2070 RESERVED_D, 2071 SLI4_OVERLAY, /* E */ 2072 KERNEL_CODE, /* F */ 2073 MAX_PROG_TYPES 2074 } emlxs_prog_type_t; 2075 2076 2077 typedef struct emlxs_fw_file 2078 { 2079 uint32_t version; 2080 uint32_t revcomp; 2081 char label[16]; 2082 uint32_t offset; 2083 } emlxs_fw_file_t; 2084 2085 typedef struct emlxs_fw_image 2086 { 2087 emlxs_fw_file_t awc; 2088 emlxs_fw_file_t bwc; 2089 emlxs_fw_file_t dwc; 2090 emlxs_fw_file_t prog[MAX_PROG_TYPES]; 2091 } emlxs_fw_image_t; 2092 2093 2094 2095 #define NOP_IMAGE_TYPE 0xe1a00000 2096 2097 #define FLASH_BASE_ADR 0x01400000 2098 #define DL_FROM_SLIM_OFFSET MBOX_EXTENSION_OFFSET 2099 2100 #ifdef MBOX_EXT_SUPPORT 2101 #define DL_SLIM_SEG_BYTE_COUNT MBOX_EXTENSION_SIZE 2102 #else 2103 #define DL_SLIM_SEG_BYTE_COUNT 128 2104 #endif /* MBOX_EXT_SUPPORT */ 2105 2106 #define SLI_CKSUM_LENGTH 4 2107 #define SLI_CKSUM_SEED 0x55555555 2108 #define SLI_CKSUM_ERR 0x1982abcd 2109 2110 #define AIF_NOOP 0xe1a00000 2111 #define AIF_BLAL 0xeb000000 2112 #define OS_EXIT 0xef000011 2113 #define OS_GETENV 0xef000010 2114 #define AIF_IMAGEBASE 0x00008000 2115 #define AIF_BLZINIT 0xeb00000c 2116 #define DEBUG_TASK 0xef041d41 2117 #define AIF_DBG_SRC 2 2118 #define AIF_DBG_LL 1 2119 #define AIF_DATABASAT 0x100 2120 2121 #define JEDEC_ID_ADDRESS 0x0080001c 2122 #define MAX_RBUS_SRAM_SIZE_ADR 0x788 2123 #define MAX_IBUS_SRAM_SIZE_ADR 0x78c 2124 #define FULL_RBUS_SRAM_CFG 0x7fffc 2125 #define FULL_IBUS_SRAM_CFG 0x187fffc 2126 #define REDUCED_RBUS_SRAM_CFG 0x5fffc 2127 #define REDUCED_IBUS_SRAM_CFG 0x183fffc 2128 2129 #define FULL_SRAM_CFG_PROG_ID 1 2130 #define REDUCED_SRAM_CFG_PROG_ID 2 2131 #define OTHER_SRAM_CFG_PROG_ID 3 2132 2133 #define NO_FLASH_MEM_AVAIL 0xf1 2134 2135 #define PROG_TYPE_MASK 0xff000000 2136 #define PROG_TYPE_SHIFT 24 2137 2138 #define FLASH_LOAD_LIST_ADR 0x79c 2139 #define RAM_LOAD_ENTRY_SIZE 9 2140 #define FLASH_LOAD_ENTRY_SIZE 6 2141 #define RAM_LOAD_ENTRY_TYPE 0 2142 #define FLASH_LOAD_ENTRY_TYPE 1 2143 2144 #define CFG_DATA_NO_REGION -3 2145 2146 #define SLI_IMAGE_START 0x20080 2147 #define SLI_VERSION_LOC 0x270 2148 2149 2150 #define SLI_HW_REVISION_CHECK(x, y) ((x & 0xf0) == y) 2151 #define SLI_FCODE_REVISION_CHECK(x, y) (x == y) 2152 2153 2154 /* ************ Tigershark ************** */ 2155 #define BE_SIGNATURE_SIZE 32 2156 #define BE_BUILD_SIZE 24 2157 #define BE_SIGNATURE "ServerEngines Corp" 2158 #define BE_DIR_SIGNATURE "*** SE FLAS" 2159 #define BE_VERSION_SIZE 32 2160 #define BE_COOKIE_SIZE 32 2161 #define BE_CONTROLLER_SIZE 8 2162 #define BE_FLASH_ENTRIES 32 2163 #define BE_MAX_XFER_SIZE 32768 /* 4K aligned */ 2164 2165 typedef struct emlxs_sli4_ufi_controller 2166 { 2167 uint32_t vendor_id; 2168 uint32_t device_id; 2169 uint32_t sub_vendor_id; 2170 uint32_t sub_device_id; 2171 2172 } emlxs_sli4_ufi_controller_t; 2173 2174 typedef struct emlxs_sli4_ufi_header /* 96 bytes */ 2175 { 2176 char signature[BE_SIGNATURE_SIZE]; 2177 uint32_t checksum; 2178 uint32_t antidote; 2179 emlxs_sli4_ufi_controller_t controller; 2180 uint32_t file_length; 2181 uint32_t chunk_num; 2182 uint32_t chunk_cnt; 2183 uint32_t image_cnt; 2184 char build[BE_BUILD_SIZE]; 2185 2186 } emlxs_sli4_ufi_header_t; 2187 2188 typedef struct emlxs_sli4_flash_header 2189 { 2190 uint32_t format_rev; 2191 uint32_t checksum; 2192 uint32_t antidote; 2193 uint32_t build_num; 2194 emlxs_sli4_ufi_controller_t controller[BE_CONTROLLER_SIZE]; 2195 uint32_t active_entry_mask; 2196 uint32_t valid_entry_mask; 2197 uint32_t orig_content_mask; 2198 uint32_t resv0; 2199 uint32_t resv1; 2200 uint32_t resv2; 2201 uint32_t resv3; 2202 uint32_t resv4; 2203 2204 } emlxs_sli4_flash_header_t; 2205 2206 typedef struct emlxs_sli4_flash_entry 2207 { 2208 uint32_t type; 2209 uint32_t offset; 2210 uint32_t pad_size; 2211 uint32_t image_size; 2212 uint32_t checksum; 2213 uint32_t entry_point; 2214 uint32_t resv0; 2215 uint32_t resv1; 2216 char version[BE_VERSION_SIZE]; 2217 2218 } emlxs_sli4_flash_entry_t; 2219 2220 typedef struct emlxs_sli4_flash_dir 2221 { 2222 char cookie[BE_COOKIE_SIZE]; 2223 emlxs_sli4_flash_header_t header; 2224 emlxs_sli4_flash_entry_t entry[BE_FLASH_ENTRIES]; 2225 2226 } emlxs_sli4_flash_dir_t; 2227 2228 2229 /* FLASH ENTRY TYPES */ 2230 #define BE_FLASHTYPE_PXE_BIOS 0x20 2231 #define BE_FLASHTYPE_FCOE_BIOS 0x21 2232 #define BE_FLASHTYPE_ISCSI_BIOS 0x22 2233 #define BE_FLASHTYPE_ISCSI_FIRMWARE 0xA0 2234 #define BE_FLASHTYPE_ISCSI_BACKUP 0xB0 2235 #define BE_FLASHTYPE_FCOE_FIRMWARE 0xA2 2236 #define BE_FLASHTYPE_FCOE_BACKUP 0xB2 2237 #define BE_FLASHTYPE_REDBOOT 0xE0 2238 2239 /* Flash types in download order */ 2240 typedef enum emlxs_be_flashtypes 2241 { 2242 ISCSI_FIRMWARE_FLASHTYPE, 2243 ISCSI_BACKUP_FLASHTYPE, 2244 FCOE_FIRMWARE_FLASHTYPE, 2245 FCOE_BACKUP_FLASHTYPE, 2246 ISCSI_BIOS_FLASHTYPE, 2247 FCOE_BIOS_FLASHTYPE, 2248 PXE_BIOS_FLASHTYPE, 2249 REDBOOT_FLASHTYPE, 2250 BE_MAX_FLASHTYPES 2251 2252 } emlxs_be_flashtypes_t; 2253 2254 /* Driver level constructs */ 2255 typedef struct emlxs_be_fw_file 2256 { 2257 uint32_t type; 2258 uint32_t image_offset; 2259 uint32_t image_size; 2260 uint32_t block_size; 2261 uint32_t block_crc; 2262 char label[BE_VERSION_SIZE]; 2263 } emlxs_be_fw_file_t; 2264 2265 typedef struct emlxs_be_fw_image 2266 { 2267 uint32_t version; 2268 char label[BE_VERSION_SIZE]; 2269 2270 emlxs_be_fw_file_t file[BE_MAX_FLASHTYPES]; 2271 } emlxs_be_fw_image_t; 2272 2273 2274 #ifdef __cplusplus 2275 } 2276 #endif 2277 2278 #endif /* _EMLXS_HW_H */ 2279