1fcf3ce44SJohn Forte /*
2fcf3ce44SJohn Forte  * CDDL HEADER START
3fcf3ce44SJohn Forte  *
4fcf3ce44SJohn Forte  * The contents of this file are subject to the terms of the
5fcf3ce44SJohn Forte  * Common Development and Distribution License (the "License").
6fcf3ce44SJohn Forte  * You may not use this file except in compliance with the License.
7fcf3ce44SJohn Forte  *
88f23e9faSHans Rosenfeld  * You can obtain a copy of the license at
98f23e9faSHans Rosenfeld  * http://www.opensource.org/licenses/cddl1.txt.
10fcf3ce44SJohn Forte  * See the License for the specific language governing permissions
11fcf3ce44SJohn Forte  * and limitations under the License.
12fcf3ce44SJohn Forte  *
13fcf3ce44SJohn Forte  * When distributing Covered Code, include this CDDL HEADER in each
14fcf3ce44SJohn Forte  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15fcf3ce44SJohn Forte  * If applicable, add the following below this CDDL HEADER, with the
16fcf3ce44SJohn Forte  * fields enclosed by brackets "[]" replaced with your own identifying
17fcf3ce44SJohn Forte  * information: Portions Copyright [yyyy] [name of copyright owner]
18fcf3ce44SJohn Forte  *
19fcf3ce44SJohn Forte  * CDDL HEADER END
20fcf3ce44SJohn Forte  */
21fcf3ce44SJohn Forte 
22fcf3ce44SJohn Forte /*
238f23e9faSHans Rosenfeld  * Copyright (c) 2004-2011 Emulex. All rights reserved.
2482527734SSukumar Swaminathan  * Use is subject to license terms.
25a3170057SPaul Winder  * Copyright 2020 RackTop Systems, Inc.
26fcf3ce44SJohn Forte  */
27fcf3ce44SJohn Forte 
28fcf3ce44SJohn Forte #ifndef _EMLXS_HW_H
29fcf3ce44SJohn Forte #define	_EMLXS_HW_H
30fcf3ce44SJohn Forte 
31fcf3ce44SJohn Forte #ifdef	__cplusplus
32fcf3ce44SJohn Forte extern "C" {
33fcf3ce44SJohn Forte #endif
34fcf3ce44SJohn Forte 
35291a2b48SSukumar Swaminathan #define	MAX_VPORTS			256	/* Max virtual ports per HBA */
36291a2b48SSukumar Swaminathan 						/* (includes physical port) */
37fcf3ce44SJohn Forte #define	MAX_VPORTS_LIMITED		101
38fcf3ce44SJohn Forte 
39291a2b48SSukumar Swaminathan #define	FC_MAX_TRANSFER			0x40000	/* Max transfer size per */
40291a2b48SSukumar Swaminathan 						/* operation */
41fcf3ce44SJohn Forte 
42fcf3ce44SJohn Forte #define	MAX_RINGS_AVAILABLE		4	/* # rings available */
43fcf3ce44SJohn Forte #define	MAX_RINGS			4	/* Max # rings used */
44fcf3ce44SJohn Forte 
45fcf3ce44SJohn Forte #define	PCB_SIZE			128
46fcf3ce44SJohn Forte 
47fcf3ce44SJohn Forte #define	SLIM_IOCB_CMD_R0_ENTRIES	128	/* SLI FCP cmd ring entries  */
48fcf3ce44SJohn Forte #define	SLIM_IOCB_RSP_R0_ENTRIES	128	/* SLI FCP rsp ring entries */
4982527734SSukumar Swaminathan #define	SLIM_IOCB_CMD_R1_ENTRIES	128	/* SLI IP cmd ring entries   */
5082527734SSukumar Swaminathan #define	SLIM_IOCB_RSP_R1_ENTRIES	128	/* SLI IP rsp ring entries  */
5182527734SSukumar Swaminathan #define	SLIM_IOCB_CMD_R2_ENTRIES	128	/* SLI ELS cmd ring entries  */
5282527734SSukumar Swaminathan #define	SLIM_IOCB_RSP_R2_ENTRIES	128	/* SLI ELS rspe ring entries */
5382527734SSukumar Swaminathan #define	SLIM_IOCB_CMD_R3_ENTRIES	128	/* SLI CT cmd ring entries   */
5482527734SSukumar Swaminathan #define	SLIM_IOCB_RSP_R3_ENTRIES	128	/* SLI CT rsp ring entries  */
55291a2b48SSukumar Swaminathan 
56291a2b48SSukumar Swaminathan /*
57291a2b48SSukumar Swaminathan  * Total: 184 Cmd's + 184 Rsp's = 368
58291a2b48SSukumar Swaminathan  * Command and response entry counts are not required to be equal
59291a2b48SSukumar Swaminathan  */
60fcf3ce44SJohn Forte 
61291a2b48SSukumar Swaminathan #define	SLIM_IOCB_CMD_ENTRIES		(SLIM_IOCB_CMD_R0_ENTRIES + \
62291a2b48SSukumar Swaminathan 					SLIM_IOCB_CMD_R1_ENTRIES + \
63291a2b48SSukumar Swaminathan 					SLIM_IOCB_CMD_R2_ENTRIES + \
64291a2b48SSukumar Swaminathan 					SLIM_IOCB_CMD_R3_ENTRIES)
65fcf3ce44SJohn Forte 
66291a2b48SSukumar Swaminathan #define	SLIM_IOCB_RSP_ENTRIES		(SLIM_IOCB_RSP_R0_ENTRIES + \
67291a2b48SSukumar Swaminathan 					SLIM_IOCB_RSP_R1_ENTRIES + \
68291a2b48SSukumar Swaminathan 					SLIM_IOCB_RSP_R2_ENTRIES + \
69291a2b48SSukumar Swaminathan 					SLIM_IOCB_RSP_R3_ENTRIES)
70fcf3ce44SJohn Forte 
71291a2b48SSukumar Swaminathan #define	SLIM_IOCB_ENTRIES		(SLIM_IOCB_CMD_ENTRIES + \
72291a2b48SSukumar Swaminathan 					SLIM_IOCB_RSP_ENTRIES)
73fcf3ce44SJohn Forte 
74fcf3ce44SJohn Forte 
75fcf3ce44SJohn Forte /* SLI1 Definitions */
76291a2b48SSukumar Swaminathan #define	SLI_SLIM1_SIZE			4096 /* Fixed size memory */
77fcf3ce44SJohn Forte 
78fcf3ce44SJohn Forte 
79fcf3ce44SJohn Forte /* SLI2 Definitions */
80fcf3ce44SJohn Forte #define	SLI2_IOCB_CMD_SIZE		32
81fcf3ce44SJohn Forte #define	SLI2_IOCB_RSP_SIZE		32
82291a2b48SSukumar Swaminathan #define	SLI2_IOCB_MAX_SIZE		((SLI2_IOCB_CMD_SIZE * \
83291a2b48SSukumar Swaminathan 					SLIM_IOCB_CMD_ENTRIES) + \
84291a2b48SSukumar Swaminathan 					(SLI2_IOCB_RSP_SIZE * \
85291a2b48SSukumar Swaminathan 					SLIM_IOCB_RSP_ENTRIES))
86291a2b48SSukumar Swaminathan #define	SLI2_SLIM2_SIZE			(MBOX_SIZE + MBOX_EXTENSION_SIZE + \
87291a2b48SSukumar Swaminathan 					PCB_SIZE + SLI2_IOCB_MAX_SIZE)
88291a2b48SSukumar Swaminathan 
89fcf3ce44SJohn Forte 
90fcf3ce44SJohn Forte /* SLI3 Definitions */
91fcf3ce44SJohn Forte #define	SLI3_MAX_BDE			7
92fcf3ce44SJohn Forte #define	SLI3_IOCB_CMD_SIZE		128
93fcf3ce44SJohn Forte #define	SLI3_IOCB_RSP_SIZE		64
94291a2b48SSukumar Swaminathan #define	SLI3_IOCB_MAX_SIZE		((SLI3_IOCB_CMD_SIZE * \
95291a2b48SSukumar Swaminathan 					SLIM_IOCB_CMD_ENTRIES) + \
96291a2b48SSukumar Swaminathan 					(SLI3_IOCB_RSP_SIZE * \
97291a2b48SSukumar Swaminathan 					SLIM_IOCB_RSP_ENTRIES))
98291a2b48SSukumar Swaminathan #define	SLI3_SLIM2_SIZE			(MBOX_SIZE + MBOX_EXTENSION_SIZE + \
99291a2b48SSukumar Swaminathan 					PCB_SIZE + SLI3_IOCB_MAX_SIZE)
100fcf3ce44SJohn Forte 
101fcf3ce44SJohn Forte #define	SLI_SLIM2_SIZE			SLI3_SLIM2_SIZE
102fcf3ce44SJohn Forte #define	SLI_IOCB_MAX_SIZE		SLI3_IOCB_MAX_SIZE
103fcf3ce44SJohn Forte 
104fcf3ce44SJohn Forte 
10582527734SSukumar Swaminathan /* These two are defined to indicate FCP cmd or non FCP cmd */
10682527734SSukumar Swaminathan #define	FC_FCP_CMD		0
10782527734SSukumar Swaminathan #define	FC_FCT_CMD		0
10882527734SSukumar Swaminathan #define	FC_IP_CMD		1
10982527734SSukumar Swaminathan #define	FC_ELS_CMD		2
11082527734SSukumar Swaminathan #define	FC_CT_CMD		3
11182527734SSukumar Swaminathan 
11282527734SSukumar Swaminathan #define	FC_NFCP_CMD		1	/* could be a bit mask */
113fcf3ce44SJohn Forte 
114fcf3ce44SJohn Forte #define	FC_MAXRETRY		3	/* max retries for ELS commands */
115291a2b48SSukumar Swaminathan #define	FC_FCP_RING		0	/* use ring 0 for FCP initiator cmds */
116291a2b48SSukumar Swaminathan #define	FC_FCT_RING		0	/* use ring 0 for FCP target cmds */
117fcf3ce44SJohn Forte 
118fcf3ce44SJohn Forte #define	FC_IP_RING		1	/* use ring 1 for IP commands */
119fcf3ce44SJohn Forte #define	FC_ELS_RING		2	/* use ring 2 for ELS commands */
120fcf3ce44SJohn Forte #define	FC_CT_RING		3	/* use ring 3 for CT commands */
121fcf3ce44SJohn Forte 
122fcf3ce44SJohn Forte #define	FF_DEF_EDTOV		2000	/* Default E_D_TOV (2000ms) */
123fcf3ce44SJohn Forte #define	FF_DEF_ALTOV		15	/* Default AL_TIME (15ms) */
124fcf3ce44SJohn Forte #define	FF_DEF_RATOV		2	/* Default RA_TOV (2s) */
125fcf3ce44SJohn Forte #define	FF_DEF_ARBTOV		1900	/* Default ARB_TOV (1900ms) */
126291a2b48SSukumar Swaminathan #define	MAX_MSG_DATA		28	/* max msg data in CMD_ADAPTER_MSG */
127291a2b48SSukumar Swaminathan 					/* iocb */
128291a2b48SSukumar Swaminathan #define	FF_REG_AREA_SIZE	256	/* size, in bytes, of i/o register */
129291a2b48SSukumar Swaminathan 					/* area */
130fcf3ce44SJohn Forte 
131fcf3ce44SJohn Forte /*
132fcf3ce44SJohn Forte  * Miscellaneous stuff....
133fcf3ce44SJohn Forte  */
1348f23e9faSHans Rosenfeld 
1358f23e9faSHans Rosenfeld #define	MAX_NODE_THROTTLE	2048
1368f23e9faSHans Rosenfeld 
137fcf3ce44SJohn Forte /* HBA Mgmt */
138fcf3ce44SJohn Forte #define	FDMI_DID		((uint32_t)0xfffffa)
13982527734SSukumar Swaminathan #define	NAMESERVER_DID		((uint32_t)0xfffffc)
140fcf3ce44SJohn Forte #define	SCR_DID			((uint32_t)0xfffffd)
14182527734SSukumar Swaminathan #define	FABRIC_DID		((uint32_t)0xfffffe)
14282527734SSukumar Swaminathan #define	BCAST_DID		((uint32_t)0xffffff)
14382527734SSukumar Swaminathan #define	MASK_DID		((uint32_t)0xffffff)
144fcf3ce44SJohn Forte #define	CT_DID_MASK		((uint32_t)0xffff00)
14582527734SSukumar Swaminathan #define	FABRIC_DID_MASK		((uint32_t)0xfff000)
146fcf3ce44SJohn Forte #define	WELL_KNOWN_DID_MASK	((uint32_t)0xfffff0)
147fcf3ce44SJohn Forte 
148fcf3ce44SJohn Forte #define	EMLXS_MENLO_DID		((uint32_t)0x00fc0e)
149fcf3ce44SJohn Forte 
150fcf3ce44SJohn Forte #define	OWN_CHIP	1	/* IOCB / Mailbox is owned by FireFly */
151fcf3ce44SJohn Forte #define	OWN_HOST	0	/* IOCB / Mailbox is owned by Host */
152291a2b48SSukumar Swaminathan #define	END_OF_CHAIN	0
153fcf3ce44SJohn Forte 
154fcf3ce44SJohn Forte 
155fcf3ce44SJohn Forte /* defines for type field in fc header */
156fcf3ce44SJohn Forte #define	EMLXS_MENLO_TYPE	0xFE
157fcf3ce44SJohn Forte 
158fcf3ce44SJohn Forte /* defines for rctl field in fc header */
159fcf3ce44SJohn Forte #define	FC_DEV_DATA	0x0
160fcf3ce44SJohn Forte #define	FC_UNSOL_CTL	0x2
161fcf3ce44SJohn Forte #define	FC_SOL_CTL	0x3
162fcf3ce44SJohn Forte #define	FC_UNSOL_DATA	0x4
163fcf3ce44SJohn Forte #define	FC_FCP_CMND	0x6
164fcf3ce44SJohn Forte #define	FC_ELS_REQ	0x22
165fcf3ce44SJohn Forte #define	FC_ELS_RSP	0x23
166fcf3ce44SJohn Forte #define	FC_NET_HDR	0x20	/* network headers for Dfctl field */
167fcf3ce44SJohn Forte 
168fcf3ce44SJohn Forte /*
169fcf3ce44SJohn Forte  * Common Transport structures and definitions
170fcf3ce44SJohn Forte  *
171fcf3ce44SJohn Forte  */
172fcf3ce44SJohn Forte #define	EMLXS_COMMAND	0
173fcf3ce44SJohn Forte #define	EMLXS_RESPONSE	1
174fcf3ce44SJohn Forte 
175291a2b48SSukumar Swaminathan typedef union CtRevisionId
176291a2b48SSukumar Swaminathan {
177fcf3ce44SJohn Forte 	/* Structure is in Big Endian format */
178291a2b48SSukumar Swaminathan 	struct
179291a2b48SSukumar Swaminathan 	{
180291a2b48SSukumar Swaminathan 		uint32_t	Revision:8;
181291a2b48SSukumar Swaminathan 		uint32_t	InId:24;
182fcf3ce44SJohn Forte 	} bits;
183291a2b48SSukumar Swaminathan 	uint32_t	word;
184fcf3ce44SJohn Forte } CtRevisionId_t;
185fcf3ce44SJohn Forte 
186291a2b48SSukumar Swaminathan typedef union CtCommandResponse
187291a2b48SSukumar Swaminathan {
188fcf3ce44SJohn Forte 	/* Structure is in Big Endian format */
189291a2b48SSukumar Swaminathan 	struct
190291a2b48SSukumar Swaminathan 	{
191291a2b48SSukumar Swaminathan 		uint32_t	CmdRsp:16;
192291a2b48SSukumar Swaminathan 		uint32_t	Size:16;
193fcf3ce44SJohn Forte 	} bits;
194291a2b48SSukumar Swaminathan 	uint32_t	word;
195fcf3ce44SJohn Forte } CtCommandResponse_t;
196fcf3ce44SJohn Forte 
197291a2b48SSukumar Swaminathan typedef struct SliCtRequest
198291a2b48SSukumar Swaminathan {
199fcf3ce44SJohn Forte 	/* Structure is in Big Endian format */
200291a2b48SSukumar Swaminathan 	CtRevisionId_t		RevisionId;
201291a2b48SSukumar Swaminathan 	uint8_t			FsType;
202291a2b48SSukumar Swaminathan 	uint8_t			FsSubType;
203291a2b48SSukumar Swaminathan 	uint8_t			Options;
204291a2b48SSukumar Swaminathan 	uint8_t			Rsrvd1;
205291a2b48SSukumar Swaminathan 	CtCommandResponse_t	CommandResponse;
206291a2b48SSukumar Swaminathan 	uint8_t			Rsrvd2;
207291a2b48SSukumar Swaminathan 	uint8_t			ReasonCode;
208291a2b48SSukumar Swaminathan 	uint8_t			Explanation;
209291a2b48SSukumar Swaminathan 	uint8_t			VendorUnique;
210291a2b48SSukumar Swaminathan 
211291a2b48SSukumar Swaminathan 	union
212291a2b48SSukumar Swaminathan 	{
213291a2b48SSukumar Swaminathan 		uint32_t	data;
214291a2b48SSukumar Swaminathan 		uint32_t	PortID;
215291a2b48SSukumar Swaminathan 
216291a2b48SSukumar Swaminathan 		struct gid
217291a2b48SSukumar Swaminathan 		{
218291a2b48SSukumar Swaminathan 			uint8_t	PortType;	/* for GID_PT requests */
219291a2b48SSukumar Swaminathan 			uint8_t	DomainScope;
220291a2b48SSukumar Swaminathan 			uint8_t	AreaScope;
221291a2b48SSukumar Swaminathan 			uint8_t	Fc4Type;	/* for GID_FT requests */
222fcf3ce44SJohn Forte 		} gid;
223291a2b48SSukumar Swaminathan 		struct rft
224291a2b48SSukumar Swaminathan 		{
225291a2b48SSukumar Swaminathan 			uint32_t	PortId;	/* For RFT_ID requests */
226fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN
227291a2b48SSukumar Swaminathan 			uint32_t	rsvd0:16;
228291a2b48SSukumar Swaminathan 			uint32_t	rsvd1:7;
229291a2b48SSukumar Swaminathan 			uint32_t	fcpReg:1;	/* Type 8 */
230291a2b48SSukumar Swaminathan 			uint32_t	rsvd2:2;
231291a2b48SSukumar Swaminathan 			uint32_t	ipReg:1;	/* Type 5 */
232291a2b48SSukumar Swaminathan 			uint32_t	rsvd3:5;
233fcf3ce44SJohn Forte #endif
234fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN
235291a2b48SSukumar Swaminathan 			uint32_t	rsvd0:16;
236291a2b48SSukumar Swaminathan 			uint32_t	fcpReg:1;	/* Type 8 */
237291a2b48SSukumar Swaminathan 			uint32_t	rsvd1:7;
238291a2b48SSukumar Swaminathan 			uint32_t	rsvd3:5;
239291a2b48SSukumar Swaminathan 			uint32_t	ipReg:1;	/* Type 5 */
240291a2b48SSukumar Swaminathan 			uint32_t	rsvd2:2;
241291a2b48SSukumar Swaminathan #endif
242291a2b48SSukumar Swaminathan 			uint32_t	rsvd[7];
243fcf3ce44SJohn Forte 		} rft;
244fcf3ce44SJohn Forte 
245291a2b48SSukumar Swaminathan 		struct rsnn
246291a2b48SSukumar Swaminathan 		{
247291a2b48SSukumar Swaminathan 			uint8_t		wwnn[8];
248291a2b48SSukumar Swaminathan 			uint8_t		snn_len;
249291a2b48SSukumar Swaminathan 			char		snn[256];
250fcf3ce44SJohn Forte 		} rsnn;
251fcf3ce44SJohn Forte 
252291a2b48SSukumar Swaminathan 		struct rspn
253291a2b48SSukumar Swaminathan 		{
254291a2b48SSukumar Swaminathan 			uint32_t	PortId;
255291a2b48SSukumar Swaminathan 			uint8_t		spn_len;
256291a2b48SSukumar Swaminathan 			char		spn[256];
257fcf3ce44SJohn Forte 		} rspn;
258fcf3ce44SJohn Forte 	} un;
259fcf3ce44SJohn Forte } SliCtRequest_t;
260fcf3ce44SJohn Forte typedef SliCtRequest_t SLI_CT_REQUEST;
261fcf3ce44SJohn Forte 
262291a2b48SSukumar Swaminathan #define	SLI_CT_REVISION	1
263fcf3ce44SJohn Forte 
264fcf3ce44SJohn Forte 
265fcf3ce44SJohn Forte /*
266fcf3ce44SJohn Forte  * FsType Definitions
267fcf3ce44SJohn Forte  */
268fcf3ce44SJohn Forte 
269291a2b48SSukumar Swaminathan #define	SLI_CT_MANAGEMENT_SERVICE		0xFA
270291a2b48SSukumar Swaminathan #define	SLI_CT_TIME_SERVICE			0xFB
271291a2b48SSukumar Swaminathan #define	SLI_CT_DIRECTORY_SERVICE		0xFC
272291a2b48SSukumar Swaminathan #define	SLI_CT_FABRIC_CONTROLLER_SERVICE	0xFD
273fcf3ce44SJohn Forte 
274fcf3ce44SJohn Forte /*
275fcf3ce44SJohn Forte  * Directory Service Subtypes
276fcf3ce44SJohn Forte  */
277fcf3ce44SJohn Forte 
278291a2b48SSukumar Swaminathan #define	SLI_CT_DIRECTORY_NAME_SERVER	0x02
279fcf3ce44SJohn Forte 
280fcf3ce44SJohn Forte /*
281fcf3ce44SJohn Forte  * Response Codes
282fcf3ce44SJohn Forte  */
283fcf3ce44SJohn Forte 
284291a2b48SSukumar Swaminathan #define	SLI_CT_RESPONSE_FS_RJT	0x8001
285291a2b48SSukumar Swaminathan #define	SLI_CT_RESPONSE_FS_ACC	0x8002
286fcf3ce44SJohn Forte 
287fcf3ce44SJohn Forte /*
288fcf3ce44SJohn Forte  * Reason Codes
289fcf3ce44SJohn Forte  */
290fcf3ce44SJohn Forte 
291291a2b48SSukumar Swaminathan #define	SLI_CT_NO_ADDITIONAL_EXPL		0x0
292291a2b48SSukumar Swaminathan #define	SLI_CT_INVALID_COMMAND			0x01
293291a2b48SSukumar Swaminathan #define	SLI_CT_INVALID_VERSION			0x02
294291a2b48SSukumar Swaminathan #define	SLI_CT_LOGICAL_ERROR			0x03
295291a2b48SSukumar Swaminathan #define	SLI_CT_INVALID_IU_SIZE			0x04
296291a2b48SSukumar Swaminathan #define	SLI_CT_LOGICAL_BUSY			0x05
297291a2b48SSukumar Swaminathan #define	SLI_CT_PROTOCOL_ERROR			0x07
298291a2b48SSukumar Swaminathan #define	SLI_CT_UNABLE_TO_PERFORM_REQ		0x09
299291a2b48SSukumar Swaminathan #define	SLI_CT_REQ_NOT_SUPPORTED		0x0b
300291a2b48SSukumar Swaminathan #define	SLI_CT_HBA_INFO_NOT_REGISTERED		0x10
301291a2b48SSukumar Swaminathan #define	SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE	0x11
302291a2b48SSukumar Swaminathan #define	SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN	0x12
303291a2b48SSukumar Swaminathan #define	SLI_CT_HBA_ATTR_NOT_PRESENT		0x13
304291a2b48SSukumar Swaminathan #define	SLI_CT_PORT_INFO_NOT_REGISTERED		0x20
305291a2b48SSukumar Swaminathan #define	SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE	0x21
306291a2b48SSukumar Swaminathan #define	SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN	0x22
307291a2b48SSukumar Swaminathan #define	SLI_CT_VENDOR_UNIQUE			0xff
308fcf3ce44SJohn Forte 
309fcf3ce44SJohn Forte /*
310fcf3ce44SJohn Forte  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
311fcf3ce44SJohn Forte  */
312fcf3ce44SJohn Forte 
313291a2b48SSukumar Swaminathan #define	SLI_CT_NO_PORT_ID		0x01
314291a2b48SSukumar Swaminathan #define	SLI_CT_NO_PORT_NAME		0x02
315291a2b48SSukumar Swaminathan #define	SLI_CT_NO_NODE_NAME		0x03
316291a2b48SSukumar Swaminathan #define	SLI_CT_NO_CLASS_OF_SERVICE	0x04
317291a2b48SSukumar Swaminathan #define	SLI_CT_NO_IP_ADDRESS		0x05
318291a2b48SSukumar Swaminathan #define	SLI_CT_NO_IPA			0x06
319291a2b48SSukumar Swaminathan #define	SLI_CT_NO_FC4_TYPES		0x07
320291a2b48SSukumar Swaminathan #define	SLI_CT_NO_SYMBOLIC_PORT_NAME	0x08
321291a2b48SSukumar Swaminathan #define	SLI_CT_NO_SYMBOLIC_NODE_NAME	0x09
322291a2b48SSukumar Swaminathan #define	SLI_CT_NO_PORT_TYPE		0x0A
323291a2b48SSukumar Swaminathan #define	SLI_CT_ACCESS_DENIED		0x10
324291a2b48SSukumar Swaminathan #define	SLI_CT_INVALID_PORT_ID		0x11
325291a2b48SSukumar Swaminathan #define	SLI_CT_DATABASE_EMPTY		0x12
326fcf3ce44SJohn Forte 
327fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN
328fcf3ce44SJohn Forte #define	CT_CMD_MASK	0xffff0000
329fcf3ce44SJohn Forte #endif
330fcf3ce44SJohn Forte 
331fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN
332fcf3ce44SJohn Forte #define	CT_CMD_MASK	0xffff
333fcf3ce44SJohn Forte #endif
334fcf3ce44SJohn Forte 
335fcf3ce44SJohn Forte /*
336fcf3ce44SJohn Forte  * Management Server Interface Command Codes
337fcf3ce44SJohn Forte  */
338fcf3ce44SJohn Forte 
339291a2b48SSukumar Swaminathan #define	MS_GTIN		0x0100
340291a2b48SSukumar Swaminathan #define	MS_GIEL		0x0101
341291a2b48SSukumar Swaminathan #define	MS_GIET		0x0111
342291a2b48SSukumar Swaminathan #define	MS_GDID		0x0112
343291a2b48SSukumar Swaminathan #define	MS_GMID		0x0113
344291a2b48SSukumar Swaminathan #define	MS_GFN		0x0114
345291a2b48SSukumar Swaminathan #define	MS_GIELN	0x0115
346291a2b48SSukumar Swaminathan #define	MS_GMAL		0x0116
347291a2b48SSukumar Swaminathan #define	MS_GIEIL	0x0117
348291a2b48SSukumar Swaminathan #define	MS_GPL		0x0118
349291a2b48SSukumar Swaminathan #define	MS_GPT		0x0121
350291a2b48SSukumar Swaminathan #define	MS_GPPN		0x0122
351291a2b48SSukumar Swaminathan #define	MS_GAPNL	0x0124
352291a2b48SSukumar Swaminathan #define	MS_GPS		0x0126
353291a2b48SSukumar Swaminathan #define	MS_GPSC		0x0127
354291a2b48SSukumar Swaminathan #define	MS_GATIN	0x0128
355291a2b48SSukumar Swaminathan #define	MS_GSES		0x0130
356291a2b48SSukumar Swaminathan #define	MS_GPLNL	0x0191
357291a2b48SSukumar Swaminathan #define	MS_GPLT		0x0192
358291a2b48SSukumar Swaminathan #define	MS_GPLML	0x0193
359291a2b48SSukumar Swaminathan #define	MS_GPAB		0x0197
360291a2b48SSukumar Swaminathan #define	MS_GNPL		0x01A1
361291a2b48SSukumar Swaminathan #define	MS_GPNL		0x01A2
362291a2b48SSukumar Swaminathan #define	MS_GPFCP	0x01A4
363291a2b48SSukumar Swaminathan #define	MS_GPLI		0x01A5
364291a2b48SSukumar Swaminathan #define	MS_GNID		0x01B1
365291a2b48SSukumar Swaminathan #define	MS_RIELN	0x0215
366291a2b48SSukumar Swaminathan #define	MS_RPL		0x0280
367291a2b48SSukumar Swaminathan #define	MS_RPLN		0x0291
368291a2b48SSukumar Swaminathan #define	MS_RPLT		0x0292
369291a2b48SSukumar Swaminathan #define	MS_RPLM		0x0293
370291a2b48SSukumar Swaminathan #define	MS_RPAB		0x0298
371291a2b48SSukumar Swaminathan #define	MS_RPFCP	0x029A
372291a2b48SSukumar Swaminathan #define	MS_RPLI		0x029B
373291a2b48SSukumar Swaminathan #define	MS_DPL		0x0380
374291a2b48SSukumar Swaminathan #define	MS_DPLN		0x0391
375291a2b48SSukumar Swaminathan #define	MS_DPLM		0x0392
376291a2b48SSukumar Swaminathan #define	MS_DPLML	0x0393
377291a2b48SSukumar Swaminathan #define	MS_DPLI		0x0394
378291a2b48SSukumar Swaminathan #define	MS_DPAB		0x0395
379291a2b48SSukumar Swaminathan #define	MS_DPALL	0x039F
380fcf3ce44SJohn Forte 
381fcf3ce44SJohn Forte /*
382fcf3ce44SJohn Forte  * Name Server Command Codes
383fcf3ce44SJohn Forte  */
384291a2b48SSukumar Swaminathan #define	SLI_CTNS_GA_NXT		0x0100
385291a2b48SSukumar Swaminathan #define	SLI_CTNS_GPN_ID		0x0112
386291a2b48SSukumar Swaminathan #define	SLI_CTNS_GNN_ID		0x0113
387291a2b48SSukumar Swaminathan #define	SLI_CTNS_GCS_ID		0x0114
388291a2b48SSukumar Swaminathan #define	SLI_CTNS_GFT_ID		0x0117
389291a2b48SSukumar Swaminathan #define	SLI_CTNS_GSPN_ID	0x0118
390291a2b48SSukumar Swaminathan #define	SLI_CTNS_GPT_ID		0x011A
391291a2b48SSukumar Swaminathan #define	SLI_CTNS_GID_PN		0x0121
392291a2b48SSukumar Swaminathan #define	SLI_CTNS_GID_NN		0x0131
393291a2b48SSukumar Swaminathan #define	SLI_CTNS_GIP_NN		0x0135
394291a2b48SSukumar Swaminathan #define	SLI_CTNS_GIPA_NN	0x0136
395291a2b48SSukumar Swaminathan #define	SLI_CTNS_GSNN_NN	0x0139
396291a2b48SSukumar Swaminathan #define	SLI_CTNS_GNN_IP		0x0153
397291a2b48SSukumar Swaminathan #define	SLI_CTNS_GIPA_IP	0x0156
398291a2b48SSukumar Swaminathan #define	SLI_CTNS_GID_FT		0x0171
399291a2b48SSukumar Swaminathan #define	SLI_CTNS_GID_PT		0x01A1
400291a2b48SSukumar Swaminathan #define	SLI_CTNS_RPN_ID		0x0212
401291a2b48SSukumar Swaminathan #define	SLI_CTNS_RNN_ID		0x0213
402291a2b48SSukumar Swaminathan #define	SLI_CTNS_RCS_ID		0x0214
403291a2b48SSukumar Swaminathan #define	SLI_CTNS_RFT_ID		0x0217
404291a2b48SSukumar Swaminathan #define	SLI_CTNS_RSPN_ID	0x0218
405291a2b48SSukumar Swaminathan #define	SLI_CTNS_RPT_ID		0x021A
406291a2b48SSukumar Swaminathan #define	SLI_CTNS_RIP_NN		0x0235
407291a2b48SSukumar Swaminathan #define	SLI_CTNS_RIPA_NN	0x0236
408291a2b48SSukumar Swaminathan #define	SLI_CTNS_RSNN_NN	0x0239
409291a2b48SSukumar Swaminathan #define	SLI_CTNS_DA_ID		0x0300
410291a2b48SSukumar Swaminathan 
411291a2b48SSukumar Swaminathan #define	SLI_CT_LOOPBACK		0xFCFC
412fcf3ce44SJohn Forte 
413fcf3ce44SJohn Forte 
414fcf3ce44SJohn Forte /*
415fcf3ce44SJohn Forte  * Port Types
416fcf3ce44SJohn Forte  */
417fcf3ce44SJohn Forte 
418291a2b48SSukumar Swaminathan #define	SLI_CTPT_N_PORT		0x01
419291a2b48SSukumar Swaminathan #define	SLI_CTPT_NL_PORT	0x02
420291a2b48SSukumar Swaminathan #define	SLI_CTPT_FNL_PORT	0x03
421291a2b48SSukumar Swaminathan #define	SLI_CTPT_IP		0x04
422291a2b48SSukumar Swaminathan #define	SLI_CTPT_FCP		0x08
423291a2b48SSukumar Swaminathan #define	SLI_CTPT_NX_PORT	0x7F
424291a2b48SSukumar Swaminathan #define	SLI_CTPT_F_PORT		0x81
425291a2b48SSukumar Swaminathan #define	SLI_CTPT_FL_PORT	0x82
426291a2b48SSukumar Swaminathan #define	SLI_CTPT_E_PORT		0x84
427fcf3ce44SJohn Forte 
428fcf3ce44SJohn Forte #define	SLI_CT_LAST_ENTRY	0x80000000
429fcf3ce44SJohn Forte 
430fcf3ce44SJohn Forte /* ===================================================================== */
431fcf3ce44SJohn Forte 
432fcf3ce44SJohn Forte /*
433fcf3ce44SJohn Forte  * Start FireFly Register definitions
434fcf3ce44SJohn Forte  */
435fcf3ce44SJohn Forte 
436fcf3ce44SJohn Forte /* PCI register offsets */
437291a2b48SSukumar Swaminathan #define	MEM_ADDR_OFFSET	0x10	/* SLIM base memory address */
438fcf3ce44SJohn Forte #define	MEMH_OFFSET	0x14	/* SLIM base memory high address */
439291a2b48SSukumar Swaminathan #define	REG_ADDR_OFFSET	0x18	/* REGISTER base memory address */
440fcf3ce44SJohn Forte #define	REGH_OFFSET	0x1c	/* REGISTER base memory high address */
441291a2b48SSukumar Swaminathan #define	IO_ADDR_OFFSET	0x20	/* BIU I/O registers */
442291a2b48SSukumar Swaminathan #define	REGIOH_OFFSET	0x24	/* REGISTER base io high address */
443fcf3ce44SJohn Forte 
444291a2b48SSukumar Swaminathan #define	CMD_REG_OFFSET	0x4	/* PCI command configuration */
445fcf3ce44SJohn Forte 
446fcf3ce44SJohn Forte /* General PCI Register Definitions */
447fcf3ce44SJohn Forte /* Refer To The PCI Specification For Detailed Explanations */
448fcf3ce44SJohn Forte 
449291a2b48SSukumar Swaminathan #define	PCI_VENDOR_ID_REGISTER		0x00	/* PCI Vendor ID Reg */
450291a2b48SSukumar Swaminathan #define	PCI_DEVICE_ID_REGISTER		0x02	/* PCI Device ID Reg */
451fcf3ce44SJohn Forte #define	PCI_CONFIG_ID_REGISTER		0x00	/* PCI Configuration ID Reg */
452291a2b48SSukumar Swaminathan #define	PCI_COMMAND_REGISTER		0x04	/* PCI Command Reg */
453291a2b48SSukumar Swaminathan #define	PCI_STATUS_REGISTER		0x06	/* PCI Status Reg */
454291a2b48SSukumar Swaminathan #define	PCI_REV_ID_REGISTER		0x08	/* PCI Revision ID Reg */
455291a2b48SSukumar Swaminathan #define	PCI_CLASS_CODE_REGISTER		0x09	/* PCI Class Code Reg */
456291a2b48SSukumar Swaminathan #define	PCI_CACHE_LINE_REGISTER		0x0C	/* PCI Cache Line Reg */
457291a2b48SSukumar Swaminathan #define	PCI_LATENCY_TMR_REGISTER	0x0D	/* PCI Latency Timer Reg */
458291a2b48SSukumar Swaminathan #define	PCI_HEADER_TYPE_REGISTER	0x0E	/* PCI Header Type Reg */
459fcf3ce44SJohn Forte #define	PCI_BIST_REGISTER		0x0F	/* PCI Built-In SelfTest Reg */
460fcf3ce44SJohn Forte #define	PCI_BAR_0_REGISTER		0x10	/* PCI Base Address Reg 0 */
461fcf3ce44SJohn Forte #define	PCI_BAR_1_REGISTER		0x14	/* PCI Base Address Reg 1 */
462fcf3ce44SJohn Forte #define	PCI_BAR_2_REGISTER		0x18	/* PCI Base Address Reg 2 */
463fcf3ce44SJohn Forte #define	PCI_BAR_3_REGISTER		0x1C	/* PCI Base Address Reg 3 */
464fcf3ce44SJohn Forte #define	PCI_BAR_4_REGISTER		0x20	/* PCI Base Address Reg 4 */
465fcf3ce44SJohn Forte #define	PCI_BAR_5_REGISTER		0x24	/* PCI Base Address Reg 5 */
466fcf3ce44SJohn Forte #define	PCI_SSID_REGISTER		0x2C
467fcf3ce44SJohn Forte #define	PCI_SSVID_REGISTER		0x2C
468fcf3ce44SJohn Forte #define	PCI_SSDID_REGISTER		0x2E
469fcf3ce44SJohn Forte #define	PCI_EXPANSION_ROM		0x30	/* PCI Expansion ROM Base Reg */
470fcf3ce44SJohn Forte #define	PCI_CAP_POINTER			0x34
471fcf3ce44SJohn Forte 
4728f23e9faSHans Rosenfeld /* PCI capatability registers are defined in pci.h */
4738f23e9faSHans Rosenfeld #define	PCI_CAP_ID_SHIFT			0
4748f23e9faSHans Rosenfeld #define	PCI_CAP_ID_MASK				0xff
4758f23e9faSHans Rosenfeld #define	PCI_CAP_NEXT_PTR_SHIFT			8
4768f23e9faSHans Rosenfeld #define	PCI_CAP_NEXT_PTR_MASK			0xff
4778f23e9faSHans Rosenfeld 
4788f23e9faSHans Rosenfeld /* PCI extended capatability registers are defined in pcie.h */
4798f23e9faSHans Rosenfeld #define	PCI_EXT_CAP_MAX_PTR		0x30
4808f23e9faSHans Rosenfeld 
4818f23e9faSHans Rosenfeld #define	PCI_EXT_CAP_ID_MRIOV		0x0000 /* ??? */
4828f23e9faSHans Rosenfeld #define	PCI_EXT_CAP_ID_SRIOV		0x0010
4838f23e9faSHans Rosenfeld #define	PCI_EXT_CAP_ID_11		0x0011
4848f23e9faSHans Rosenfeld #define	PCI_EXT_CAP_ID_12		0x0012
4858f23e9faSHans Rosenfeld #define	PCI_EXT_CAP_ID_13		0x0013
4868f23e9faSHans Rosenfeld #define	PCI_EXT_CAP_ID_14		0x0014
4878f23e9faSHans Rosenfeld #define	PCI_EXT_CAP_ID_15		0x0015
4888f23e9faSHans Rosenfeld #define	PCI_EXT_CAP_ID_16		0x0016
4898f23e9faSHans Rosenfeld #define	PCI_EXT_CAP_ID_TPH		0x0017
4908f23e9faSHans Rosenfeld #define	PCI_EXT_CAP_ID_18		0x0018
4918f23e9faSHans Rosenfeld #define	PCI_EXT_CAP_ID_SEC_PCI		0x0019
4928f23e9faSHans Rosenfeld 
4938f23e9faSHans Rosenfeld /* Vendor Specific (VS) register */
4948f23e9faSHans Rosenfeld #define	PCI_VS_SLI_INTF_OFFSET	4
495fcf3ce44SJohn Forte 
496fcf3ce44SJohn Forte /* PCI access methods */
497fcf3ce44SJohn Forte #define	P_CONF_T1	1
498fcf3ce44SJohn Forte #define	P_CONF_T2	2
499fcf3ce44SJohn Forte 
500fcf3ce44SJohn Forte /* max number of pci buses */
501291a2b48SSukumar Swaminathan #define	MAX_PCI_BUSES	0xFF
502fcf3ce44SJohn Forte 
503fcf3ce44SJohn Forte /* number of PCI config bytes to access */
504fcf3ce44SJohn Forte #define	PCI_BYTE	1
505fcf3ce44SJohn Forte #define	PCI_WORD	2
506fcf3ce44SJohn Forte #define	PCI_DWORD	4
507fcf3ce44SJohn Forte 
508fcf3ce44SJohn Forte /* PCI related constants */
509fcf3ce44SJohn Forte #define	CMD_IO_ENBL	0x0001
510291a2b48SSukumar Swaminathan #define	CMD_MEM_ENBL	0x0002
511291a2b48SSukumar Swaminathan #define	CMD_BUS_MASTER	0x0004
512fcf3ce44SJohn Forte #define	CMD_MWI		0x0010
513291a2b48SSukumar Swaminathan #define	CMD_PARITY_CHK	0x0040
514291a2b48SSukumar Swaminathan #define	CMD_SERR_ENBL	0x0100
515fcf3ce44SJohn Forte 
516291a2b48SSukumar Swaminathan #define	CMD_CFG_VALUE	0x156	/* mem enable, master, MWI, SERR, PERR */
517fcf3ce44SJohn Forte 
518fcf3ce44SJohn Forte /* PCI addresses */
519fcf3ce44SJohn Forte #define	PCI_SPACE_ENABLE		0x0CF8
520fcf3ce44SJohn Forte #define	CF1_CONFIG_ADDR_REGISTER	0x0CF8
521fcf3ce44SJohn Forte #define	CF1_CONFIG_DATA_REGISTER	0x0CFC
522fcf3ce44SJohn Forte #define	CF2_FORWARD_REGISTER		0x0CFA
523fcf3ce44SJohn Forte #define	CF2_BASE_ADDRESS		0xC000
524fcf3ce44SJohn Forte 
525fcf3ce44SJohn Forte 
526291a2b48SSukumar Swaminathan #define	DEFAULT_PCI_LATENCY_CLOCKS	0xf8	/* 0xF8 is a special value */
527291a2b48SSukumar Swaminathan 						/* for FF11.1N6 firmware. */
528291a2b48SSukumar Swaminathan 						/* Use 0x80 for pre-FF11.1N6 */
529291a2b48SSukumar Swaminathan 						/* &N7, etc */
530fcf3ce44SJohn Forte #define	PCI_LATENCY_VALUE		0xf8
531fcf3ce44SJohn Forte 
532fcf3ce44SJohn Forte 
533fcf3ce44SJohn Forte 
534fcf3ce44SJohn Forte /* ==== Register Bit Definitions ==== */
535fcf3ce44SJohn Forte 
536fcf3ce44SJohn Forte /* Used by SBUS adapter */
537fcf3ce44SJohn Forte /* SBUS Control Register */
538fcf3ce44SJohn Forte #define	SBUS_CTRL_REG_OFFSET	0	/* Word offset from reg base addr */
539fcf3ce44SJohn Forte 
540fcf3ce44SJohn Forte #define	SBUS_CTRL_SBRST 	0x00000001	/* Bit  0 */
541fcf3ce44SJohn Forte #define	SBUS_CTRL_BKOFF 	0x00000002	/* Bit  1 */
542fcf3ce44SJohn Forte #define	SBUS_CTRL_ENP 		0x00000004	/* Bit  2 */
543fcf3ce44SJohn Forte #define	SBUS_CTRL_EN64		0x00000008	/* Bit  3 */
544291a2b48SSukumar Swaminathan #define	SBUS_CTRL_SIR_1 	0x00000010	/* Bit [6:4] IRL 1, */
545291a2b48SSukumar Swaminathan 						/* lowset priority */
546fcf3ce44SJohn Forte #define	SBUS_CTRL_SIR_2 	0x00000020
547fcf3ce44SJohn Forte #define	SBUS_CTRL_SIR_3 	0x00000030
548fcf3ce44SJohn Forte #define	SBUS_CTRL_SIR_4 	0x00000040
549fcf3ce44SJohn Forte #define	SBUS_CTRL_SIR_5 	0x00000050
550fcf3ce44SJohn Forte #define	SBUS_CTRL_SIR_6 	0x00000060
551fcf3ce44SJohn Forte #define	SBUS_CTRL_SIR_7 	0x00000070	/* IRL 7, highest priority */
552fcf3ce44SJohn Forte 
553fcf3ce44SJohn Forte /* SBUS Status Register */
554fcf3ce44SJohn Forte #define	SBUS_STAT_REG_OFFSET	1	/* Word offset from reg base addr */
555fcf3ce44SJohn Forte #define	SBUS_STAT_IP		0x00000001	/* Bit  0 */
556fcf3ce44SJohn Forte #define	SBUS_STAT_LERR		0x00000002	/* Bit  1 */
557fcf3ce44SJohn Forte #define	SBUS_STAT_SBPE		0x00000004	/* Bit  2 */
558fcf3ce44SJohn Forte #define	SBUS_STAT_TE		0x00000008	/* Bit  3 */
559fcf3ce44SJohn Forte #define	SBUS_STAT_WPE		0x00000010	/* Bit  4 */
560fcf3ce44SJohn Forte #define	SBUS_STAT_PERR		0x00000020	/* Bit  5 */
561fcf3ce44SJohn Forte #define	SBUS_STAT_SERR		0x00000040	/* Bit  6 */
562fcf3ce44SJohn Forte #define	SBUS_STAT_PTA		0x00000080	/* Bit  7 */
563fcf3ce44SJohn Forte 
564fcf3ce44SJohn Forte /* SBUS Update Register */
565fcf3ce44SJohn Forte #define	SBUS_UPDATE_REG_OFFSET	2	/* Word offfset from reg base addr */
566fcf3ce44SJohn Forte 
567fcf3ce44SJohn Forte #define	SBUS_UPDATE_DATA	0x00000001	/* Bit  0 */
568fcf3ce44SJohn Forte #define	SBUS_UPDATE_SPCLK	0x00000002	/* Bit  1 */
569fcf3ce44SJohn Forte #define	SBUS_UPDATE_SPCE	0x00000004	/* Bit  2 */
570fcf3ce44SJohn Forte #define	SBUS_UPDATE_SPRST	0x00000008	/* Bit  3 */
571fcf3ce44SJohn Forte #define	SBUS_UPDATE_SPWE	0x00000010	/* Bit  4 */
572fcf3ce44SJohn Forte #define	SBUS_UPDATE_LDFPGA	0x00000080	/* Bit  7 */
573fcf3ce44SJohn Forte 
574fcf3ce44SJohn Forte /* Host Attention Register */
575fcf3ce44SJohn Forte 
576fcf3ce44SJohn Forte #define	HA_REG_OFFSET  0	/* Word offset from register base address */
577fcf3ce44SJohn Forte 
578fcf3ce44SJohn Forte #define	HA_R0RE_REQ	0x00000001	/* Bit  0 */
579fcf3ce44SJohn Forte #define	HA_R0CE_RSP	0x00000002	/* Bit  1 */
580fcf3ce44SJohn Forte #define	HA_R0ATT	0x00000008	/* Bit  3 */
581fcf3ce44SJohn Forte #define	HA_R1RE_REQ	0x00000010	/* Bit  4 */
582fcf3ce44SJohn Forte #define	HA_R1CE_RSP	0x00000020	/* Bit  5 */
583fcf3ce44SJohn Forte #define	HA_R1ATT	0x00000080	/* Bit  7 */
584fcf3ce44SJohn Forte #define	HA_R2RE_REQ	0x00000100	/* Bit  8 */
585fcf3ce44SJohn Forte #define	HA_R2CE_RSP	0x00000200	/* Bit  9 */
586fcf3ce44SJohn Forte #define	HA_R2ATT	0x00000800	/* Bit 11 */
587fcf3ce44SJohn Forte #define	HA_R3RE_REQ	0x00001000	/* Bit 12 */
588fcf3ce44SJohn Forte #define	HA_R3CE_RSP	0x00002000	/* Bit 13 */
589fcf3ce44SJohn Forte #define	HA_R3ATT	0x00008000	/* Bit 15 */
590fcf3ce44SJohn Forte #define	HA_LATT		0x20000000	/* Bit 29 */
591fcf3ce44SJohn Forte #define	HA_MBATT	0x40000000	/* Bit 30 */
592fcf3ce44SJohn Forte #define	HA_ERATT	0x80000000	/* Bit 31 */
593fcf3ce44SJohn Forte 
594fcf3ce44SJohn Forte 
595fcf3ce44SJohn Forte #ifdef MSI_SUPPORT
596fcf3ce44SJohn Forte 
59782527734SSukumar Swaminathan 
598fcf3ce44SJohn Forte /* Host attention interrupt map */
599291a2b48SSukumar Swaminathan #define	EMLXS_MSI_MAP8	{0, HA_R0ATT, HA_R1ATT, HA_R2ATT, \
600291a2b48SSukumar Swaminathan 	HA_R3ATT, HA_LATT, HA_MBATT, HA_ERATT}
601291a2b48SSukumar Swaminathan #define	EMLXS_MSI_MAP4	{0, HA_R0ATT, HA_R1ATT, HA_R2ATT, 0, 0, 0, 0}
602291a2b48SSukumar Swaminathan #define	EMLXS_MSI_MAP2	{0, HA_R0ATT, 0, 0, 0, 0, 0, 0}
603291a2b48SSukumar Swaminathan #define	EMLXS_MSI_MAP1	{0, 0, 0, 0, 0, 0, 0, 0}
604fcf3ce44SJohn Forte 
605fcf3ce44SJohn Forte /* MSI 0 interrupt mask */
606291a2b48SSukumar Swaminathan #define	EMLXS_MSI0_MASK8	0
607291a2b48SSukumar Swaminathan #define	EMLXS_MSI0_MASK4	(HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \
608291a2b48SSukumar Swaminathan 				HC_ERINT_ENA)
609291a2b48SSukumar Swaminathan #define	EMLXS_MSI0_MASK2	(HC_R1INT_ENA|HC_R2INT_ENA|HC_R3INT_ENA| \
610291a2b48SSukumar Swaminathan 				HC_MBINT_ENA|HC_LAINT_ENA|HC_ERINT_ENA)
611291a2b48SSukumar Swaminathan #define	EMLXS_MSI0_MASK1	(HC_R0INT_ENA|HC_R1INT_ENA|HC_R2INT_ENA| \
612291a2b48SSukumar Swaminathan 				HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \
613291a2b48SSukumar Swaminathan 				HC_ERINT_ENA)
614fcf3ce44SJohn Forte 
615fcf3ce44SJohn Forte 
616291a2b48SSukumar Swaminathan #define	EMLXS_MSI_MAX_INTRS	8
617fcf3ce44SJohn Forte 
618291a2b48SSukumar Swaminathan #define	EMLXS_MSI_MODE1		0
619291a2b48SSukumar Swaminathan #define	EMLXS_MSI_MODE2		1
620291a2b48SSukumar Swaminathan #define	EMLXS_MSI_MODE4		2
621291a2b48SSukumar Swaminathan #define	EMLXS_MSI_MODE8		3
622291a2b48SSukumar Swaminathan #define	EMLXS_MSI_MODES		4
623fcf3ce44SJohn Forte 
624fcf3ce44SJohn Forte #endif	/* MSI_SUPPORT */
625fcf3ce44SJohn Forte 
626fcf3ce44SJohn Forte 
627291a2b48SSukumar Swaminathan #define	IO_THROTTLE_RESERVE	12
628fcf3ce44SJohn Forte 
629fcf3ce44SJohn Forte 
630fcf3ce44SJohn Forte 
631fcf3ce44SJohn Forte 
632fcf3ce44SJohn Forte /* Chip Attention Register */
633fcf3ce44SJohn Forte 
634291a2b48SSukumar Swaminathan #define	CA_REG_OFFSET	1	/* Word offset from register base address */
635fcf3ce44SJohn Forte 
636fcf3ce44SJohn Forte #define	CA_R0CE_REQ	0x00000001	/* Bit  0 */
637fcf3ce44SJohn Forte #define	CA_R0RE_RSP	0x00000002	/* Bit  1 */
638fcf3ce44SJohn Forte #define	CA_R0ATT	0x00000008	/* Bit  3 */
639fcf3ce44SJohn Forte #define	CA_R1CE_REQ	0x00000010	/* Bit  4 */
640fcf3ce44SJohn Forte #define	CA_R1RE_RSP	0x00000020	/* Bit  5 */
641fcf3ce44SJohn Forte #define	CA_R1ATT	0x00000080	/* Bit  7 */
642fcf3ce44SJohn Forte #define	CA_R2CE_REQ	0x00000100	/* Bit  8 */
643fcf3ce44SJohn Forte #define	CA_R2RE_RSP	0x00000200	/* Bit  9 */
644fcf3ce44SJohn Forte #define	CA_R2ATT	0x00000800	/* Bit 11 */
645fcf3ce44SJohn Forte #define	CA_R3CE_REQ	0x00001000	/* Bit 12 */
646fcf3ce44SJohn Forte #define	CA_R3RE_RSP	0x00002000	/* Bit 13 */
647fcf3ce44SJohn Forte #define	CA_R3ATT	0x00008000	/* Bit 15 */
648fcf3ce44SJohn Forte #define	CA_MBATT	0x40000000	/* Bit 30 */
649fcf3ce44SJohn Forte 
650fcf3ce44SJohn Forte /* Host Status Register */
651fcf3ce44SJohn Forte 
652291a2b48SSukumar Swaminathan #define	HS_REG_OFFSET	2	/* Word offset from register base address */
653fcf3ce44SJohn Forte 
654fcf3ce44SJohn Forte #define	HS_OVERTEMP	0x00000100	/* Bit 8 */
655fcf3ce44SJohn Forte #define	HS_MBRDY	0x00400000	/* Bit 22 */
656fcf3ce44SJohn Forte #define	HS_FFRDY	0x00800000	/* Bit 23 */
657fcf3ce44SJohn Forte #define	HS_FFER8	0x01000000	/* Bit 24 */
658fcf3ce44SJohn Forte #define	HS_FFER7	0x02000000	/* Bit 25 */
659fcf3ce44SJohn Forte #define	HS_FFER6	0x04000000	/* Bit 26 */
660fcf3ce44SJohn Forte #define	HS_FFER5	0x08000000	/* Bit 27 */
661fcf3ce44SJohn Forte #define	HS_FFER4	0x10000000	/* Bit 28 */
662fcf3ce44SJohn Forte #define	HS_FFER3	0x20000000	/* Bit 29 */
663fcf3ce44SJohn Forte #define	HS_FFER2	0x40000000	/* Bit 30 */
664fcf3ce44SJohn Forte #define	HS_FFER1	0x80000000	/* Bit 31 */
665fcf3ce44SJohn Forte #define	HS_FFERM	0xFF000000	/* Mask for error bits 31:24 */
666fcf3ce44SJohn Forte 
667fcf3ce44SJohn Forte /* Host Control Register */
668fcf3ce44SJohn Forte 
669291a2b48SSukumar Swaminathan #define	HC_REG_OFFSET	3	/* Word offset from register base address */
670fcf3ce44SJohn Forte 
671fcf3ce44SJohn Forte #define	HC_MBINT_ENA	0x00000001	/* Bit  0 */
672fcf3ce44SJohn Forte #define	HC_R0INT_ENA	0x00000002	/* Bit  1 */
673fcf3ce44SJohn Forte #define	HC_R1INT_ENA	0x00000004	/* Bit  2 */
674fcf3ce44SJohn Forte #define	HC_R2INT_ENA	0x00000008	/* Bit  3 */
675fcf3ce44SJohn Forte #define	HC_R3INT_ENA	0x00000010	/* Bit  4 */
676fcf3ce44SJohn Forte #define	HC_INITHBI	0x02000000	/* Bit 25 */
677fcf3ce44SJohn Forte #define	HC_INITMB	0x04000000	/* Bit 26 */
678fcf3ce44SJohn Forte #define	HC_INITFF	0x08000000	/* Bit 27 */
679fcf3ce44SJohn Forte #define	HC_LAINT_ENA	0x20000000	/* Bit 29 */
680fcf3ce44SJohn Forte #define	HC_ERINT_ENA	0x80000000	/* Bit 31 */
681fcf3ce44SJohn Forte 
682fcf3ce44SJohn Forte /* BIU Configuration Register */
683fcf3ce44SJohn Forte 
684291a2b48SSukumar Swaminathan #define	BC_REG_OFFSET	4	/* Word offset from register base address */
685fcf3ce44SJohn Forte 
686fcf3ce44SJohn Forte #define	BC_BSE		0x00000001	/* Bit 0 */
687fcf3ce44SJohn Forte #define	BC_BSE_SWAP	0x01000000	/* Bit 0 - swapped */
688fcf3ce44SJohn Forte 
689fcf3ce44SJohn Forte /*
690fcf3ce44SJohn Forte  * End FireFly Register definitions
691fcf3ce44SJohn Forte  */
692fcf3ce44SJohn Forte 
69382527734SSukumar Swaminathan /*