1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at 9 * http://www.opensource.org/licenses/cddl1.txt. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2004-2011 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 * Copyright 2020 RackTop Systems, Inc. 26 */ 27 28 #ifndef _EMLXS_HW_H 29 #define _EMLXS_HW_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define MAX_VPORTS 256 /* Max virtual ports per HBA */ 36 /* (includes physical port) */ 37 #define MAX_VPORTS_LIMITED 101 38 39 #define FC_MAX_TRANSFER 0x40000 /* Max transfer size per */ 40 /* operation */ 41 42 #define MAX_RINGS_AVAILABLE 4 /* # rings available */ 43 #define MAX_RINGS 4 /* Max # rings used */ 44 45 #define PCB_SIZE 128 46 47 #define SLIM_IOCB_CMD_R0_ENTRIES 128 /* SLI FCP cmd ring entries */ 48 #define SLIM_IOCB_RSP_R0_ENTRIES 128 /* SLI FCP rsp ring entries */ 49 #define SLIM_IOCB_CMD_R1_ENTRIES 128 /* SLI IP cmd ring entries */ 50 #define SLIM_IOCB_RSP_R1_ENTRIES 128 /* SLI IP rsp ring entries */ 51 #define SLIM_IOCB_CMD_R2_ENTRIES 128 /* SLI ELS cmd ring entries */ 52 #define SLIM_IOCB_RSP_R2_ENTRIES 128 /* SLI ELS rspe ring entries */ 53 #define SLIM_IOCB_CMD_R3_ENTRIES 128 /* SLI CT cmd ring entries */ 54 #define SLIM_IOCB_RSP_R3_ENTRIES 128 /* SLI CT rsp ring entries */ 55 56 /* 57 * Total: 184 Cmd's + 184 Rsp's = 368 58 * Command and response entry counts are not required to be equal 59 */ 60 61 #define SLIM_IOCB_CMD_ENTRIES (SLIM_IOCB_CMD_R0_ENTRIES + \ 62 SLIM_IOCB_CMD_R1_ENTRIES + \ 63 SLIM_IOCB_CMD_R2_ENTRIES + \ 64 SLIM_IOCB_CMD_R3_ENTRIES) 65 66 #define SLIM_IOCB_RSP_ENTRIES (SLIM_IOCB_RSP_R0_ENTRIES + \ 67 SLIM_IOCB_RSP_R1_ENTRIES + \ 68 SLIM_IOCB_RSP_R2_ENTRIES + \ 69 SLIM_IOCB_RSP_R3_ENTRIES) 70 71 #define SLIM_IOCB_ENTRIES (SLIM_IOCB_CMD_ENTRIES + \ 72 SLIM_IOCB_RSP_ENTRIES) 73 74 75 /* SLI1 Definitions */ 76 #define SLI_SLIM1_SIZE 4096 /* Fixed size memory */ 77 78 79 /* SLI2 Definitions */ 80 #define SLI2_IOCB_CMD_SIZE 32 81 #define SLI2_IOCB_RSP_SIZE 32 82 #define SLI2_IOCB_MAX_SIZE ((SLI2_IOCB_CMD_SIZE * \ 83 SLIM_IOCB_CMD_ENTRIES) + \ 84 (SLI2_IOCB_RSP_SIZE * \ 85 SLIM_IOCB_RSP_ENTRIES)) 86 #define SLI2_SLIM2_SIZE (MBOX_SIZE + MBOX_EXTENSION_SIZE + \ 87 PCB_SIZE + SLI2_IOCB_MAX_SIZE) 88 89 90 /* SLI3 Definitions */ 91 #define SLI3_MAX_BDE 7 92 #define SLI3_IOCB_CMD_SIZE 128 93 #define SLI3_IOCB_RSP_SIZE 64 94 #define SLI3_IOCB_MAX_SIZE ((SLI3_IOCB_CMD_SIZE * \ 95 SLIM_IOCB_CMD_ENTRIES) + \ 96 (SLI3_IOCB_RSP_SIZE * \ 97 SLIM_IOCB_RSP_ENTRIES)) 98 #define SLI3_SLIM2_SIZE (MBOX_SIZE + MBOX_EXTENSION_SIZE + \ 99 PCB_SIZE + SLI3_IOCB_MAX_SIZE) 100 101 #define SLI_SLIM2_SIZE SLI3_SLIM2_SIZE 102 #define SLI_IOCB_MAX_SIZE SLI3_IOCB_MAX_SIZE 103 104 105 /* These two are defined to indicate FCP cmd or non FCP cmd */ 106 #define FC_FCP_CMD 0 107 #define FC_FCT_CMD 0 108 #define FC_IP_CMD 1 109 #define FC_ELS_CMD 2 110 #define FC_CT_CMD 3 111 112 #define FC_NFCP_CMD 1 /* could be a bit mask */ 113 114 #define FC_MAXRETRY 3 /* max retries for ELS commands */ 115 #define FC_FCP_RING 0 /* use ring 0 for FCP initiator cmds */ 116 #define FC_FCT_RING 0 /* use ring 0 for FCP target cmds */ 117 118 #define FC_IP_RING 1 /* use ring 1 for IP commands */ 119 #define FC_ELS_RING 2 /* use ring 2 for ELS commands */ 120 #define FC_CT_RING 3 /* use ring 3 for CT commands */ 121 122 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 123 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 124 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 125 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 126 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG */ 127 /* iocb */ 128 #define FF_REG_AREA_SIZE 256 /* size, in bytes, of i/o register */ 129 /* area */ 130 131 /* 132 * Miscellaneous stuff.... 133 */ 134 135 #define MAX_NODE_THROTTLE 2048 136 137 /* HBA Mgmt */ 138 #define FDMI_DID ((uint32_t)0xfffffa) 139 #define NAMESERVER_DID ((uint32_t)0xfffffc) 140 #define SCR_DID ((uint32_t)0xfffffd) 141 #define FABRIC_DID ((uint32_t)0xfffffe) 142 #define BCAST_DID ((uint32_t)0xffffff) 143 #define MASK_DID ((uint32_t)0xffffff) 144 #define CT_DID_MASK ((uint32_t)0xffff00) 145 #define FABRIC_DID_MASK ((uint32_t)0xfff000) 146 #define WELL_KNOWN_DID_MASK ((uint32_t)0xfffff0) 147 148 #define EMLXS_MENLO_DID ((uint32_t)0x00fc0e) 149 150 #define OWN_CHIP 1 /* IOCB / Mailbox is owned by FireFly */ 151 #define OWN_HOST 0 /* IOCB / Mailbox is owned by Host */ 152 #define END_OF_CHAIN 0 153 154 155 /* defines for type field in fc header */ 156 #define EMLXS_MENLO_TYPE 0xFE 157 158 /* defines for rctl field in fc header */ 159 #define FC_DEV_DATA 0x0 160 #define FC_UNSOL_CTL 0x2 161 #define FC_SOL_CTL 0x3 162 #define FC_UNSOL_DATA 0x4 163 #define FC_FCP_CMND 0x6 164 #define FC_ELS_REQ 0x22 165 #define FC_ELS_RSP 0x23 166 #define FC_NET_HDR 0x20 /* network headers for Dfctl field */ 167 168 /* 169 * Common Transport structures and definitions 170 * 171 */ 172 #define EMLXS_COMMAND 0 173 #define EMLXS_RESPONSE 1 174 175 typedef union CtRevisionId 176 { 177 /* Structure is in Big Endian format */ 178 struct 179 { 180 uint32_t Revision:8; 181 uint32_t InId:24; 182 } bits; 183 uint32_t word; 184 } CtRevisionId_t; 185 186 typedef union CtCommandResponse 187 { 188 /* Structure is in Big Endian format */ 189 struct 190 { 191 uint32_t CmdRsp:16; 192 uint32_t Size:16; 193 } bits; 194 uint32_t word; 195 } CtCommandResponse_t; 196 197 typedef struct SliCtRequest 198 { 199 /* Structure is in Big Endian format */ 200 CtRevisionId_t RevisionId; 201 uint8_t FsType; 202 uint8_t FsSubType; 203 uint8_t Options; 204 uint8_t Rsrvd1; 205 CtCommandResponse_t CommandResponse; 206 uint8_t Rsrvd2; 207 uint8_t ReasonCode; 208 uint8_t Explanation; 209 uint8_t VendorUnique; 210 211 union 212 { 213 uint32_t data; 214 uint32_t PortID; 215 216 struct gid 217 { 218 uint8_t PortType; /* for GID_PT requests */ 219 uint8_t DomainScope; 220 uint8_t AreaScope; 221 uint8_t Fc4Type; /* for GID_FT requests */ 222 } gid; 223 struct rft 224 { 225 uint32_t PortId; /* For RFT_ID requests */ 226 #ifdef EMLXS_BIG_ENDIAN 227 uint32_t rsvd0:16; 228 uint32_t rsvd1:7; 229 uint32_t fcpReg:1; /* Type 8 */ 230 uint32_t rsvd2:2; 231 uint32_t ipReg:1; /* Type 5 */ 232 uint32_t rsvd3:5; 233 #endif 234 #ifdef EMLXS_LITTLE_ENDIAN 235 uint32_t rsvd0:16; 236 uint32_t fcpReg:1; /* Type 8 */ 237 uint32_t rsvd1:7; 238 uint32_t rsvd3:5; 239 uint32_t ipReg:1; /* Type 5 */ 240 uint32_t rsvd2:2; 241 #endif 242 uint32_t rsvd[7]; 243 } rft; 244 245 struct rsnn 246 { 247 uint8_t wwnn[8]; 248 uint8_t snn_len; 249 char snn[256]; 250 } rsnn; 251 252 struct rspn 253 { 254 uint32_t PortId; 255 uint8_t spn_len; 256 char spn[256]; 257 } rspn; 258 } un; 259 } SliCtRequest_t; 260 typedef SliCtRequest_t SLI_CT_REQUEST; 261 262 #define SLI_CT_REVISION 1 263 264 265 /* 266 * FsType Definitions 267 */ 268 269 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 270 #define SLI_CT_TIME_SERVICE 0xFB 271 #define SLI_CT_DIRECTORY_SERVICE 0xFC 272 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 273 274 /* 275 * Directory Service Subtypes 276 */ 277 278 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 279 280 /* 281 * Response Codes 282 */ 283 284 #define SLI_CT_RESPONSE_FS_RJT 0x8001 285 #define SLI_CT_RESPONSE_FS_ACC 0x8002 286 287 /* 288 * Reason Codes 289 */ 290 291 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 292 #define SLI_CT_INVALID_COMMAND 0x01 293 #define SLI_CT_INVALID_VERSION 0x02 294 #define SLI_CT_LOGICAL_ERROR 0x03 295 #define SLI_CT_INVALID_IU_SIZE 0x04 296 #define SLI_CT_LOGICAL_BUSY 0x05 297 #define SLI_CT_PROTOCOL_ERROR 0x07 298 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 299 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 300 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 301 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 302 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 303 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 304 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 305 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 306 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 307 #define SLI_CT_VENDOR_UNIQUE 0xff 308 309 /* 310 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 311 */ 312 313 #define SLI_CT_NO_PORT_ID 0x01 314 #define SLI_CT_NO_PORT_NAME 0x02 315 #define SLI_CT_NO_NODE_NAME 0x03 316 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 317 #define SLI_CT_NO_IP_ADDRESS 0x05 318 #define SLI_CT_NO_IPA 0x06 319 #define SLI_CT_NO_FC4_TYPES 0x07 320 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 321 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 322 #define SLI_CT_NO_PORT_TYPE 0x0A 323 #define SLI_CT_ACCESS_DENIED 0x10 324 #define SLI_CT_INVALID_PORT_ID 0x11 325 #define SLI_CT_DATABASE_EMPTY 0x12 326 327 #ifdef EMLXS_BIG_ENDIAN 328 #define CT_CMD_MASK 0xffff0000 329 #endif 330 331 #ifdef EMLXS_LITTLE_ENDIAN 332 #define CT_CMD_MASK 0xffff 333 #endif 334 335 /* 336 * Management Server Interface Command Codes 337 */ 338 339 #define MS_GTIN 0x0100 340 #define MS_GIEL 0x0101 341 #define MS_GIET 0x0111 342 #define MS_GDID 0x0112 343 #define MS_GMID 0x0113 344 #define MS_GFN 0x0114 345 #define MS_GIELN 0x0115 346 #define MS_GMAL 0x0116 347 #define MS_GIEIL 0x0117 348 #define MS_GPL 0x0118 349 #define MS_GPT 0x0121 350 #define MS_GPPN 0x0122 351 #define MS_GAPNL 0x0124 352 #define MS_GPS 0x0126 353 #define MS_GPSC 0x0127 354 #define MS_GATIN 0x0128 355 #define MS_GSES 0x0130 356 #define MS_GPLNL 0x0191 357 #define MS_GPLT 0x0192 358 #define MS_GPLML 0x0193 359 #define MS_GPAB 0x0197 360 #define MS_GNPL 0x01A1 361 #define MS_GPNL 0x01A2 362 #define MS_GPFCP 0x01A4 363 #define MS_GPLI 0x01A5 364 #define MS_GNID 0x01B1 365 #define MS_RIELN 0x0215 366 #define MS_RPL 0x0280 367 #define MS_RPLN 0x0291 368 #define MS_RPLT 0x0292 369 #define MS_RPLM 0x0293 370 #define MS_RPAB 0x0298 371 #define MS_RPFCP 0x029A 372 #define MS_RPLI 0x029B 373 #define MS_DPL 0x0380 374 #define MS_DPLN 0x0391 375 #define MS_DPLM 0x0392 376 #define MS_DPLML 0x0393 377 #define MS_DPLI 0x0394 378 #define MS_DPAB 0x0395 379 #define MS_DPALL 0x039F 380 381 /* 382 * Name Server Command Codes 383 */ 384 #define SLI_CTNS_GA_NXT 0x0100 385 #define SLI_CTNS_GPN_ID 0x0112 386 #define SLI_CTNS_GNN_ID 0x0113 387 #define SLI_CTNS_GCS_ID 0x0114 388 #define SLI_CTNS_GFT_ID 0x0117 389 #define SLI_CTNS_GSPN_ID 0x0118 390 #define SLI_CTNS_GPT_ID 0x011A 391 #define SLI_CTNS_GID_PN 0x0121 392 #define SLI_CTNS_GID_NN 0x0131 393 #define SLI_CTNS_GIP_NN 0x0135 394 #define SLI_CTNS_GIPA_NN 0x0136 395 #define SLI_CTNS_GSNN_NN 0x0139 396 #define SLI_CTNS_GNN_IP 0x0153 397 #define SLI_CTNS_GIPA_IP 0x0156 398 #define SLI_CTNS_GID_FT 0x0171 399 #define SLI_CTNS_GID_PT 0x01A1 400 #define SLI_CTNS_RPN_ID 0x0212 401 #define SLI_CTNS_RNN_ID 0x0213 402 #define SLI_CTNS_RCS_ID 0x0214 403 #define SLI_CTNS_RFT_ID 0x0217 404 #define SLI_CTNS_RSPN_ID 0x0218 405 #define SLI_CTNS_RPT_ID 0x021A 406 #define SLI_CTNS_RIP_NN 0x0235 407 #define SLI_CTNS_RIPA_NN 0x0236 408 #define SLI_CTNS_RSNN_NN 0x0239 409 #define SLI_CTNS_DA_ID 0x0300 410 411 #define SLI_CT_LOOPBACK 0xFCFC 412 413 414 /* 415 * Port Types 416 */ 417 418 #define SLI_CTPT_N_PORT 0x01 419 #define SLI_CTPT_NL_PORT 0x02 420 #define SLI_CTPT_FNL_PORT 0x03 421 #define SLI_CTPT_IP 0x04 422 #define SLI_CTPT_FCP 0x08 423 #define SLI_CTPT_NX_PORT 0x7F 424 #define SLI_CTPT_F_PORT 0x81 425 #define SLI_CTPT_FL_PORT 0x82 426 #define SLI_CTPT_E_PORT 0x84 427 428 #define SLI_CT_LAST_ENTRY 0x80000000 429 430 /* ===================================================================== */ 431 432 /* 433 * Start FireFly Register definitions 434 */ 435 436 /* PCI register offsets */ 437 #define MEM_ADDR_OFFSET 0x10 /* SLIM base memory address */ 438 #define MEMH_OFFSET 0x14 /* SLIM base memory high address */ 439 #define REG_ADDR_OFFSET 0x18 /* REGISTER base memory address */ 440 #define REGH_OFFSET 0x1c /* REGISTER base memory high address */ 441 #define IO_ADDR_OFFSET 0x20 /* BIU I/O registers */ 442 #define REGIOH_OFFSET 0x24 /* REGISTER base io high address */ 443 444 #define CMD_REG_OFFSET 0x4 /* PCI command configuration */ 445 446 /* General PCI Register Definitions */ 447 /* Refer To The PCI Specification For Detailed Explanations */ 448 449 #define PCI_VENDOR_ID_REGISTER 0x00 /* PCI Vendor ID Reg */ 450 #define PCI_DEVICE_ID_REGISTER 0x02 /* PCI Device ID Reg */ 451 #define PCI_CONFIG_ID_REGISTER 0x00 /* PCI Configuration ID Reg */ 452 #define PCI_COMMAND_REGISTER 0x04 /* PCI Command Reg */ 453 #define PCI_STATUS_REGISTER 0x06 /* PCI Status Reg */ 454 #define PCI_REV_ID_REGISTER 0x08 /* PCI Revision ID Reg */ 455 #define PCI_CLASS_CODE_REGISTER 0x09 /* PCI Class Code Reg */ 456 #define PCI_CACHE_LINE_REGISTER 0x0C /* PCI Cache Line Reg */ 457 #define PCI_LATENCY_TMR_REGISTER 0x0D /* PCI Latency Timer Reg */ 458 #define PCI_HEADER_TYPE_REGISTER 0x0E /* PCI Header Type Reg */ 459 #define PCI_BIST_REGISTER 0x0F /* PCI Built-In SelfTest Reg */ 460 #define PCI_BAR_0_REGISTER 0x10 /* PCI Base Address Reg 0 */ 461 #define PCI_BAR_1_REGISTER 0x14 /* PCI Base Address Reg 1 */ 462 #define PCI_BAR_2_REGISTER 0x18 /* PCI Base Address Reg 2 */ 463 #define PCI_BAR_3_REGISTER 0x1C /* PCI Base Address Reg 3 */ 464 #define PCI_BAR_4_REGISTER 0x20 /* PCI Base Address Reg 4 */ 465 #define PCI_BAR_5_REGISTER 0x24 /* PCI Base Address Reg 5 */ 466 #define PCI_SSID_REGISTER 0x2C 467 #define PCI_SSVID_REGISTER 0x2C 468 #define PCI_SSDID_REGISTER 0x2E 469 #define PCI_EXPANSION_ROM 0x30 /* PCI Expansion ROM Base Reg */ 470 #define PCI_CAP_POINTER 0x34 471 472 /* PCI capatability registers are defined in pci.h */ 473 #define PCI_CAP_ID_SHIFT 0 474 #define PCI_CAP_ID_MASK 0xff 475 #define PCI_CAP_NEXT_PTR_SHIFT 8 476 #define PCI_CAP_NEXT_PTR_MASK 0xff 477 478 /* PCI extended capatability registers are defined in pcie.h */ 479 #define PCI_EXT_CAP_MAX_PTR 0x30 480 481 #define PCI_EXT_CAP_ID_MRIOV 0x0000 /* ??? */ 482 #define PCI_EXT_CAP_ID_SRIOV 0x0010 483 #define PCI_EXT_CAP_ID_11 0x0011 484 #define PCI_EXT_CAP_ID_12 0x0012 485 #define PCI_EXT_CAP_ID_13 0x0013 486 #define PCI_EXT_CAP_ID_14 0x0014 487 #define PCI_EXT_CAP_ID_15 0x0015 488 #define PCI_EXT_CAP_ID_16 0x0016 489 #define PCI_EXT_CAP_ID_TPH 0x0017 490 #define PCI_EXT_CAP_ID_18 0x0018 491 #define PCI_EXT_CAP_ID_SEC_PCI 0x0019 492 493 /* Vendor Specific (VS) register */ 494 #define PCI_VS_SLI_INTF_OFFSET 4 495 496 /* PCI access methods */ 497 #define P_CONF_T1 1 498 #define P_CONF_T2 2 499 500 /* max number of pci buses */ 501 #define MAX_PCI_BUSES 0xFF 502 503 /* number of PCI config bytes to access */ 504 #define PCI_BYTE 1 505 #define PCI_WORD 2 506 #define PCI_DWORD 4 507 508 /* PCI related constants */ 509 #define CMD_IO_ENBL 0x0001 510 #define CMD_MEM_ENBL 0x0002 511 #define CMD_BUS_MASTER 0x0004 512 #define CMD_MWI 0x0010 513 #define CMD_PARITY_CHK 0x0040 514 #define CMD_SERR_ENBL 0x0100 515 516 #define CMD_CFG_VALUE 0x156 /* mem enable, master, MWI, SERR, PERR */ 517 518 /* PCI addresses */ 519 #define PCI_SPACE_ENABLE 0x0CF8 520 #define CF1_CONFIG_ADDR_REGISTER 0x0CF8 521 #define CF1_CONFIG_DATA_REGISTER 0x0CFC 522 #define CF2_FORWARD_REGISTER 0x0CFA 523 #define CF2_BASE_ADDRESS 0xC000 524 525 526 #define DEFAULT_PCI_LATENCY_CLOCKS 0xf8 /* 0xF8 is a special value */ 527 /* for FF11.1N6 firmware. */ 528 /* Use 0x80 for pre-FF11.1N6 */ 529 /* &N7, etc */ 530 #define PCI_LATENCY_VALUE 0xf8 531 532 533 534 /* ==== Register Bit Definitions ==== */ 535 536 /* Used by SBUS adapter */ 537 /* SBUS Control Register */ 538 #define SBUS_CTRL_REG_OFFSET 0 /* Word offset from reg base addr */ 539 540 #define SBUS_CTRL_SBRST 0x00000001 /* Bit 0 */ 541 #define SBUS_CTRL_BKOFF 0x00000002 /* Bit 1 */ 542 #define SBUS_CTRL_ENP 0x00000004 /* Bit 2 */ 543 #define SBUS_CTRL_EN64 0x00000008 /* Bit 3 */ 544 #define SBUS_CTRL_SIR_1 0x00000010 /* Bit [6:4] IRL 1, */ 545 /* lowset priority */ 546 #define SBUS_CTRL_SIR_2 0x00000020 547 #define SBUS_CTRL_SIR_3 0x00000030 548 #define SBUS_CTRL_SIR_4 0x00000040 549 #define SBUS_CTRL_SIR_5 0x00000050 550 #define SBUS_CTRL_SIR_6 0x00000060 551 #define SBUS_CTRL_SIR_7 0x00000070 /* IRL 7, highest priority */ 552 553 /* SBUS Status Register */ 554 #define SBUS_STAT_REG_OFFSET 1 /* Word offset from reg base addr */ 555 #define SBUS_STAT_IP 0x00000001 /* Bit 0 */ 556 #define SBUS_STAT_LERR 0x00000002 /* Bit 1 */ 557 #define SBUS_STAT_SBPE 0x00000004 /* Bit 2 */ 558 #define SBUS_STAT_TE 0x00000008 /* Bit 3 */ 559 #define SBUS_STAT_WPE 0x00000010 /* Bit 4 */ 560 #define SBUS_STAT_PERR 0x00000020 /* Bit 5 */ 561 #define SBUS_STAT_SERR 0x00000040 /* Bit 6 */ 562 #define SBUS_STAT_PTA 0x00000080 /* Bit 7 */ 563 564 /* SBUS Update Register */ 565 #define SBUS_UPDATE_REG_OFFSET 2 /* Word offfset from reg base addr */ 566 567 #define SBUS_UPDATE_DATA 0x00000001 /* Bit 0 */ 568 #define SBUS_UPDATE_SPCLK 0x00000002 /* Bit 1 */ 569 #define SBUS_UPDATE_SPCE 0x00000004 /* Bit 2 */ 570 #define SBUS_UPDATE_SPRST 0x00000008 /* Bit 3 */ 571 #define SBUS_UPDATE_SPWE 0x00000010 /* Bit 4 */ 572 #define SBUS_UPDATE_LDFPGA 0x00000080 /* Bit 7 */ 573 574 /* Host Attention Register */ 575 576 #define HA_REG_OFFSET 0 /* Word offset from register base address */ 577 578 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 579 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 580 #define HA_R0ATT 0x00000008 /* Bit 3 */ 581 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 582 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 583 #define HA_R1ATT 0x00000080 /* Bit 7 */ 584 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 585 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 586 #define HA_R2ATT 0x00000800 /* Bit 11 */ 587 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 588 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 589 #define HA_R3ATT 0x00008000 /* Bit 15 */ 590 #define HA_LATT 0x20000000 /* Bit 29 */ 591 #define HA_MBATT 0x40000000 /* Bit 30 */ 592 #define HA_ERATT 0x80000000 /* Bit 31 */ 593 594 595 #ifdef MSI_SUPPORT 596 597 598 /* Host attention interrupt map */ 599 #define EMLXS_MSI_MAP8 {0, HA_R0ATT, HA_R1ATT, HA_R2ATT, \ 600 HA_R3ATT, HA_LATT, HA_MBATT, HA_ERATT} 601 #define EMLXS_MSI_MAP4 {0, HA_R0ATT, HA_R1ATT, HA_R2ATT, 0, 0, 0, 0} 602 #define EMLXS_MSI_MAP2 {0, HA_R0ATT, 0, 0, 0, 0, 0, 0} 603 #define EMLXS_MSI_MAP1 {0, 0, 0, 0, 0, 0, 0, 0} 604 605 /* MSI 0 interrupt mask */ 606 #define EMLXS_MSI0_MASK8 0 607 #define EMLXS_MSI0_MASK4 (HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \ 608 HC_ERINT_ENA) 609 #define EMLXS_MSI0_MASK2 (HC_R1INT_ENA|HC_R2INT_ENA|HC_R3INT_ENA| \ 610 HC_MBINT_ENA|HC_LAINT_ENA|HC_ERINT_ENA) 611 #define EMLXS_MSI0_MASK1 (HC_R0INT_ENA|HC_R1INT_ENA|HC_R2INT_ENA| \ 612 HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \ 613 HC_ERINT_ENA) 614 615 616 #define EMLXS_MSI_MAX_INTRS 8 617 618 #define EMLXS_MSI_MODE1 0 619 #define EMLXS_MSI_MODE2 1 620 #define EMLXS_MSI_MODE4 2 621 #define EMLXS_MSI_MODE8 3 622 #define EMLXS_MSI_MODES 4 623 624 #endif /* MSI_SUPPORT */ 625 626 627 #define IO_THROTTLE_RESERVE 12 628 629 630 631 632 /* Chip Attention Register */ 633 634 #define CA_REG_OFFSET 1 /* Word offset from register base address */ 635 636 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 637 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 638 #define CA_R0ATT 0x00000008 /* Bit 3 */ 639 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 640 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 641 #define CA_R1ATT 0x00000080 /* Bit 7 */ 642 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 643 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 644 #define CA_R2ATT 0x00000800 /* Bit 11 */ 645 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 646 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 647 #define CA_R3ATT 0x00008000 /* Bit 15 */ 648 #define CA_MBATT 0x40000000 /* Bit 30 */ 649 650 /* Host Status Register */ 651 652 #define HS_REG_OFFSET 2 /* Word offset from register base address */ 653 654 #define HS_OVERTEMP 0x00000100 /* Bit 8 */ 655 #define HS_MBRDY 0x00400000 /* Bit 22 */ 656 #define HS_FFRDY 0x00800000 /* Bit 23 */ 657 #define HS_FFER8 0x01000000 /* Bit 24 */ 658 #define HS_FFER7 0x02000000 /* Bit 25 */ 659 #define HS_FFER6 0x04000000 /* Bit 26 */ 660 #define HS_FFER5 0x08000000 /* Bit 27 */ 661 #define HS_FFER4 0x10000000 /* Bit 28 */ 662 #define HS_FFER3 0x20000000 /* Bit 29 */ 663 #define HS_FFER2 0x40000000 /* Bit 30 */ 664 #define HS_FFER1 0x80000000 /* Bit 31 */ 665 #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */ 666 667 /* Host Control Register */ 668 669 #define HC_REG_OFFSET 3 /* Word offset from register base address */ 670 671 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 672 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 673 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 674 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 675 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 676 #define HC_INITHBI 0x02000000 /* Bit 25 */ 677 #define HC_INITMB 0x04000000 /* Bit 26 */ 678 #define HC_INITFF 0x08000000 /* Bit 27 */ 679 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 680 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 681 682 /* BIU Configuration Register */ 683 684 #define BC_REG_OFFSET 4 /* Word offset from register base address */ 685 686 #define BC_BSE 0x00000001 /* Bit 0 */ 687 #define BC_BSE_SWAP 0x01000000 /* Bit 0 - swapped */ 688 689 /* 690 * End FireFly Register definitions 691 */ 692 693 /* 694 * Start SLI 4 section. 695 */ 696 697 /* PCI Config Register offsets */ 698 #define PCICFG_UE_STATUS_LO_OFFSET 0xA0 /* Error Indication - low */ 699 #define PCICFG_UE_STATUS_HI_OFFSET 0xA4 /* Error Indication - high */ 700 #define PCICFG_UE_MASK_LO_OFFSET 0xA8 /* Error mask - low */ 701 #define PCICFG_UE_MASK_HI_OFFSET 0xAC /* Error mask - high */ 702 #define PCICFG_UE_STATUS_ONLINE1 0xB0 /* Error status1 */ 703 #define PCICFG_UE_STATUS_ONLINE2 0xB4 /* Error status2 */ 704 705 /* BAR1 and BAR2 register offsets */ 706 707 /* BAR1 offsets for principal registers */ 708 #define CSR_ISR0_OFFSET 0x0C18 /* CSR for EQ interrupt indications */ 709 #define CSR_IMR0_OFFSET 0x0C48 /* CSR for EQ interrupt masking */ 710 #define CSR_ISCR0_OFFSET 0x0C78 /* CSR for EQ interrupt clearing */ 711 712 #define ISR0_EQ0_INDC 0x00000001 /* Indication bit for EQ0 */ 713 #define ISR0_EQ1_INDC 0x00000002 /* Indication bit for EQ1 */ 714 #define ISR0_EQ2_INDC 0x00000004 /* Indication bit for EQ2 */ 715 #define ISR0_EQ3_INDC 0x00000008 /* Indication bit for EQ3 */ 716 #define ISR0_EQ4_INDC 0x00000010 /* Indication bit for EQ4 */ 717 #define ISR0_EQ5_INDC 0x00000020 /* Indication bit for EQ5 */ 718 #define ISR0_EQ6_INDC 0x00000040 /* Indication bit for EQ6 */ 719 #define ISR0_EQ7_INDC 0x00000080 /* Indication bit for EQ7 */ 720 721 /* MPU EP Semaphore register (ARM POST) */ 722 #define CSR_MPU_EP_SEMAPHORE_OFFSET 0x00AC 723 724 /* SLI Status register */ 725 #define SLI_STATUS_ERROR 0x80000000 726 #define SLI_STATUS_BE 0x40000000 727 #define SLI_STATUS_OTI 0x20000000 728 #define SLI_STATUS_DUMP_LOCATION 0x04000000 729 #define SLI_STATUS_DUMP_IMAGE_PRESENT 0x02000000 730 #define SLI_STATUS_RESET_NEEDED 0x01000000 731 #define SLI_STATUS_READY 0x00800000 732 #define SLI_STATUS_INTERRUPT_DISABLE 0x00400000 733 734 /* SLI Control register */ 735 #define SLI_CNTL_BE 0x40000000 736 #define SLI_CNTL_INIT_PORT 0x08000000 737 738 /* SLI PHYDEV Control register */ 739 #define SLI_PHYDEV_RERROR 0x80000000 740 #define SLI_PHYDEV_INP 0x40000000 741 #define SLI_PHYDEV_IPLD 0x00008000 742 #define SLI_PHYDEV_GPC 0x00004000 743 #define SLI_PHYDEV_GP 0x00002000 744 745 #define SLI_PHYDEV_RC_MASK 0x00000700 746 #define SLI_PHYDEV_RC_UNKNOWN 0x00000000 747 #define SLI_PHYDEV_RC_PROFILE 0x00000100 748 #define SLI_PHYDEV_RC_FACTORY 0x00000200 749 750 #define SLI_PHYDEV_FRL_MASK 0x000000F0 751 #define SLI_PHYDEV_FRL_ALL 0x00000000 752 #define SLI_PHYDEV_FRL_FCOE 0x00000010 753 754 #define SLI_PHYDEV_LC 0x00000008 755 #define SLI_PHYDEV_DD 0x00000004 756 #define SLI_PHYDEV_FRST 0x00000002 757 #define SLI_PHYDEV_DRST 0x00000001 758 759 /* POST Stages of interest */ 760 #define ARM_POST_FATAL 0x80000000 761 #define ARM_POST_READY 0xc000 762 #define ARM_POST_MASK 0xffff 763 #define ARM_UNRECOVERABLE_ERROR 0xf000 764 765 #define MPU_EP_DL 0x04000000 /* Driverloadedbitmask */ 766 #define MPU_EP_ORI 0x08000000 /* OptionROMinstalledbitmask */ 767 #define MPU_EP_IPC 0x10000000 /* IPaddressconflictmask */ 768 #define MPU_EP_NIP 0x20000000 /* NoIPaddressmask */ 769 #define MPU_EP_BFW 0x40000000 /* BackupFWinusemask */ 770 #define MPU_EP_ERR 0x80000000 /* POSTfatalerrormask */ 771 772 /* BAR2 offsets for principal doorbell registers */ 773 774 #define PD_RQ_DB_OFFSET 0x00A0 /* Doorbell notify of posted RQEs */ 775 #define PD_WQ_DB_OFFSET 0x0040 /* Doorbell notify of posted WQEs */ 776 #define PD_CQ_DB_OFFSET 0x0120 /* Doorbell notify of processed CQEs or EQEs */ 777 #define PD_MQ_DB_OFFSET 0x0140 /* Doorbell notify of posted MQEs */ 778 #define PD_MB_DB_OFFSET 0x0160 /* Doorbell Bootstrap Mailbox */ 779 780 #define SLIPORT_SEMAPHORE_OFFSET 0x0400 781 #define SLIPORT_STATUS_OFFSET 0x0404 782 #define SLIPORT_CONTROL_OFFSET 0x0408 783 #define SLIPORT_ERROR1_OFFSET 0x040C 784 #define SLIPORT_ERROR2_OFFSET 0x0410 785 #define PHYSDEV_CONTROL_OFFSET 0x0414 786 787 788 /* Doorbell definitions */ 789 790 /* Defines for MQ doorbell */ 791 #define MQ_DB_POP_SHIFT 16 /* shift for entries popped */ 792 #define MQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ 793 794 /* Defines for CQ doorbell */ 795 #define CQ_DB_POP_SHIFT 16 /* shift for entries popped */ 796 #define CQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ 797 #define CQ_DB_REARM 0x20000000 /* Bit 29, rearm */ 798 #define CQ_ID_LO_BITS 10 /* num of id bits that are "low" */ 799 #define CQ_DB_ID_LO_MASK ((1 << CQ_ID_LO_BITS) - 1) 800 #define CQ_DB_ID_HI_SHIFT 11 801 #define CQ_DB_ID_HI_MASK (0x1F << CQ_DB_ID_HI_SHIFT) 802 803 /* Defines for EQ doorbell */ 804 #define EQ_DB_CLEAR 0x00000200 /* Bit 9, designates clear EQ ISR */ 805 #define EQ_DB_EVENT 0x00000400 /* Bit 10, designates EQ */ 806 #define EQ_DB_POP_SHIFT 16 /* shift for entries popped */ 807 #define EQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ 808 #define EQ_DB_REARM 0x20000000 /* Bit 29, rearm */ 809 #define EQ_ID_LO_BITS 9 /* num of id bits that are "low" */ 810 #define EQ_DB_ID_LO_MASK ((1 << EQ_ID_LO_BITS) - 1) 811 #define EQ_DB_ID_HI_SHIFT 11 812 #define EQ_DB_ID_HI_MASK (0x1F << EQ_DB_ID_HI_SHIFT) 813 814 /* Defines for WQ doorbell */ 815 #define WQ_DB_POST_SHIFT 24 816 #define WQ_DB_POST_MASK (0xFF << WQ_DB_POST_SHIFT) 817 #define WQ_DB_IDX_SHIFT 16 818 #define WQ_DB_IDX_MASK (0xFF << WQ_DB_IDX_SHIFT) 819 820 /* bootstrap mailbox doorbell defines */ 821 #define BMBX_READY 0x00000001 /* Mask for Port Ready bit */ 822 #define BMBX_ADDR_HI 0x00000002 /* Mask for Addr Hi bit */ 823 #define BMBX_ADDR 0xFFFFFFFC /* Mask for Addr bits */ 824 825 /* Sizeof bootstrap mailbox */ 826 #define EMLXS_BOOTSTRAP_MB_SIZE 256 827 828 #define FW_INITIALIZE_WORD0 0xFF1234FF /* Initialize bootstrap wd 0 */ 829 #define FW_INITIALIZE_WORD1 0xFF5678FF /* Initialize bootstrap wd 1 */ 830 831 #define FW_DEINITIALIZE_WORD0 0xFFAABBFF /* DeInitialize bootstrap wd 0 */ 832 #define FW_DEINITIALIZE_WORD1 0xFFCCDDFF /* DeInitialize bootstrap wd 1 */ 833 834 /* ===================================================================== */ 835 836 /* 837 * Start of FCP specific structures 838 */ 839 840 typedef struct emlxs_fcp_rsp 841 { 842 uint32_t rspRsvd1; /* FC Word 0, byte 0:3 */ 843 uint32_t rspRsvd2; /* FC Word 1, byte 0:3 */ 844 845 uint8_t rspStatus0; /* FCP_STATUS byte 0 (reserved) */ 846 uint8_t rspStatus1; /* FCP_STATUS byte 1 (reserved) */ 847 uint8_t rspStatus2; /* FCP_STATUS byte 2 field validity */ 848 #define RSP_LEN_VALID 0x01 /* bit 0 */ 849 #define SNS_LEN_VALID 0x02 /* bit 1 */ 850 #define RESID_OVER 0x04 /* bit 2 */ 851 #define RESID_UNDER 0x08 /* bit 3 */ 852 853 uint8_t rspStatus3; /* FCP_STATUS byte 3 SCSI status byte */ 854 #define SCSI_STAT_GOOD 0x00 855 #define SCSI_STAT_CHECK_COND 0x02 856 #define SCSI_STAT_COND_MET 0x04 857 #define SCSI_STAT_BUSY 0x08 858 #define SCSI_STAT_INTERMED 0x10 859 #define SCSI_STAT_INTERMED_CM 0x14 860 #define SCSI_STAT_RES_CNFLCT 0x18 861 #define SCSI_STAT_CMD_TERM 0x22 862 #define SCSI_STAT_QUE_FULL 0x28 863 #define SCSI_STAT_ACA_ACTIVE 0x30 864 #define SCSI_STAT_TASK_ABORT 0x40 865 866 uint32_t rspResId; /* Residual xfer if RESID_xxxx set */ 867 /* in fcpStatus2. */ 868 /* Received in Big Endian format */ 869 uint32_t rspSnsLen; /* Length of sense data in fcpSnsInfo */ 870 /* Received in Big Endian format */ 871 uint32_t rspRspLen; /* Length of FCP response data */ 872 /* in fcpRspInfo */ 873 /* Received in Big Endian format */ 874 875 uint8_t rspInfo0; /* FCP_RSP_INFO byte 0 (reserved) */ 876 uint8_t rspInfo1; /* FCP_RSP_INFO byte 1 (reserved) */ 877 uint8_t rspInfo2; /* FCP_RSP_INFO byte 2 (reserved) */ 878 uint8_t rspInfo3; /* FCP_RSP_INFO RSP_CODE byte 3 */ 879 880 #define RSP_NO_FAILURE 0x00 881 #define RSP_DATA_BURST_ERR 0x01 882 #define RSP_CMD_FIELD_ERR 0x02 883 #define RSP_RO_MISMATCH_ERR 0x03 884 #define RSP_TM_NOT_SUPPORTED 0x04 /* Task mgmt function not supported */ 885 #define RSP_TM_NOT_COMPLETED 0x05 /* Task mgmt function not performed */ 886 887 uint32_t rspInfoRsvd; /* FCP_RSP_INFO bytes 4-7 (reserved) */ 888 889 /* 890 * Define maximum size of SCSI Sense buffer. 891 * Seagate never issues more than 18 bytes of Sense data 892 */ 893 #define MAX_FCP_SNS 128 894 uint8_t rspSnsInfo[MAX_FCP_SNS]; 895 } emlxs_fcp_rsp; 896 typedef emlxs_fcp_rsp FCP_RSP; 897 898 899 typedef struct emlxs_fcp_cmd 900 { 901 uint32_t fcpLunMsl; /* most significant lun word */ 902 uint32_t fcpLunLsl; /* least significant lun word */ 903 904 /* 905 * # of bits to shift lun id to end up in right payload word, 906 * little endian = 8, big = 16. 907 */ 908 #ifdef EMLXS_LITTLE_ENDIAN 909 #define FC_LUN_SHIFT 8 910 #define FC_ADDR_MODE_SHIFT 0 911 #endif 912 #ifdef EMLXS_BIG_ENDIAN 913 #define FC_LUN_SHIFT 16 914 #define FC_ADDR_MODE_SHIFT 24 915 #endif 916 917 uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */ 918 uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */ 919 #define SIMPLE_Q 0x00 920 #define HEAD_OF_Q 0x01 921 #define ORDERED_Q 0x02 922 #define ACA_Q 0x04 923 #define UNTAGGED 0x05 924 925 uint8_t fcpCntl2; /* FCP_CTL byte 2 task management */ 926 /* codes */ 927 #define ABORT_TASK_SET 0x02 /* Bit 1 */ 928 #define CLEAR_TASK_SET 0x04 /* bit 2 */ 929 #define LUN_RESET 0x10 /* bit 4 */ 930 #define TARGET_RESET 0x20 /* bit 5 */ 931 #define CLEAR_ACA 0x40 /* bit 6 */ 932 #define TERMINATE_TASK 0x80 /* bit 7 */ 933 934 uint8_t fcpCntl3; 935 #define WRITE_DATA 0x01 /* Bit 0 */ 936 #define READ_DATA 0x02 /* Bit 1 */ 937 938 uint8_t fcpCdb[16]; /* SRB cdb field is copied here */ 939 uint32_t fcpDl; /* Total transfer length */ 940 } emlxs_fcp_cmd_t; 941 typedef emlxs_fcp_cmd_t FCP_CMND; 942 943 944 945 946 /* SCSI INQUIRY Command Structure */ 947 948 typedef struct emlxs_inquiryDataType 949 { 950 uint8_t DeviceType:5; 951 uint8_t DeviceTypeQualifier:3; 952 953 uint8_t DeviceTypeModifier:7; 954 uint8_t RemovableMedia:1; 955 956 uint8_t Versions; 957 uint8_t ResponseDataFormat; 958 uint8_t AdditionalLength; 959 uint8_t Reserved[2]; 960 961 uint8_t SoftReset:1; 962 uint8_t CommandQueue:1; 963 uint8_t Reserved2:1; 964 uint8_t LinkedCommands:1; 965 uint8_t Synchronous:1; 966 uint8_t Wide16Bit:1; 967 uint8_t Wide32Bit:1; 968 uint8_t RelativeAddressing:1; 969 970 uint8_t VendorId[8]; 971 uint8_t ProductId[16]; 972 uint8_t ProductRevisionLevel[4]; 973 uint8_t VendorSpecific[20]; 974 uint8_t Reserved3[40]; 975 } emlxs_inquiry_data_type_t; 976 typedef emlxs_inquiry_data_type_t INQUIRY_DATA_DEF; 977 978 979 typedef struct emlxs_read_capacity_data 980 { 981 uint32_t LogicalBlockAddress; 982 uint32_t BytesPerBlock; 983 } emlxs_read_capacity_data_t; 984 typedef emlxs_read_capacity_data_t READ_CAPACITY_DATA_DEF; 985 986 987 /* SCSI CDB command codes */ 988 #define FCP_SCSI_FORMAT_UNIT 0x04 989 #define FCP_SCSI_INQUIRY 0x12 990 #define FCP_SCSI_MODE_SELECT 0x15 991 #define FCP_SCSI_MODE_SENSE 0x1A 992 #define FCP_SCSI_PAUSE_RESUME 0x4B 993 #define FCP_SCSI_PLAY_AUDIO 0x45 994 #define FCP_SCSI_PLAY_AUDIO_EXT 0xA5 995 #define FCP_SCSI_PLAY_AUDIO_MSF 0x47 996 #define FCP_SCSI_PLAY_AUDIO_TRK_INDX 0x48 997 #define FCP_SCSI_PREVENT_ALLOW_REMOVAL 0x1E 998 #define FCP_SCSI_READ_CMD 0x08 999 #define FCP_SCSI_READ_BUFFER 0x3C 1000 #define FCP_SCSI_READ_CAPACITY 0x25 1001 #define FCP_SCSI_READ_DEFECT_LIST 0x37 1002 #define FCP_SCSI_READ_EXTENDED 0x28 1003 #define FCP_SCSI_READ_HEADER 0x44 1004 #define FCP_SCSI_READ_LONG 0xE8 1005 #define FCP_SCSI_READ_SUB_CHANNEL 0x42 1006 #define FCP_SCSI_READ_TOC 0x43 1007 #define FCP_SCSI_REASSIGN_BLOCK 0x07 1008 #define FCP_SCSI_RECEIVE_DIAGNOSTIC_RESULTS 0x1C 1009 #define FCP_SCSI_RELEASE_UNIT 0x17 1010 #define FCP_SCSI_REPORT_LUNS 0xa0 1011 #define FCP_SCSI_REQUEST_SENSE 0x03 1012 #define FCP_SCSI_RESERVE_UNIT 0x16 1013 #define FCP_SCSI_REZERO_UNIT 0x01 1014 #define FCP_SCSI_SEEK 0x0B 1015 #define FCP_SCSI_SEEK_EXTENDED 0x2B 1016 #define FCP_SCSI_SEND_DIAGNOSTIC 0x1D 1017 #define FCP_SCSI_START_STOP_UNIT 0x1B 1018 #define FCP_SCSI_TEST_UNIT_READY 0x00 1019 #define FCP_SCSI_VERIFY 0x2F 1020 #define FCP_SCSI_WRITE_CMD 0x0A 1021 #define FCP_SCSI_WRITE_AND_VERIFY 0x2E 1022 #define FCP_SCSI_WRITE_BUFFER 0x3B 1023 #define FCP_SCSI_WRITE_EXTENDED 0x2A 1024 #define FCP_SCSI_WRITE_LONG 0xEA 1025 #define FCP_SCSI_RELEASE_LUNR 0xBB 1026 #define FCP_SCSI_RELEASE_LUNV 0xBF 1027 1028 #define HPVA_SETPASSTHROUGHMODE 0x27 1029 #define HPVA_EXECUTEPASSTHROUGH 0x29 1030 #define HPVA_CREATELUN 0xE2 1031 #define HPVA_SETLUNSECURITYLIST 0xED 1032 #define HPVA_SETCLOCK 0xF9 1033 #define HPVA_RECOVER 0xFA 1034 #define HPVA_GENERICSERVICEOUT 0xFD 1035 1036 #define DMEP_EXPORT_IN 0x85 1037 #define DMEP_EXPORT_OUT 0x89 1038 1039 #define MDACIOCTL_DIRECT_CMD 0x22 1040 #define MDACIOCTL_STOREIMAGE 0x2C 1041 #define MDACIOCTL_WRITESIGNATURE 0xA6 1042 #define MDACIOCTL_SETREALTIMECLOCK 0xAC 1043 #define MDACIOCTL_PASS_THRU_CDB 0xAD 1044 #define MDACIOCTL_PASS_THRU_INITIATE 0xAE 1045 #define MDACIOCTL_CREATENEWCONF 0xC0 1046 #define MDACIOCTL_ADDNEWCONF 0xC4 1047 #define MDACIOCTL_MORE 0xC6 1048 #define MDACIOCTL_SETPHYSDEVPARAMETER 0xC8 1049 #define MDACIOCTL_SETLOGDEVPARAMETER 0xCF 1050 #define MDACIOCTL_SETCONTROLLERPARAMETER 0xD1 1051 #define MDACIOCTL_WRITESANMAP 0xD4 1052 #define MDACIOCTL_SETMACADDRESS 0xD5 1053 1054 /* 1055 * End of FCP specific structures 1056 */ 1057 1058 #define FL_ALPA 0x00 /* AL_PA of FL_Port */ 1059 1060 /* Fibre Channel Service Parameter definitions */ 1061 1062 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 1063 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 1064 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 1065 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 1066 1067 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 1068 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 1069 #define FC_PH3 0x20 /* FC-PH-3 version */ 1070 1071 #define FF_FRAME_SIZE 2048 1072 1073 1074 typedef struct emlxs_rings 1075 { 1076 #ifdef EMLXS_BIG_ENDIAN 1077 uint32_t crReserved:16; 1078 uint32_t crBegin:8; 1079 uint32_t crEnd:8; /* Low order bit first word */ 1080 uint32_t rrReserved:16; 1081 uint32_t rrBegin:8; 1082 uint32_t rrEnd:8; /* Low order bit second word */ 1083 #endif 1084 #ifdef EMLXS_LITTLE_ENDIAN 1085 uint32_t crEnd:8; /* Low order bit first word */ 1086 uint32_t crBegin:8; 1087 uint32_t crReserved:16; 1088 uint32_t rrEnd:8; /* Low order bit second word */ 1089 uint32_t rrBegin:8; 1090 uint32_t rrReserved:16; 1091 #endif 1092 } emlxs_rings_t; 1093 typedef emlxs_rings_t RINGS; 1094 1095 1096 typedef struct emlxs_ring_def 1097 { 1098 #ifdef EMLXS_BIG_ENDIAN 1099 uint16_t offCiocb; 1100 uint16_t numCiocb; 1101 uint16_t offRiocb; 1102 uint16_t numRiocb; 1103 #endif 1104 #ifdef EMLXS_LITTLE_ENDIAN 1105 uint16_t numCiocb; 1106 uint16_t offCiocb; 1107 uint16_t numRiocb; 1108 uint16_t offRiocb; 1109 #endif 1110 } emlxs_ring_def_t; 1111 typedef emlxs_ring_def_t RING_DEF; 1112 1113 /* 1114 * The following F.C. frame stuctures are defined in Big Endian format. 1115 */ 1116 1117 typedef struct emlxs_name_type 1118 { 1119 #ifdef EMLXS_BIG_ENDIAN 1120 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 1121 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 */ 1122 /* of IEEE ext */ 1123 #endif 1124 #ifdef EMLXS_LITTLE_ENDIAN 1125 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 */ 1126 /* of IEEE ext */ 1127 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 1128 #endif 1129 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 1130 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 1131 #define NAME_FC_TYPE 0x3 /* FC native name type */ 1132 #define NAME_IP_TYPE 0x4 /* IP address */ 1133 #define NAME_CCITT_TYPE 0xC 1134 #define NAME_CCITT_GR_TYPE 0xE 1135 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, */ 1136 /* IEEE extended Lsb */ 1137 uint8_t IEEE[6]; /* FC IEEE address */ 1138 } emlxs_name_type_t; 1139 typedef emlxs_name_type_t NAME_TYPE; 1140 1141 1142 /* 1143 * Word 1 Bit 31 in common service parameter is overloaded. 1144 * Word 1 Bit 31 in FLOGI/FDISC request is multiple NPort request 1145 * Word 1 Bit 31 in FLOGI/FDISC response is clean address bit 1146 */ 1147 #define CLEAN_ADDRESS_BIT reqMultipleNPort /* Word 1, bit 31 */ 1148 1149 typedef struct emlxs_csp 1150 { 1151 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 1152 uint8_t fcphLow; 1153 uint8_t bbCreditMsb; 1154 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 1155 #ifdef EMLXS_BIG_ENDIAN 1156 uint16_t reqMultipleNPort:1; /* FC Word 1, bit 31 */ 1157 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 1158 uint16_t rspMultipleNPort:1; /* FC Word 1, bit 29 */ 1159 uint16_t fPort:1; /* FC Word 1, bit 28 */ 1160 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 1161 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 1162 uint16_t multicast:1; /* FC Word 1, bit 25 */ 1163 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 1164 1165 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 1166 uint16_t simplex:1; /* FC Word 1, bit 22 */ 1167 1168 uint16_t fcsp_support:1; /* FC Word 1, bit 21 */ 1169 uint16_t word1Reserved20:1; /* FC Word 1, bit 20 */ 1170 uint16_t word1Reserved19:1; /* FC Word 1, bit 19 */ 1171 1172 uint16_t dhd:1; /* FC Word 1, bit 18 */ 1173 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 1174 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 1175 #endif 1176 #ifdef EMLXS_LITTLE_ENDIAN 1177 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 1178 uint16_t multicast:1; /* FC Word 1, bit 25 */ 1179 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 1180 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 1181 uint16_t fPort:1; /* FC Word 1, bit 28 */ 1182 uint16_t rspMultipleNPort:1; /* FC Word 1, bit 29 */ 1183 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 1184 uint16_t reqMultipleNPort:1; /* FC Word 1, bit 31 */ 1185 1186 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 1187 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 1188 uint16_t dhd:1; /* FC Word 1, bit 18 */ 1189 1190 uint16_t word1Reserved19:1; /* FC Word 1, bit 19 */ 1191 uint16_t word1Reserved20:1; /* FC Word 1, bit 20 */ 1192 uint16_t fcsp_support:1; /* FC Word 1, bit 21 */ 1193 1194 uint16_t simplex:1; /* FC Word 1, bit 22 */ 1195 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 1196 #endif 1197 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 1198 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 1199 union 1200 { 1201 struct 1202 { 1203 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 1204 1205 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 1206 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 1207 1208 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 1209 } nPort; 1210 uint32_t r_a_tov; /* R_A_TOV must be in Big */ 1211 /* Endian format */ 1212 } w2; 1213 1214 uint32_t e_d_tov; /* E_D_TOV must be in Big */ 1215 /* Endian format */ 1216 } emlxs_csp_t; 1217 typedef emlxs_csp_t CSP; 1218 1219 1220 typedef struct emlxs_class_parms 1221 { 1222 #ifdef EMLXS_BIG_ENDIAN 1223 uint8_t classValid:1; /* FC Word 0, bit 31 */ 1224 uint8_t intermix:1; /* FC Word 0, bit 30 */ 1225 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 1226 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 1227 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 1228 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 1229 #endif 1230 #ifdef EMLXS_LITTLE_ENDIAN 1231 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 1232 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 1233 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 1234 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 1235 uint8_t intermix:1; /* FC Word 0, bit 30 */ 1236 uint8_t classValid:1; /* FC Word 0, bit 31 */ 1237 1238 #endif 1239 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 1240 #ifdef EMLXS_BIG_ENDIAN 1241 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 1242 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 1243 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 1244 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 1245 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 1246 #endif 1247 #ifdef EMLXS_LITTLE_ENDIAN 1248 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 1249 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 1250 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 1251 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 1252 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 1253 #endif 1254 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 1255 #ifdef EMLXS_BIG_ENDIAN 1256 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 1257 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 1258 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 1259 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 1260 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 1261 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 1262 #endif 1263 #ifdef EMLXS_LITTLE_ENDIAN 1264 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 1265 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 1266 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 1267 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 1268 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 1269 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 1270 #endif 1271 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 1272 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 1273 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 1274 1275 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 1276 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 1277 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 1278 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 1279 1280 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 1281 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 1282 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 1283 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 1284 } emlxs_class_parms_t; 1285 typedef emlxs_class_parms_t CLASS_PARMS; 1286 1287 1288 typedef struct emlxs_serv_parms 1289 { /* Structure is in Big Endian format */ 1290 CSP cmn; 1291 NAME_TYPE portName; 1292 NAME_TYPE nodeName; 1293 CLASS_PARMS cls1; 1294 CLASS_PARMS cls2; 1295 CLASS_PARMS cls3; 1296 CLASS_PARMS cls4; 1297 uint8_t vendorVersion[16]; 1298 } emlxs_serv_parms_t; 1299 typedef emlxs_serv_parms_t SERV_PARM; 1300 1301 typedef struct 1302 { 1303 union 1304 { 1305 uint32_t word0; 1306 struct 1307 { 1308 #ifdef EMLXS_BIG_ENDIAN 1309 uint32_t rsvd0:8; /* Word 0, Byte 3 */ 1310 uint32_t oui:24; /* Elx Organization */ 1311 /* Unique ID (0000C9) */ 1312 #endif 1313 #ifdef EMLXS_LITTLE_ENDIAN 1314 uint32_t oui:24; /* Elx Organization */ 1315 /* Unique ID (0000C9) */ 1316 uint32_t rsvd0:8; /* Word 0, Byte 3 */ 1317 #endif 1318 } w0; 1319 } un0; 1320 union 1321 { 1322 uint32_t word1; 1323 struct 1324 { 1325 #ifdef EMLXS_BIG_ENDIAN 1326 uint32_t vport:1; /* Word 1, Bit 31 */ 1327 uint32_t rsvd1:31; /* Word 1, Bit 0-30 */ 1328 #endif 1329 #ifdef EMLXS_LITTLE_ENDIAN 1330 uint32_t rsvd1:31; /* Word 1, Bit 0-30 */ 1331 uint32_t vport:1; /* Word 1, Bit 31 */ 1332 #endif 1333 } w1; 1334 } un1; 1335 uint8_t rsvd2[8]; 1336 } emlxs_vvl_fmt_t; 1337 1338 #define VALID_VENDOR_VERSION cmn.rspMultipleNPort 1339 1340 1341 1342 /* 1343 * Extended Link Service LS_COMMAND codes (Payload BYTE 0) 1344 */ 1345 #ifdef EMLXS_BIG_ENDIAN 1346 #define ELS_CMD_SHIFT 24 1347 #define ELS_CMD_MASK 0xff000000 1348 #define ELS_RSP_MASK 0xff000000 1349 #define ELS_CMD_LS_RJT 0x01000000 1350 #define ELS_CMD_ACC 0x02000000 1351 #define ELS_CMD_PLOGI 0x03000000 1352 #define ELS_CMD_FLOGI 0x04000000 1353 #define ELS_CMD_LOGO 0x05000000 1354 #define ELS_CMD_ABTX 0x06000000 1355 #define ELS_CMD_RCS 0x07000000 1356 #define ELS_CMD_RES 0x08000000 1357 #define ELS_CMD_RSS 0x09000000 1358 #define ELS_CMD_RSI 0x0A000000 1359 #define ELS_CMD_ESTS 0x0B000000 1360 #define ELS_CMD_ESTC 0x0C000000 1361 #define ELS_CMD_ADVC 0x0D000000 1362 #define ELS_CMD_RTV 0x0E000000 1363 #define ELS_CMD_RLS 0x0F000000 1364 #define ELS_CMD_ECHO 0x10000000 1365 #define ELS_CMD_TEST 0x11000000 1366 #define ELS_CMD_RRQ 0x12000000 1367 #define ELS_CMD_REC 0x13000000 1368 #define ELS_CMD_PRLI 0x20000000 1369 #define ELS_CMD_PRLO 0x21000000 1370 #define ELS_CMD_SCN 0x22000000 1371 #define ELS_CMD_TPLS 0x23000000 1372 #define ELS_CMD_GPRLO 0x24000000 1373 #define ELS_CMD_GAID 0x30000000 1374 #define ELS_CMD_FACT 0x31000000 1375 #define ELS_CMD_FDACT 0x32000000 1376 #define ELS_CMD_NACT 0x33000000 1377 #define ELS_CMD_NDACT 0x34000000 1378 #define ELS_CMD_QoSR 0x40000000 1379 #define ELS_CMD_RVCS 0x41000000 1380 #define ELS_CMD_PDISC 0x50000000 1381 #define ELS_CMD_FDISC 0x51000000 1382 #define ELS_CMD_ADISC 0x52000000 1383 #define ELS_CMD_FARP 0x54000000 1384 #define ELS_CMD_FARPR 0x55000000 1385 #define ELS_CMD_FAN 0x60000000 1386 #define ELS_CMD_RSCN 0x61000000 1387 #define ELS_CMD_SCR 0x62000000 1388 #define ELS_CMD_LINIT 0x70000000 1389 #define ELS_CMD_RNID 0x78000000 1390 #define ELS_CMD_AUTH 0x90000000 1391 #endif 1392 1393 #ifdef EMLXS_LITTLE_ENDIAN 1394 #define ELS_CMD_SHIFT 0 1395 #define ELS_CMD_MASK 0xff 1396 #define ELS_RSP_MASK 0xff 1397 #define ELS_CMD_LS_RJT 0x01 1398 #define ELS_CMD_ACC 0x02 1399 #define ELS_CMD_PLOGI 0x03 1400 #define ELS_CMD_FLOGI 0x04 1401 #define ELS_CMD_LOGO 0x05 1402 #define ELS_CMD_ABTX 0x06 1403 #define ELS_CMD_RCS 0x07 1404 #define ELS_CMD_RES 0x08 1405 #define ELS_CMD_RSS 0x09 1406 #define ELS_CMD_RSI 0x0A 1407 #define ELS_CMD_ESTS 0x0B 1408 #define ELS_CMD_ESTC 0x0C 1409 #define ELS_CMD_ADVC 0x0D 1410 #define ELS_CMD_RTV 0x0E 1411 #define ELS_CMD_RLS 0x0F 1412 #define ELS_CMD_ECHO 0x10 1413 #define ELS_CMD_TEST 0x11 1414 #define ELS_CMD_RRQ 0x12 1415 #define ELS_CMD_REC 0x13 1416 #define ELS_CMD_PRLI 0x20 1417 #define ELS_CMD_PRLO 0x21 1418 #define ELS_CMD_SCN 0x22 1419 #define ELS_CMD_TPLS 0x23 1420 #define ELS_CMD_GPRLO 0x24 1421 #define ELS_CMD_GAID 0x30 1422 #define ELS_CMD_FACT 0x31 1423 #define ELS_CMD_FDACT 0x32 1424 #define ELS_CMD_NACT 0x33 1425 #define ELS_CMD_NDACT 0x34 1426 #define ELS_CMD_QoSR 0x40 1427 #define ELS_CMD_RVCS 0x41 1428 #define ELS_CMD_PDISC 0x50 1429 #define ELS_CMD_FDISC 0x51 1430 #define ELS_CMD_ADISC 0x52 1431 #define ELS_CMD_FARP 0x54 1432 #define ELS_CMD_FARPR 0x55 1433 #define ELS_CMD_FAN 0x60 1434 #define ELS_CMD_RSCN 0x61 1435 #define ELS_CMD_SCR 0x62 1436 #define ELS_CMD_LINIT 0x70 1437 #define ELS_CMD_RNID 0x78 1438 #define ELS_CMD_AUTH 0x90 1439 #endif 1440 1441 1442 /* 1443 * LS_RJT Payload Definition 1444 */ 1445 1446 typedef struct _LS_RJT 1447 { /* Structure is in Big Endian format */ 1448 union 1449 { 1450 uint32_t lsRjtError; 1451 struct 1452 { 1453 uint8_t lsRjtRsvd0; /* FC Word 0, */ 1454 /* bit 24:31 */ 1455 1456 uint8_t lsRjtRsnCode; /* FC Word 0, */ 1457 /* bit 16:23 */ 1458 /* LS_RJT reason codes */ 1459 #define LSRJT_INVALID_CMD 0x01 1460 #define LSRJT_LOGICAL_ERR 0x03 1461 #define LSRJT_LOGICAL_BSY 0x05 1462 #define LSRJT_PROTOCOL_ERR 0x07 1463 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 1464 #define LSRJT_CMD_UNSUPPORTED 0x0B 1465 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 1466 1467 uint8_t lsRjtRsnCodeExp; /* FC Word 0, */ 1468 /* bit 8:15 */ 1469 /* LS_RJT reason explanation */ 1470 #define LSEXP_NOTHING_MORE 0x00 1471 #define LSEXP_SPARM_OPTIONS 0x01 1472 #define LSEXP_SPARM_ICTL 0x03 1473 #define LSEXP_SPARM_RCTL 0x05 1474 #define LSEXP_SPARM_RCV_SIZE 0x07 1475 #define LSEXP_SPARM_CONCUR_SEQ 0x09 1476 #define LSEXP_SPARM_CREDIT 0x0B 1477 #define LSEXP_INVALID_PNAME 0x0D 1478 #define LSEXP_INVALID_NNAME 0x0E 1479 #define LSEXP_INVALID_CSP 0x0F 1480 #define LSEXP_INVALID_ASSOC_HDR 0x11 1481 #define LSEXP_ASSOC_HDR_REQ 0x13 1482 #define LSEXP_INVALID_O_SID 0x15 1483 #define LSEXP_INVALID_OX_RX 0x17 1484 #define LSEXP_CMD_IN_PROGRESS 0x19 1485 #define LSEXP_INVALID_NPORT_ID 0x1F 1486 #define LSEXP_INVALID_SEQ_ID 0x21 1487 #define LSEXP_INVALID_XCHG 0x23 1488 #define LSEXP_INACTIVE_XCHG 0x25 1489 #define LSEXP_RQ_REQUIRED 0x27 1490 #define LSEXP_OUT_OF_RESOURCE 0x29 1491 #define LSEXP_CANT_GIVE_DATA 0x2A 1492 #define LSEXP_REQ_UNSUPPORTED 0x2C 1493 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 1494 } b; 1495 } un; 1496 } LS_RJT; 1497 1498 1499 /* 1500 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 1501 */ 1502 1503 typedef struct _LOGO 1504 { /* Structure is in Big Endian format */ 1505 union 1506 { 1507 uint32_t nPortId32; /* Access nPortId as a word */ 1508 struct 1509 { 1510 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 1511 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 1512 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 1513 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 1514 } b; 1515 } un; 1516 NAME_TYPE portName; /* N_port name field */ 1517 } LOGO; 1518 1519 1520 /* 1521 * FCP Login (PRLI Request / ACC) Payload Definition 1522 */ 1523 1524 #define PRLX_PAGE_LEN 0x10 1525 #define TPRLO_PAGE_LEN 0x14 1526 1527 typedef struct _PRLI 1528 { /* Structure is in Big Endian format */ 1529 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 1530 1531 #define PRLI_FCP_TYPE 0x08 1532 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 1533 1534 #ifdef EMLXS_BIG_ENDIAN 1535 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1536 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1537 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 1538 1539 /* ACC = imagePairEstablished */ 1540 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 1541 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1542 /* ACC ONLY */ 1543 #endif 1544 #ifdef EMLXS_LITTLE_ENDIAN 1545 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1546 /* ACC ONLY */ 1547 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 1548 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 1549 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1550 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1551 /* ACC = imagePairEstablished */ 1552 #endif 1553 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 1554 #define PRLI_NO_RESOURCES 0x2 1555 #define PRLI_INIT_INCOMPLETE 0x3 1556 #define PRLI_NO_SUCH_PA 0x4 1557 #define PRLI_PREDEF_CONFIG 0x5 1558 #define PRLI_PARTIAL_SUCCESS 0x6 1559 #define PRLI_INVALID_PAGE_CNT 0x7 1560 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 1561 1562 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 1563 1564 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 1565 1566 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 1567 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 1568 #ifdef EMLXS_BIG_ENDIAN 1569 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 1570 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 1571 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 1572 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 1573 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 1574 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 1575 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 1576 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 1577 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 1578 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 1579 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 1580 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 1581 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 1582 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 1583 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 1584 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 1585 #endif 1586 #ifdef EMLXS_LITTLE_ENDIAN 1587 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 1588 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 1589 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 1590 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 1591 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 1592 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 1593 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 1594 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 1595 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 1596 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 1597 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 1598 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 1599 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 1600 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 1601 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 1602 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 1603 #endif 1604 } PRLI; 1605 1606 /* 1607 * FCP Logout (PRLO Request / ACC) Payload Definition 1608 */ 1609 1610 typedef struct _PRLO 1611 { /* Structure is in Big Endian format */ 1612 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 1613 1614 #define PRLO_FCP_TYPE 0x08 1615 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 1616 1617 #ifdef EMLXS_BIG_ENDIAN 1618 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1619 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1620 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 1621 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1622 /* ACC ONLY */ 1623 #endif 1624 #ifdef EMLXS_LITTLE_ENDIAN 1625 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1626 /* ACC ONLY */ 1627 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 1628 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1629 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1630 #endif 1631 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 1632 #define PRLO_NO_SUCH_IMAGE 0x4 1633 #define PRLO_INVALID_PAGE_CNT 0x7 1634 1635 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 1636 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 1637 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 1638 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 1639 } PRLO; 1640 1641 1642 typedef struct _ADISC 1643 { /* Structure is in Big Endian format */ 1644 uint32_t hardAL_PA; 1645 NAME_TYPE portName; 1646 NAME_TYPE nodeName; 1647 uint32_t DID; 1648 } ADISC; 1649 1650 1651 typedef struct _FARP 1652 { /* Structure is in Big Endian format */ 1653 uint32_t Mflags:8; 1654 uint32_t Odid:24; 1655 #define FARP_NO_ACTION 0 /* FARP information enclosed, no action */ 1656 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 1657 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 1658 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 1659 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not supported */ 1660 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not supported */ 1661 uint32_t Rflags:8; 1662 uint32_t Rdid:24; 1663 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 1664 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 1665 NAME_TYPE OportName; 1666 NAME_TYPE OnodeName; 1667 NAME_TYPE RportName; 1668 NAME_TYPE RnodeName; 1669 uint8_t Oipaddr[16]; 1670 uint8_t Ripaddr[16]; 1671 } FARP; 1672 1673 typedef struct _FAN 1674 { /* Structure is in Big Endian format */ 1675 uint32_t Fdid; 1676 NAME_TYPE FportName; 1677 NAME_TYPE FnodeName; 1678 } FAN; 1679 1680 typedef struct _SCR 1681 { /* Structure is in Big Endian format */ 1682 uint8_t resvd1; 1683 uint8_t resvd2; 1684 uint8_t resvd3; 1685 uint8_t Function; 1686 #define SCR_FUNC_FABRIC 0x01 1687 #define SCR_FUNC_NPORT 0x02 1688 #define SCR_FUNC_FULL 0x03 1689 #define SCR_CLEAR 0xff 1690 } SCR; 1691 1692 typedef struct _RNID_TOP_DISC 1693 { 1694 NAME_TYPE portName; 1695 uint8_t resvd[8]; 1696 uint32_t unitType; 1697 #define RNID_HBA 0x7 1698 #define RNID_HOST 0xa 1699 #define RNID_DRIVER 0xd 1700 uint32_t physPort; 1701 uint32_t attachedNodes; 1702 uint16_t ipVersion; 1703 #define RNID_IPV4 0x1 1704 #define RNID_IPV6 0x2 1705 uint16_t UDPport; 1706 uint8_t ipAddr[16]; 1707 uint16_t resvd1; 1708 uint16_t flags; 1709 #define RNID_TD_SUPPORT 0x1 1710 #define RNID_LP_VALID 0x2 1711 } RNID_TOP_DISC; 1712 1713 typedef struct _RNID 1714 { /* Structure is in Big Endian format */ 1715 uint8_t Format; 1716 #define RNID_TOPOLOGY_DISC 0xdf 1717 uint8_t CommonLen; 1718 uint8_t resvd1; 1719 uint8_t SpecificLen; 1720 NAME_TYPE portName; 1721 NAME_TYPE nodeName; 1722 union 1723 { 1724 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 1725 } un; 1726 } RNID; 1727 1728 typedef struct _RRQ 1729 { /* Structure is in Big Endian format */ 1730 uint32_t SID; 1731 uint16_t Oxid; 1732 uint16_t Rxid; 1733 uint8_t resv[32]; /* optional association hdr */ 1734 } RRQ; 1735 1736 1737 /* This is used for RSCN command */ 1738 typedef struct _D_ID 1739 { /* Structure is in Big Endian format */ 1740 union 1741 { 1742 uint32_t word; 1743 struct 1744 { 1745 #ifdef EMLXS_BIG_ENDIAN 1746 uint8_t resv; 1747 uint8_t domain; 1748 uint8_t area; 1749 uint8_t id; 1750 #endif 1751 #ifdef EMLXS_LITTLE_ENDIAN 1752 uint8_t id; 1753 uint8_t area; 1754 uint8_t domain; 1755 uint8_t resv; 1756 #endif 1757 } b; 1758 } un; 1759 } D_ID; 1760 1761 /* 1762 * Structure to define all ELS Payload types 1763 */ 1764 1765 typedef struct _ELS_PKT 1766 { /* Structure is in Big Endian format */ 1767 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 1768 uint8_t elsByte1; 1769 uint8_t elsByte2; 1770 uint8_t elsByte3; 1771 union 1772 { 1773 LS_RJT lsRjt; /* Payload for LS_RJT */ 1774 SERV_PARM logi; /* Payload for PLOGI, FLOGI */ 1775 /* PDISC, ACC */ 1776 LOGO logo; /* Payload for PLOGO, FLOGO */ 1777 /* ACC */ 1778 PRLI prli; /* Payload for PRLI/ACC */ 1779 PRLO prlo; /* Payload for PRLO/ACC */ 1780 ADISC adisc; /* Payload for ADISC/ACC */ 1781 FARP farp; /* Payload for FARP/ACC */ 1782 FAN fan; /* Payload for FAN */ 1783 SCR scr; /* Payload for SCR/ACC */ 1784 RRQ rrq; /* Payload for RRQ */ 1785 RNID rnid; /* Payload for RNID */ 1786 uint8_t pad[128 - 4]; /* Pad out to payload of */ 1787 /* 128 bytes */ 1788 } un; 1789 } ELS_PKT; 1790 1791 1792 typedef struct 1793 { 1794 uint32_t bdeAddress; 1795 #ifdef EMLXS_BIG_ENDIAN 1796 uint32_t bdeReserved:4; 1797 uint32_t bdeAddrHigh:4; 1798 uint32_t bdeSize:24; 1799 #endif 1800 #ifdef EMLXS_LITTLE_ENDIAN 1801 uint32_t bdeSize:24; 1802 uint32_t bdeAddrHigh:4; 1803 uint32_t bdeReserved:4; 1804 #endif 1805 } ULP_BDE; 1806 1807 typedef struct ULP_BDE_64 1808 { /* SLI-2 */ 1809 union ULP_BDE_TUS 1810 { 1811 uint32_t w; 1812 struct 1813 { 1814 #ifdef EMLXS_BIG_ENDIAN 1815 uint32_t bdeFlags:8; /* BDE Flags 0 IS A */ 1816 /* SUPPORTED VALUE !! */ 1817 uint32_t bdeSize:24; /* buff size in bytes */ 1818 #endif 1819 #ifdef EMLXS_LITTLE_ENDIAN 1820 uint32_t bdeSize:24; /* buff size in bytes */ 1821 uint32_t bdeFlags:8; /* BDE Flags 0 IS A */ 1822 /* SUPPORTED VALUE !! */ 1823 #endif 1824 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 1825 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 1826 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 1827 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, */ 1828 /* 0=xmit buffer */ 1829 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr */ 1830 /* 0=64 bit addr */ 1831 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 1832 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 1833 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 1834 } f; 1835 } tus; 1836 uint32_t addrLow; 1837 uint32_t addrHigh; 1838 } ULP_BDE64; 1839 1840 #define BDE64_SIZE_WORD 0 1841 #define BPL64_SIZE_WORD 0x40 1842 1843 /* ULP */ 1844 typedef struct ULP_BPL_64 1845 { 1846 ULP_BDE64 fccmd_payload; 1847 ULP_BDE64 fcrsp_payload; 1848 ULP_BDE64 fcdat_payload; 1849 ULP_BDE64 pat0; 1850 } ULP_BPL64; 1851 1852 typedef struct ULP_BDL 1853 { /* SLI-2 */ 1854 #ifdef EMLXS_BIG_ENDIAN 1855 uint32_t bdeFlags:8; /* BDL Flags */ 1856 uint32_t bdeSize:24; /* Size of BDL array in host */ 1857 /* memory (bytes) */ 1858 #endif 1859 #ifdef EMLXS_LITTLE_ENDIAN 1860 uint32_t bdeSize:24; /* Size of BDL array in host */ 1861 /* memory (bytes) */ 1862 uint32_t bdeFlags:8; /* BDL Flags */ 1863 #endif 1864 uint32_t addrLow; /* Address 0:31 */ 1865 uint32_t addrHigh; /* Address 32:63 */ 1866 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1867 } ULP_BDL; 1868 1869 typedef struct ULP_SGE_64 1870 { /* SLI-4 */ 1871 uint32_t addrHigh; /* Address 32:63 */ 1872 uint32_t addrLow; /* Address 0:31 */ 1873 #ifdef EMLXS_BIG_ENDIAN 1874 uint32_t last:1; /* Last entry in SGL */ 1875 uint32_t type:4; 1876 uint32_t offset:27; 1877 #endif 1878 #ifdef EMLXS_LITTLE_ENDIAN 1879 uint32_t offset:27; 1880 uint32_t type:4; 1881 uint32_t last:1; /* Last entry in SGL */ 1882 #endif 1883 #define EMLXS_SGE_TYPE_DATA 0x0 1884 #define EMLXS_SGE_TYPE_DIF 0x4 1885 #define EMLXS_SGE_TYPE_LSP 0x5 1886 #define EMLXS_SGE_TYPE_ENC_DIF 0x6 1887 #define EMLXS_SGE_TYPE_ENC_SEED 0x7 1888 #define EMLXS_SGE_TYPE_SEED 0x8 1889 #define EMLXS_SGE_TYPE_ENC 0x9 1890 #define EMLXS_SGE_TYPE_SKIP 0xC 1891 1892 uint32_t length; 1893 #define EMLXS_MAX_SGE_SIZE 0x10000 /* 64K max length */ 1894 } ULP_SGE64; 1895 1896 #define EMLXS_XFER_RDY_SIZE 12 /* Payload size of a FCP Transfer Ready */ 1897 1898 typedef struct _BE_PHYS_ADDR 1899 { 1900 uint32_t addrLow; 1901 uint32_t addrHigh; 1902 } BE_PHYS_ADDR; 1903 1904 1905 typedef struct 1906 { 1907 void *fc_mptr; 1908 struct emlxs_memseg *segment; /* Parent segment */ 1909 1910 void *virt; /* virtual address ptr */ 1911 uint64_t phys; /* mapped address */ 1912 uint32_t size; 1913 1914 void *data_handle; 1915 void *dma_handle; 1916 uint32_t tag; 1917 uint32_t flag; 1918 #define MAP_POOL_ALLOCATED 0x00000001 1919 #define MAP_BUF_ALLOCATED 0x00000002 1920 #define MAP_TABLE_ALLOCATED 0x00000004 1921 1922 #ifdef SFCT_SUPPORT 1923 void *fct_private; 1924 #endif /* SFCT_SUPPORT */ 1925 } MATCHMAP; 1926 1927 1928 /* 1929 * This file defines the Header File for the FDMI HBA Management Service 1930 */ 1931 1932 /* 1933 * FDMI HBA MAnagement Operations Command Codes 1934 */ 1935 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1936 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1937 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1938 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1939 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1940 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 1941 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1942 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1943 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1944 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1945 1946 /* 1947 * Management Service Subtypes 1948 */ 1949 #define SLI_CT_FDMI_SUBTYPES 0x10 1950 1951 1952 /* 1953 * HBA Management Service Reject Code 1954 */ 1955 #define REJECT_CODE 0x9 /* Unable to perform command request */ 1956 1957 /* 1958 * HBA Management Service Reject Reason Code 1959 * Please refer to the Reason Codes above 1960 */ 1961 1962 /* 1963 * HBA Attribute Types 1964 */ 1965 #define NODE_NAME 0x1 1966 #define MANUFACTURER 0x2 1967 #define SERIAL_NUMBER 0x3 1968 #define MODEL 0x4 1969 #define MODEL_DESCRIPTION 0x5 1970 #define HARDWARE_VERSION 0x6 1971 #define DRIVER_VERSION 0x7 1972 #define OPTION_ROM_VERSION 0x8 1973 #define FIRMWARE_VERSION 0x9 1974 #define VENDOR_SPECIFIC 0xa 1975 #define DRV_NAME 0xb 1976 #define OS_NAME_VERSION 0xc 1977 #define MAX_CT_PAYLOAD_LEN 0xd 1978 1979 /* 1980 * Port Attrubute Types 1981 */ 1982 #define SUPPORTED_FC4_TYPES 0x1 1983 #define SUPPORTED_SPEED 0x2 1984 #define PORT_SPEED 0x3 1985 #define MAX_FRAME_SIZE 0x4 1986 #define OS_DEVICE_NAME 0x5 1987 1988 union AttributesDef 1989 { 1990 /* Structure is in Big Endian format */ 1991 struct 1992 { 1993 uint32_t AttrType:16; 1994 uint32_t AttrLen:16; 1995 } bits; 1996 uint32_t word; 1997 }; 1998 1999 /* 2000 * HBA Attribute Entry (8 - 260 bytes) 2001 */ 2002 typedef struct 2003 { 2004 union AttributesDef ad; 2005 union 2006 { 2007 uint32_t VendorSpecific; 2008 uint32_t SupportSpeed; 2009 uint32_t PortSpeed; 2010 uint32_t MaxFrameSize; 2011 uint32_t MaxCTPayloadLen; 2012 uint8_t SupportFC4Types[32]; 2013 uint8_t OsDeviceName[256]; 2014 uint8_t Manufacturer[64]; 2015 uint8_t SerialNumber[64]; 2016 uint8_t Model[256]; 2017 uint8_t ModelDescription[256]; 2018 uint8_t HardwareVersion[256]; 2019 uint8_t DriverVersion[256]; 2020 uint8_t OptionROMVersion[256]; 2021 uint8_t FirmwareVersion[256]; 2022 uint8_t DriverName[256]; 2023 NAME_TYPE NodeName; 2024 } un; 2025 } ATTRIBUTE_ENTRY, *PATTRIBUTE_ENTRY; 2026 2027 2028 /* 2029 * HBA Attribute Block 2030 */ 2031 typedef struct 2032 { 2033 uint32_t EntryCnt; /* Number of HBA attribute entries */ 2034 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 2035 } ATTRIBUTE_BLOCK, *PATTRIBUTE_BLOCK; 2036 2037 2038 /* 2039 * Port Entry 2040 */ 2041 typedef struct 2042 { 2043 NAME_TYPE PortName; 2044 } PORT_ENTRY, *PPORT_ENTRY; 2045 2046 /* 2047 * HBA Identifier 2048 */ 2049 typedef struct 2050 { 2051 NAME_TYPE PortName; 2052 } HBA_IDENTIFIER, *PHBA_IDENTIFIER; 2053 2054 /* 2055 * Registered Port List Format 2056 */ 2057 typedef struct 2058 { 2059 uint32_t EntryCnt; 2060 PORT_ENTRY pe; /* Variable-length array */ 2061 } REG_PORT_LIST, *PREG_PORT_LIST; 2062 2063 /* 2064 * Register HBA(RHBA) 2065 */ 2066 typedef struct 2067 { 2068 HBA_IDENTIFIER hi; 2069 REG_PORT_LIST rpl; /* variable-length array */ 2070 } REG_HBA, *PREG_HBA; 2071 2072 /* 2073 * Register HBA Attributes (RHAT) 2074 */ 2075 typedef struct 2076 { 2077 NAME_TYPE HBA_PortName; 2078 ATTRIBUTE_BLOCK ab; 2079 } REG_HBA_ATTRIBUTE, *PREG_HBA_ATTRIBUTE; 2080 2081 /* 2082 * Register Port Attributes (RPA) 2083 */ 2084 typedef struct 2085 { 2086 NAME_TYPE HBA_PortName; 2087 NAME_TYPE PortName; 2088 ATTRIBUTE_BLOCK ab; 2089 } REG_PORT_ATTRIBUTE, *PREG_PORT_ATTRIBUTE; 2090 2091 /* 2092 * Get Registered HBA List (GRHL) Accept Payload Format 2093 */ 2094 typedef struct 2095 { 2096 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Ids */ 2097 NAME_TYPE HBA_PortName; /* Variable-length array */ 2098 } GRHL_ACC_PAYLOAD, *PGRHL_ACC_PAYLOAD; 2099 2100 /* 2101 * Get Registered Port List (GRPL) Accept Payload Format 2102 */ 2103 typedef struct 2104 { 2105 uint32_t RPL_Entry_Cnt; /* No of Reg Port Entries */ 2106 PORT_ENTRY eg_Port_Entry[1]; /* Variable-length array */ 2107 } GRPL_ACC_PAYLOAD, *PGRPL_ACC_PAYLOAD; 2108 2109 /* 2110 * Get Port Attributes (GPAT) Accept Payload Format 2111 */ 2112 2113 typedef struct 2114 { 2115 ATTRIBUTE_BLOCK pab; 2116 } GPAT_ACC_PAYLOAD, *PGPAT_ACC_PAYLOAD; 2117 2118 /* 2119 * Use for Firmware DownLoad 2120 */ 2121 2122 /* download.h */ 2123 2124 #define REDUCED_SRAM_CFG 0x7FFFC /* 9802DC */ 2125 #define FULL_SRAM_CFG 0x13FFFC /* 9802 */ 2126 2127 #define SLI_FW_TYPE_SHIFT(x) ((x << 20)) 2128 #define SLI_FW_ADAPTER_TYPE_MASK 0x00f00000 2129 #define SLI_FW_TYPE_6000 SLI_FW_TYPE_SHIFT(0) 2130 #define SLI_FW_TYPE_7000 SLI_FW_TYPE_SHIFT(1) 2131 #define SLI_FW_TYPE_8000 SLI_FW_TYPE_SHIFT(2) 2132 #define SLI_FW_TYPE_850 SLI_FW_TYPE_SHIFT(3) 2133 #define SLI_FW_TYPE_9000 SLI_FW_TYPE_SHIFT(4) 2134 #define SLI_FW_TYPE_950 SLI_FW_TYPE_SHIFT(5) 2135 #define SLI_FW_TYPE_9802 SLI_FW_TYPE_SHIFT(6) /* [022702] */ 2136 #define SLI_FW_TYPE_982 SLI_FW_TYPE_SHIFT(7) 2137 #define SLI_FW_TYPE_10000 SLI_FW_TYPE_SHIFT(8) 2138 #define SLI_FW_TYPE_1050 SLI_FW_TYPE_SHIFT(9) 2139 #define SLI_FW_TYPE_X1000 SLI_FW_TYPE_SHIFT(0xa) 2140 #define SLI_FW_TYPE_101 SLI_FW_TYPE_SHIFT(0xb) /* LP101 */ 2141 2142 2143 typedef enum emlxs_prog_type 2144 { 2145 TEST_PROGRAM, /* 0 */ 2146 UTIL_PROGRAM, /* 1 */ 2147 FUNC_FIRMWARE, /* 2 */ 2148 BOOT_BIOS, /* 3 */ 2149 CONFIG_DATA, /* 4 */ 2150 SEQUENCER_CODE, /* 5 */ 2151 SLI1_OVERLAY, /* 6 */ 2152 SLI2_OVERLAY, /* 7 */ 2153 GASKET, /* 8 */ 2154 HARDWARE_IMAGE, /* 9 */ 2155 SBUS_FCODE, /* A */ 2156 SLI3_OVERLAY, /* B */ 2157 RESERVED_C, 2158 RESERVED_D, 2159 SLI4_OVERLAY, /* E */ 2160 KERNEL_CODE, /* F */ 2161 MAX_PROG_TYPES 2162 } emlxs_prog_type_t; 2163 2164 2165 typedef struct emlxs_fw_file 2166 { 2167 uint32_t version; 2168 uint32_t revcomp; 2169 char label[16]; 2170 uint32_t offset; 2171 } emlxs_fw_file_t; 2172 2173 typedef struct emlxs_fw_image 2174 { 2175 emlxs_fw_file_t awc; 2176 emlxs_fw_file_t bwc; 2177 emlxs_fw_file_t dwc; 2178 emlxs_fw_file_t prog[MAX_PROG_TYPES]; 2179 } emlxs_fw_image_t; 2180 2181 2182 2183 #define NOP_IMAGE_TYPE 0xe1a00000 2184 2185 #define FLASH_BASE_ADR 0x01400000 2186 #define DL_FROM_SLIM_OFFSET MBOX_EXTENSION_OFFSET 2187 2188 #ifdef MBOX_EXT_SUPPORT 2189 #define DL_SLIM_SEG_BYTE_COUNT MBOX_EXTENSION_SIZE 2190 #else 2191 #define DL_SLIM_SEG_BYTE_COUNT 128 2192 #endif /* MBOX_EXT_SUPPORT */ 2193 2194 #define SLI_CKSUM_LENGTH 4 2195 #define SLI_CKSUM_SEED 0x55555555 2196 #define SLI_CKSUM_ERR 0x1982abcd 2197 2198 #define AIF_NOOP 0xe1a00000 2199 #define AIF_BLAL 0xeb000000 2200 #define OS_EXIT 0xef000011 2201 #define OS_GETENV 0xef000010 2202 #define AIF_IMAGEBASE 0x00008000 2203 #define AIF_BLZINIT 0xeb00000c 2204 #define DEBUG_TASK 0xef041d41 2205 #define AIF_DBG_SRC 2 2206 #define AIF_DBG_LL 1 2207 #define AIF_DATABASAT 0x100 2208 2209 #define JEDEC_ID_ADDRESS 0x0080001c 2210 #define MAX_RBUS_SRAM_SIZE_ADR 0x788 2211 #define MAX_IBUS_SRAM_SIZE_ADR 0x78c 2212 #define FULL_RBUS_SRAM_CFG 0x7fffc 2213 #define FULL_IBUS_SRAM_CFG 0x187fffc 2214 #define REDUCED_RBUS_SRAM_CFG 0x5fffc 2215 #define REDUCED_IBUS_SRAM_CFG 0x183fffc 2216 2217 #define FULL_SRAM_CFG_PROG_ID 1 2218 #define REDUCED_SRAM_CFG_PROG_ID 2 2219 #define OTHER_SRAM_CFG_PROG_ID 3 2220 2221 #define NO_FLASH_MEM_AVAIL 0xf1 2222 2223 #define PROG_TYPE_MASK 0xff000000 2224 #define PROG_TYPE_SHIFT 24 2225 2226 #define FLASH_LOAD_LIST_ADR 0x79c 2227 #define RAM_LOAD_ENTRY_SIZE 9 2228 #define FLASH_LOAD_ENTRY_SIZE 6 2229 #define RAM_LOAD_ENTRY_TYPE 0 2230 #define FLASH_LOAD_ENTRY_TYPE 1 2231 2232 #define CFG_DATA_NO_REGION -3 2233 2234 #define SLI_IMAGE_START 0x20080 2235 #define SLI_VERSION_LOC 0x270 2236 2237 2238 #define SLI_HW_REVISION_CHECK(x, y) ((x & 0xf0) == y) 2239 #define SLI_FCODE_REVISION_CHECK(x, y) (x == y) 2240 2241 2242 /* ************ OBJ firmware ************** */ 2243 #define OBJ_MAX_XFER_SIZE 32768 2244 2245 2246 /* ************ BladeEngine ************** */ 2247 #define BE_SIGNATURE "ServerEngines" 2248 #define BE_DIR_SIGNATURE "*** SE FLAS" 2249 #define BE_BUILD_SIZE 24 2250 #define BE_VERSION_SIZE 32 2251 #define BE_COOKIE_SIZE 32 2252 #define BE_CONTROLLER_SIZE 8 2253 #define BE_FLASH_ENTRIES 32 2254 #define BE_MAX_XFER_SIZE 32768 /* 4K aligned */ 2255 2256 /* ************** BE3 **************** */ 2257 #define BE3_SIGNATURE_SIZE 52 2258 #define BE3_MAX_IMAGE_HEADERS 32 2259 2260 typedef struct emlxs_be3_image_header 2261 { 2262 uint32_t id; 2263 #define UFI_BE3_FLASH_ID 0x01 2264 2265 uint32_t offset; 2266 uint32_t length; 2267 uint32_t checksum; 2268 uint8_t version[BE_VERSION_SIZE]; 2269 2270 } emlxs_be3_image_header_t; 2271 2272 typedef struct emlxs_be3_ufi_header 2273 { 2274 char signature[BE3_SIGNATURE_SIZE]; 2275 uint32_t ufi_version; 2276 uint32_t file_length; 2277 uint32_t checksum; 2278 uint32_t antidote; 2279 uint32_t image_cnt; 2280 char build[BE_BUILD_SIZE]; 2281 uint8_t resv1[32]; 2282 2283 } emlxs_be3_ufi_header_t; 2284 2285 typedef struct emlxs_be3_ufi_controller 2286 { 2287 uint32_t vendor_id; 2288 uint32_t device_id; 2289 uint32_t sub_vendor_id; 2290 uint32_t sub_device_id; 2291 2292 } emlxs_be3_ufi_controller_t; 2293 2294 typedef struct emlxs_be3_flash_header 2295 { 2296 uint32_t format_rev; 2297 uint32_t checksum; 2298 uint32_t antidote; 2299 uint32_t entry_count; 2300 emlxs_be3_ufi_controller_t controller[BE_CONTROLLER_SIZE]; 2301 uint32_t resv0; 2302 uint32_t resv1; 2303 uint32_t resv2; 2304 uint32_t resv3; 2305 } emlxs_be3_flash_header_t; 2306 2307 typedef struct emlxs_be3_flash_entry 2308 { 2309 uint32_t type; 2310 uint32_t offset; 2311 uint32_t block_size; 2312 uint32_t image_size; 2313 uint32_t checksum; 2314 uint32_t entry_point; 2315 uint32_t resv0; 2316 uint32_t resv1; 2317 char version[BE_VERSION_SIZE]; 2318 2319 } emlxs_be3_flash_entry_t; 2320 2321 typedef struct emlxs_be3_flash_dir 2322 { 2323 char cookie[BE_COOKIE_SIZE]; 2324 emlxs_be3_flash_header_t header; 2325 emlxs_be3_flash_entry_t entry[BE_FLASH_ENTRIES]; 2326 2327 } emlxs_be3_flash_dir_t; 2328 2329 typedef struct emlxs_be3_ncsi_header { 2330 uint32_t magic; 2331 uint8_t hdr_len; 2332 uint8_t type; 2333 uint16_t hdr_ver; 2334 uint16_t rsvd0; 2335 uint16_t load_offset; 2336 uint32_t len; 2337 uint32_t flash_offset; 2338 uint8_t ver[16]; 2339 uint8_t name[24]; 2340 uint32_t img_cksum; 2341 uint32_t rsvd1; 2342 uint32_t hdr_cksum; 2343 } emlxs_be3_ncsi_header_t; 2344 2345 2346 /* ************** BE2 **************** */ 2347 #define BE2_SIGNATURE_SIZE 32 2348 2349 2350 typedef struct emlxs_be2_ufi_controller 2351 { 2352 uint32_t vendor_id; 2353 uint32_t device_id; 2354 uint32_t sub_vendor_id; 2355 uint32_t sub_device_id; 2356 2357 } emlxs_be2_ufi_controller_t; 2358 2359 typedef struct emlxs_be2_ufi_header 2360 { 2361 char signature[BE2_SIGNATURE_SIZE]; 2362 uint32_t checksum; 2363 uint32_t antidote; 2364 emlxs_be2_ufi_controller_t controller; 2365 uint32_t file_length; 2366 uint32_t chunk_num; 2367 uint32_t chunk_cnt; 2368 uint32_t image_cnt; 2369 char build[BE_BUILD_SIZE]; 2370 2371 } emlxs_be2_ufi_header_t; 2372 2373 typedef struct emlxs_be2_flash_header /* 96 bytes */ 2374 { 2375 uint32_t format_rev; 2376 uint32_t checksum; 2377 uint32_t antidote; 2378 uint32_t build_num; 2379 emlxs_be2_ufi_controller_t controller[BE_CONTROLLER_SIZE]; 2380 uint32_t active_entry_mask; 2381 uint32_t valid_entry_mask; 2382 uint32_t orig_content_mask; 2383 uint32_t resv0; 2384 uint32_t resv1; 2385 uint32_t resv2; 2386 uint32_t resv3; 2387 uint32_t resv4; 2388 2389 } emlxs_be2_flash_header_t; 2390 2391 typedef struct emlxs_be2_flash_entry 2392 { 2393 uint32_t type; 2394 uint32_t offset; 2395 uint32_t pad_size; 2396 uint32_t image_size; 2397 uint32_t checksum; 2398 uint32_t entry_point; 2399 uint32_t resv0; 2400 uint32_t resv1; 2401 char version[BE_VERSION_SIZE]; 2402 2403 } emlxs_be2_flash_entry_t; 2404 2405 typedef struct emlxs_be2_flash_dir 2406 { 2407 char cookie[BE_COOKIE_SIZE]; 2408 emlxs_be2_flash_header_t header; 2409 emlxs_be2_flash_entry_t entry[BE_FLASH_ENTRIES]; 2410 2411 } emlxs_be2_flash_dir_t; 2412 2413 2414 /* FLASH ENTRY TYPES */ 2415 #define BE_FLASHTYPE_NCSI_FIRMWARE 0x10 /* BE3 */ 2416 #define BE_FLASHTYPE_PXE_BIOS 0x20 2417 #define BE_FLASHTYPE_FCOE_BIOS 0x21 2418 #define BE_FLASHTYPE_ISCSI_BIOS 0x22 2419 #define BE_FLASHTYPE_FLASH_ISM 0x30 /* BE3 */ 2420 #define BE_FLASHTYPE_ISCSI_FIRMWARE 0xA0 2421 #define BE_FLASHTYPE_ISCSI_FIRMWARE_COMP 0xA1 2422 #define BE_FLASHTYPE_FCOE_FIRMWARE 0xA2 2423 #define BE_FLASHTYPE_FCOE_FIRMWARE_COMP 0xA3 2424 #define BE_FLASHTYPE_ISCSI_BACKUP 0xB0 2425 #define BE_FLASHTYPE_ISCSI_BACKUP_COMP 0xB1 2426 #define BE_FLASHTYPE_FCOE_BACKUP 0xB2 2427 #define BE_FLASHTYPE_FCOE_BACKUP_COMP 0xB3 2428 #define BE_FLASHTYPE_PHY_FIRMWARE 0xC0 /* 10Base-T */ 2429 #define BE_FLASHTYPE_REDBOOT 0xE0 2430 2431 /* Flash types in download order */ 2432 typedef enum emlxs_be_flashtypes 2433 { 2434 PHY_FIRMWARE_FLASHTYPE, 2435 NCSI_FIRMWARE_FLASHTYPE, 2436 ISCSI_FIRMWARE_FLASHTYPE, 2437 ISCSI_BACKUP_FLASHTYPE, 2438 FCOE_FIRMWARE_FLASHTYPE, 2439 FCOE_BACKUP_FLASHTYPE, 2440 ISCSI_BIOS_FLASHTYPE, 2441 FCOE_BIOS_FLASHTYPE, 2442 PXE_BIOS_FLASHTYPE, 2443 REDBOOT_FLASHTYPE, 2444 BE_MAX_FLASHTYPES 2445 2446 } emlxs_be_flashtypes_t; 2447 2448 /* Driver level constructs */ 2449 typedef struct emlxs_be_fw_file 2450 { 2451 uint32_t be_version; 2452 uint32_t ufi_plus; 2453 2454 uint32_t type; 2455 uint32_t image_offset; 2456 uint32_t image_size; 2457 uint32_t block_size; 2458 uint32_t block_crc; 2459 uint32_t load_address; /* BE3 */ 2460 char label[BE_VERSION_SIZE]; 2461 } emlxs_be_fw_file_t; 2462 2463 typedef struct emlxs_be_fw_image 2464 { 2465 uint32_t be_version; 2466 uint32_t ufi_plus; 2467 2468 uint32_t fcoe_version; 2469 char fcoe_label[BE_VERSION_SIZE]; 2470 2471 uint32_t iscsi_version; 2472 char iscsi_label[BE_VERSION_SIZE]; 2473 2474 emlxs_be_fw_file_t file[BE_MAX_FLASHTYPES]; 2475 } emlxs_be_fw_image_t; 2476 2477 2478 typedef struct emlxs_obj_header 2479 { 2480 uint32_t FileSize; 2481 2482 #ifdef EMLXS_BIG_ENDIAN 2483 uint16_t MagicNumHi; 2484 uint16_t MagicNumLo; 2485 2486 uint32_t FileType:8; 2487 uint32_t Id:8; 2488 uint32_t rsvd0:16; 2489 #endif 2490 2491 #ifdef EMLXS_LITTLE_ENDIAN 2492 uint16_t MagicNumLo; 2493 uint16_t MagicNumHi; 2494 2495 uint32_t rsvd0:16; 2496 uint32_t Id:8; 2497 uint32_t FileType:8; 2498 #endif 2499 2500 #define OBJ_MAGIC_NUM_HI 0xFEAA 2501 #define OBJ_MAGIC_NUM_LO 0x0001 2502 2503 #define OBJ_GRP_FILE_TYPE 0xF7 2504 2505 #define OBJ_LANCER_ID 0xA2 2506 2507 char RevName[128]; 2508 char Date[12]; 2509 char Revision[32]; 2510 } emlxs_obj_header_t; 2511 2512 2513 #ifdef __cplusplus 2514 } 2515 #endif 2516 2517 #endif /* _EMLXS_HW_H */ 2518