1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*7c478bd9Sstevel@tonic-gate * Use is subject to license terms. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #ifndef _SYS_DMA_I8237A_H 28*7c478bd9Sstevel@tonic-gate #define _SYS_DMA_I8237A_H 29*7c478bd9Sstevel@tonic-gate 30*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 31*7c478bd9Sstevel@tonic-gate extern "C" { 32*7c478bd9Sstevel@tonic-gate #endif 33*7c478bd9Sstevel@tonic-gate 34*7c478bd9Sstevel@tonic-gate /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 35*7c478bd9Sstevel@tonic-gate /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 36*7c478bd9Sstevel@tonic-gate /* All Rights Reserved */ 37*7c478bd9Sstevel@tonic-gate 38*7c478bd9Sstevel@tonic-gate #define D37A_MAX_CHAN 8 39*7c478bd9Sstevel@tonic-gate #define D37A_DFR_ALIGN 0xf 40*7c478bd9Sstevel@tonic-gate #define D37A_MIN_CHAN 0x0 41*7c478bd9Sstevel@tonic-gate 42*7c478bd9Sstevel@tonic-gate /* 43*7c478bd9Sstevel@tonic-gate * Defines for PC AT DMA controllers. 44*7c478bd9Sstevel@tonic-gate */ 45*7c478bd9Sstevel@tonic-gate 46*7c478bd9Sstevel@tonic-gate /* 47*7c478bd9Sstevel@tonic-gate * The PC/AT has two Intel 8237A-5 DMA controllers that provide 8 channels 48*7c478bd9Sstevel@tonic-gate */ 49*7c478bd9Sstevel@tonic-gate #define DMA_0WCNT 0x01 /* Channel word count */ 50*7c478bd9Sstevel@tonic-gate #define DMA_1WCNT 0x03 /* Channel word count */ 51*7c478bd9Sstevel@tonic-gate #define DMA_2WCNT 0x05 /* Channel word count */ 52*7c478bd9Sstevel@tonic-gate #define DMA_3WCNT 0x07 /* Channel word count */ 53*7c478bd9Sstevel@tonic-gate #define DMA_4WCNT 0xC2 /* (RESERVED) Channel word count */ 54*7c478bd9Sstevel@tonic-gate #define DMA_5WCNT 0xC6 /* Channel word count */ 55*7c478bd9Sstevel@tonic-gate #define DMA_6WCNT 0xCA /* Channel word count */ 56*7c478bd9Sstevel@tonic-gate #define DMA_7WCNT 0xCE /* Channel word count */ 57*7c478bd9Sstevel@tonic-gate 58*7c478bd9Sstevel@tonic-gate #define DMA_0ADR 0x00 /* Channel address register */ 59*7c478bd9Sstevel@tonic-gate #define DMA_1ADR 0x02 /* Channel address register */ 60*7c478bd9Sstevel@tonic-gate #define DMA_2ADR 0x04 /* Channel address register */ 61*7c478bd9Sstevel@tonic-gate #define DMA_3ADR 0x06 /* Channel address register */ 62*7c478bd9Sstevel@tonic-gate #define DMA_4ADR 0xC0 /* (RESERVED) Channel address register */ 63*7c478bd9Sstevel@tonic-gate #define DMA_5ADR 0xC4 /* Channel address register */ 64*7c478bd9Sstevel@tonic-gate #define DMA_6ADR 0xC8 /* Channel address register */ 65*7c478bd9Sstevel@tonic-gate #define DMA_7ADR 0xCC /* Channel address register */ 66*7c478bd9Sstevel@tonic-gate 67*7c478bd9Sstevel@tonic-gate /* 68*7c478bd9Sstevel@tonic-gate * The Intel DMA controllers are augmented with 8-bit page registers 69*7c478bd9Sstevel@tonic-gate * for each channel, allowing access to a 16MB address space. 70*7c478bd9Sstevel@tonic-gate */ 71*7c478bd9Sstevel@tonic-gate #define DMA_0PAGE 0x87 /* Channel 0 address extension reg */ 72*7c478bd9Sstevel@tonic-gate #define DMA_1PAGE 0x83 /* Channel 1 address extension reg */ 73*7c478bd9Sstevel@tonic-gate #define DMA_2PAGE 0x81 /* Channel 2 address extension reg */ 74*7c478bd9Sstevel@tonic-gate #define DMA_3PAGE 0x82 /* Channel 3 address extension reg */ 75*7c478bd9Sstevel@tonic-gate #define DMA_4PAGE 0 /* dummy address for dma chan. 4 page reg. */ 76*7c478bd9Sstevel@tonic-gate #define DMA_5PAGE 0x8B /* Channel 5 address extension reg */ 77*7c478bd9Sstevel@tonic-gate #define DMA_6PAGE 0x89 /* Channel 6 address extension reg */ 78*7c478bd9Sstevel@tonic-gate #define DMA_7PAGE 0x8A /* Channel 7 address extension reg */ 79*7c478bd9Sstevel@tonic-gate 80*7c478bd9Sstevel@tonic-gate /* 81*7c478bd9Sstevel@tonic-gate * The EISA has an 8-bit high-page register for each channel 82*7c478bd9Sstevel@tonic-gate * for access to a 32-bit address space. 83*7c478bd9Sstevel@tonic-gate */ 84*7c478bd9Sstevel@tonic-gate #define DMA_0HPG 0x487 /* port address for dma channel 0 */ 85*7c478bd9Sstevel@tonic-gate /* high page reg */ 86*7c478bd9Sstevel@tonic-gate #define DMA_1HPG 0x483 /* port address for dma channel 1 */ 87*7c478bd9Sstevel@tonic-gate /* high page reg */ 88*7c478bd9Sstevel@tonic-gate #define DMA_2HPG 0x481 /* port address for dma channel 2 */ 89*7c478bd9Sstevel@tonic-gate /* high page reg */ 90*7c478bd9Sstevel@tonic-gate #define DMA_3HPG 0x482 /* port address for dma channel 3 */ 91*7c478bd9Sstevel@tonic-gate /* high page reg */ 92*7c478bd9Sstevel@tonic-gate #define DMA_4HPG 0 /* dummy address for dma channel 4 */ 93*7c478bd9Sstevel@tonic-gate /* high page reg */ 94*7c478bd9Sstevel@tonic-gate #define DMA_5HPG 0x48B /* port address for dma channel 5 */ 95*7c478bd9Sstevel@tonic-gate /* high page reg */ 96*7c478bd9Sstevel@tonic-gate #define DMA_6HPG 0x489 /* port address for dma channel 6 */ 97*7c478bd9Sstevel@tonic-gate /* high page reg */ 98*7c478bd9Sstevel@tonic-gate #define DMA_7HPG 0x48A /* port address for dma channel 7 */ 99*7c478bd9Sstevel@tonic-gate /* high page reg */ 100*7c478bd9Sstevel@tonic-gate 101*7c478bd9Sstevel@tonic-gate /* 102*7c478bd9Sstevel@tonic-gate * The EISA has an 8-bit high-count register for each channel 103*7c478bd9Sstevel@tonic-gate * for xfer sizes up to 16MB. 104*7c478bd9Sstevel@tonic-gate */ 105*7c478bd9Sstevel@tonic-gate #define DMA_0XCNT 0x401 /* chan. 0 base and current count high */ 106*7c478bd9Sstevel@tonic-gate #define DMA_1XCNT 0x403 /* chan. 1 base and current count high */ 107*7c478bd9Sstevel@tonic-gate #define DMA_2XCNT 0x405 /* chan. 2 base and current count high */ 108*7c478bd9Sstevel@tonic-gate #define DMA_3XCNT 0x407 /* chan. 3 base and current count high */ 109*7c478bd9Sstevel@tonic-gate #define DMA_4XCNT 0 /* dummy chan. 4 base and current count high */ 110*7c478bd9Sstevel@tonic-gate #define DMA_5XCNT 0x4C6 /* chan. 5 base and current count high */ 111*7c478bd9Sstevel@tonic-gate #define DMA_6XCNT 0x4CA /* chan. 6 base and current count high */ 112*7c478bd9Sstevel@tonic-gate #define DMA_7XCNT 0x4CE /* chan. 7 base and current count high */ 113*7c478bd9Sstevel@tonic-gate 114*7c478bd9Sstevel@tonic-gate /* 115*7c478bd9Sstevel@tonic-gate * I/O port addresses for controller 1 116*7c478bd9Sstevel@tonic-gate */ 117*7c478bd9Sstevel@tonic-gate #define DMAC1_CMD 0x08 /* Command reg */ 118*7c478bd9Sstevel@tonic-gate #define DMAC1_REQ 0x09 /* request reg */ 119*7c478bd9Sstevel@tonic-gate #define DMAC1_STAT 0x08 /* Status reg */ 120*7c478bd9Sstevel@tonic-gate #define DMAC1_MASK 0x0A /* Mask set/reset register */ 121*7c478bd9Sstevel@tonic-gate #define DMAC1_MODE 0x0B /* Mode reg */ 122*7c478bd9Sstevel@tonic-gate #define DMAC1_CLFF 0x0C /* Clear byte pointer first/last flip-flop */ 123*7c478bd9Sstevel@tonic-gate #define DMA1RTRWMC 0x0D /* read temp reg/write master clear */ 124*7c478bd9Sstevel@tonic-gate #define DMA1CMR 0x0E /* clear mask register */ 125*7c478bd9Sstevel@tonic-gate #define DMAC1_ALLMASK 0x0F /* Mask all registers */ 126*7c478bd9Sstevel@tonic-gate #define DMAC1_SCM 0x40A /* set chain mode */ 127*7c478bd9Sstevel@tonic-gate #define DMAC1_EWM 0x40B /* extended write mode */ 128*7c478bd9Sstevel@tonic-gate 129*7c478bd9Sstevel@tonic-gate /* 130*7c478bd9Sstevel@tonic-gate * I/O port addresses for controller 2 131*7c478bd9Sstevel@tonic-gate */ 132*7c478bd9Sstevel@tonic-gate #define DMAC2_CMD 0xD0 /* Command reg */ 133*7c478bd9Sstevel@tonic-gate #define DMAC2_STAT 0xD0 /* Status reg */ 134*7c478bd9Sstevel@tonic-gate #define DMAC2_REQ 0xD2 /* request reg */ 135*7c478bd9Sstevel@tonic-gate #define DMAC2_MASK 0xD4 /* Mask set/reset register */ 136*7c478bd9Sstevel@tonic-gate #define DMAC2_MODE 0xD6 /* Mode reg */ 137*7c478bd9Sstevel@tonic-gate #define DMAC2_CLFF 0xD8 /* Clear byte pointer first/last flip-flop */ 138*7c478bd9Sstevel@tonic-gate #define DMA2RTRWMC 0xDA /* read temp reg/write master clear */ 139*7c478bd9Sstevel@tonic-gate #define DMA2CMR 0xDC /* clear mask register */ 140*7c478bd9Sstevel@tonic-gate #define DMAC2_ALLMASK 0xDE /* Mask all registers */ 141*7c478bd9Sstevel@tonic-gate #define DMAC2_SCM 0x4D4 /* set chain mode */ 142*7c478bd9Sstevel@tonic-gate #define DMAC2_EWM 0x4D6 /* extended write mode */ 143*7c478bd9Sstevel@tonic-gate 144*7c478bd9Sstevel@tonic-gate /* 145*7c478bd9Sstevel@tonic-gate * Write-only Command register definitions. 146*7c478bd9Sstevel@tonic-gate */ 147*7c478bd9Sstevel@tonic-gate #define DMACMD_MEM_TO_MEM 0x01 /* memory-to-memory copy (1=enable) */ 148*7c478bd9Sstevel@tonic-gate #define DMACMD_CHAN_HOLD 0x02 /* Channel 0 address hold (1=enable) */ 149*7c478bd9Sstevel@tonic-gate #define DMACMD_CTLR_ENABLE 0x04 /* Controller disable (0=enabled) */ 150*7c478bd9Sstevel@tonic-gate #define DMACMD_TIMING 0x08 /* normal/compressed timing (0=nrml) */ 151*7c478bd9Sstevel@tonic-gate #define DMACMD_FIX_PRIO 0x10 /* fixed/rotating priority (0=fixed) */ 152*7c478bd9Sstevel@tonic-gate #define DMACMD_WRT_SELECT 0x20 /* late/ext write selection (1=ext) */ 153*7c478bd9Sstevel@tonic-gate #define DMACMD_DREQ_LEVEL 0x40 /* DREQ sense active (0=actv. high) */ 154*7c478bd9Sstevel@tonic-gate #define DMACMD_DACK_LEVEL 0x80 /* DACK sense active (0=actv. low) */ 155*7c478bd9Sstevel@tonic-gate 156*7c478bd9Sstevel@tonic-gate /* 157*7c478bd9Sstevel@tonic-gate * Initialization value for DMA controller. 158*7c478bd9Sstevel@tonic-gate */ 159*7c478bd9Sstevel@tonic-gate #define DMA_CTLR_INIT ~(DMACMD_MEM_TO_MEM | DMACMD_CHAN_HOLD | \ 160*7c478bd9Sstevel@tonic-gate DMACMD_CTLR_ENABLE | DMACMD_TIMING | \ 161*7c478bd9Sstevel@tonic-gate DMACMD_FIX_PRIO | DMACMD_WRT_SELECT | \ 162*7c478bd9Sstevel@tonic-gate DMACMD_DREQ_LEVEL | DMACMD_DACK_LEVEL) 163*7c478bd9Sstevel@tonic-gate 164*7c478bd9Sstevel@tonic-gate /* 165*7c478bd9Sstevel@tonic-gate * Write-only Mode register. There is actually a 6-bit Mode register 166*7c478bd9Sstevel@tonic-gate * associated with each channel. These are written one at a time, with 167*7c478bd9Sstevel@tonic-gate * the channel number indicated by the low-order 2 bits. 168*7c478bd9Sstevel@tonic-gate */ 169*7c478bd9Sstevel@tonic-gate 170*7c478bd9Sstevel@tonic-gate #define DMAMODE_CHAN 0x03 /* Mask for the "channel select" bits. */ 171*7c478bd9Sstevel@tonic-gate /* These indicate channel 0-3 */ 172*7c478bd9Sstevel@tonic-gate #define DMAMODE_VERF 0x00 /* Verify Transfer */ 173*7c478bd9Sstevel@tonic-gate #define DMAMODE_READ 0x04 /* Read Transfer */ 174*7c478bd9Sstevel@tonic-gate #define DMAMODE_WRITE 0x08 /* Write Transfer */ 175*7c478bd9Sstevel@tonic-gate /* Note: Above settings for bits 2-3 are */ 176*7c478bd9Sstevel@tonic-gate /* "don't care" if bits 6-7 indicate */ 177*7c478bd9Sstevel@tonic-gate /* cascade mode */ 178*7c478bd9Sstevel@tonic-gate #define DMAMODE_AUTO 0x10 /* enable Autoinitialization on completion */ 179*7c478bd9Sstevel@tonic-gate #define DMAMODE_DECR 0x20 /* Address Decrement. If 0, address incr */ 180*7c478bd9Sstevel@tonic-gate #define DMAMODE_DEMAND 0x00 /* Select Demand mode */ 181*7c478bd9Sstevel@tonic-gate /* Each DREQ causes transfers at full speed */ 182*7c478bd9Sstevel@tonic-gate /* until DREQ goes inactive (after which it */ 183*7c478bd9Sstevel@tonic-gate /* can be resumed) or either terminal-count */ 184*7c478bd9Sstevel@tonic-gate /* happens or EOP is asserted */ 185*7c478bd9Sstevel@tonic-gate #define DMAMODE_SINGLE 0x40 /* Select Single mode */ 186*7c478bd9Sstevel@tonic-gate /* Each DREQ causes a single byte/word xfer */ 187*7c478bd9Sstevel@tonic-gate #define DMAMODE_BLOCK 0x80 /* Select Block mode */ 188*7c478bd9Sstevel@tonic-gate /* Each DREQ causes transfers at full speed */ 189*7c478bd9Sstevel@tonic-gate /* until terminal count or EOP */ 190*7c478bd9Sstevel@tonic-gate #define DMAMODE_CASC 0xC0 /* Select Cascade mode. On the PC-AT, this */ 191*7c478bd9Sstevel@tonic-gate /* should be set for DMA 2 channel 0 ONLY */ 192*7c478bd9Sstevel@tonic-gate 193*7c478bd9Sstevel@tonic-gate 194*7c478bd9Sstevel@tonic-gate #define EISA_DMAIS 0x40a /* interrupt status register */ 195*7c478bd9Sstevel@tonic-gate 196*7c478bd9Sstevel@tonic-gate #define DMA_MSK 0x0A /* Mask, enable disk, disable others */ 197*7c478bd9Sstevel@tonic-gate #define DMA_CLEAR 0x1A /* Master clear */ 198*7c478bd9Sstevel@tonic-gate #define IOCR 0x56 /* IO controller */ 199*7c478bd9Sstevel@tonic-gate 200*7c478bd9Sstevel@tonic-gate /* 201*7c478bd9Sstevel@tonic-gate * DMA Channels. d_chan field of dmareq. 202*7c478bd9Sstevel@tonic-gate */ 203*7c478bd9Sstevel@tonic-gate 204*7c478bd9Sstevel@tonic-gate /* 8 bit channels */ 205*7c478bd9Sstevel@tonic-gate #define DMAE_CH0 0 /* Channel 0 */ 206*7c478bd9Sstevel@tonic-gate #define DMAE_CH1 1 /* Channel 1 */ 207*7c478bd9Sstevel@tonic-gate #define DMAE_CH2 2 /* Channel 2 */ 208*7c478bd9Sstevel@tonic-gate #define DMAE_CH3 3 /* Channel 3 */ 209*7c478bd9Sstevel@tonic-gate #define DMAE_CH4 4 /* Channel 4 */ 210*7c478bd9Sstevel@tonic-gate /* 16 bit channels */ 211*7c478bd9Sstevel@tonic-gate #define DMAE_CH5 5 /* Channel 5 */ 212*7c478bd9Sstevel@tonic-gate #define DMAE_CH6 6 /* Channel 6 */ 213*7c478bd9Sstevel@tonic-gate #define DMAE_CH7 7 /* Channel 7 */ 214*7c478bd9Sstevel@tonic-gate 215*7c478bd9Sstevel@tonic-gate /* 216*7c478bd9Sstevel@tonic-gate * DMA Masks. 217*7c478bd9Sstevel@tonic-gate */ 218*7c478bd9Sstevel@tonic-gate #define DMA_SETMSK 4 /* Set mask bit */ 219*7c478bd9Sstevel@tonic-gate #define DMA_CLRMSK 0 /* Clear mask bit */ 220*7c478bd9Sstevel@tonic-gate 221*7c478bd9Sstevel@tonic-gate /* dma_alloc modes */ 222*7c478bd9Sstevel@tonic-gate #define DMA_BLOCK 0 /* blocking task time allocation */ 223*7c478bd9Sstevel@tonic-gate #define DMA_NBLOCK 1 /* non-blocking task time allocation */ 224*7c478bd9Sstevel@tonic-gate 225*7c478bd9Sstevel@tonic-gate #define EISA_DMA_8 0 /* 8-bit data path */ 226*7c478bd9Sstevel@tonic-gate #define EISA_DMA_16 1<<2 /* 16-bit data path, word count */ 227*7c478bd9Sstevel@tonic-gate #define EISA_DMA_32 2<<2 /* 32-bit data path */ 228*7c478bd9Sstevel@tonic-gate #define EISA_DMA_16B 3<<2 /* 16-bit data path, byte count */ 229*7c478bd9Sstevel@tonic-gate 230*7c478bd9Sstevel@tonic-gate #define EISA_ENCM 4 /* enable chaining mode */ 231*7c478bd9Sstevel@tonic-gate #define EISA_CMOK 8 /* chaining mode completed (OK) */ 232*7c478bd9Sstevel@tonic-gate 233*7c478bd9Sstevel@tonic-gate 234*7c478bd9Sstevel@tonic-gate /* 235*7c478bd9Sstevel@tonic-gate * Channel Address Array - makes life much easier 236*7c478bd9Sstevel@tonic-gate */ 237*7c478bd9Sstevel@tonic-gate struct d37A_chan_reg_addr { 238*7c478bd9Sstevel@tonic-gate uchar_t addr_reg; /* address register */ 239*7c478bd9Sstevel@tonic-gate uchar_t cnt_reg; /* count register */ 240*7c478bd9Sstevel@tonic-gate uchar_t page_reg; /* page register */ 241*7c478bd9Sstevel@tonic-gate uchar_t ff_reg; /* first-last flipflop */ 242*7c478bd9Sstevel@tonic-gate uchar_t cmd_reg; /* command register */ 243*7c478bd9Sstevel@tonic-gate uchar_t mode_reg; /* mode register */ 244*7c478bd9Sstevel@tonic-gate uchar_t mask_reg; /* mask register */ 245*7c478bd9Sstevel@tonic-gate uchar_t stat_reg; /* status register */ 246*7c478bd9Sstevel@tonic-gate uchar_t reqt_reg; /* request register */ 247*7c478bd9Sstevel@tonic-gate ushort_t hpage_reg; /* high page register */ 248*7c478bd9Sstevel@tonic-gate ushort_t hcnt_reg; /* high count register */ 249*7c478bd9Sstevel@tonic-gate ushort_t emode_reg; /* extended mode register */ 250*7c478bd9Sstevel@tonic-gate ushort_t scm_reg; /* set chaining mode register */ 251*7c478bd9Sstevel@tonic-gate }; 252*7c478bd9Sstevel@tonic-gate 253*7c478bd9Sstevel@tonic-gate /* 254*7c478bd9Sstevel@tonic-gate * macro to initialize array of d37A_chan_reg_addr structures 255*7c478bd9Sstevel@tonic-gate */ 256*7c478bd9Sstevel@tonic-gate #define D37A_BASE_REGS_VALUES \ 257*7c478bd9Sstevel@tonic-gate {DMA_0ADR, DMA_0WCNT, DMA_0PAGE, DMAC1_CLFF, \ 258*7c478bd9Sstevel@tonic-gate DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \ 259*7c478bd9Sstevel@tonic-gate DMA_0HPG, DMA_0XCNT, DMAC1_EWM, DMAC1_SCM}, \ 260*7c478bd9Sstevel@tonic-gate {DMA_1ADR, DMA_1WCNT, DMA_1PAGE, DMAC1_CLFF, \ 261*7c478bd9Sstevel@tonic-gate DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \ 262*7c478bd9Sstevel@tonic-gate DMA_1HPG, DMA_1XCNT, DMAC1_EWM, DMAC1_SCM}, \ 263*7c478bd9Sstevel@tonic-gate {DMA_2ADR, DMA_2WCNT, DMA_2PAGE, DMAC1_CLFF, \ 264*7c478bd9Sstevel@tonic-gate DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \ 265*7c478bd9Sstevel@tonic-gate DMA_2HPG, DMA_2XCNT, DMAC1_EWM, DMAC1_SCM}, \ 266*7c478bd9Sstevel@tonic-gate {DMA_3ADR, DMA_3WCNT, DMA_3PAGE, DMAC1_CLFF, \ 267*7c478bd9Sstevel@tonic-gate DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \ 268*7c478bd9Sstevel@tonic-gate DMA_3HPG, DMA_3XCNT, DMAC1_EWM, DMAC1_SCM}, \ 269*7c478bd9Sstevel@tonic-gate {DMA_4ADR, DMA_4WCNT, DMA_4PAGE, DMAC2_CLFF, \ 270*7c478bd9Sstevel@tonic-gate DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \ 271*7c478bd9Sstevel@tonic-gate DMA_4HPG, DMA_4XCNT, DMAC2_EWM, DMAC2_SCM}, \ 272*7c478bd9Sstevel@tonic-gate {DMA_5ADR, DMA_5WCNT, DMA_5PAGE, DMAC2_CLFF, \ 273*7c478bd9Sstevel@tonic-gate DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \ 274*7c478bd9Sstevel@tonic-gate DMA_5HPG, DMA_5XCNT, DMAC2_EWM, DMAC2_SCM}, \ 275*7c478bd9Sstevel@tonic-gate {DMA_6ADR, DMA_6WCNT, DMA_6PAGE, DMAC2_CLFF, \ 276*7c478bd9Sstevel@tonic-gate DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \ 277*7c478bd9Sstevel@tonic-gate DMA_6HPG, DMA_6XCNT, DMAC2_EWM, DMAC2_SCM}, \ 278*7c478bd9Sstevel@tonic-gate {DMA_7ADR, DMA_7WCNT, DMA_7PAGE, DMAC2_CLFF, \ 279*7c478bd9Sstevel@tonic-gate DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \ 280*7c478bd9Sstevel@tonic-gate DMA_7HPG, DMA_7XCNT, DMAC2_EWM, DMAC2_SCM} 281*7c478bd9Sstevel@tonic-gate 282*7c478bd9Sstevel@tonic-gate extern int d37A_init(dev_info_t *); 283*7c478bd9Sstevel@tonic-gate extern void d37A_dma_disable(int); 284*7c478bd9Sstevel@tonic-gate extern void d37A_dma_enable(int); 285*7c478bd9Sstevel@tonic-gate extern void d37A_dma_swstart(int); 286*7c478bd9Sstevel@tonic-gate extern void d37A_dma_stop(int); 287*7c478bd9Sstevel@tonic-gate extern void d37A_get_chan_stat(int, ulong_t *, int *); 288*7c478bd9Sstevel@tonic-gate extern int d37A_dma_valid(int); 289*7c478bd9Sstevel@tonic-gate extern void d37A_dma_release(int); 290*7c478bd9Sstevel@tonic-gate 291*7c478bd9Sstevel@tonic-gate /* The following 3 routines are intel specific : man page ddi_dmae_req(9S) */ 292*7c478bd9Sstevel@tonic-gate #if defined(__i386) || defined(__amd64) 293*7c478bd9Sstevel@tonic-gate extern uchar_t d37A_get_best_mode(struct ddi_dmae_req *); 294*7c478bd9Sstevel@tonic-gate extern int d37A_prog_chan(struct ddi_dmae_req *, ddi_dma_cookie_t *, int); 295*7c478bd9Sstevel@tonic-gate extern int d37A_dma_swsetup(struct ddi_dmae_req *, ddi_dma_cookie_t *, int); 296*7c478bd9Sstevel@tonic-gate #endif 297*7c478bd9Sstevel@tonic-gate 298*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 299*7c478bd9Sstevel@tonic-gate } 300*7c478bd9Sstevel@tonic-gate #endif 301*7c478bd9Sstevel@tonic-gate 302*7c478bd9Sstevel@tonic-gate #endif /* _SYS_DMA_I8237A_H */ 303