17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5ae115bc7Smrj * Common Development and Distribution License (the "License"). 6ae115bc7Smrj * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 227af88ac7SKuriakose Kuruvilla * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. 23e4f6ce70SRobert Mustacchi * Copyright 2019, Joyent, Inc. 24*56726c7eSRobert Mustacchi * Copyright 2022 Oxide Computer Company 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #ifndef _SYS_AUXV_386_H 287c478bd9Sstevel@tonic-gate #define _SYS_AUXV_386_H 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #ifdef __cplusplus 317c478bd9Sstevel@tonic-gate extern "C" { 327c478bd9Sstevel@tonic-gate #endif 337c478bd9Sstevel@tonic-gate 347c478bd9Sstevel@tonic-gate /* 357c478bd9Sstevel@tonic-gate * Flags used in AT_SUN_HWCAP elements to describe various userland 367c478bd9Sstevel@tonic-gate * instruction set extensions available on different processors. 377c478bd9Sstevel@tonic-gate * The basic assumption is that of the i386 ABI; that is, i386 plus i387 387c478bd9Sstevel@tonic-gate * floating point. 397c478bd9Sstevel@tonic-gate * 407c478bd9Sstevel@tonic-gate * Note that if a given bit is set; the implication is that the kernel 417c478bd9Sstevel@tonic-gate * provides all the underlying architectural support for the correct 427c478bd9Sstevel@tonic-gate * functioning of the extended instruction(s). 437c478bd9Sstevel@tonic-gate */ 447c478bd9Sstevel@tonic-gate #define AV_386_FPU 0x00001 /* x87-style floating point */ 457c478bd9Sstevel@tonic-gate #define AV_386_TSC 0x00002 /* rdtsc insn */ 467c478bd9Sstevel@tonic-gate #define AV_386_CX8 0x00004 /* cmpxchg8b insn */ 477c478bd9Sstevel@tonic-gate #define AV_386_SEP 0x00008 /* sysenter and sysexit */ 487c478bd9Sstevel@tonic-gate #define AV_386_AMD_SYSC 0x00010 /* AMD's syscall and sysret */ 497c478bd9Sstevel@tonic-gate #define AV_386_CMOV 0x00020 /* conditional move insns */ 507c478bd9Sstevel@tonic-gate #define AV_386_MMX 0x00040 /* MMX insns */ 517c478bd9Sstevel@tonic-gate #define AV_386_AMD_MMX 0x00080 /* AMD's MMX insns */ 527c478bd9Sstevel@tonic-gate #define AV_386_AMD_3DNow 0x00100 /* AMD's 3Dnow! insns */ 537c478bd9Sstevel@tonic-gate #define AV_386_AMD_3DNowx 0x00200 /* AMD's 3Dnow! extended insns */ 547c478bd9Sstevel@tonic-gate #define AV_386_FXSR 0x00400 /* fxsave and fxrstor */ 557c478bd9Sstevel@tonic-gate #define AV_386_SSE 0x00800 /* SSE insns and regs */ 567c478bd9Sstevel@tonic-gate #define AV_386_SSE2 0x01000 /* SSE2 insns and regs */ 574e12d685SRod Evans /* 0x02000 withdrawn - do not assign */ 587c478bd9Sstevel@tonic-gate #define AV_386_SSE3 0x04000 /* SSE3 insns and regs */ 594e12d685SRod Evans /* 0x08000 withdrawn - do not assign */ 607c478bd9Sstevel@tonic-gate #define AV_386_CX16 0x10000 /* cmpxchg16b insn */ 61ae115bc7Smrj #define AV_386_AHF 0x20000 /* lahf/sahf insns */ 62ae115bc7Smrj #define AV_386_TSCP 0x40000 /* rdtscp instruction */ 63f8801251Skk #define AV_386_AMD_SSE4A 0x80000 /* AMD's SSE4A insns */ 64f8801251Skk #define AV_386_POPCNT 0x100000 /* POPCNT insn */ 65f8801251Skk #define AV_386_AMD_LZCNT 0x200000 /* AMD's LZCNT insn */ 66d0f8ff6eSkk #define AV_386_SSSE3 0x400000 /* Intel SSSE3 insns */ 67d0f8ff6eSkk #define AV_386_SSE4_1 0x800000 /* Intel SSE4.1 insns */ 68d0f8ff6eSkk #define AV_386_SSE4_2 0x1000000 /* Intel SSE4.2 insns */ 695087e485SKrishnendu Sadhukhan - Sun Microsystems #define AV_386_MOVBE 0x2000000 /* Intel MOVBE insns */ 70a50a8b93SKuriakose Kuruvilla #define AV_386_AES 0x4000000 /* Intel AES insns */ 71a50a8b93SKuriakose Kuruvilla #define AV_386_PCLMULQDQ 0x8000000 /* Intel PCLMULQDQ insn */ 727af88ac7SKuriakose Kuruvilla #define AV_386_XSAVE 0x10000000 /* Intel XSAVE/XRSTOR insns */ 737af88ac7SKuriakose Kuruvilla #define AV_386_AVX 0x20000000 /* Intel AVX insns */ 74faa20166SBryan Cantrill #define AV_386_VMX 0x40000000 /* Intel VMX support */ 75faa20166SBryan Cantrill #define AV_386_AMD_SVM 0x80000000 /* AMD SVM support */ 767c478bd9Sstevel@tonic-gate 777c478bd9Sstevel@tonic-gate #define FMT_AV_386 \ 78faa20166SBryan Cantrill "\020" \ 79faa20166SBryan Cantrill "\040svm\037vmx\036avx\035xsave" \ 80faa20166SBryan Cantrill "\034pclmulqdq\033aes" \ 81faa20166SBryan Cantrill "\032movbe\031sse4.2" \ 82faa20166SBryan Cantrill "\030sse4.1\027ssse3\026amd_lzcnt\025popcnt" \ 83faa20166SBryan Cantrill "\024amd_sse4a\023tscp\022ahf\021cx16" \ 84faa20166SBryan Cantrill "\017sse3\015sse2\014sse\013fxsr\012amd3dx\011amd3d" \ 85faa20166SBryan Cantrill "\010amdmmx\07mmx\06cmov\05amdsysc\04sep\03cx8\02tsc\01fpu" 867c478bd9Sstevel@tonic-gate 87088d69f8SJerry Jelinek /* 88088d69f8SJerry Jelinek * Flags used in AT_SUN_HWCAP2 elements 89088d69f8SJerry Jelinek */ 90cff040f3SRobert Mustacchi #define AV_386_2_F16C 0x00000001 /* F16C half percision extensions */ 91cff040f3SRobert Mustacchi #define AV_386_2_RDRAND 0x00000002 /* RDRAND insn */ 92cff040f3SRobert Mustacchi #define AV_386_2_BMI1 0x00000004 /* BMI1 insns */ 93cff040f3SRobert Mustacchi #define AV_386_2_BMI2 0x00000008 /* BMI2 insns */ 94cff040f3SRobert Mustacchi #define AV_386_2_FMA 0x00000010 /* FMA insns */ 95cff040f3SRobert Mustacchi #define AV_386_2_AVX2 0x00000020 /* AVX2 insns */ 96cff040f3SRobert Mustacchi #define AV_386_2_ADX 0x00000040 /* ADX insns */ 97cff040f3SRobert Mustacchi #define AV_386_2_RDSEED 0x00000080 /* RDSEED insn */ 98cff040f3SRobert Mustacchi #define AV_386_2_AVX512F 0x00000100 /* AVX512 foundation insns */ 99cff040f3SRobert Mustacchi #define AV_386_2_AVX512DQ 0x00000200 /* AVX512DQ insns */ 100cff040f3SRobert Mustacchi #define AV_386_2_AVX512IFMA 0x00000400 /* AVX512IFMA insns */ 101cff040f3SRobert Mustacchi #define AV_386_2_AVX512PF 0x00000800 /* AVX512PF insns */ 102cff040f3SRobert Mustacchi #define AV_386_2_AVX512ER 0x00001000 /* AVX512ER insns */ 103cff040f3SRobert Mustacchi #define AV_386_2_AVX512CD 0x00002000 /* AVX512CD insns */ 104cff040f3SRobert Mustacchi #define AV_386_2_AVX512BW 0x00004000 /* AVX512BW insns */ 105cff040f3SRobert Mustacchi #define AV_386_2_AVX512VL 0x00008000 /* AVX512VL insns */ 106cff040f3SRobert Mustacchi #define AV_386_2_AVX512VBMI 0x00010000 /* AVX512VBMI insns */ 107cff040f3SRobert Mustacchi #define AV_386_2_AVX512VPOPCDQ 0x00020000 /* AVX512VPOPCNTDQ insns */ 108cff040f3SRobert Mustacchi #define AV_386_2_AVX512_4NNIW 0x00040000 /* AVX512 4NNIW insns */ 109cff040f3SRobert Mustacchi #define AV_386_2_AVX512_4FMAPS 0x00080000 /* AVX512 4FMAPS insns */ 110cff040f3SRobert Mustacchi #define AV_386_2_SHA 0x00100000 /* SHA insns */ 111cff040f3SRobert Mustacchi #define AV_386_2_FSGSBASE 0x00200000 /* FSBASE/GSBASE */ 112cff040f3SRobert Mustacchi #define AV_386_2_CLFLUSHOPT 0x00400000 /* CLFLUSHOPT instr */ 113cff040f3SRobert Mustacchi #define AV_386_2_CLWB 0x00800000 /* CLWB insn */ 114cff040f3SRobert Mustacchi #define AV_386_2_MONITORX 0x01000000 /* MONITORX insns */ 115cff040f3SRobert Mustacchi #define AV_386_2_CLZERO 0x02000000 /* CLZERO */ 116e4f6ce70SRobert Mustacchi #define AV_386_2_AVX512_VNNI 0x04000000 /* AVX512_VNNI */ 1175edbd2feSRobert Mustacchi #define AV_386_2_VPCLMULQDQ 0x08000000 /* VPCLMULQDQ */ 1185edbd2feSRobert Mustacchi #define AV_386_2_VAES 0x10000000 /* VAES */ 119*56726c7eSRobert Mustacchi #define AV_386_2_GFNI 0x20000000 /* GFNI */ 120*56726c7eSRobert Mustacchi #define AV_386_2_AVX512_VP2INT 0x40000000 /* AVX512 VP2INTERESECT */ 121*56726c7eSRobert Mustacchi #define AV_386_2_AVX512_BITALG 0x80000000 /* AVX512 BITALG */ 122ebb8ac07SRobert Mustacchi 123ebb8ac07SRobert Mustacchi #define FMT_AV_386_2 \ 124*56726c7eSRobert Mustacchi "\040avx512_vbmi2\037avx512_vp2intersect" \ 125*56726c7eSRobert Mustacchi "\036gfni\035vaes\034vpclmulqdq\033avx512_vnni" \ 126e4f6ce70SRobert Mustacchi "\032clzero\031monitorx\030clwb\027clflushopt\026fsgsbase" \ 127008b34beSRobert Mustacchi "\025sha\024avx512_4fmaps\023avx512_4nniw\022avx512vpopcntdq" \ 128088d69f8SJerry Jelinek "\021avx512vbmi\020avx512vl\017avx512bw\016avx512cd" \ 129088d69f8SJerry Jelinek "\015avx512er\014avx512pf\013avx512ifma\012avx512dq\011avx512f" \ 130088d69f8SJerry Jelinek "\010rdseed\07adx\06avx2\05fma\04bmi2\03bmi1\02rdrand\01f16c" 131ebb8ac07SRobert Mustacchi 132*56726c7eSRobert Mustacchi /* 133*56726c7eSRobert Mustacchi * Flags used in AT_SUN_HWCAP3 elements 134*56726c7eSRobert Mustacchi */ 135*56726c7eSRobert Mustacchi #define AV_386_3_AVX512_VBMI2 0x00000001 /* AVX512_VBMI2 */ 136*56726c7eSRobert Mustacchi #define AV_386_3_AVX512_BF16 0x00000002 /* AVX512_BF16 */ 137*56726c7eSRobert Mustacchi 138*56726c7eSRobert Mustacchi #define FMT_AV_386_3 \ 139*56726c7eSRobert Mustacchi "\02avx512_bf16\01avx512_vbmi2" 140*56726c7eSRobert Mustacchi 141d0158222SRobert Mustacchi /* 142d0158222SRobert Mustacchi * Flags used in AT_SUN_FPTYPE on x86. 143d0158222SRobert Mustacchi * 144d0158222SRobert Mustacchi * We don't currently support xsavec in illumos. However, when we do, then we 145d0158222SRobert Mustacchi * should add this to the type list and extend our primary consumer (rtld) to 146d0158222SRobert Mustacchi * use it. xsaveopt is not in this list because it is not appropriate for the 147d0158222SRobert Mustacchi * stack based storage. 148d0158222SRobert Mustacchi */ 149d0158222SRobert Mustacchi #define AT_386_FPINFO_NONE 0 150d0158222SRobert Mustacchi #define AT_386_FPINFO_FXSAVE 1 151d0158222SRobert Mustacchi #define AT_386_FPINFO_XSAVE 2 152d0158222SRobert Mustacchi #define AT_386_FPINFO_XSAVE_AMD 3 153d0158222SRobert Mustacchi 1547c478bd9Sstevel@tonic-gate #ifdef __cplusplus 1557c478bd9Sstevel@tonic-gate } 1567c478bd9Sstevel@tonic-gate #endif 1577c478bd9Sstevel@tonic-gate 1587c478bd9Sstevel@tonic-gate #endif /* !_SYS_AUXV_386_H */ 159