1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2002 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_1394_TARGETS_AV1394_ISOCH_H 28 #define _SYS_1394_TARGETS_AV1394_ISOCH_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * isoch module definitions 34 */ 35 36 #include <sys/note.h> 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /* 43 * isoch DMA memory management: segments and pools 44 * 45 * isoch segment - a contiguous chunk of kernel memory 46 */ 47 typedef struct av1394_isoch_seg_s { 48 caddr_t is_kaddr; /* segment kernel virt addr */ 49 int is_size; /* segment size */ 50 ddi_umem_cookie_t is_umem_cookie; /* umem cookie */ 51 size_t is_umem_size; /* umem size (page-aligned) */ 52 ddi_dma_handle_t is_dma_hdl; /* bind handle */ 53 ddi_dma_cookie_t is_dma_cookie; /* dma cookie */ 54 uint_t is_dma_ncookies; /* # of cookies */ 55 } av1394_isoch_seg_t; 56 57 /* 58 * isoch pool - a set of one or more isoch segments 59 */ 60 typedef struct av1394_isoch_pool_s { 61 av1394_isoch_seg_t *ip_seg; /* array of segments */ 62 int ip_nsegs; /* # of valid segments */ 63 int ip_alloc_size; /* array alloc'd size */ 64 int ip_size; /* total pool size */ 65 int ip_umem_size; /* total alloc'd memory size */ 66 } av1394_isoch_pool_t; 67 68 /* 69 * many members are protected because they are modified during channel 70 * initialization or/and during isoch transfer, both of which are 71 * single-threaded processes. after that these members remain read-only. 72 */ 73 _NOTE(SCHEME_PROTECTS_DATA("single-threaded", av1394_isoch_seg_s)) 74 _NOTE(SCHEME_PROTECTS_DATA("single-threaded", av1394_isoch_pool_s)) 75 76 /* 77 * IXL receive data block (one or more RECV_BUF commands will follow the label) 78 */ 79 typedef struct av1394_ir_ixl_data_s { 80 ixl1394_label_t rd_label; 81 ixl1394_callback_t rd_cb; /* buffer completion callback */ 82 ixl1394_jump_t rd_jump; /* next command */ 83 } av1394_ir_ixl_data_t; 84 85 _NOTE(SCHEME_PROTECTS_DATA("single-threaded", av1394_ir_ixl_data_s)) 86 87 /* 88 * isoch receive structure 89 */ 90 typedef struct av1394_ir_s { 91 av1394_isoch_pool_t ir_data_pool; /* pool for data packets */ 92 /* IXL */ 93 ixl1394_command_t *ir_ixlp; /* IXL chain */ 94 av1394_ir_ixl_data_t *ir_ixl_data; /* data block array */ 95 ixl1394_xfer_buf_t *ir_ixl_buf; /* RECV_BUF command array */ 96 int ir_ixl_nbufs; /* # of commands in array */ 97 size_t ir_ixl_bpf; /* # of buffers per frame - 1 */ 98 size_t ir_ixl_bufsz; /* buffer size */ 99 size_t ir_ixl_tailsz; /* tail buffer size */ 100 /* xfer */ 101 int ir_nfull; /* # of full frames */ 102 int ir_first_full; /* first full frame */ 103 int ir_nempty; /* # of empty frames */ 104 int ir_last_empty; /* last produced frame */ 105 int ir_hiwat; /* high water mark */ 106 int ir_lowat; /* low water mark */ 107 int ir_overflow_idx; /* overflow frame index */ 108 /* read() support */ 109 int ir_read_idx; /* first full frame */ 110 int ir_read_cnt; /* number of full frames */ 111 off_t ir_read_off; /* offset into the frame */ 112 } av1394_ir_t; 113 114 _NOTE(SCHEME_PROTECTS_DATA("single-threaded", av1394_ir_s::{ 115 ir_ixlp 116 ir_ixl_buf 117 ir_ixl_nbufs 118 ir_ixl_bpf 119 ir_ixl_bufsz 120 ir_ixl_tailsz 121 })) 122 123 /* 124 * IXL transmit begin block, used to get a starting point for timestamping 125 */ 126 enum { AV1394_IT_IXL_BEGIN_NPOST = 3 }; 127 128 typedef struct av1394_it_ixl_begin_s { 129 ixl1394_label_t be_label; 130 ixl1394_xfer_pkt_t be_empty_pre; /* needed for next command */ 131 ixl1394_store_timestamp_t be_store_ts; /* store timestamp */ 132 ixl1394_callback_t be_cb; /* timestamp handling */ 133 ixl1394_xfer_pkt_t be_empty_post[AV1394_IT_IXL_BEGIN_NPOST]; 134 ixl1394_jump_t be_jump; /* next command */ 135 } av1394_it_ixl_begin_t; 136 137 _NOTE(SCHEME_PROTECTS_DATA("single-threaded", av1394_it_ixl_begin_s)) 138 139 /* 140 * common part of transmit commands that are in a linked list 141 */ 142 typedef struct av1394_it_ixl_common_s { 143 struct av1394_it_ixl_common_s *tc_next; /* next in the list */ 144 int tc_size; /* structure size */ 145 } av1394_it_ixl_common_t; 146 147 /* 148 * IXL transmit data block 149 */ 150 typedef struct av1394_it_ixl_buf_s { 151 av1394_it_ixl_common_t tb_common; 152 int tb_flags; 153 int tb_framenum; /* frame number */ 154 struct av1394_ic_s *tb_icp; 155 ixl1394_label_t tb_label; 156 ixl1394_xfer_buf_t tb_buf; /* transmit packets */ 157 ixl1394_store_timestamp_t tb_store_ts; /* cycle time feedback */ 158 ixl1394_callback_t tb_cb; /* callback */ 159 ixl1394_jump_t tb_jump; /* next command */ 160 } av1394_it_ixl_buf_t; 161 162 _NOTE(SCHEME_PROTECTS_DATA("single-threaded", av1394_it_ixl_buf_s)) 163 164 /* tb_flags */ 165 enum { 166 AV1394_IT_IXL_BUF_NEXT_EMPTY = 0x01, /* followed by empty CIP */ 167 AV1394_IT_IXL_BUF_SOF = 0x02, /* start of frame */ 168 AV1394_IT_IXL_BUF_EOF = 0x04 /* end of frame */ 169 }; 170 171 /* 172 * empty CIP 173 */ 174 typedef struct av1394_it_ixl_empty_cip_s { 175 av1394_it_ixl_common_t te_common; 176 ixl1394_label_t te_label; 177 ixl1394_xfer_pkt_t te_pkt; 178 ixl1394_jump_t te_jump; /* next command */ 179 } av1394_it_ixl_empty_cip_t; 180 181 _NOTE(SCHEME_PROTECTS_DATA("single-threaded", av1394_it_ixl_empty_cip_s)) 182 183 /* 184 * per-frame information 185 */ 186 typedef struct av1394_it_frame_info_s { 187 caddr_t fi_ts_off; /* where to put a timestamp */ 188 int fi_ncycs; /* # of bus cycles */ 189 av1394_it_ixl_buf_t *fi_first_buf; /* first IXL buffer */ 190 av1394_it_ixl_buf_t *fi_last_buf; /* last IXL buffer */ 191 } av1394_it_frame_info_t; 192 193 _NOTE(SCHEME_PROTECTS_DATA("single-threaded", av1394_it_frame_info_s)) 194 195 /* 196 * timestamp type 197 */ 198 typedef union av1394_it_ts { 199 uint16_t ts_syt; /* SYT timestamp */ 200 } av1394_it_ts_t; 201 202 /* 203 * isoch transmit structure 204 */ 205 typedef struct av1394_it_s { 206 av1394_isoch_pool_t it_data_pool; /* pool for data packets */ 207 /* IXL */ 208 ixl1394_command_t *it_ixlp; /* IXL chain */ 209 av1394_it_ixl_begin_t it_ixl_begin; /* begin block */ 210 av1394_it_ixl_common_t *it_ixl_data; /* data block */ 211 av1394_it_frame_info_t *it_frame_info; /* frame info array */ 212 av1394_it_ixl_empty_cip_t *it_skipped_cip; /* last skipped CIP */ 213 /* xfer */ 214 int it_first_empty; /* first empty frame # */ 215 int it_nempty; /* # of empty frames */ 216 int it_last_full; /* last full frame # */ 217 int it_nfull; /* # of full frames */ 218 int it_hiwat; /* high water mark */ 219 int it_lowat; /* low water mark */ 220 int it_start_thre; /* xfer start threshold */ 221 av1394_it_ts_t it_ts_init; /* initial timestamp */ 222 /* underrun data */ 223 int it_underrun_idx; /* underrun frame index */ 224 ixl1394_command_t *it_saved_label; /* saved buffer label */ 225 /* write() support */ 226 int it_write_idx; /* first empty frame */ 227 int it_write_cnt; /* # of empty frames */ 228 off_t it_write_off; /* offset into the frame */ 229 } av1394_it_t; 230 231 _NOTE(SCHEME_PROTECTS_DATA("single-threaded", av1394_it_s::{ 232 it_ixlp 233 it_ixl_begin 234 it_ixl_data 235 it_frame_info 236 it_ts_init 237 it_skipped_cip 238 })) 239 240 /* misc channel parameters */ 241 typedef struct av1394_ic_param_s { 242 int cp_bus_speed; /* bus speed */ 243 int cp_dbs; /* DBS */ 244 int cp_fn; /* FN */ 245 int cp_n; /* rate numerator */ 246 int cp_d; /* rate denominator */ 247 int cp_ts_mode; /* timestamp mode */ 248 } av1394_ic_param_t; 249 250 /* channel state */ 251 typedef enum { 252 AV1394_IC_IDLE, /* nothing happens */ 253 AV1394_IC_STARTED, /* channel has been started */ 254 AV1394_IC_DMA, /* DMA transfer is in progress */ 255 AV1394_IC_SUSPENDED /* transfer on the channel suspended */ 256 } av1394_ic_state_t; 257 258 /* 259 * isoch channel structure, common for both recv and xmit 260 */ 261 typedef struct av1394_ic_s { 262 kmutex_t ic_mutex; /* structure mutex */ 263 struct av1394_inst_s *ic_avp; /* backpointer to instance */ 264 int ic_num; /* channel # */ 265 int ic_dir; /* xfer direction */ 266 av1394_ic_state_t ic_state; /* state */ 267 int ic_pktsz; /* packet size */ 268 int ic_npkts; /* # of packets/frame */ 269 size_t ic_framesz; /* frame size (pktsz * npkts) */ 270 int ic_nframes; /* # of frames */ 271 av1394_ic_param_t ic_param; /* misc parameters */ 272 size_t ic_mmap_sz; /* mmap size */ 273 off_t ic_mmap_off; /* mmap offset */ 274 t1394_isoch_single_handle_t ic_sii_hdl; /* isoch single handle */ 275 t1394_isoch_dma_handle_t ic_isoch_hdl; /* 1394 isoch handle */ 276 kcondvar_t ic_xfer_cv; /* xfer cv */ 277 int ic_preq; /* postponed request */ 278 av1394_ir_t ic_ir; /* recv */ 279 av1394_it_t ic_it; /* xmit */ 280 } av1394_ic_t; 281 282 _NOTE(MUTEX_PROTECTS_DATA(av1394_ic_s::ic_mutex, av1394_ic_s)) 283 _NOTE(SCHEME_PROTECTS_DATA("single-threaded", av1394_ic_s::{ 284 ic_avp 285 ic_num 286 ic_dir 287 ic_sii_hdl 288 ic_isoch_hdl 289 ic_pktsz 290 ic_npkts 291 ic_framesz 292 ic_nframes 293 ic_param 294 ic_mmap_sz 295 ic_mmap_off 296 })) 297 298 /* xfer directions */ 299 enum { 300 AV1394_IR, 301 AV1394_IT 302 }; 303 304 /* CIP type */ 305 enum { 306 AV1394_CIP_FULL, 307 AV1394_CIP_EMPTY 308 }; 309 310 /* misc constants */ 311 enum { 312 AV1394_IC_FRAME_SIZE_MAX = 1024 * 1024, /* max frame size */ 313 AV1394_MEM_MAX_PERCENT = (100/10), /* max percent of physmem */ 314 AV1394_SEGSZ_MAX_SHIFT = 16, /* maximum segment size */ 315 AV1394_SEGSZ_MAX = (1UL << AV1394_SEGSZ_MAX_SHIFT), 316 AV1394_SEGSZ_MAX_OFFSET = AV1394_SEGSZ_MAX - 1, 317 AV1394_IXL_BUFSZ_MAX = 57344, /* max buf size (uint16_t) */ 318 /* 57344 is ptob(btop(65535)) */ 319 AV1394_IR_NFRAMES_MIN = 3, /* minimum frame count */ 320 AV1394_IT_NFRAMES_MIN = 3, /* minimum frame count */ 321 AV1394_CIPSZ = 8, /* CIP header size */ 322 AV1394_DV_NTSC_FRAMESZ = 250, /* DV-NTSC frame size in pkts */ 323 AV1394_DV_PAL_FRAMESZ = 300 /* DV-PAL frame size in pkts */ 324 }; 325 326 #define AV1394_TS_MODE_GET_OFF(mode) ((mode) & 0xff) 327 #define AV1394_TS_MODE_GET_SIZE(mode) (((mode) >> 8) & 0xff) 328 329 /* private ISOCH_INIT flag */ 330 #define IEC61883_PRIV_ISOCH_NOALLOC 0x40000000 331 332 /* 333 * autoxmit (isoch xmit via write(2)) support 334 */ 335 typedef struct av1394_isoch_autoxmit_s { 336 uchar_t ax_ciph[AV1394_CIPSZ]; /* first CIP hdr */ 337 boolean_t ax_copy_ciph; /* need to copy hdr */ 338 int ax_fmt; /* data format */ 339 } av1394_isoch_autoxmit_t; 340 341 /* autoxmit formats */ 342 enum { 343 AV1394_ISOCH_AUTOXMIT_DV = 0x10, 344 AV1394_ISOCH_AUTOXMIT_UNKNOWN = 0, 345 AV1394_ISOCH_AUTOXMIT_DV_NTSC = 1 | AV1394_ISOCH_AUTOXMIT_DV, 346 AV1394_ISOCH_AUTOXMIT_DV_PAL = 2 | AV1394_ISOCH_AUTOXMIT_DV 347 }; 348 349 350 /* 351 * User processes calling mmap(2) pass the 'offset' and 'len' arguments, 352 * returned by IEC61883_ISOCH_INIT ioctl. These arguments uniquely identify 353 * the DMA buffer associated with a channel. For each isochronous channel 354 * a part of this "address space" should be allocated to prevent conflicts 355 * with other channels. 356 */ 357 typedef struct av1394_as_s { 358 off_t as_end; /* address space end */ 359 } av1394_as_t; 360 361 362 /* 363 * CMP (Connection Management Procedures) 364 * 365 * PCR address map (Ref: IEC 61883-1 Fig 14) 366 */ 367 #define AV1394_PCR_ADDR_START 0xFFFFF0000900 368 #define AV1394_PCR_ADDR_OMPR 0xFFFFF0000900 369 #define AV1394_PCR_ADDR_OPCR0 0xFFFFF0000904 370 #define AV1394_PCR_ADDR_NOPCR 31 371 #define AV1394_PCR_ADDR_IMPR 0xFFFFF0000980 372 #define AV1394_PCR_ADDR_IPCR0 0xFFFFF0000984 373 #define AV1394_PCR_ADDR_NIPCR 31 374 375 /* initial values and bus reset masks (Ref: IEC 61883-1 Fig 10-13) */ 376 #define AV1394_OMPR_INIT_VAL 0xBFFFFF00 377 #define AV1394_IMPR_INIT_VAL 0x80FFFF00 378 #define AV1394_PCR_INIT_VAL 0x00000000 /* both iPCR and oPCR */ 379 #define AV1394_OPCR_BR_CLEAR_MASK 0x7FC03C00 380 #define AV1394_IPCR_BR_CLEAR_MASK 0x7FC0FFFF 381 382 /* 383 * local plug control register 384 */ 385 typedef struct av1394_pcr_s { 386 uint32_t pcr_val; /* value */ 387 t1394_addr_handle_t pcr_addr_hdl; /* address handle */ 388 } av1394_pcr_t; 389 390 enum { 391 AV1394_OMPR_IDX = 0, /* oMPR index */ 392 AV1394_OPCR0_IDX = 1, /* oPCR0 index */ 393 AV1394_IMPR_IDX = 32, /* iMPR index */ 394 AV1394_IPCR0_IDX = 33, /* iPCR0 index */ 395 AV1394_NPCR = 64 /* total number of PCRs */ 396 }; 397 398 /* plug handle manipulation */ 399 enum { 400 AV1394_PCR_REMOTE = 0x40000000 401 }; 402 403 /* 404 * per-instance CMP structure 405 */ 406 typedef struct av1394_cmp_s { 407 krwlock_t cmp_pcr_rwlock; /* rwlock for PCRs */ 408 av1394_pcr_t *cmp_pcr[AV1394_NPCR]; /* array of PCRs */ 409 } av1394_cmp_t; 410 411 _NOTE(SCHEME_PROTECTS_DATA("cmp_pcr_rwlock", av1394_cmp_s::cmp_pcr)) 412 413 414 /* 415 * per-instance soft state structure 416 */ 417 typedef struct av1394_isoch_s { 418 kmutex_t i_mutex; /* structure mutex */ 419 int i_nopen; /* number of opens */ 420 av1394_cmp_t i_cmp; /* CMP information */ 421 av1394_ic_t *i_ic[64]; /* array of channels */ 422 av1394_as_t i_mmap_as; /* mmap virtual addr space */ 423 ddi_softintr_t i_softintr_id; /* soft interrupt id */ 424 uint64_t i_softintr_ch; /* channels to service */ 425 av1394_isoch_autoxmit_t i_autoxmit; /* autoxmit support */ 426 } av1394_isoch_t; 427 428 _NOTE(MUTEX_PROTECTS_DATA(av1394_isoch_s::i_mutex, av1394_isoch_s)) 429 _NOTE(DATA_READABLE_WITHOUT_LOCK(av1394_isoch_s::{ 430 i_ic 431 i_softintr_id 432 })) 433 _NOTE(SCHEME_PROTECTS_DATA("single-threaded", av1394_isoch_autoxmit_s)) 434 435 _NOTE(LOCK_ORDER(av1394_isoch_s::i_mutex av1394_ic_s::ic_mutex)) 436 437 /* postponed request types */ 438 enum { 439 AV1394_PREQ_IR_OVERFLOW = 0x01, 440 AV1394_PREQ_IT_UNDERRUN = 0x02 441 }; 442 443 444 /* TNF probes */ 445 #define AV1394_TNF_CMP "1394 av1394 cmp " 446 #define AV1394_TNF_CMP_STACK "1394 av1394 cmp stacktrace " 447 #define AV1394_TNF_CMP_ERROR "1394 av1394 cmp error " 448 #define AV1394_TNF_ISOCH "1394 av1394 isoch " 449 #define AV1394_TNF_ISOCH_STACK "1394 av1394 isoch stacktrace " 450 #define AV1394_TNF_ISOCH_ERROR "1394 av1394 isoch error " 451 452 453 /* isoch channel */ 454 int av1394_ic_open(struct av1394_inst_s *, int); 455 int av1394_ic_close(struct av1394_inst_s *, int); 456 int av1394_ic_init(struct av1394_inst_s *avp, iec61883_isoch_init_t *ii, 457 av1394_ic_t **icpp); 458 void av1394_ic_fini(av1394_ic_t *icp); 459 int av1394_ic_alloc_pool(av1394_isoch_pool_t *pool, size_t segsz, int cnt, 460 int mincnt); 461 void av1394_ic_free_pool(av1394_isoch_pool_t *pool); 462 int av1394_ic_dma_setup(av1394_ic_t *icp, av1394_isoch_pool_t *pool); 463 void av1394_ic_dma_cleanup(av1394_ic_t *icp, av1394_isoch_pool_t *pool); 464 int av1394_ic_ixl_seg_decomp(size_t segsz, size_t pktsz, size_t *bufszp, 465 size_t *tailszp); 466 void av1394_ic_dma_sync_frames(av1394_ic_t *icp, int idx, int cnt, 467 av1394_isoch_pool_t *pool, uint_t type); 468 int av1394_ic_start(av1394_ic_t *icp); 469 int av1394_ic_stop(av1394_ic_t *icp); 470 void av1394_ic_ixl_dump(ixl1394_command_t *cmd); 471 void av1394_ic_trigger_softintr(av1394_ic_t *icp, int num, int preq); 472 473 /* isoch receive */ 474 int av1394_ir_init(av1394_ic_t *icp, int *error); 475 void av1394_ir_fini(av1394_ic_t *icp); 476 int av1394_ir_start(av1394_ic_t *icp); 477 int av1394_ir_stop(av1394_ic_t *icp); 478 int av1394_ir_recv(av1394_ic_t *icp, iec61883_recv_t *recv); 479 int av1394_ir_read(av1394_ic_t *icp, struct uio *uiop); 480 void av1394_ir_overflow(av1394_ic_t *icp); 481 482 /* isoch transmit */ 483 int av1394_it_init(av1394_ic_t *icp, int *error); 484 void av1394_it_fini(av1394_ic_t *icp); 485 int av1394_it_start(av1394_ic_t *icp); 486 int av1394_it_stop(av1394_ic_t *icp); 487 int av1394_it_xmit(av1394_ic_t *icp, iec61883_xmit_t *xmit); 488 int av1394_it_write(av1394_ic_t *icp, struct uio *uiop); 489 void av1394_it_underrun(av1394_ic_t *icp); 490 491 /* address space for mmap(2) */ 492 void av1394_as_init(av1394_as_t *as); 493 void av1394_as_fini(av1394_as_t *as); 494 off_t av1394_as_alloc(av1394_as_t *as, size_t size); 495 void av1394_as_free(av1394_as_t *as, off_t); 496 497 /* CMP */ 498 int av1394_cmp_init(struct av1394_inst_s *avp); 499 void av1394_cmp_fini(struct av1394_inst_s *avp); 500 void av1394_cmp_bus_reset(struct av1394_inst_s *avp); 501 void av1394_cmp_close(struct av1394_inst_s *avp); 502 int av1394_ioctl_plug_init(struct av1394_inst_s *, void *, int); 503 int av1394_ioctl_plug_fini(struct av1394_inst_s *, void *, int); 504 int av1394_ioctl_plug_reg_read(struct av1394_inst_s *, void *, int); 505 int av1394_ioctl_plug_reg_cas(struct av1394_inst_s *, void *, int); 506 507 /* isoch common */ 508 int av1394_isoch_attach(struct av1394_inst_s *); 509 void av1394_isoch_detach(struct av1394_inst_s *); 510 int av1394_isoch_cpr_suspend(struct av1394_inst_s *); 511 int av1394_isoch_cpr_resume(struct av1394_inst_s *); 512 void av1394_isoch_bus_reset(struct av1394_inst_s *); 513 void av1394_isoch_disconnect(struct av1394_inst_s *); 514 void av1394_isoch_reconnect(struct av1394_inst_s *); 515 int av1394_isoch_open(struct av1394_inst_s *, int); 516 int av1394_isoch_close(struct av1394_inst_s *, int); 517 int av1394_isoch_read(struct av1394_inst_s *, struct uio *); 518 int av1394_isoch_write(struct av1394_inst_s *, struct uio *); 519 int av1394_isoch_ioctl(struct av1394_inst_s *, int, intptr_t, int, int *); 520 int av1394_isoch_devmap(struct av1394_inst_s *, devmap_cookie_t, offset_t, 521 size_t, size_t *, uint_t); 522 523 #ifdef __cplusplus 524 } 525 #endif 526 527 #endif /* _SYS_1394_TARGETS_AV1394_ISOCH_H */ 528