1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24*7c478bd9Sstevel@tonic-gate * All rights reserved. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #ifndef _SYS_1394_ADAPTERS_HCI1394_CSR_H 28*7c478bd9Sstevel@tonic-gate #define _SYS_1394_ADAPTERS_HCI1394_CSR_H 29*7c478bd9Sstevel@tonic-gate 30*7c478bd9Sstevel@tonic-gate /* 31*7c478bd9Sstevel@tonic-gate * hci1394_csr.h 32*7c478bd9Sstevel@tonic-gate * This file contains the code for the CSR registers handled by the HAL in 33*7c478bd9Sstevel@tonic-gate * SW. The HW implemented CSR registers are in hci1394_ohci.c 34*7c478bd9Sstevel@tonic-gate * 35*7c478bd9Sstevel@tonic-gate * For more information on CSR registers, see 36*7c478bd9Sstevel@tonic-gate * IEEE 1212 37*7c478bd9Sstevel@tonic-gate * IEEE 1394-1995 38*7c478bd9Sstevel@tonic-gate * section 8.3.2 39*7c478bd9Sstevel@tonic-gate * IEEE P1394A Draft 3.0 40*7c478bd9Sstevel@tonic-gate * sections 10.32,10.33 41*7c478bd9Sstevel@tonic-gate * 42*7c478bd9Sstevel@tonic-gate * NOTE: A read/write to a CSR SW based register will first go to the Services 43*7c478bd9Sstevel@tonic-gate * Layer which will do some filtering and then come through the s1394if. 44*7c478bd9Sstevel@tonic-gate */ 45*7c478bd9Sstevel@tonic-gate 46*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 47*7c478bd9Sstevel@tonic-gate extern "C" { 48*7c478bd9Sstevel@tonic-gate #endif 49*7c478bd9Sstevel@tonic-gate 50*7c478bd9Sstevel@tonic-gate #include <sys/ddi.h> 51*7c478bd9Sstevel@tonic-gate #include <sys/modctl.h> 52*7c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 53*7c478bd9Sstevel@tonic-gate 54*7c478bd9Sstevel@tonic-gate #include <sys/1394/adapters/hci1394_def.h> 55*7c478bd9Sstevel@tonic-gate 56*7c478bd9Sstevel@tonic-gate 57*7c478bd9Sstevel@tonic-gate /* 58*7c478bd9Sstevel@tonic-gate * The 1394 bus sends out cycle start packets periodically. The time in 59*7c478bd9Sstevel@tonic-gate * between these packets is commonly referred to as a bus cycle. The 1394 60*7c478bd9Sstevel@tonic-gate * cycle start packets come every 125uS. split_timeout is represented in 1394 61*7c478bd9Sstevel@tonic-gate * bus cycles (e.g. to have ATREQ ACK_PENDED timeout after 100mS, you would set 62*7c478bd9Sstevel@tonic-gate * split_timeout to 800). 63*7c478bd9Sstevel@tonic-gate * 64*7c478bd9Sstevel@tonic-gate * The CSR register interface has the split timeout broken into two registers, 65*7c478bd9Sstevel@tonic-gate * split_timeout_hi and split_timeout_lo. The least significant 3 bits of 66*7c478bd9Sstevel@tonic-gate * split_timeout_hi contain the # of seconds and the most significant 13 bits 67*7c478bd9Sstevel@tonic-gate * of split_timeout_lo contain the fraction of a seconds in 125uS increments. 68*7c478bd9Sstevel@tonic-gate * There is a further constraint that the value in split_timeout_lo must be >= 69*7c478bd9Sstevel@tonic-gate * 800 && <= 7999 (>=100mS && < 1S). (don't forget that this value is in the 70*7c478bd9Sstevel@tonic-gate * most significant 13 bits, i.e. 800 << 19) We will threshold the writes into 71*7c478bd9Sstevel@tonic-gate * these registers to make sure they always have legal values (i.e. if 72*7c478bd9Sstevel@tonic-gate * [8000 << 19] is written to split_timeout_lo, we will write [7999 << 19]. 73*7c478bd9Sstevel@tonic-gate * 74*7c478bd9Sstevel@tonic-gate * The split timeout CSR registers have some inherent problems. There is a race 75*7c478bd9Sstevel@tonic-gate * condition when updating the split timeout value since you cannot atomically 76*7c478bd9Sstevel@tonic-gate * write to both the hi and lo registers. This should not be a serious problem 77*7c478bd9Sstevel@tonic-gate * since we should never get close to having a split timeout of 1S or greater. 78*7c478bd9Sstevel@tonic-gate */ 79*7c478bd9Sstevel@tonic-gate 80*7c478bd9Sstevel@tonic-gate 81*7c478bd9Sstevel@tonic-gate /* CSR Register Address Offsets (1394-1995 8.3.2.2) */ 82*7c478bd9Sstevel@tonic-gate #define CSR_STATE_CLEAR 0x000 83*7c478bd9Sstevel@tonic-gate #define CSR_STATE_SET 0x004 84*7c478bd9Sstevel@tonic-gate #define CSR_NODE_IDS 0x008 85*7c478bd9Sstevel@tonic-gate #define CSR_RESET_START 0x00C 86*7c478bd9Sstevel@tonic-gate #define CSR_SPLIT_TIMEOUT_HI 0x018 87*7c478bd9Sstevel@tonic-gate #define CSR_SPLIT_TIMEOUT_LO 0x01C 88*7c478bd9Sstevel@tonic-gate #define CSR_CYCLE_TIME 0x200 89*7c478bd9Sstevel@tonic-gate #define CSR_BUS_TIME 0x204 90*7c478bd9Sstevel@tonic-gate #define CSR_BUSY_TIMEOUT 0x210 91*7c478bd9Sstevel@tonic-gate #define CSR_BUS_MANAGER_ID 0x21C 92*7c478bd9Sstevel@tonic-gate #define CSR_BANDWIDTH_AVAILABLE 0x220 93*7c478bd9Sstevel@tonic-gate #define CSR_CHANNELS_AVAILABLE_HI 0x224 94*7c478bd9Sstevel@tonic-gate #define CSR_CHANNELS_AVAILABLE_LO 0x228 95*7c478bd9Sstevel@tonic-gate 96*7c478bd9Sstevel@tonic-gate 97*7c478bd9Sstevel@tonic-gate typedef struct hci1394_csr_s { 98*7c478bd9Sstevel@tonic-gate /* SW registers */ 99*7c478bd9Sstevel@tonic-gate uint32_t csr_state; 100*7c478bd9Sstevel@tonic-gate uint32_t csr_split_timeout_lo; 101*7c478bd9Sstevel@tonic-gate uint32_t csr_split_timeout_hi; 102*7c478bd9Sstevel@tonic-gate 103*7c478bd9Sstevel@tonic-gate /* split timeout that we are observing */ 104*7c478bd9Sstevel@tonic-gate uint_t csr_split_timeout; 105*7c478bd9Sstevel@tonic-gate 106*7c478bd9Sstevel@tonic-gate /* were we root last bus reset */ 107*7c478bd9Sstevel@tonic-gate boolean_t csr_was_root; 108*7c478bd9Sstevel@tonic-gate 109*7c478bd9Sstevel@tonic-gate /* our node capabilities */ 110*7c478bd9Sstevel@tonic-gate uint32_t csr_capabilities; 111*7c478bd9Sstevel@tonic-gate 112*7c478bd9Sstevel@tonic-gate /* copies of OpenHCI handle and pointer to general driver info */ 113*7c478bd9Sstevel@tonic-gate hci1394_ohci_handle_t csr_ohci; 114*7c478bd9Sstevel@tonic-gate hci1394_drvinfo_t *csr_drvinfo; 115*7c478bd9Sstevel@tonic-gate 116*7c478bd9Sstevel@tonic-gate kmutex_t csr_mutex; 117*7c478bd9Sstevel@tonic-gate } hci1394_csr_t; 118*7c478bd9Sstevel@tonic-gate 119*7c478bd9Sstevel@tonic-gate /* handle passed back from init() and used for rest of functions */ 120*7c478bd9Sstevel@tonic-gate typedef struct hci1394_csr_s *hci1394_csr_handle_t; 121*7c478bd9Sstevel@tonic-gate 122*7c478bd9Sstevel@tonic-gate 123*7c478bd9Sstevel@tonic-gate void hci1394_csr_init(hci1394_drvinfo_t *drvinfo, hci1394_ohci_handle_t ohci, 124*7c478bd9Sstevel@tonic-gate hci1394_csr_handle_t *csr_handle); 125*7c478bd9Sstevel@tonic-gate void hci1394_csr_fini(hci1394_csr_handle_t *csr_handle); 126*7c478bd9Sstevel@tonic-gate void hci1394_csr_resume(hci1394_csr_handle_t csr_handle); 127*7c478bd9Sstevel@tonic-gate 128*7c478bd9Sstevel@tonic-gate void hci1394_csr_node_capabilities(hci1394_csr_handle_t csr_handle, 129*7c478bd9Sstevel@tonic-gate uint32_t *capabilities); 130*7c478bd9Sstevel@tonic-gate 131*7c478bd9Sstevel@tonic-gate void hci1394_csr_state_get(hci1394_csr_handle_t csr_handle, uint32_t *state); 132*7c478bd9Sstevel@tonic-gate void hci1394_csr_state_bset(hci1394_csr_handle_t csr_handle, uint32_t state); 133*7c478bd9Sstevel@tonic-gate void hci1394_csr_state_bclr(hci1394_csr_handle_t csr_handle, uint32_t state); 134*7c478bd9Sstevel@tonic-gate 135*7c478bd9Sstevel@tonic-gate void hci1394_csr_split_timeout_hi_get(hci1394_csr_handle_t csr_handle, 136*7c478bd9Sstevel@tonic-gate uint32_t *split_timeout_hi); 137*7c478bd9Sstevel@tonic-gate void hci1394_csr_split_timeout_lo_get(hci1394_csr_handle_t csr_handle, 138*7c478bd9Sstevel@tonic-gate uint32_t *split_timeout_lo); 139*7c478bd9Sstevel@tonic-gate void hci1394_csr_split_timeout_hi_set(hci1394_csr_handle_t csr_handle, 140*7c478bd9Sstevel@tonic-gate uint32_t split_timeout_hi); 141*7c478bd9Sstevel@tonic-gate void hci1394_csr_split_timeout_lo_set(hci1394_csr_handle_t csr_handle, 142*7c478bd9Sstevel@tonic-gate uint32_t split_timeout_lo); 143*7c478bd9Sstevel@tonic-gate uint_t hci1394_csr_split_timeout_get(hci1394_csr_handle_t csr_handle); 144*7c478bd9Sstevel@tonic-gate 145*7c478bd9Sstevel@tonic-gate void hci1394_csr_bus_reset(hci1394_csr_handle_t csr_handle); 146*7c478bd9Sstevel@tonic-gate 147*7c478bd9Sstevel@tonic-gate 148*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 149*7c478bd9Sstevel@tonic-gate } 150*7c478bd9Sstevel@tonic-gate #endif 151*7c478bd9Sstevel@tonic-gate 152*7c478bd9Sstevel@tonic-gate #endif /* _SYS_1394_ADAPTERS_HCI1394_CSR_H */ 153