xref: /illumos-gate/usr/src/uts/common/os/sunpci.c (revision d083fed0)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
54ab75253Smrj  * Common Development and Distribution License (the "License").
64ab75253Smrj  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
226f6c7d2bSVincent Wang  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
237c478bd9Sstevel@tonic-gate  */
247c478bd9Sstevel@tonic-gate 
257c478bd9Sstevel@tonic-gate #include <sys/types.h>
267c478bd9Sstevel@tonic-gate #include <sys/sunndi.h>
2700d0963fSdilpreet #include <sys/sysmacros.h>
287c478bd9Sstevel@tonic-gate #include <sys/pci.h>
299164eb65Stimh #include <sys/pcie.h>
307c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h>
317c478bd9Sstevel@tonic-gate #include <sys/epm.h>
327c478bd9Sstevel@tonic-gate 
336f6c7d2bSVincent Wang int	pci_enable_wakeup = 1;
346f6c7d2bSVincent Wang 
357c478bd9Sstevel@tonic-gate int
pci_config_setup(dev_info_t * dip,ddi_acc_handle_t * handle)367c478bd9Sstevel@tonic-gate pci_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle)
377c478bd9Sstevel@tonic-gate {
387c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
397c478bd9Sstevel@tonic-gate 	ddi_device_acc_attr_t attr;
407c478bd9Sstevel@tonic-gate 
417c478bd9Sstevel@tonic-gate 	attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
427c478bd9Sstevel@tonic-gate 	attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
437c478bd9Sstevel@tonic-gate 	attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
447c478bd9Sstevel@tonic-gate 
457c478bd9Sstevel@tonic-gate 	/* Check for fault management capabilities */
4600d0963fSdilpreet 	if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(dip))) {
4700d0963fSdilpreet 		attr.devacc_attr_version = DDI_DEVICE_ATTR_V1;
487c478bd9Sstevel@tonic-gate 		attr.devacc_attr_access = DDI_FLAGERR_ACC;
4900d0963fSdilpreet 	}
507c478bd9Sstevel@tonic-gate 
517c478bd9Sstevel@tonic-gate 	return (ddi_regs_map_setup(dip, 0, &cfgaddr, 0, 0, &attr, handle));
527c478bd9Sstevel@tonic-gate }
537c478bd9Sstevel@tonic-gate 
547c478bd9Sstevel@tonic-gate void
pci_config_teardown(ddi_acc_handle_t * handle)557c478bd9Sstevel@tonic-gate pci_config_teardown(ddi_acc_handle_t *handle)
567c478bd9Sstevel@tonic-gate {
577c478bd9Sstevel@tonic-gate 	ddi_regs_map_free(handle);
587c478bd9Sstevel@tonic-gate }
597c478bd9Sstevel@tonic-gate 
607c478bd9Sstevel@tonic-gate uint8_t
pci_config_get8(ddi_acc_handle_t handle,off_t offset)617c478bd9Sstevel@tonic-gate pci_config_get8(ddi_acc_handle_t handle, off_t offset)
627c478bd9Sstevel@tonic-gate {
637c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
647c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
657c478bd9Sstevel@tonic-gate 
667c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
677c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
687c478bd9Sstevel@tonic-gate 	return (ddi_get8(handle, (uint8_t *)cfgaddr));
697c478bd9Sstevel@tonic-gate }
707c478bd9Sstevel@tonic-gate 
717c478bd9Sstevel@tonic-gate uint16_t
pci_config_get16(ddi_acc_handle_t handle,off_t offset)727c478bd9Sstevel@tonic-gate pci_config_get16(ddi_acc_handle_t handle, off_t offset)
737c478bd9Sstevel@tonic-gate {
747c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
757c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
767c478bd9Sstevel@tonic-gate 
777c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
787c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
797c478bd9Sstevel@tonic-gate 	return (ddi_get16(handle, (uint16_t *)cfgaddr));
807c478bd9Sstevel@tonic-gate }
817c478bd9Sstevel@tonic-gate 
827c478bd9Sstevel@tonic-gate uint32_t
pci_config_get32(ddi_acc_handle_t handle,off_t offset)837c478bd9Sstevel@tonic-gate pci_config_get32(ddi_acc_handle_t handle, off_t offset)
847c478bd9Sstevel@tonic-gate {
857c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
867c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
877c478bd9Sstevel@tonic-gate 
887c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
897c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
907c478bd9Sstevel@tonic-gate 	return (ddi_get32(handle, (uint32_t *)cfgaddr));
917c478bd9Sstevel@tonic-gate }
927c478bd9Sstevel@tonic-gate 
937c478bd9Sstevel@tonic-gate uint64_t
pci_config_get64(ddi_acc_handle_t handle,off_t offset)947c478bd9Sstevel@tonic-gate pci_config_get64(ddi_acc_handle_t handle, off_t offset)
957c478bd9Sstevel@tonic-gate {
967c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
977c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
987c478bd9Sstevel@tonic-gate 
997c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
1007c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
1017c478bd9Sstevel@tonic-gate 	return (ddi_get64(handle, (uint64_t *)cfgaddr));
1027c478bd9Sstevel@tonic-gate }
1037c478bd9Sstevel@tonic-gate 
1047c478bd9Sstevel@tonic-gate void
pci_config_put8(ddi_acc_handle_t handle,off_t offset,uint8_t value)1057c478bd9Sstevel@tonic-gate pci_config_put8(ddi_acc_handle_t handle, off_t offset, uint8_t value)
1067c478bd9Sstevel@tonic-gate {
1077c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
1087c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
1097c478bd9Sstevel@tonic-gate 
1107c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
1117c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
1127c478bd9Sstevel@tonic-gate 	ddi_put8(handle, (uint8_t *)cfgaddr, value);
1137c478bd9Sstevel@tonic-gate }
1147c478bd9Sstevel@tonic-gate 
1157c478bd9Sstevel@tonic-gate void
pci_config_put16(ddi_acc_handle_t handle,off_t offset,uint16_t value)1167c478bd9Sstevel@tonic-gate pci_config_put16(ddi_acc_handle_t handle, off_t offset, uint16_t value)
1177c478bd9Sstevel@tonic-gate {
1187c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
1197c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
1207c478bd9Sstevel@tonic-gate 
1217c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
1227c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
1237c478bd9Sstevel@tonic-gate 	ddi_put16(handle, (uint16_t *)cfgaddr, value);
1247c478bd9Sstevel@tonic-gate }
1257c478bd9Sstevel@tonic-gate 
1267c478bd9Sstevel@tonic-gate void
pci_config_put32(ddi_acc_handle_t handle,off_t offset,uint32_t value)1277c478bd9Sstevel@tonic-gate pci_config_put32(ddi_acc_handle_t handle, off_t offset, uint32_t value)
1287c478bd9Sstevel@tonic-gate {
1297c478bd9Sstevel@tonic-gate 	caddr_t	cfgaddr;
1307c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
1317c478bd9Sstevel@tonic-gate 
1327c478bd9Sstevel@tonic-gate 	hp = impl_acc_hdl_get(handle);
1337c478bd9Sstevel@tonic-gate 	cfgaddr = hp->ah_addr + offset;
1347c478bd9Sstevel@tonic-gate 	ddi_put32(handle, (uint32_t *)cfgaddr, value);
1357c478bd9Sstevel@tonic-gate }
1367c478bd9Sstevel@tonic-gate 
1377c478bd9Sstevel@tonic-gate void
pci_config_put64(ddi_acc_handle_t handle,off_t offset,uint64_t value)1387c478bd9Sstevel@tonic-gate pci_config_put64(ddi_acc_handle_t handle, off_t offset, uint64_t value)
1394ab75253Smrj {
1404ab75253Smrj 	caddr_t	cfgaddr;
1414ab75253Smrj 	ddi_acc_hdl_t *hp;
1424ab75253Smrj 
1434ab75253Smrj 	hp = impl_acc_hdl_get(handle);
1444ab75253Smrj 	cfgaddr = hp->ah_addr + offset;
1454ab75253Smrj 	ddi_put64(handle, (uint64_t *)cfgaddr, value);
1464ab75253Smrj }
1474ab75253Smrj 
1487c478bd9Sstevel@tonic-gate /*ARGSUSED*/
1497c478bd9Sstevel@tonic-gate int
pci_report_pmcap(dev_info_t * dip,int cap,void * arg)1507c478bd9Sstevel@tonic-gate pci_report_pmcap(dev_info_t *dip, int cap, void *arg)
1517c478bd9Sstevel@tonic-gate {
1527c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
1537c478bd9Sstevel@tonic-gate }
1547c478bd9Sstevel@tonic-gate 
1557c478bd9Sstevel@tonic-gate /*
1567c478bd9Sstevel@tonic-gate  * Note about saving and restoring config space.
1577c478bd9Sstevel@tonic-gate  * PCI devices have only upto 256 bytes of config space while PCI Express
1587c478bd9Sstevel@tonic-gate  * devices can have upto 4k config space. In case of PCI Express device,
1597c478bd9Sstevel@tonic-gate  * we save all 4k config space and restore it even if it doesn't make use
1607c478bd9Sstevel@tonic-gate  * of all 4k. But some devices don't respond to reads to non-existent
1617c478bd9Sstevel@tonic-gate  * registers within the config space. To avoid any panics, we use ddi_peek
1627c478bd9Sstevel@tonic-gate  * to do the reads. A bit mask is used to indicate which words of the
1637c478bd9Sstevel@tonic-gate  * config space are accessible. While restoring the config space, only those
1647c478bd9Sstevel@tonic-gate  * readable words are restored. We do all this in 32 bit size words.
1657c478bd9Sstevel@tonic-gate  */
1667c478bd9Sstevel@tonic-gate #define	INDEX_SHIFT		3
1677c478bd9Sstevel@tonic-gate #define	BITMASK			0x7
1687c478bd9Sstevel@tonic-gate 
1697c478bd9Sstevel@tonic-gate static uint32_t pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf,
1707c478bd9Sstevel@tonic-gate     pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp);
1717c478bd9Sstevel@tonic-gate static void pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf,
1727c478bd9Sstevel@tonic-gate     pci_cap_save_desc_t *cap_descp, uint32_t elements);
1737c478bd9Sstevel@tonic-gate static uint32_t pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
1747c478bd9Sstevel@tonic-gate     uint32_t *regbuf, uint32_t nwords);
1757c478bd9Sstevel@tonic-gate static uint32_t pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
1767c478bd9Sstevel@tonic-gate     uint32_t *regbuf, uint32_t notused);
1777c478bd9Sstevel@tonic-gate static uint32_t pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
1787c478bd9Sstevel@tonic-gate     uint32_t *regbuf, uint32_t notused);
1797c478bd9Sstevel@tonic-gate static uint32_t pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
1807c478bd9Sstevel@tonic-gate     uint32_t *regbuf, uint32_t notused);
181cb7ea99dSJimmy Vetayases static uint32_t pci_ht_addrmap_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
182cb7ea99dSJimmy Vetayases     uint32_t *regbuf, uint32_t notused);
183cb7ea99dSJimmy Vetayases static uint32_t pci_ht_funcext_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
184cb7ea99dSJimmy Vetayases     uint32_t *regbuf, uint32_t notused);
1857c478bd9Sstevel@tonic-gate static void pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
1867c478bd9Sstevel@tonic-gate     uint32_t *regbuf, uint32_t nwords);
1877c478bd9Sstevel@tonic-gate static uint32_t cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf,
1887c478bd9Sstevel@tonic-gate     pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace);
1897c478bd9Sstevel@tonic-gate static void pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf,
1907c478bd9Sstevel@tonic-gate     uint16_t pmcap_offset);
1917c478bd9Sstevel@tonic-gate 
1927c478bd9Sstevel@tonic-gate /*
1937c478bd9Sstevel@tonic-gate  * Table below specifies the number of registers to be saved for each PCI
1947c478bd9Sstevel@tonic-gate  * capability. pci_generic_save saves the number of words specified in the
1957c478bd9Sstevel@tonic-gate  * table. Any special considerations will be taken care by the capability
1967c478bd9Sstevel@tonic-gate  * specific save function e.g. use pci_msi_save to save registers associated
1977c478bd9Sstevel@tonic-gate  * with MSI capability. PCI_UNKNOWN_SIZE indicates that number of registers
1987c478bd9Sstevel@tonic-gate  * to be saved is variable and will be determined by the specific save function.
1997c478bd9Sstevel@tonic-gate  * Currently we save/restore all the registers associated with the capability
2007c478bd9Sstevel@tonic-gate  * including read only registers. Regsiters are saved and restored in 32 bit
2017c478bd9Sstevel@tonic-gate  * size words.
2027c478bd9Sstevel@tonic-gate  */
2037c478bd9Sstevel@tonic-gate static pci_cap_entry_t pci_cap_table[] = {
204cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_PM, 0, 0, PCI_PMCAP_NDWORDS, pci_generic_save},
205cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_AGP, 0, 0, PCI_AGP_NDWORDS, pci_generic_save},
206cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_SLOT_ID, 0, 0, PCI_SLOTID_NDWORDS, pci_generic_save},
207cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_MSI_X, 0, 0, PCI_MSIX_NDWORDS, pci_generic_save},
208cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_MSI, 0, 0, PCI_CAP_SZUNKNOWN, pci_msi_save},
209cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_PCIX, 0, 0, PCI_CAP_SZUNKNOWN, pci_pcix_save},
210cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_PCI_E, 0, 0, PCI_CAP_SZUNKNOWN, pci_pcie_save},
211cb7ea99dSJimmy Vetayases 
212cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_SLPRI_TYPE, PCI_HTCAP_TYPE_SLHOST_MASK,
213cb7ea99dSJimmy Vetayases 		PCI_HTCAP_SLPRI_NDWORDS, pci_generic_save},
214cb7ea99dSJimmy Vetayases 
215cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_HOSTSEC_TYPE, PCI_HTCAP_TYPE_SLHOST_MASK,
216cb7ea99dSJimmy Vetayases 		PCI_HTCAP_HOSTSEC_NDWORDS, pci_generic_save},
217cb7ea99dSJimmy Vetayases 
218cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_INTCONF_TYPE, PCI_HTCAP_TYPE_MASK,
219cb7ea99dSJimmy Vetayases 		PCI_HTCAP_INTCONF_NDWORDS, pci_generic_save},
220cb7ea99dSJimmy Vetayases 
221cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_REVID_TYPE, PCI_HTCAP_TYPE_MASK,
222cb7ea99dSJimmy Vetayases 		PCI_HTCAP_REVID_NDWORDS, pci_generic_save},
223cb7ea99dSJimmy Vetayases 
224cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_UNITID_CLUMP_TYPE, PCI_HTCAP_TYPE_MASK,
225cb7ea99dSJimmy Vetayases 		PCI_HTCAP_UNITID_CLUMP_NDWORDS, pci_generic_save},
226cb7ea99dSJimmy Vetayases 
227cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_ECFG_TYPE, PCI_HTCAP_TYPE_MASK,
228cb7ea99dSJimmy Vetayases 		PCI_HTCAP_ECFG_NDWORDS, pci_generic_save},
229cb7ea99dSJimmy Vetayases 
230cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_ADDRMAP_TYPE, PCI_HTCAP_TYPE_MASK,
231cb7ea99dSJimmy Vetayases 		PCI_CAP_SZUNKNOWN, pci_ht_addrmap_save},
232cb7ea99dSJimmy Vetayases 
233cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_MSIMAP_TYPE, PCI_HTCAP_TYPE_MASK,
234cb7ea99dSJimmy Vetayases 		PCI_HTCAP_MSIMAP_NDWORDS, pci_generic_save},
235cb7ea99dSJimmy Vetayases 
236cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_DIRROUTE_TYPE, PCI_HTCAP_TYPE_MASK,
237cb7ea99dSJimmy Vetayases 		PCI_HTCAP_DIRROUTE_NDWORDS, pci_generic_save},
238cb7ea99dSJimmy Vetayases 
239cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_VCSET_TYPE, PCI_HTCAP_TYPE_MASK,
240cb7ea99dSJimmy Vetayases 		PCI_HTCAP_VCSET_NDWORDS, pci_generic_save},
241cb7ea99dSJimmy Vetayases 
242cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_RETRYMODE_TYPE, PCI_HTCAP_TYPE_MASK,
243cb7ea99dSJimmy Vetayases 		PCI_HTCAP_RETRYMODE_NDWORDS, pci_generic_save},
244cb7ea99dSJimmy Vetayases 
245cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_GEN3_TYPE, PCI_HTCAP_TYPE_MASK,
246cb7ea99dSJimmy Vetayases 		PCI_HTCAP_GEN3_NDWORDS, pci_generic_save},
247cb7ea99dSJimmy Vetayases 
248cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_FUNCEXT_TYPE, PCI_HTCAP_TYPE_MASK,
249cb7ea99dSJimmy Vetayases 		PCI_CAP_SZUNKNOWN, pci_ht_funcext_save},
250cb7ea99dSJimmy Vetayases 
251cb7ea99dSJimmy Vetayases 	{PCI_CAP_ID_HT, PCI_HTCAP_PM_TYPE, PCI_HTCAP_TYPE_MASK,
252cb7ea99dSJimmy Vetayases 		PCI_HTCAP_PM_NDWORDS, pci_generic_save},
253cb7ea99dSJimmy Vetayases 
2547c478bd9Sstevel@tonic-gate 	/*
2557c478bd9Sstevel@tonic-gate 	 * {PCI_CAP_ID_cPCI_CRC, 0, NULL},
2567c478bd9Sstevel@tonic-gate 	 * {PCI_CAP_ID_VPD, 0, NULL},
2577c478bd9Sstevel@tonic-gate 	 * {PCI_CAP_ID_cPCI_HS, 0, NULL},
2587c478bd9Sstevel@tonic-gate 	 * {PCI_CAP_ID_PCI_HOTPLUG, 0, NULL},
2597c478bd9Sstevel@tonic-gate 	 * {PCI_CAP_ID_AGP_8X, 0, NULL},
2607c478bd9Sstevel@tonic-gate 	 * {PCI_CAP_ID_SECURE_DEV, 0, NULL},
2617c478bd9Sstevel@tonic-gate 	 */
2627e12ceb3SToomas Soome 	{PCI_CAP_NEXT_PTR_NULL, 0, 0}
2637c478bd9Sstevel@tonic-gate };
2647c478bd9Sstevel@tonic-gate 
265cb7ea99dSJimmy Vetayases 
2667c478bd9Sstevel@tonic-gate /*
2677c478bd9Sstevel@tonic-gate  * Save the configuration registers for cdip as a property
2687c478bd9Sstevel@tonic-gate  * so that it persists after detach/uninitchild.
2697c478bd9Sstevel@tonic-gate  */
2707c478bd9Sstevel@tonic-gate int
pci_save_config_regs(dev_info_t * dip)2717c478bd9Sstevel@tonic-gate pci_save_config_regs(dev_info_t *dip)
2727c478bd9Sstevel@tonic-gate {
2737c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t confhdl;
2747c478bd9Sstevel@tonic-gate 	pci_config_header_state_t *chsp;
2757c478bd9Sstevel@tonic-gate 	pci_cap_save_desc_t *pci_cap_descp;
2767c478bd9Sstevel@tonic-gate 	int ret;
2777c478bd9Sstevel@tonic-gate 	uint32_t i, ncaps, nwords;
2787c478bd9Sstevel@tonic-gate 	uint32_t *regbuf, *p;
2797c478bd9Sstevel@tonic-gate 	uint8_t *maskbuf;
2807c478bd9Sstevel@tonic-gate 	size_t maskbufsz, regbufsz, capbufsz;
281c4e64f25Sgs #ifdef __sparc
2827c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
283c4e64f25Sgs #else
284c4e64f25Sgs 	ddi_device_acc_attr_t attr;
285c4e64f25Sgs 	caddr_t cfgaddr;
286c4e64f25Sgs #endif
2877c478bd9Sstevel@tonic-gate 	off_t offset = 0;
2887c478bd9Sstevel@tonic-gate 	uint8_t cap_ptr, cap_id;
2897c478bd9Sstevel@tonic-gate 	int pcie = 0;
290c602bc24Syf 	uint16_t status;
291c602bc24Syf 
2922df1fe9cSrandyf 	PMD(PMD_SX, ("pci_save_config_regs %s:%d\n", ddi_driver_name(dip),
2932df1fe9cSrandyf 	    ddi_get_instance(dip)))
2947c478bd9Sstevel@tonic-gate 
295c4e64f25Sgs #ifdef __sparc
2967c478bd9Sstevel@tonic-gate 	if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) {
2977c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN, "%s%d can't get config handle",
2982df1fe9cSrandyf 		    ddi_driver_name(dip), ddi_get_instance(dip));
2997c478bd9Sstevel@tonic-gate 
3007c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
3017c478bd9Sstevel@tonic-gate 	}
302c4e64f25Sgs #else
303c4e64f25Sgs 	/* Set up cautious config access handle */
304c4e64f25Sgs 	attr.devacc_attr_version = DDI_DEVICE_ATTR_V1;
305c4e64f25Sgs 	attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
306c4e64f25Sgs 	attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
307c4e64f25Sgs 	attr.devacc_attr_access = DDI_CAUTIOUS_ACC;
308c4e64f25Sgs 	if (ddi_regs_map_setup(dip, 0, &cfgaddr, 0, 0, &attr, &confhdl)
309c4e64f25Sgs 	    != DDI_SUCCESS) {
310c4e64f25Sgs 		cmn_err(CE_WARN, "%s%d can't setup cautious config handle",
311c4e64f25Sgs 		    ddi_driver_name(dip), ddi_get_instance(dip));
312c4e64f25Sgs 
313c4e64f25Sgs 		return (DDI_FAILURE);
314c4e64f25Sgs 	}
315c4e64f25Sgs #endif
316c602bc24Syf 
317c602bc24Syf 	/*
318c602bc24Syf 	 * Determine if it implements capabilities
319c602bc24Syf 	 */
320c602bc24Syf 	status = pci_config_get16(confhdl, PCI_CONF_STAT);
321c602bc24Syf 	if (!(status & 0x10)) {
322c602bc24Syf 		goto no_cap;
323c602bc24Syf 	}
3247c478bd9Sstevel@tonic-gate 	/*
3257c478bd9Sstevel@tonic-gate 	 * Determine if it is a pci express device. If it is, save entire
3267c478bd9Sstevel@tonic-gate 	 * 4k config space treating it as a array of 32 bit integers.
3277c478bd9Sstevel@tonic-gate 	 * If it is not, do it in a usual PCI way.
3287c478bd9Sstevel@tonic-gate 	 */
3297c478bd9Sstevel@tonic-gate 	cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR);
3307c478bd9Sstevel@tonic-gate 	/*
3317c478bd9Sstevel@tonic-gate 	 * Walk the capabilities searching for pci express capability
3327c478bd9Sstevel@tonic-gate 	 */
3337c478bd9Sstevel@tonic-gate 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
3347c478bd9Sstevel@tonic-gate 		cap_id = pci_config_get8(confhdl,
3357c478bd9Sstevel@tonic-gate 		    cap_ptr + PCI_CAP_ID);
3367c478bd9Sstevel@tonic-gate 		if (cap_id == PCI_CAP_ID_PCI_E) {
3377c478bd9Sstevel@tonic-gate 			pcie = 1;
3387c478bd9Sstevel@tonic-gate 			break;
3397c478bd9Sstevel@tonic-gate 		}
3407c478bd9Sstevel@tonic-gate 		cap_ptr = pci_config_get8(confhdl,
3417c478bd9Sstevel@tonic-gate 		    cap_ptr + PCI_CAP_NEXT_PTR);
3427c478bd9Sstevel@tonic-gate 	}
343c602bc24Syf no_cap:
3447c478bd9Sstevel@tonic-gate 	if (pcie) {
3457c478bd9Sstevel@tonic-gate 		/* PCI express device. Can have data in all 4k space */
3467c478bd9Sstevel@tonic-gate 		regbuf = (uint32_t *)kmem_zalloc((size_t)PCIE_CONF_HDR_SIZE,
3472df1fe9cSrandyf 		    KM_SLEEP);
3487c478bd9Sstevel@tonic-gate 		p = regbuf;
3497c478bd9Sstevel@tonic-gate 		/*
3507c478bd9Sstevel@tonic-gate 		 * Allocate space for mask.
3517c478bd9Sstevel@tonic-gate 		 * mask size is 128 bytes (4096 / 4 / 8 )
3527c478bd9Sstevel@tonic-gate 		 */
3537c478bd9Sstevel@tonic-gate 		maskbufsz = (size_t)((PCIE_CONF_HDR_SIZE/ sizeof (uint32_t)) >>
3547c478bd9Sstevel@tonic-gate 		    INDEX_SHIFT);
3557c478bd9Sstevel@tonic-gate 		maskbuf = (uint8_t *)kmem_zalloc(maskbufsz, KM_SLEEP);
356c4e64f25Sgs #ifdef __sparc
3577c478bd9Sstevel@tonic-gate 		hp = impl_acc_hdl_get(confhdl);
358c4e64f25Sgs #endif
3597c478bd9Sstevel@tonic-gate 		for (i = 0; i < (PCIE_CONF_HDR_SIZE / sizeof (uint32_t)); i++) {
360c4e64f25Sgs #ifdef __sparc
361c4e64f25Sgs 			ret = ddi_peek32(dip, (int32_t *)(hp->ah_addr + offset),
362c4e64f25Sgs 			    (int32_t *)p);
363abee7076Sgs 			if (ret == DDI_SUCCESS) {
364c4e64f25Sgs #else
365c4e64f25Sgs 			/*
366c4e64f25Sgs 			 * ddi_peek doesn't work on x86, so we use cautious pci
367c4e64f25Sgs 			 * config access instead.
368c4e64f25Sgs 			 */
369c4e64f25Sgs 			*p = pci_config_get32(confhdl, offset);
370c4e64f25Sgs 			if (*p != -1) {
371c4e64f25Sgs #endif
3727c478bd9Sstevel@tonic-gate 				/* it is readable register. set the bit */
3737c478bd9Sstevel@tonic-gate 				maskbuf[i >> INDEX_SHIFT] |=
3747c478bd9Sstevel@tonic-gate 				    (uint8_t)(1 << (i & BITMASK));
3757c478bd9Sstevel@tonic-gate 			}
3767c478bd9Sstevel@tonic-gate 			p++;
3777c478bd9Sstevel@tonic-gate 			offset += sizeof (uint32_t);
3787c478bd9Sstevel@tonic-gate 		}
3797c478bd9Sstevel@tonic-gate 
3807c478bd9Sstevel@tonic-gate 		if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip,
3817c478bd9Sstevel@tonic-gate 		    SAVED_CONFIG_REGS_MASK, (uchar_t *)maskbuf,
3827c478bd9Sstevel@tonic-gate 		    maskbufsz)) != DDI_PROP_SUCCESS) {
3837c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "couldn't create %s property while"
3847c478bd9Sstevel@tonic-gate 			    "saving config space for %s@%d\n",
3857c478bd9Sstevel@tonic-gate 			    SAVED_CONFIG_REGS_MASK, ddi_driver_name(dip),
3867c478bd9Sstevel@tonic-gate 			    ddi_get_instance(dip));
3877c478bd9Sstevel@tonic-gate 		} else if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE,
3887c478bd9Sstevel@tonic-gate 		    dip, SAVED_CONFIG_REGS, (uchar_t *)regbuf,
3897c478bd9Sstevel@tonic-gate 		    (size_t)PCIE_CONF_HDR_SIZE)) != DDI_PROP_SUCCESS) {
3907c478bd9Sstevel@tonic-gate 			(void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
3917c478bd9Sstevel@tonic-gate 			    SAVED_CONFIG_REGS_MASK);
3927c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "%s%d can't update prop %s",
3937c478bd9Sstevel@tonic-gate 			    ddi_driver_name(dip), ddi_get_instance(dip),
3947c478bd9Sstevel@tonic-gate 			    SAVED_CONFIG_REGS);
3957c478bd9Sstevel@tonic-gate 		}
3967c478bd9Sstevel@tonic-gate 
3977c478bd9Sstevel@tonic-gate 		kmem_free(maskbuf, (size_t)maskbufsz);
3987c478bd9Sstevel@tonic-gate 		kmem_free(regbuf, (size_t)PCIE_CONF_HDR_SIZE);
3997c478bd9Sstevel@tonic-gate 	} else {
4007c478bd9Sstevel@tonic-gate 		regbuf = (uint32_t *)kmem_zalloc((size_t)PCI_CONF_HDR_SIZE,
4012df1fe9cSrandyf 		    KM_SLEEP);
4027c478bd9Sstevel@tonic-gate 		chsp = (pci_config_header_state_t *)regbuf;
4037c478bd9Sstevel@tonic-gate 
4047c478bd9Sstevel@tonic-gate 		chsp->chs_command = pci_config_get16(confhdl, PCI_CONF_COMM);
4057c478bd9Sstevel@tonic-gate 		chsp->chs_header_type =	pci_config_get8(confhdl,
4062df1fe9cSrandyf 		    PCI_CONF_HEADER);
4077c478bd9Sstevel@tonic-gate 		if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) ==
4087c478bd9Sstevel@tonic-gate 		    PCI_HEADER_ONE)
4097c478bd9Sstevel@tonic-gate 			chsp->chs_bridge_control =
4107c478bd9Sstevel@tonic-gate 			    pci_config_get16(confhdl, PCI_BCNF_BCNTRL);
4117c478bd9Sstevel@tonic-gate 		chsp->chs_cache_line_size = pci_config_get8(confhdl,
4127c478bd9Sstevel@tonic-gate 		    PCI_CONF_CACHE_LINESZ);
4137c478bd9Sstevel@tonic-gate 		chsp->chs_latency_timer = pci_config_get8(confhdl,
4147c478bd9Sstevel@tonic-gate 		    PCI_CONF_LATENCY_TIMER);
4157c478bd9Sstevel@tonic-gate 		if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) ==
4167c478bd9Sstevel@tonic-gate 		    PCI_HEADER_ONE) {
4177c478bd9Sstevel@tonic-gate 			chsp->chs_sec_latency_timer =
4187c478bd9Sstevel@tonic-gate 			    pci_config_get8(confhdl, PCI_BCNF_LATENCY_TIMER);
4197c478bd9Sstevel@tonic-gate 		}
4207c478bd9Sstevel@tonic-gate 
4217c478bd9Sstevel@tonic-gate 		chsp->chs_base0 = pci_config_get32(confhdl, PCI_CONF_BASE0);
4227c478bd9Sstevel@tonic-gate 		chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1);
4237c478bd9Sstevel@tonic-gate 		chsp->chs_base2 = pci_config_get32(confhdl, PCI_CONF_BASE2);
4247c478bd9Sstevel@tonic-gate 		chsp->chs_base3 = pci_config_get32(confhdl, PCI_CONF_BASE3);
4257c478bd9Sstevel@tonic-gate 		chsp->chs_base4 = pci_config_get32(confhdl, PCI_CONF_BASE4);
4267c478bd9Sstevel@tonic-gate 		chsp->chs_base5 = pci_config_get32(confhdl, PCI_CONF_BASE5);
4277c478bd9Sstevel@tonic-gate 
4287c478bd9Sstevel@tonic-gate 		/*
4297c478bd9Sstevel@tonic-gate 		 * Allocate maximum space required for capability descriptions.
4307c478bd9Sstevel@tonic-gate 		 * The maximum number of capabilties saved is the number of
4317c478bd9Sstevel@tonic-gate 		 * capabilities listed in the pci_cap_table.
4327c478bd9Sstevel@tonic-gate 		 */
4337c478bd9Sstevel@tonic-gate 		ncaps = (sizeof (pci_cap_table) / sizeof (pci_cap_entry_t));
4347c478bd9Sstevel@tonic-gate 		capbufsz = ncaps * sizeof (pci_cap_save_desc_t);
4357c478bd9Sstevel@tonic-gate 		pci_cap_descp = (pci_cap_save_desc_t *)kmem_zalloc(
4367c478bd9Sstevel@tonic-gate 		    capbufsz, KM_SLEEP);
4377c478bd9Sstevel@tonic-gate 		p = (uint32_t *)((caddr_t)regbuf +
4387c478bd9Sstevel@tonic-gate 		    sizeof (pci_config_header_state_t));
4397c478bd9Sstevel@tonic-gate 		nwords = pci_save_caps(confhdl, p, pci_cap_descp, &ncaps);
4407c478bd9Sstevel@tonic-gate 		regbufsz = sizeof (pci_config_header_state_t) +
4417c478bd9Sstevel@tonic-gate 		    nwords * sizeof (uint32_t);
4427c478bd9Sstevel@tonic-gate 
4437c478bd9Sstevel@tonic-gate 		if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip,
4447c478bd9Sstevel@tonic-gate 		    SAVED_CONFIG_REGS, (uchar_t *)regbuf, regbufsz)) !=
4457c478bd9Sstevel@tonic-gate 		    DDI_PROP_SUCCESS) {
4467c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "%s%d can't update prop %s",
4477c478bd9Sstevel@tonic-gate 			    ddi_driver_name(dip), ddi_get_instance(dip),
4487c478bd9Sstevel@tonic-gate 			    SAVED_CONFIG_REGS);
4497c478bd9Sstevel@tonic-gate 		} else if (ncaps) {
4507c478bd9Sstevel@tonic-gate 			ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip,
4517c478bd9Sstevel@tonic-gate 			    SAVED_CONFIG_REGS_CAPINFO, (uchar_t *)pci_cap_descp,
4527c478bd9Sstevel@tonic-gate 			    ncaps * sizeof (pci_cap_save_desc_t));
4537c478bd9Sstevel@tonic-gate 			if (ret != DDI_PROP_SUCCESS)
4547c478bd9Sstevel@tonic-gate 				(void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
4557c478bd9Sstevel@tonic-gate 				    SAVED_CONFIG_REGS);
4567c478bd9Sstevel@tonic-gate 		}
4577c478bd9Sstevel@tonic-gate 		kmem_free(regbuf, (size_t)PCI_CONF_HDR_SIZE);
4587c478bd9Sstevel@tonic-gate 		kmem_free(pci_cap_descp, capbufsz);
4597c478bd9Sstevel@tonic-gate 	}
4607c478bd9Sstevel@tonic-gate 	pci_config_teardown(&confhdl);
4617c478bd9Sstevel@tonic-gate 
4627c478bd9Sstevel@tonic-gate 	if (ret != DDI_PROP_SUCCESS)
4637c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
4647c478bd9Sstevel@tonic-gate 
4657c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
4667c478bd9Sstevel@tonic-gate }
4677c478bd9Sstevel@tonic-gate 
4687c478bd9Sstevel@tonic-gate /*
4697c478bd9Sstevel@tonic-gate  * Saves registers associated with PCI capabilities.
4707c478bd9Sstevel@tonic-gate  * Returns number of 32 bit words saved.
4717c478bd9Sstevel@tonic-gate  * Number of capabilities saved is returned in ncapsp.
4727c478bd9Sstevel@tonic-gate  */
4737c478bd9Sstevel@tonic-gate static uint32_t
4747c478bd9Sstevel@tonic-gate pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf,
4757c478bd9Sstevel@tonic-gate     pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp)
4767c478bd9Sstevel@tonic-gate {
4777c478bd9Sstevel@tonic-gate 	return (cap_walk_and_save(confhdl, regbuf, cap_descp, ncapsp, 0));
4787c478bd9Sstevel@tonic-gate }
4797c478bd9Sstevel@tonic-gate 
4807c478bd9Sstevel@tonic-gate static uint32_t
4817c478bd9Sstevel@tonic-gate cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf,
4827c478bd9Sstevel@tonic-gate     pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace)
4837c478bd9Sstevel@tonic-gate {
4847c478bd9Sstevel@tonic-gate 	pci_cap_entry_t *pci_cap_entp;
485c602bc24Syf 	uint16_t cap_id, offset, status;
4867c478bd9Sstevel@tonic-gate 	uint32_t words_saved = 0, nwords = 0;
4877c478bd9Sstevel@tonic-gate 	uint16_t cap_ptr = PCI_CAP_NEXT_PTR_NULL;
488cb7ea99dSJimmy Vetayases 	uint16_t cap_reg;
4897c478bd9Sstevel@tonic-gate 
4907c478bd9Sstevel@tonic-gate 	*ncapsp = 0;
491c602bc24Syf 
492c602bc24Syf 	/*
493c602bc24Syf 	 * Determine if it implements capabilities
494c602bc24Syf 	 */
495c602bc24Syf 	status = pci_config_get16(confhdl, PCI_CONF_STAT);
496c602bc24Syf 	if (!(status & 0x10)) {
497c602bc24Syf 		return (words_saved);
498c602bc24Syf 	}
499c602bc24Syf 
5007c478bd9Sstevel@tonic-gate 	if (!xspace)
5017c478bd9Sstevel@tonic-gate 		cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR);
5027c478bd9Sstevel@tonic-gate 	/*
5037c478bd9Sstevel@tonic-gate 	 * Walk the capabilities
5047c478bd9Sstevel@tonic-gate 	 */
5057c478bd9Sstevel@tonic-gate 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
5067c478bd9Sstevel@tonic-gate 		cap_id = CAP_ID(confhdl, cap_ptr, xspace);
507cb7ea99dSJimmy Vetayases 
5087c478bd9Sstevel@tonic-gate 		/* Search for this cap id in our table */
509cb7ea99dSJimmy Vetayases 		if (!xspace) {
5107c478bd9Sstevel@tonic-gate 			pci_cap_entp = pci_cap_table;
511cb7ea99dSJimmy Vetayases 			cap_reg = pci_config_get16(confhdl,
512cb7ea99dSJimmy Vetayases 			    cap_ptr + PCI_CAP_ID_REGS_OFF);
513cb7ea99dSJimmy Vetayases 		}
514cb7ea99dSJimmy Vetayases 
515cb7ea99dSJimmy Vetayases 		while (pci_cap_entp->cap_id != PCI_CAP_NEXT_PTR_NULL) {
516cb7ea99dSJimmy Vetayases 			if (pci_cap_entp->cap_id == cap_id &&
517cb7ea99dSJimmy Vetayases 			    (cap_reg & pci_cap_entp->cap_mask) ==
518cb7ea99dSJimmy Vetayases 			    pci_cap_entp->cap_reg)
519cb7ea99dSJimmy Vetayases 				break;
520cb7ea99dSJimmy Vetayases 
5217c478bd9Sstevel@tonic-gate 			pci_cap_entp++;
522cb7ea99dSJimmy Vetayases 		}
5237c478bd9Sstevel@tonic-gate 
5247c478bd9Sstevel@tonic-gate 		offset = cap_ptr;
5257c478bd9Sstevel@tonic-gate 		cap_ptr = NEXT_CAP(confhdl, cap_ptr, xspace);
5267c478bd9Sstevel@tonic-gate 		/*
5277c478bd9Sstevel@tonic-gate 		 * If this cap id is not found in the table, there is nothing
5287c478bd9Sstevel@tonic-gate 		 * to save.
5297c478bd9Sstevel@tonic-gate 		 */
5307c478bd9Sstevel@tonic-gate 		if (pci_cap_entp->cap_id == PCI_CAP_NEXT_PTR_NULL)
5317c478bd9Sstevel@tonic-gate 			continue;
5327c478bd9Sstevel@tonic-gate 		if (pci_cap_entp->cap_save_func) {
5337c478bd9Sstevel@tonic-gate 			if ((nwords = pci_cap_entp->cap_save_func(confhdl,
5347c478bd9Sstevel@tonic-gate 			    offset, regbuf, pci_cap_entp->cap_ndwords))) {
5357c478bd9Sstevel@tonic-gate 				cap_descp->cap_nregs = nwords;
5367c478bd9Sstevel@tonic-gate 				cap_descp->cap_offset = offset;
5377c478bd9Sstevel@tonic-gate 				cap_descp->cap_id = cap_id;
5387c478bd9Sstevel@tonic-gate 				regbuf += nwords;
5397c478bd9Sstevel@tonic-gate 				cap_descp++;
5407c478bd9Sstevel@tonic-gate 				words_saved += nwords;
5417c478bd9Sstevel@tonic-gate 				(*ncapsp)++;
5427c478bd9Sstevel@tonic-gate 			}
5437c478bd9Sstevel@tonic-gate 		}
5447c478bd9Sstevel@tonic-gate 
5457c478bd9Sstevel@tonic-gate 	}
5467c478bd9Sstevel@tonic-gate 	return (words_saved);
5477c478bd9Sstevel@tonic-gate }
5487c478bd9Sstevel@tonic-gate 
5497c478bd9Sstevel@tonic-gate static void
5507c478bd9Sstevel@tonic-gate pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
5517c478bd9Sstevel@tonic-gate     uint32_t *regbuf, uint32_t nwords)
5527c478bd9Sstevel@tonic-gate {
5537c478bd9Sstevel@tonic-gate 	int i;
5547c478bd9Sstevel@tonic-gate 
5557c478bd9Sstevel@tonic-gate 	for (i = 0; i < nwords; i++) {
5567c478bd9Sstevel@tonic-gate 		*regbuf = pci_config_get32(confhdl, cap_ptr);
5577c478bd9Sstevel@tonic-gate 		regbuf++;
5587c478bd9Sstevel@tonic-gate 		cap_ptr += 4;
5597c478bd9Sstevel@tonic-gate 	}
5607c478bd9Sstevel@tonic-gate }
5617c478bd9Sstevel@tonic-gate 
5627c478bd9Sstevel@tonic-gate static uint32_t
5637c478bd9Sstevel@tonic-gate pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf,
5647c478bd9Sstevel@tonic-gate     uint32_t nwords)
5657c478bd9Sstevel@tonic-gate {
5667c478bd9Sstevel@tonic-gate 	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
5677c478bd9Sstevel@tonic-gate 	return (nwords);
5687c478bd9Sstevel@tonic-gate }
5697c478bd9Sstevel@tonic-gate 
5707c478bd9Sstevel@tonic-gate /*ARGSUSED*/
5717c478bd9Sstevel@tonic-gate static uint32_t
5727c478bd9Sstevel@tonic-gate pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf,
5737c478bd9Sstevel@tonic-gate     uint32_t notused)
5747c478bd9Sstevel@tonic-gate {
5757c478bd9Sstevel@tonic-gate 	uint32_t nwords = PCI_MSI_MIN_WORDS;
5767c478bd9Sstevel@tonic-gate 	uint16_t msi_ctrl;
5777c478bd9Sstevel@tonic-gate 
5787c478bd9Sstevel@tonic-gate 	/* Figure out how many registers to be saved */
5797c478bd9Sstevel@tonic-gate 	msi_ctrl = pci_config_get16(confhdl, cap_ptr + PCI_MSI_CTRL);
5807c478bd9Sstevel@tonic-gate 	/* If 64 bit address capable add one word */
5817c478bd9Sstevel@tonic-gate 	if (msi_ctrl & PCI_MSI_64BIT_MASK)
5827c478bd9Sstevel@tonic-gate 		nwords++;
5837c478bd9Sstevel@tonic-gate 	/* If per vector masking capable, add two more words */
5847c478bd9Sstevel@tonic-gate 	if (msi_ctrl & PCI_MSI_PVM_MASK)
5857c478bd9Sstevel@tonic-gate 		nwords += 2;
5867c478bd9Sstevel@tonic-gate 	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
5877c478bd9Sstevel@tonic-gate 
5887c478bd9Sstevel@tonic-gate 	return (nwords);
5897c478bd9Sstevel@tonic-gate }
5907c478bd9Sstevel@tonic-gate 
5917c478bd9Sstevel@tonic-gate /*ARGSUSED*/
5927c478bd9Sstevel@tonic-gate static uint32_t
5937c478bd9Sstevel@tonic-gate pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf,
5947c478bd9Sstevel@tonic-gate     uint32_t notused)
5957c478bd9Sstevel@tonic-gate {
5967c478bd9Sstevel@tonic-gate 	uint32_t nwords = PCI_PCIX_MIN_WORDS;
5977c478bd9Sstevel@tonic-gate 	uint16_t pcix_command;
5987c478bd9Sstevel@tonic-gate 
5997c478bd9Sstevel@tonic-gate 	/* Figure out how many registers to be saved */
6007c478bd9Sstevel@tonic-gate 	pcix_command = pci_config_get16(confhdl, cap_ptr + PCI_PCIX_COMMAND);
6017c478bd9Sstevel@tonic-gate 	/* If it is version 1 or version 2, add 4 words */
6027c478bd9Sstevel@tonic-gate 	if (((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_1) ||
6037c478bd9Sstevel@tonic-gate 	    ((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_2))
6047c478bd9Sstevel@tonic-gate 		nwords += 4;
6057c478bd9Sstevel@tonic-gate 	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
6067c478bd9Sstevel@tonic-gate 
6077c478bd9Sstevel@tonic-gate 	return (nwords);
6087c478bd9Sstevel@tonic-gate }
6097c478bd9Sstevel@tonic-gate 
6107c478bd9Sstevel@tonic-gate /*ARGSUSED*/
6117c478bd9Sstevel@tonic-gate static uint32_t
6127c478bd9Sstevel@tonic-gate pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf,
6137c478bd9Sstevel@tonic-gate     uint32_t notused)
6147c478bd9Sstevel@tonic-gate {
6157c478bd9Sstevel@tonic-gate 	return (0);
6167c478bd9Sstevel@tonic-gate }
6177c478bd9Sstevel@tonic-gate 
618cb7ea99dSJimmy Vetayases /*ARGSUSED*/
619cb7ea99dSJimmy Vetayases static uint32_t
620cb7ea99dSJimmy Vetayases pci_ht_addrmap_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
621cb7ea99dSJimmy Vetayases     uint32_t *regbuf, uint32_t notused)
622cb7ea99dSJimmy Vetayases {
623cb7ea99dSJimmy Vetayases 	uint32_t nwords = 0;
624cb7ea99dSJimmy Vetayases 	uint16_t reg;
625cb7ea99dSJimmy Vetayases 
626cb7ea99dSJimmy Vetayases 	reg = pci_config_get16(confhdl, cap_ptr + PCI_CAP_ID_REGS_OFF);
627cb7ea99dSJimmy Vetayases 
628cb7ea99dSJimmy Vetayases 	switch ((reg & PCI_HTCAP_ADDRMAP_MAPTYPE_MASK) >>
629cb7ea99dSJimmy Vetayases 	    PCI_HTCAP_ADDRMAP_MAPTYPE_SHIFT) {
630cb7ea99dSJimmy Vetayases 	case PCI_HTCAP_ADDRMAP_40BIT_ID:
631cb7ea99dSJimmy Vetayases 		/* HT3.1 spec, ch 7.7, 40-bit dma */
632cb7ea99dSJimmy Vetayases 		nwords = 3 + ((reg & PCI_HTCAP_ADDRMAP_NUMMAP_MASK) * 2);
633cb7ea99dSJimmy Vetayases 		break;
634cb7ea99dSJimmy Vetayases 	case PCI_HTCAP_ADDRMAP_64BIT_ID:
635cb7ea99dSJimmy Vetayases 		/* HT3.1 spec, ch 7.8, 64-bit dma */
636cb7ea99dSJimmy Vetayases 		nwords = 4;
637cb7ea99dSJimmy Vetayases 		break;
638cb7ea99dSJimmy Vetayases 	default:
639cb7ea99dSJimmy Vetayases 		nwords = 0;
640cb7ea99dSJimmy Vetayases 	}
641cb7ea99dSJimmy Vetayases 
642cb7ea99dSJimmy Vetayases 	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
643cb7ea99dSJimmy Vetayases 	return (nwords);
644cb7ea99dSJimmy Vetayases }
645cb7ea99dSJimmy Vetayases 
646cb7ea99dSJimmy Vetayases /*ARGSUSED*/
647cb7ea99dSJimmy Vetayases static uint32_t
648cb7ea99dSJimmy Vetayases pci_ht_funcext_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr,
649cb7ea99dSJimmy Vetayases     uint32_t *regbuf, uint32_t notused)
650cb7ea99dSJimmy Vetayases {
651cb7ea99dSJimmy Vetayases 	uint32_t nwords;
652cb7ea99dSJimmy Vetayases 	uint16_t reg;
653cb7ea99dSJimmy Vetayases 
654cb7ea99dSJimmy Vetayases 	reg = pci_config_get16(confhdl, cap_ptr + PCI_CAP_ID_REGS_OFF);
655cb7ea99dSJimmy Vetayases 
656cb7ea99dSJimmy Vetayases 	/* HT3.1 spec, ch 7.17 */
657cb7ea99dSJimmy Vetayases 	nwords = 1 + (reg & PCI_HTCAP_FUNCEXT_LEN_MASK);
658cb7ea99dSJimmy Vetayases 
659cb7ea99dSJimmy Vetayases 	pci_fill_buf(confhdl, cap_ptr, regbuf, nwords);
660cb7ea99dSJimmy Vetayases 	return (nwords);
661cb7ea99dSJimmy Vetayases }
662cb7ea99dSJimmy Vetayases 
6637c478bd9Sstevel@tonic-gate static void
6647c478bd9Sstevel@tonic-gate pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf,
6657c478bd9Sstevel@tonic-gate     uint16_t pmcap_offset)
6667c478bd9Sstevel@tonic-gate {
6677c478bd9Sstevel@tonic-gate 	uint16_t pmcsr;
6687c478bd9Sstevel@tonic-gate 	uint16_t pmcsr_offset = pmcap_offset + PCI_PMCSR;
6697c478bd9Sstevel@tonic-gate 	uint32_t *saved_pmcsrp = (uint32_t *)((caddr_t)regbuf + PCI_PMCSR);
6707c478bd9Sstevel@tonic-gate 
6717c478bd9Sstevel@tonic-gate 	/*
6727c478bd9Sstevel@tonic-gate 	 * Copy the power state bits from the PMCSR to our saved copy.
6737c478bd9Sstevel@tonic-gate 	 * This is to make sure that we don't change the D state when
6747c478bd9Sstevel@tonic-gate 	 * we restore config space of the device.
6757c478bd9Sstevel@tonic-gate 	 */
6767c478bd9Sstevel@tonic-gate 	pmcsr = pci_config_get16(confhdl, pmcsr_offset);
6777c478bd9Sstevel@tonic-gate 	(*saved_pmcsrp) &= ~PCI_PMCSR_STATE_MASK;
6787c478bd9Sstevel@tonic-gate 	(*saved_pmcsrp) |= (pmcsr & PCI_PMCSR_STATE_MASK);
6797c478bd9Sstevel@tonic-gate }
6807c478bd9Sstevel@tonic-gate 
6817c478bd9Sstevel@tonic-gate static void
6827c478bd9Sstevel@tonic-gate pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf,
6837c478bd9Sstevel@tonic-gate     pci_cap_save_desc_t *cap_descp, uint32_t elements)
6847c478bd9Sstevel@tonic-gate {
6857c478bd9Sstevel@tonic-gate 	int i, j;
6867c478bd9Sstevel@tonic-gate 	uint16_t offset;
6877c478bd9Sstevel@tonic-gate 
6887c478bd9Sstevel@tonic-gate 	for (i = 0; i < (elements / sizeof (pci_cap_save_desc_t)); i++) {
6897c478bd9Sstevel@tonic-gate 		offset = cap_descp->cap_offset;
6907c478bd9Sstevel@tonic-gate 		if (cap_descp->cap_id == PCI_CAP_ID_PM)
6917c478bd9Sstevel@tonic-gate 			pci_pmcap_check(confhdl, regbuf, offset);
6927c478bd9Sstevel@tonic-gate 		for (j = 0; j < cap_descp->cap_nregs; j++) {
6937c478bd9Sstevel@tonic-gate 			pci_config_put32(confhdl, offset, *regbuf);
6947c478bd9Sstevel@tonic-gate 			regbuf++;
6957c478bd9Sstevel@tonic-gate 			offset += 4;
6967c478bd9Sstevel@tonic-gate 		}
6977c478bd9Sstevel@tonic-gate 		cap_descp++;
6987c478bd9Sstevel@tonic-gate 	}
6997c478bd9Sstevel@tonic-gate }
7007c478bd9Sstevel@tonic-gate 
7017c478bd9Sstevel@tonic-gate /*
7027c478bd9Sstevel@tonic-gate  * Restore config_regs from a single devinfo node.
7037c478bd9Sstevel@tonic-gate  */
7047c478bd9Sstevel@tonic-gate int
7057c478bd9Sstevel@tonic-gate pci_restore_config_regs(dev_info_t *dip)
7067c478bd9Sstevel@tonic-gate {
7077c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t confhdl;
7087c478bd9Sstevel@tonic-gate 	pci_config_header_state_t *chs_p;
7097c478bd9Sstevel@tonic-gate 	pci_cap_save_desc_t *cap_descp;
7107c478bd9Sstevel@tonic-gate 	uint32_t elements, i;
7117c478bd9Sstevel@tonic-gate 	uint8_t *maskbuf;
7127c478bd9Sstevel@tonic-gate 	uint32_t *regbuf, *p;
7137c478bd9Sstevel@tonic-gate 	off_t offset = 0;
7147c478bd9Sstevel@tonic-gate 
7157c478bd9Sstevel@tonic-gate 	if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) {
7167c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN, "%s%d can't get config handle",
7177c478bd9Sstevel@tonic-gate 		    ddi_driver_name(dip), ddi_get_instance(dip));
7187c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
7197c478bd9Sstevel@tonic-gate 	}
7207c478bd9Sstevel@tonic-gate 
7217c478bd9Sstevel@tonic-gate 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
7227c478bd9Sstevel@tonic-gate 	    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS_MASK,
7237c478bd9Sstevel@tonic-gate 	    (uchar_t **)&maskbuf, &elements) == DDI_PROP_SUCCESS) {
7247c478bd9Sstevel@tonic-gate 
7257c478bd9Sstevel@tonic-gate 		if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
7267c478bd9Sstevel@tonic-gate 		    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS,
7277c478bd9Sstevel@tonic-gate 		    (uchar_t **)&regbuf, &elements) != DDI_PROP_SUCCESS) {
7287c478bd9Sstevel@tonic-gate 			goto restoreconfig_err;
7297c478bd9Sstevel@tonic-gate 		}
7307c478bd9Sstevel@tonic-gate 		ASSERT(elements == PCIE_CONF_HDR_SIZE);
7317c478bd9Sstevel@tonic-gate 		/* pcie device and has 4k config space saved */
7327c478bd9Sstevel@tonic-gate 		p = regbuf;
7337c478bd9Sstevel@tonic-gate 		for (i = 0; i < PCIE_CONF_HDR_SIZE / sizeof (uint32_t); i++) {
7347c478bd9Sstevel@tonic-gate 			/* If the word is readable then restore it */
7357c478bd9Sstevel@tonic-gate 			if (maskbuf[i >> INDEX_SHIFT] &
7367c478bd9Sstevel@tonic-gate 			    (uint8_t)(1 << (i & BITMASK)))
7377c478bd9Sstevel@tonic-gate 				pci_config_put32(confhdl, offset, *p);
7387c478bd9Sstevel@tonic-gate 			p++;
7397c478bd9Sstevel@tonic-gate 			offset += sizeof (uint32_t);
7407c478bd9Sstevel@tonic-gate 		}
7417c478bd9Sstevel@tonic-gate 		ddi_prop_free(regbuf);
7427c478bd9Sstevel@tonic-gate 		ddi_prop_free(maskbuf);
7437c478bd9Sstevel@tonic-gate 		if (ndi_prop_remove(DDI_DEV_T_NONE, dip,
7447c478bd9Sstevel@tonic-gate 		    SAVED_CONFIG_REGS_MASK) != DDI_PROP_SUCCESS) {
7457c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "%s%d can't remove prop %s",
7467c478bd9Sstevel@tonic-gate 			    ddi_driver_name(dip), ddi_get_instance(dip),
7477c478bd9Sstevel@tonic-gate 			    SAVED_CONFIG_REGS_MASK);
7487c478bd9Sstevel@tonic-gate 		}
7497c478bd9Sstevel@tonic-gate 	} else {
7507c478bd9Sstevel@tonic-gate 		if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
7517c478bd9Sstevel@tonic-gate 		    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS,
7527c478bd9Sstevel@tonic-gate 		    (uchar_t **)&regbuf, &elements) != DDI_PROP_SUCCESS) {
7537c478bd9Sstevel@tonic-gate 
7547c478bd9Sstevel@tonic-gate 			pci_config_teardown(&confhdl);
755abee7076Sgs 			return (DDI_SUCCESS);
7567c478bd9Sstevel@tonic-gate 		}
7577c478bd9Sstevel@tonic-gate 
7587c478bd9Sstevel@tonic-gate 		chs_p = (pci_config_header_state_t *)regbuf;
7597c478bd9Sstevel@tonic-gate 		pci_config_put16(confhdl, PCI_CONF_COMM,
7607c478bd9Sstevel@tonic-gate 		    chs_p->chs_command);
7617c478bd9Sstevel@tonic-gate 		if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) ==
7627c478bd9Sstevel@tonic-gate 		    PCI_HEADER_ONE) {
7637c478bd9Sstevel@tonic-gate 			pci_config_put16(confhdl, PCI_BCNF_BCNTRL,
7647c478bd9Sstevel@tonic-gate 			    chs_p->chs_bridge_control);
7657c478bd9Sstevel@tonic-gate 		}
7667c478bd9Sstevel@tonic-gate 		pci_config_put8(confhdl, PCI_CONF_CACHE_LINESZ,
7677c478bd9Sstevel@tonic-gate 		    chs_p->chs_cache_line_size);
7687c478bd9Sstevel@tonic-gate 		pci_config_put8(confhdl, PCI_CONF_LATENCY_TIMER,
7697c478bd9Sstevel@tonic-gate 		    chs_p->chs_latency_timer);
7707c478bd9Sstevel@tonic-gate 		if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) ==
7717c478bd9Sstevel@tonic-gate 		    PCI_HEADER_ONE)
7727c478bd9Sstevel@tonic-gate 			pci_config_put8(confhdl, PCI_BCNF_LATENCY_TIMER,
7737c478bd9Sstevel@tonic-gate 			    chs_p->chs_sec_latency_timer);
7747c478bd9Sstevel@tonic-gate 
7757c478bd9Sstevel@tonic-gate 		pci_config_put32(confhdl, PCI_CONF_BASE0, chs_p->chs_base0);
7767c478bd9Sstevel@tonic-gate 		pci_config_put32(confhdl, PCI_CONF_BASE1, chs_p->chs_base1);
7777c478bd9Sstevel@tonic-gate 		pci_config_put32(confhdl, PCI_CONF_BASE2, chs_p->chs_base2);
7787c478bd9Sstevel@tonic-gate 		pci_config_put32(confhdl, PCI_CONF_BASE3, chs_p->chs_base3);
7797c478bd9Sstevel@tonic-gate 		pci_config_put32(confhdl, PCI_CONF_BASE4, chs_p->chs_base4);
7807c478bd9Sstevel@tonic-gate 		pci_config_put32(confhdl, PCI_CONF_BASE5, chs_p->chs_base5);
7817c478bd9Sstevel@tonic-gate 
7827c478bd9Sstevel@tonic-gate 		if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip,
7837c478bd9Sstevel@tonic-gate 		    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM,
7847c478bd9Sstevel@tonic-gate 		    SAVED_CONFIG_REGS_CAPINFO,
7857c478bd9Sstevel@tonic-gate 		    (uchar_t **)&cap_descp, &elements) == DDI_PROP_SUCCESS) {
7867c478bd9Sstevel@tonic-gate 			/*
7877c478bd9Sstevel@tonic-gate 			 * PCI capability related regsiters are saved.
7887c478bd9Sstevel@tonic-gate 			 * Restore them based on the description.
7897c478bd9Sstevel@tonic-gate 			 */
7907c478bd9Sstevel@tonic-gate 			p = (uint32_t *)((caddr_t)regbuf +
7917c478bd9Sstevel@tonic-gate 			    sizeof (pci_config_header_state_t));
7927c478bd9Sstevel@tonic-gate 			pci_restore_caps(confhdl, p, cap_descp, elements);
7937c478bd9Sstevel@tonic-gate 			ddi_prop_free(cap_descp);
7947c478bd9Sstevel@tonic-gate 		}
7957c478bd9Sstevel@tonic-gate 
7967c478bd9Sstevel@tonic-gate 		ddi_prop_free(regbuf);
7977c478bd9Sstevel@tonic-gate 	}
7987c478bd9Sstevel@tonic-gate 
7997c478bd9Sstevel@tonic-gate 	/*
8007c478bd9Sstevel@tonic-gate 	 * Make sure registers are flushed
8017c478bd9Sstevel@tonic-gate 	 */
8027c478bd9Sstevel@tonic-gate 	(void) pci_config_get32(confhdl, PCI_CONF_BASE5);
8037c478bd9Sstevel@tonic-gate 
8047c478bd9Sstevel@tonic-gate 
8057c478bd9Sstevel@tonic-gate 	if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS) !=
8067c478bd9Sstevel@tonic-gate 	    DDI_PROP_SUCCESS) {
8077c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN, "%s%d can't remove prop %s",
8087c478bd9Sstevel@tonic-gate 		    ddi_driver_name(dip), ddi_get_instance(dip),
8097c478bd9Sstevel@tonic-gate 		    SAVED_CONFIG_REGS);
8107c478bd9Sstevel@tonic-gate 	}
8117c478bd9Sstevel@tonic-gate 
8127c478bd9Sstevel@tonic-gate 	pci_config_teardown(&confhdl);
8137c478bd9Sstevel@tonic-gate 
8147c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
8157c478bd9Sstevel@tonic-gate 
8167c478bd9Sstevel@tonic-gate restoreconfig_err:
8177c478bd9Sstevel@tonic-gate 	ddi_prop_free(maskbuf);
8187c478bd9Sstevel@tonic-gate 	if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS_MASK) !=
8197c478bd9Sstevel@tonic-gate 	    DDI_PROP_SUCCESS) {
8207c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN, "%s%d can't remove prop %s",
8217c478bd9Sstevel@tonic-gate 		    ddi_driver_name(dip), ddi_get_instance(dip),
8227c478bd9Sstevel@tonic-gate 		    SAVED_CONFIG_REGS_MASK);
8237c478bd9Sstevel@tonic-gate 	}
8247c478bd9Sstevel@tonic-gate 	pci_config_teardown(&confhdl);
8257c478bd9Sstevel@tonic-gate 	return (DDI_FAILURE);
8267c478bd9Sstevel@tonic-gate }
8272df1fe9cSrandyf 
8282df1fe9cSrandyf /*ARGSUSED*/
8292df1fe9cSrandyf static int
8302df1fe9cSrandyf pci_lookup_pmcap(dev_info_t *dip, ddi_acc_handle_t conf_hdl,
831*d083fed0SRichard Lowe     uint16_t *pmcap_offsetp)
8322df1fe9cSrandyf {
8332df1fe9cSrandyf 	uint8_t cap_ptr;
8342df1fe9cSrandyf 	uint8_t cap_id;
8352df1fe9cSrandyf 	uint8_t header_type;
8362df1fe9cSrandyf 	uint16_t status;
8372df1fe9cSrandyf 
8382df1fe9cSrandyf 	header_type = pci_config_get8(conf_hdl, PCI_CONF_HEADER);
8392df1fe9cSrandyf 	header_type &= PCI_HEADER_TYPE_M;
8402df1fe9cSrandyf 
8412df1fe9cSrandyf 	/* we don't deal with bridges, etc here */
8422df1fe9cSrandyf 	if (header_type != PCI_HEADER_ZERO) {
8432df1fe9cSrandyf 		return (DDI_FAILURE);
8442df1fe9cSrandyf 	}
8452df1fe9cSrandyf 
8462df1fe9cSrandyf 	status = pci_config_get16(conf_hdl, PCI_CONF_STAT);
8472df1fe9cSrandyf 	if ((status & PCI_STAT_CAP) == 0) {
8482df1fe9cSrandyf 		return (DDI_FAILURE);
8492df1fe9cSrandyf 	}
8502df1fe9cSrandyf 
8512df1fe9cSrandyf 	cap_ptr = pci_config_get8(conf_hdl, PCI_CONF_CAP_PTR);
8522df1fe9cSrandyf 
8532df1fe9cSrandyf 	/*
8542df1fe9cSrandyf 	 * Walk the capabilities searching for a PM entry.
8552df1fe9cSrandyf 	 */
8562df1fe9cSrandyf 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
8572df1fe9cSrandyf 		cap_id = pci_config_get8(conf_hdl, cap_ptr + PCI_CAP_ID);
8582df1fe9cSrandyf 		if (cap_id == PCI_CAP_ID_PM) {
8592df1fe9cSrandyf 			break;
8602df1fe9cSrandyf 		}
8612df1fe9cSrandyf 		cap_ptr = pci_config_get8(conf_hdl,
8622df1fe9cSrandyf 		    cap_ptr + PCI_CAP_NEXT_PTR);
8632df1fe9cSrandyf 	}
8642df1fe9cSrandyf 
8652df1fe9cSrandyf 	if (cap_ptr == PCI_CAP_NEXT_PTR_NULL) {
8662df1fe9cSrandyf 		return (DDI_FAILURE);
8672df1fe9cSrandyf 	}
8682df1fe9cSrandyf 	*pmcap_offsetp = cap_ptr;
8692df1fe9cSrandyf 	return (DDI_SUCCESS);
8702df1fe9cSrandyf }
8712df1fe9cSrandyf 
8722df1fe9cSrandyf /*
8732df1fe9cSrandyf  * Do common pci-specific suspend actions:
8742df1fe9cSrandyf  *  - enable wakeup if appropriate for the device
8752df1fe9cSrandyf  *  - put device in lowest D-state that supports wakeup, or D3 if none
8762df1fe9cSrandyf  *  - turn off bus mastering in control register
8772df1fe9cSrandyf  * For lack of per-dip storage (parent private date is pretty busy)
8782df1fe9cSrandyf  * we use properties to store the necessary context
8792df1fe9cSrandyf  * To avoid grotting through pci config space on every suspend,
8802df1fe9cSrandyf  * we leave the prop in existence after resume, cause we know that
8812df1fe9cSrandyf  * the detach framework code will dispose of it for us.
8822df1fe9cSrandyf  */
8832df1fe9cSrandyf 
8842df1fe9cSrandyf typedef struct pci_pm_context {
8852df1fe9cSrandyf 	int		ppc_flags;
8862df1fe9cSrandyf 	uint16_t	ppc_cap_offset;	/* offset in config space to pm cap */
8872df1fe9cSrandyf 	uint16_t	ppc_pmcsr;	/* need this too */
8882df1fe9cSrandyf 	uint16_t	ppc_suspend_level;
8892df1fe9cSrandyf } pci_pm_context_t;
8902df1fe9cSrandyf 
8912df1fe9cSrandyf #define	SAVED_PM_CONTEXT	"pci-pm-context"
8922df1fe9cSrandyf 
8932df1fe9cSrandyf /* values for ppc_flags	*/
8942df1fe9cSrandyf #define	PPCF_NOPMCAP	1
8952df1fe9cSrandyf 
8962df1fe9cSrandyf /*
8972df1fe9cSrandyf  * Handle pci-specific suspend processing
8982df1fe9cSrandyf  *   PM CSR and PCI CMD are saved by pci_save_config_regs().
8992df1fe9cSrandyf  *   If device can wake up system via PME, enable it to do so
9002df1fe9cSrandyf  *   Set device power level to lowest that can generate PME, or D3 if none can
9012df1fe9cSrandyf  *   Turn off bus master enable in pci command register
9022df1fe9cSrandyf  */
9032df1fe9cSrandyf #if defined(__x86)
9042df1fe9cSrandyf extern int acpi_ddi_setwake(dev_info_t *dip, int level);
9052df1fe9cSrandyf #endif
9062df1fe9cSrandyf 
9072df1fe9cSrandyf int
908