17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 54ab75253Smrj * Common Development and Distribution License (the "License"). 64ab75253Smrj * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 214ab75253Smrj 227c478bd9Sstevel@tonic-gate /* 23*abee7076Sgs * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #include <sys/types.h> 307c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 3100d0963fSdilpreet #include <sys/sysmacros.h> 327c478bd9Sstevel@tonic-gate #include <sys/pci.h> 339164eb65Stimh #include <sys/pcie.h> 347c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h> 357c478bd9Sstevel@tonic-gate #include <sys/epm.h> 367c478bd9Sstevel@tonic-gate 377c478bd9Sstevel@tonic-gate int 387c478bd9Sstevel@tonic-gate pci_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle) 397c478bd9Sstevel@tonic-gate { 407c478bd9Sstevel@tonic-gate caddr_t cfgaddr; 417c478bd9Sstevel@tonic-gate ddi_device_acc_attr_t attr; 427c478bd9Sstevel@tonic-gate 437c478bd9Sstevel@tonic-gate attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 447c478bd9Sstevel@tonic-gate attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 457c478bd9Sstevel@tonic-gate attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 467c478bd9Sstevel@tonic-gate 477c478bd9Sstevel@tonic-gate /* Check for fault management capabilities */ 4800d0963fSdilpreet if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(dip))) { 4900d0963fSdilpreet attr.devacc_attr_version = DDI_DEVICE_ATTR_V1; 507c478bd9Sstevel@tonic-gate attr.devacc_attr_access = DDI_FLAGERR_ACC; 5100d0963fSdilpreet } 527c478bd9Sstevel@tonic-gate 537c478bd9Sstevel@tonic-gate return (ddi_regs_map_setup(dip, 0, &cfgaddr, 0, 0, &attr, handle)); 547c478bd9Sstevel@tonic-gate } 557c478bd9Sstevel@tonic-gate 567c478bd9Sstevel@tonic-gate void 577c478bd9Sstevel@tonic-gate pci_config_teardown(ddi_acc_handle_t *handle) 587c478bd9Sstevel@tonic-gate { 597c478bd9Sstevel@tonic-gate ddi_regs_map_free(handle); 607c478bd9Sstevel@tonic-gate } 617c478bd9Sstevel@tonic-gate 627c478bd9Sstevel@tonic-gate uint8_t 637c478bd9Sstevel@tonic-gate pci_config_get8(ddi_acc_handle_t handle, off_t offset) 647c478bd9Sstevel@tonic-gate { 657c478bd9Sstevel@tonic-gate caddr_t cfgaddr; 667c478bd9Sstevel@tonic-gate ddi_acc_hdl_t *hp; 677c478bd9Sstevel@tonic-gate 687c478bd9Sstevel@tonic-gate hp = impl_acc_hdl_get(handle); 697c478bd9Sstevel@tonic-gate cfgaddr = hp->ah_addr + offset; 707c478bd9Sstevel@tonic-gate return (ddi_get8(handle, (uint8_t *)cfgaddr)); 717c478bd9Sstevel@tonic-gate } 727c478bd9Sstevel@tonic-gate 737c478bd9Sstevel@tonic-gate uint16_t 747c478bd9Sstevel@tonic-gate pci_config_get16(ddi_acc_handle_t handle, off_t offset) 757c478bd9Sstevel@tonic-gate { 767c478bd9Sstevel@tonic-gate caddr_t cfgaddr; 777c478bd9Sstevel@tonic-gate ddi_acc_hdl_t *hp; 787c478bd9Sstevel@tonic-gate 797c478bd9Sstevel@tonic-gate hp = impl_acc_hdl_get(handle); 807c478bd9Sstevel@tonic-gate cfgaddr = hp->ah_addr + offset; 817c478bd9Sstevel@tonic-gate return (ddi_get16(handle, (uint16_t *)cfgaddr)); 827c478bd9Sstevel@tonic-gate } 837c478bd9Sstevel@tonic-gate 847c478bd9Sstevel@tonic-gate uint32_t 857c478bd9Sstevel@tonic-gate pci_config_get32(ddi_acc_handle_t handle, off_t offset) 867c478bd9Sstevel@tonic-gate { 877c478bd9Sstevel@tonic-gate caddr_t cfgaddr; 887c478bd9Sstevel@tonic-gate ddi_acc_hdl_t *hp; 897c478bd9Sstevel@tonic-gate 907c478bd9Sstevel@tonic-gate hp = impl_acc_hdl_get(handle); 917c478bd9Sstevel@tonic-gate cfgaddr = hp->ah_addr + offset; 927c478bd9Sstevel@tonic-gate return (ddi_get32(handle, (uint32_t *)cfgaddr)); 937c478bd9Sstevel@tonic-gate } 947c478bd9Sstevel@tonic-gate 957c478bd9Sstevel@tonic-gate uint64_t 967c478bd9Sstevel@tonic-gate pci_config_get64(ddi_acc_handle_t handle, off_t offset) 977c478bd9Sstevel@tonic-gate { 987c478bd9Sstevel@tonic-gate caddr_t cfgaddr; 997c478bd9Sstevel@tonic-gate ddi_acc_hdl_t *hp; 1007c478bd9Sstevel@tonic-gate 1017c478bd9Sstevel@tonic-gate hp = impl_acc_hdl_get(handle); 1027c478bd9Sstevel@tonic-gate cfgaddr = hp->ah_addr + offset; 1037c478bd9Sstevel@tonic-gate return (ddi_get64(handle, (uint64_t *)cfgaddr)); 1047c478bd9Sstevel@tonic-gate } 1057c478bd9Sstevel@tonic-gate 1067c478bd9Sstevel@tonic-gate void 1077c478bd9Sstevel@tonic-gate pci_config_put8(ddi_acc_handle_t handle, off_t offset, uint8_t value) 1087c478bd9Sstevel@tonic-gate { 1097c478bd9Sstevel@tonic-gate caddr_t cfgaddr; 1107c478bd9Sstevel@tonic-gate ddi_acc_hdl_t *hp; 1117c478bd9Sstevel@tonic-gate 1127c478bd9Sstevel@tonic-gate hp = impl_acc_hdl_get(handle); 1137c478bd9Sstevel@tonic-gate cfgaddr = hp->ah_addr + offset; 1147c478bd9Sstevel@tonic-gate ddi_put8(handle, (uint8_t *)cfgaddr, value); 1157c478bd9Sstevel@tonic-gate } 1167c478bd9Sstevel@tonic-gate 1177c478bd9Sstevel@tonic-gate void 1187c478bd9Sstevel@tonic-gate pci_config_put16(ddi_acc_handle_t handle, off_t offset, uint16_t value) 1197c478bd9Sstevel@tonic-gate { 1207c478bd9Sstevel@tonic-gate caddr_t cfgaddr; 1217c478bd9Sstevel@tonic-gate ddi_acc_hdl_t *hp; 1227c478bd9Sstevel@tonic-gate 1237c478bd9Sstevel@tonic-gate hp = impl_acc_hdl_get(handle); 1247c478bd9Sstevel@tonic-gate cfgaddr = hp->ah_addr + offset; 1257c478bd9Sstevel@tonic-gate ddi_put16(handle, (uint16_t *)cfgaddr, value); 1267c478bd9Sstevel@tonic-gate } 1277c478bd9Sstevel@tonic-gate 1287c478bd9Sstevel@tonic-gate void 1297c478bd9Sstevel@tonic-gate pci_config_put32(ddi_acc_handle_t handle, off_t offset, uint32_t value) 1307c478bd9Sstevel@tonic-gate { 1317c478bd9Sstevel@tonic-gate caddr_t cfgaddr; 1327c478bd9Sstevel@tonic-gate ddi_acc_hdl_t *hp; 1337c478bd9Sstevel@tonic-gate 1347c478bd9Sstevel@tonic-gate hp = impl_acc_hdl_get(handle); 1357c478bd9Sstevel@tonic-gate cfgaddr = hp->ah_addr + offset; 1367c478bd9Sstevel@tonic-gate ddi_put32(handle, (uint32_t *)cfgaddr, value); 1377c478bd9Sstevel@tonic-gate } 1387c478bd9Sstevel@tonic-gate 1397c478bd9Sstevel@tonic-gate void 1407c478bd9Sstevel@tonic-gate pci_config_put64(ddi_acc_handle_t handle, off_t offset, uint64_t value) 1414ab75253Smrj { 1424ab75253Smrj caddr_t cfgaddr; 1434ab75253Smrj ddi_acc_hdl_t *hp; 1444ab75253Smrj 1454ab75253Smrj hp = impl_acc_hdl_get(handle); 1464ab75253Smrj cfgaddr = hp->ah_addr + offset; 1474ab75253Smrj ddi_put64(handle, (uint64_t *)cfgaddr, value); 1484ab75253Smrj } 1494ab75253Smrj 1504ab75253Smrj /* 1514ab75253Smrj * We need to separate the old interfaces from the new ones and leave them 1524ab75253Smrj * in here for a while. Previous versions of the OS defined the new interfaces 1534ab75253Smrj * to the old interfaces. This way we can fix things up so that we can 1544ab75253Smrj * eventually remove these interfaces. 1554ab75253Smrj * e.g. A 3rd party module/driver using pci_config_get8 and built against S10 1564ab75253Smrj * or earlier will actually have a reference to pci_config_getb in the binary. 1574ab75253Smrj */ 1584ab75253Smrj #ifdef _ILP32 1594ab75253Smrj uint8_t 1604ab75253Smrj pci_config_getb(ddi_acc_handle_t handle, off_t offset) 1614ab75253Smrj { 1624ab75253Smrj caddr_t cfgaddr; 1634ab75253Smrj ddi_acc_hdl_t *hp; 1644ab75253Smrj 1654ab75253Smrj hp = impl_acc_hdl_get(handle); 1664ab75253Smrj cfgaddr = hp->ah_addr + offset; 1674ab75253Smrj return (ddi_get8(handle, (uint8_t *)cfgaddr)); 1684ab75253Smrj } 1694ab75253Smrj 1704ab75253Smrj uint16_t 1714ab75253Smrj pci_config_getw(ddi_acc_handle_t handle, off_t offset) 1724ab75253Smrj { 1734ab75253Smrj caddr_t cfgaddr; 1744ab75253Smrj ddi_acc_hdl_t *hp; 1754ab75253Smrj 1764ab75253Smrj hp = impl_acc_hdl_get(handle); 1774ab75253Smrj cfgaddr = hp->ah_addr + offset; 1784ab75253Smrj return (ddi_get16(handle, (uint16_t *)cfgaddr)); 1794ab75253Smrj } 1804ab75253Smrj 1814ab75253Smrj uint32_t 1824ab75253Smrj pci_config_getl(ddi_acc_handle_t handle, off_t offset) 1834ab75253Smrj { 1844ab75253Smrj caddr_t cfgaddr; 1854ab75253Smrj ddi_acc_hdl_t *hp; 1864ab75253Smrj 1874ab75253Smrj hp = impl_acc_hdl_get(handle); 1884ab75253Smrj cfgaddr = hp->ah_addr + offset; 1894ab75253Smrj return (ddi_get32(handle, (uint32_t *)cfgaddr)); 1904ab75253Smrj } 1914ab75253Smrj 1924ab75253Smrj uint64_t 1934ab75253Smrj pci_config_getll(ddi_acc_handle_t handle, off_t offset) 1944ab75253Smrj { 1954ab75253Smrj caddr_t cfgaddr; 1964ab75253Smrj ddi_acc_hdl_t *hp; 1974ab75253Smrj 1984ab75253Smrj hp = impl_acc_hdl_get(handle); 1994ab75253Smrj cfgaddr = hp->ah_addr + offset; 2004ab75253Smrj return (ddi_get64(handle, (uint64_t *)cfgaddr)); 2014ab75253Smrj } 2024ab75253Smrj 2034ab75253Smrj void 2044ab75253Smrj pci_config_putb(ddi_acc_handle_t handle, off_t offset, uint8_t value) 2054ab75253Smrj { 2064ab75253Smrj caddr_t cfgaddr; 2074ab75253Smrj ddi_acc_hdl_t *hp; 2084ab75253Smrj 2094ab75253Smrj hp = impl_acc_hdl_get(handle); 2104ab75253Smrj cfgaddr = hp->ah_addr + offset; 2114ab75253Smrj ddi_put8(handle, (uint8_t *)cfgaddr, value); 2124ab75253Smrj } 2134ab75253Smrj 2144ab75253Smrj void 2154ab75253Smrj pci_config_putw(ddi_acc_handle_t handle, off_t offset, uint16_t value) 2164ab75253Smrj { 2174ab75253Smrj caddr_t cfgaddr; 2184ab75253Smrj ddi_acc_hdl_t *hp; 2194ab75253Smrj 2204ab75253Smrj hp = impl_acc_hdl_get(handle); 2214ab75253Smrj cfgaddr = hp->ah_addr + offset; 2224ab75253Smrj ddi_put16(handle, (uint16_t *)cfgaddr, value); 2234ab75253Smrj } 2244ab75253Smrj 2254ab75253Smrj void 2264ab75253Smrj pci_config_putl(ddi_acc_handle_t handle, off_t offset, uint32_t value) 2274ab75253Smrj { 2284ab75253Smrj caddr_t cfgaddr; 2294ab75253Smrj ddi_acc_hdl_t *hp; 2304ab75253Smrj 2314ab75253Smrj hp = impl_acc_hdl_get(handle); 2324ab75253Smrj cfgaddr = hp->ah_addr + offset; 2334ab75253Smrj ddi_put32(handle, (uint32_t *)cfgaddr, value); 2344ab75253Smrj } 2354ab75253Smrj 2367c478bd9Sstevel@tonic-gate void 2377c478bd9Sstevel@tonic-gate pci_config_putll(ddi_acc_handle_t handle, off_t offset, uint64_t value) 2387c478bd9Sstevel@tonic-gate { 2397c478bd9Sstevel@tonic-gate caddr_t cfgaddr; 2407c478bd9Sstevel@tonic-gate ddi_acc_hdl_t *hp; 2417c478bd9Sstevel@tonic-gate 2427c478bd9Sstevel@tonic-gate hp = impl_acc_hdl_get(handle); 2437c478bd9Sstevel@tonic-gate cfgaddr = hp->ah_addr + offset; 2447c478bd9Sstevel@tonic-gate ddi_put64(handle, (uint64_t *)cfgaddr, value); 2457c478bd9Sstevel@tonic-gate } 2464ab75253Smrj #endif /* _ILP32 */ 2477c478bd9Sstevel@tonic-gate 2487c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 2497c478bd9Sstevel@tonic-gate int 2507c478bd9Sstevel@tonic-gate pci_report_pmcap(dev_info_t *dip, int cap, void *arg) 2517c478bd9Sstevel@tonic-gate { 2527c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 2537c478bd9Sstevel@tonic-gate } 2547c478bd9Sstevel@tonic-gate 2557c478bd9Sstevel@tonic-gate /* 2567c478bd9Sstevel@tonic-gate * Note about saving and restoring config space. 2577c478bd9Sstevel@tonic-gate * PCI devices have only upto 256 bytes of config space while PCI Express 2587c478bd9Sstevel@tonic-gate * devices can have upto 4k config space. In case of PCI Express device, 2597c478bd9Sstevel@tonic-gate * we save all 4k config space and restore it even if it doesn't make use 2607c478bd9Sstevel@tonic-gate * of all 4k. But some devices don't respond to reads to non-existent 2617c478bd9Sstevel@tonic-gate * registers within the config space. To avoid any panics, we use ddi_peek 2627c478bd9Sstevel@tonic-gate * to do the reads. A bit mask is used to indicate which words of the 2637c478bd9Sstevel@tonic-gate * config space are accessible. While restoring the config space, only those 2647c478bd9Sstevel@tonic-gate * readable words are restored. We do all this in 32 bit size words. 2657c478bd9Sstevel@tonic-gate */ 2667c478bd9Sstevel@tonic-gate #define INDEX_SHIFT 3 2677c478bd9Sstevel@tonic-gate #define BITMASK 0x7 2687c478bd9Sstevel@tonic-gate 2697c478bd9Sstevel@tonic-gate static uint32_t pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 2707c478bd9Sstevel@tonic-gate pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp); 2717c478bd9Sstevel@tonic-gate static void pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 2727c478bd9Sstevel@tonic-gate pci_cap_save_desc_t *cap_descp, uint32_t elements); 2737c478bd9Sstevel@tonic-gate static uint32_t pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 2747c478bd9Sstevel@tonic-gate uint32_t *regbuf, uint32_t nwords); 2757c478bd9Sstevel@tonic-gate static uint32_t pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 2767c478bd9Sstevel@tonic-gate uint32_t *regbuf, uint32_t notused); 2777c478bd9Sstevel@tonic-gate static uint32_t pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 2787c478bd9Sstevel@tonic-gate uint32_t *regbuf, uint32_t notused); 2797c478bd9Sstevel@tonic-gate static uint32_t pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 2807c478bd9Sstevel@tonic-gate uint32_t *regbuf, uint32_t notused); 2817c478bd9Sstevel@tonic-gate static void pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 2827c478bd9Sstevel@tonic-gate uint32_t *regbuf, uint32_t nwords); 2837c478bd9Sstevel@tonic-gate static uint32_t cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf, 2847c478bd9Sstevel@tonic-gate pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace); 2857c478bd9Sstevel@tonic-gate static void pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf, 2867c478bd9Sstevel@tonic-gate uint16_t pmcap_offset); 2877c478bd9Sstevel@tonic-gate 2887c478bd9Sstevel@tonic-gate /* 2897c478bd9Sstevel@tonic-gate * Table below specifies the number of registers to be saved for each PCI 2907c478bd9Sstevel@tonic-gate * capability. pci_generic_save saves the number of words specified in the 2917c478bd9Sstevel@tonic-gate * table. Any special considerations will be taken care by the capability 2927c478bd9Sstevel@tonic-gate * specific save function e.g. use pci_msi_save to save registers associated 2937c478bd9Sstevel@tonic-gate * with MSI capability. PCI_UNKNOWN_SIZE indicates that number of registers 2947c478bd9Sstevel@tonic-gate * to be saved is variable and will be determined by the specific save function. 2957c478bd9Sstevel@tonic-gate * Currently we save/restore all the registers associated with the capability 2967c478bd9Sstevel@tonic-gate * including read only registers. Regsiters are saved and restored in 32 bit 2977c478bd9Sstevel@tonic-gate * size words. 2987c478bd9Sstevel@tonic-gate */ 2997c478bd9Sstevel@tonic-gate static pci_cap_entry_t pci_cap_table[] = { 3007c478bd9Sstevel@tonic-gate {PCI_CAP_ID_PM, PCI_PMCAP_NDWORDS, pci_generic_save}, 3017c478bd9Sstevel@tonic-gate {PCI_CAP_ID_AGP, PCI_AGP_NDWORDS, pci_generic_save}, 3027c478bd9Sstevel@tonic-gate {PCI_CAP_ID_SLOT_ID, PCI_SLOTID_NDWORDS, pci_generic_save}, 3037c478bd9Sstevel@tonic-gate {PCI_CAP_ID_MSI_X, PCI_MSIX_NDWORDS, pci_generic_save}, 3047c478bd9Sstevel@tonic-gate {PCI_CAP_ID_MSI, PCI_CAP_SZUNKNOWN, pci_msi_save}, 3057c478bd9Sstevel@tonic-gate {PCI_CAP_ID_PCIX, PCI_CAP_SZUNKNOWN, pci_pcix_save}, 3067c478bd9Sstevel@tonic-gate {PCI_CAP_ID_PCI_E, PCI_CAP_SZUNKNOWN, pci_pcie_save}, 3077c478bd9Sstevel@tonic-gate /* 3087c478bd9Sstevel@tonic-gate * {PCI_CAP_ID_cPCI_CRC, 0, NULL}, 3097c478bd9Sstevel@tonic-gate * {PCI_CAP_ID_VPD, 0, NULL}, 3107c478bd9Sstevel@tonic-gate * {PCI_CAP_ID_cPCI_HS, 0, NULL}, 3117c478bd9Sstevel@tonic-gate * {PCI_CAP_ID_PCI_HOTPLUG, 0, NULL}, 3127c478bd9Sstevel@tonic-gate * {PCI_CAP_ID_AGP_8X, 0, NULL}, 3137c478bd9Sstevel@tonic-gate * {PCI_CAP_ID_SECURE_DEV, 0, NULL}, 3147c478bd9Sstevel@tonic-gate */ 3157c478bd9Sstevel@tonic-gate {PCI_CAP_NEXT_PTR_NULL, 0, NULL} 3167c478bd9Sstevel@tonic-gate }; 3177c478bd9Sstevel@tonic-gate 3187c478bd9Sstevel@tonic-gate /* 3197c478bd9Sstevel@tonic-gate * Save the configuration registers for cdip as a property 3207c478bd9Sstevel@tonic-gate * so that it persists after detach/uninitchild. 3217c478bd9Sstevel@tonic-gate */ 3227c478bd9Sstevel@tonic-gate int 3237c478bd9Sstevel@tonic-gate pci_save_config_regs(dev_info_t *dip) 3247c478bd9Sstevel@tonic-gate { 325*abee7076Sgs peekpoke_ctlops_t cautacc_ctlops_arg; 3267c478bd9Sstevel@tonic-gate ddi_acc_handle_t confhdl; 3277c478bd9Sstevel@tonic-gate pci_config_header_state_t *chsp; 3287c478bd9Sstevel@tonic-gate pci_cap_save_desc_t *pci_cap_descp; 3297c478bd9Sstevel@tonic-gate int ret; 3307c478bd9Sstevel@tonic-gate uint32_t i, ncaps, nwords; 3317c478bd9Sstevel@tonic-gate uint32_t *regbuf, *p; 3327c478bd9Sstevel@tonic-gate uint8_t *maskbuf; 3337c478bd9Sstevel@tonic-gate size_t maskbufsz, regbufsz, capbufsz; 3347c478bd9Sstevel@tonic-gate ddi_acc_hdl_t *hp; 3357c478bd9Sstevel@tonic-gate off_t offset = 0; 3367c478bd9Sstevel@tonic-gate uint8_t cap_ptr, cap_id; 3377c478bd9Sstevel@tonic-gate int pcie = 0; 3382df1fe9cSrandyf PMD(PMD_SX, ("pci_save_config_regs %s:%d\n", ddi_driver_name(dip), 3392df1fe9cSrandyf ddi_get_instance(dip))) 3407c478bd9Sstevel@tonic-gate 3417c478bd9Sstevel@tonic-gate if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) { 3427c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d can't get config handle", 3432df1fe9cSrandyf ddi_driver_name(dip), ddi_get_instance(dip)); 3447c478bd9Sstevel@tonic-gate 3457c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 3467c478bd9Sstevel@tonic-gate } 3477c478bd9Sstevel@tonic-gate /* 3487c478bd9Sstevel@tonic-gate * Determine if it is a pci express device. If it is, save entire 3497c478bd9Sstevel@tonic-gate * 4k config space treating it as a array of 32 bit integers. 3507c478bd9Sstevel@tonic-gate * If it is not, do it in a usual PCI way. 3517c478bd9Sstevel@tonic-gate */ 3527c478bd9Sstevel@tonic-gate cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR); 3537c478bd9Sstevel@tonic-gate /* 3547c478bd9Sstevel@tonic-gate * Walk the capabilities searching for pci express capability 3557c478bd9Sstevel@tonic-gate */ 3567c478bd9Sstevel@tonic-gate while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 3577c478bd9Sstevel@tonic-gate cap_id = pci_config_get8(confhdl, 3587c478bd9Sstevel@tonic-gate cap_ptr + PCI_CAP_ID); 3597c478bd9Sstevel@tonic-gate if (cap_id == PCI_CAP_ID_PCI_E) { 3607c478bd9Sstevel@tonic-gate pcie = 1; 3617c478bd9Sstevel@tonic-gate break; 3627c478bd9Sstevel@tonic-gate } 3637c478bd9Sstevel@tonic-gate cap_ptr = pci_config_get8(confhdl, 3647c478bd9Sstevel@tonic-gate cap_ptr + PCI_CAP_NEXT_PTR); 3657c478bd9Sstevel@tonic-gate } 3667c478bd9Sstevel@tonic-gate 3677c478bd9Sstevel@tonic-gate if (pcie) { 3687c478bd9Sstevel@tonic-gate /* PCI express device. Can have data in all 4k space */ 3697c478bd9Sstevel@tonic-gate regbuf = (uint32_t *)kmem_zalloc((size_t)PCIE_CONF_HDR_SIZE, 3702df1fe9cSrandyf KM_SLEEP); 3717c478bd9Sstevel@tonic-gate p = regbuf; 3727c478bd9Sstevel@tonic-gate /* 3737c478bd9Sstevel@tonic-gate * Allocate space for mask. 3747c478bd9Sstevel@tonic-gate * mask size is 128 bytes (4096 / 4 / 8 ) 3757c478bd9Sstevel@tonic-gate */ 3767c478bd9Sstevel@tonic-gate maskbufsz = (size_t)((PCIE_CONF_HDR_SIZE/ sizeof (uint32_t)) >> 3777c478bd9Sstevel@tonic-gate INDEX_SHIFT); 3787c478bd9Sstevel@tonic-gate maskbuf = (uint8_t *)kmem_zalloc(maskbufsz, KM_SLEEP); 3797c478bd9Sstevel@tonic-gate hp = impl_acc_hdl_get(confhdl); 380*abee7076Sgs cautacc_ctlops_arg.size = sizeof (uint32_t); 381*abee7076Sgs cautacc_ctlops_arg.handle = confhdl; 382*abee7076Sgs cautacc_ctlops_arg.repcount = 1; 383*abee7076Sgs cautacc_ctlops_arg.flags = 0; 3847c478bd9Sstevel@tonic-gate for (i = 0; i < (PCIE_CONF_HDR_SIZE / sizeof (uint32_t)); i++) { 385*abee7076Sgs cautacc_ctlops_arg.dev_addr = (uintptr_t)(hp->ah_addr + 386*abee7076Sgs offset); 387*abee7076Sgs cautacc_ctlops_arg.host_addr = (uintptr_t)p; 388*abee7076Sgs ret = ddi_ctlops(dip, dip, DDI_CTLOPS_PEEK, 389*abee7076Sgs &cautacc_ctlops_arg, NULL); 390*abee7076Sgs if (ret == DDI_SUCCESS) { 3917c478bd9Sstevel@tonic-gate /* it is readable register. set the bit */ 3927c478bd9Sstevel@tonic-gate maskbuf[i >> INDEX_SHIFT] |= 3937c478bd9Sstevel@tonic-gate (uint8_t)(1 << (i & BITMASK)); 3947c478bd9Sstevel@tonic-gate } 3957c478bd9Sstevel@tonic-gate p++; 3967c478bd9Sstevel@tonic-gate offset += sizeof (uint32_t); 3977c478bd9Sstevel@tonic-gate } 3987c478bd9Sstevel@tonic-gate 3997c478bd9Sstevel@tonic-gate if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 4007c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS_MASK, (uchar_t *)maskbuf, 4017c478bd9Sstevel@tonic-gate maskbufsz)) != DDI_PROP_SUCCESS) { 4027c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "couldn't create %s property while" 4037c478bd9Sstevel@tonic-gate "saving config space for %s@%d\n", 4047c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS_MASK, ddi_driver_name(dip), 4057c478bd9Sstevel@tonic-gate ddi_get_instance(dip)); 4067c478bd9Sstevel@tonic-gate } else if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, 4077c478bd9Sstevel@tonic-gate dip, SAVED_CONFIG_REGS, (uchar_t *)regbuf, 4087c478bd9Sstevel@tonic-gate (size_t)PCIE_CONF_HDR_SIZE)) != DDI_PROP_SUCCESS) { 4097c478bd9Sstevel@tonic-gate (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 4107c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS_MASK); 4117c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d can't update prop %s", 4127c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 4137c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS); 4147c478bd9Sstevel@tonic-gate } 4157c478bd9Sstevel@tonic-gate 4167c478bd9Sstevel@tonic-gate kmem_free(maskbuf, (size_t)maskbufsz); 4177c478bd9Sstevel@tonic-gate kmem_free(regbuf, (size_t)PCIE_CONF_HDR_SIZE); 4187c478bd9Sstevel@tonic-gate } else { 4197c478bd9Sstevel@tonic-gate regbuf = (uint32_t *)kmem_zalloc((size_t)PCI_CONF_HDR_SIZE, 4202df1fe9cSrandyf KM_SLEEP); 4217c478bd9Sstevel@tonic-gate chsp = (pci_config_header_state_t *)regbuf; 4227c478bd9Sstevel@tonic-gate 4237c478bd9Sstevel@tonic-gate chsp->chs_command = pci_config_get16(confhdl, PCI_CONF_COMM); 4247c478bd9Sstevel@tonic-gate chsp->chs_header_type = pci_config_get8(confhdl, 4252df1fe9cSrandyf PCI_CONF_HEADER); 4267c478bd9Sstevel@tonic-gate if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) == 4277c478bd9Sstevel@tonic-gate PCI_HEADER_ONE) 4287c478bd9Sstevel@tonic-gate chsp->chs_bridge_control = 4297c478bd9Sstevel@tonic-gate pci_config_get16(confhdl, PCI_BCNF_BCNTRL); 4307c478bd9Sstevel@tonic-gate chsp->chs_cache_line_size = pci_config_get8(confhdl, 4317c478bd9Sstevel@tonic-gate PCI_CONF_CACHE_LINESZ); 4327c478bd9Sstevel@tonic-gate chsp->chs_latency_timer = pci_config_get8(confhdl, 4337c478bd9Sstevel@tonic-gate PCI_CONF_LATENCY_TIMER); 4347c478bd9Sstevel@tonic-gate if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) == 4357c478bd9Sstevel@tonic-gate PCI_HEADER_ONE) { 4367c478bd9Sstevel@tonic-gate chsp->chs_sec_latency_timer = 4377c478bd9Sstevel@tonic-gate pci_config_get8(confhdl, PCI_BCNF_LATENCY_TIMER); 4387c478bd9Sstevel@tonic-gate } 4397c478bd9Sstevel@tonic-gate 4407c478bd9Sstevel@tonic-gate chsp->chs_base0 = pci_config_get32(confhdl, PCI_CONF_BASE0); 4417c478bd9Sstevel@tonic-gate chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1); 4427c478bd9Sstevel@tonic-gate chsp->chs_base2 = pci_config_get32(confhdl, PCI_CONF_BASE2); 4437c478bd9Sstevel@tonic-gate chsp->chs_base3 = pci_config_get32(confhdl, PCI_CONF_BASE3); 4447c478bd9Sstevel@tonic-gate chsp->chs_base4 = pci_config_get32(confhdl, PCI_CONF_BASE4); 4457c478bd9Sstevel@tonic-gate chsp->chs_base5 = pci_config_get32(confhdl, PCI_CONF_BASE5); 4467c478bd9Sstevel@tonic-gate 4477c478bd9Sstevel@tonic-gate /* 4487c478bd9Sstevel@tonic-gate * Allocate maximum space required for capability descriptions. 4497c478bd9Sstevel@tonic-gate * The maximum number of capabilties saved is the number of 4507c478bd9Sstevel@tonic-gate * capabilities listed in the pci_cap_table. 4517c478bd9Sstevel@tonic-gate */ 4527c478bd9Sstevel@tonic-gate ncaps = (sizeof (pci_cap_table) / sizeof (pci_cap_entry_t)); 4537c478bd9Sstevel@tonic-gate capbufsz = ncaps * sizeof (pci_cap_save_desc_t); 4547c478bd9Sstevel@tonic-gate pci_cap_descp = (pci_cap_save_desc_t *)kmem_zalloc( 4557c478bd9Sstevel@tonic-gate capbufsz, KM_SLEEP); 4567c478bd9Sstevel@tonic-gate p = (uint32_t *)((caddr_t)regbuf + 4577c478bd9Sstevel@tonic-gate sizeof (pci_config_header_state_t)); 4587c478bd9Sstevel@tonic-gate nwords = pci_save_caps(confhdl, p, pci_cap_descp, &ncaps); 4597c478bd9Sstevel@tonic-gate regbufsz = sizeof (pci_config_header_state_t) + 4607c478bd9Sstevel@tonic-gate nwords * sizeof (uint32_t); 4617c478bd9Sstevel@tonic-gate 4627c478bd9Sstevel@tonic-gate if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 4637c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS, (uchar_t *)regbuf, regbufsz)) != 4647c478bd9Sstevel@tonic-gate DDI_PROP_SUCCESS) { 4657c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d can't update prop %s", 4667c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 4677c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS); 4687c478bd9Sstevel@tonic-gate } else if (ncaps) { 4697c478bd9Sstevel@tonic-gate ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 4707c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS_CAPINFO, (uchar_t *)pci_cap_descp, 4717c478bd9Sstevel@tonic-gate ncaps * sizeof (pci_cap_save_desc_t)); 4727c478bd9Sstevel@tonic-gate if (ret != DDI_PROP_SUCCESS) 4737c478bd9Sstevel@tonic-gate (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 4747c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS); 4757c478bd9Sstevel@tonic-gate } 4767c478bd9Sstevel@tonic-gate kmem_free(regbuf, (size_t)PCI_CONF_HDR_SIZE); 4777c478bd9Sstevel@tonic-gate kmem_free(pci_cap_descp, capbufsz); 4787c478bd9Sstevel@tonic-gate } 4797c478bd9Sstevel@tonic-gate pci_config_teardown(&confhdl); 4807c478bd9Sstevel@tonic-gate 4817c478bd9Sstevel@tonic-gate if (ret != DDI_PROP_SUCCESS) 4827c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 4837c478bd9Sstevel@tonic-gate 4847c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 4857c478bd9Sstevel@tonic-gate } 4867c478bd9Sstevel@tonic-gate 4877c478bd9Sstevel@tonic-gate /* 4887c478bd9Sstevel@tonic-gate * Saves registers associated with PCI capabilities. 4897c478bd9Sstevel@tonic-gate * Returns number of 32 bit words saved. 4907c478bd9Sstevel@tonic-gate * Number of capabilities saved is returned in ncapsp. 4917c478bd9Sstevel@tonic-gate */ 4927c478bd9Sstevel@tonic-gate static uint32_t 4937c478bd9Sstevel@tonic-gate pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 4947c478bd9Sstevel@tonic-gate pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp) 4957c478bd9Sstevel@tonic-gate { 4967c478bd9Sstevel@tonic-gate return (cap_walk_and_save(confhdl, regbuf, cap_descp, ncapsp, 0)); 4977c478bd9Sstevel@tonic-gate } 4987c478bd9Sstevel@tonic-gate 4997c478bd9Sstevel@tonic-gate static uint32_t 5007c478bd9Sstevel@tonic-gate cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf, 5017c478bd9Sstevel@tonic-gate pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace) 5027c478bd9Sstevel@tonic-gate { 5037c478bd9Sstevel@tonic-gate pci_cap_entry_t *pci_cap_entp; 5047c478bd9Sstevel@tonic-gate uint16_t cap_id, offset; 5057c478bd9Sstevel@tonic-gate uint32_t words_saved = 0, nwords = 0; 5067c478bd9Sstevel@tonic-gate uint16_t cap_ptr = PCI_CAP_NEXT_PTR_NULL; 5077c478bd9Sstevel@tonic-gate 5087c478bd9Sstevel@tonic-gate *ncapsp = 0; 5097c478bd9Sstevel@tonic-gate if (!xspace) 5107c478bd9Sstevel@tonic-gate cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR); 5117c478bd9Sstevel@tonic-gate /* 5127c478bd9Sstevel@tonic-gate * Walk the capabilities 5137c478bd9Sstevel@tonic-gate */ 5147c478bd9Sstevel@tonic-gate while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 5157c478bd9Sstevel@tonic-gate cap_id = CAP_ID(confhdl, cap_ptr, xspace); 5167c478bd9Sstevel@tonic-gate /* Search for this cap id in our table */ 5177c478bd9Sstevel@tonic-gate if (!xspace) 5187c478bd9Sstevel@tonic-gate pci_cap_entp = pci_cap_table; 5197c478bd9Sstevel@tonic-gate while (pci_cap_entp->cap_id != PCI_CAP_NEXT_PTR_NULL && 5207c478bd9Sstevel@tonic-gate pci_cap_entp->cap_id != cap_id) 5217c478bd9Sstevel@tonic-gate pci_cap_entp++; 5227c478bd9Sstevel@tonic-gate 5237c478bd9Sstevel@tonic-gate offset = cap_ptr; 5247c478bd9Sstevel@tonic-gate cap_ptr = NEXT_CAP(confhdl, cap_ptr, xspace); 5257c478bd9Sstevel@tonic-gate /* 5267c478bd9Sstevel@tonic-gate * If this cap id is not found in the table, there is nothing 5277c478bd9Sstevel@tonic-gate * to save. 5287c478bd9Sstevel@tonic-gate */ 5297c478bd9Sstevel@tonic-gate if (pci_cap_entp->cap_id == PCI_CAP_NEXT_PTR_NULL) 5307c478bd9Sstevel@tonic-gate continue; 5317c478bd9Sstevel@tonic-gate if (pci_cap_entp->cap_save_func) { 5327c478bd9Sstevel@tonic-gate if ((nwords = pci_cap_entp->cap_save_func(confhdl, 5337c478bd9Sstevel@tonic-gate offset, regbuf, pci_cap_entp->cap_ndwords))) { 5347c478bd9Sstevel@tonic-gate cap_descp->cap_nregs = nwords; 5357c478bd9Sstevel@tonic-gate cap_descp->cap_offset = offset; 5367c478bd9Sstevel@tonic-gate cap_descp->cap_id = cap_id; 5377c478bd9Sstevel@tonic-gate regbuf += nwords; 5387c478bd9Sstevel@tonic-gate cap_descp++; 5397c478bd9Sstevel@tonic-gate words_saved += nwords; 5407c478bd9Sstevel@tonic-gate (*ncapsp)++; 5417c478bd9Sstevel@tonic-gate } 5427c478bd9Sstevel@tonic-gate } 5437c478bd9Sstevel@tonic-gate 5447c478bd9Sstevel@tonic-gate } 5457c478bd9Sstevel@tonic-gate return (words_saved); 5467c478bd9Sstevel@tonic-gate } 5477c478bd9Sstevel@tonic-gate 5487c478bd9Sstevel@tonic-gate static void 5497c478bd9Sstevel@tonic-gate pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 5507c478bd9Sstevel@tonic-gate uint32_t *regbuf, uint32_t nwords) 5517c478bd9Sstevel@tonic-gate { 5527c478bd9Sstevel@tonic-gate int i; 5537c478bd9Sstevel@tonic-gate 5547c478bd9Sstevel@tonic-gate for (i = 0; i < nwords; i++) { 5557c478bd9Sstevel@tonic-gate *regbuf = pci_config_get32(confhdl, cap_ptr); 5567c478bd9Sstevel@tonic-gate regbuf++; 5577c478bd9Sstevel@tonic-gate cap_ptr += 4; 5587c478bd9Sstevel@tonic-gate } 5597c478bd9Sstevel@tonic-gate } 5607c478bd9Sstevel@tonic-gate 5617c478bd9Sstevel@tonic-gate static uint32_t 5627c478bd9Sstevel@tonic-gate pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 5637c478bd9Sstevel@tonic-gate uint32_t nwords) 5647c478bd9Sstevel@tonic-gate { 5657c478bd9Sstevel@tonic-gate pci_fill_buf(confhdl, cap_ptr, regbuf, nwords); 5667c478bd9Sstevel@tonic-gate return (nwords); 5677c478bd9Sstevel@tonic-gate } 5687c478bd9Sstevel@tonic-gate 5697c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 5707c478bd9Sstevel@tonic-gate static uint32_t 5717c478bd9Sstevel@tonic-gate pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 5727c478bd9Sstevel@tonic-gate uint32_t notused) 5737c478bd9Sstevel@tonic-gate { 5747c478bd9Sstevel@tonic-gate uint32_t nwords = PCI_MSI_MIN_WORDS; 5757c478bd9Sstevel@tonic-gate uint16_t msi_ctrl; 5767c478bd9Sstevel@tonic-gate 5777c478bd9Sstevel@tonic-gate /* Figure out how many registers to be saved */ 5787c478bd9Sstevel@tonic-gate msi_ctrl = pci_config_get16(confhdl, cap_ptr + PCI_MSI_CTRL); 5797c478bd9Sstevel@tonic-gate /* If 64 bit address capable add one word */ 5807c478bd9Sstevel@tonic-gate if (msi_ctrl & PCI_MSI_64BIT_MASK) 5817c478bd9Sstevel@tonic-gate nwords++; 5827c478bd9Sstevel@tonic-gate /* If per vector masking capable, add two more words */ 5837c478bd9Sstevel@tonic-gate if (msi_ctrl & PCI_MSI_PVM_MASK) 5847c478bd9Sstevel@tonic-gate nwords += 2; 5857c478bd9Sstevel@tonic-gate pci_fill_buf(confhdl, cap_ptr, regbuf, nwords); 5867c478bd9Sstevel@tonic-gate 5877c478bd9Sstevel@tonic-gate return (nwords); 5887c478bd9Sstevel@tonic-gate } 5897c478bd9Sstevel@tonic-gate 5907c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 5917c478bd9Sstevel@tonic-gate static uint32_t 5927c478bd9Sstevel@tonic-gate pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 5937c478bd9Sstevel@tonic-gate uint32_t notused) 5947c478bd9Sstevel@tonic-gate { 5957c478bd9Sstevel@tonic-gate uint32_t nwords = PCI_PCIX_MIN_WORDS; 5967c478bd9Sstevel@tonic-gate uint16_t pcix_command; 5977c478bd9Sstevel@tonic-gate 5987c478bd9Sstevel@tonic-gate /* Figure out how many registers to be saved */ 5997c478bd9Sstevel@tonic-gate pcix_command = pci_config_get16(confhdl, cap_ptr + PCI_PCIX_COMMAND); 6007c478bd9Sstevel@tonic-gate /* If it is version 1 or version 2, add 4 words */ 6017c478bd9Sstevel@tonic-gate if (((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_1) || 6027c478bd9Sstevel@tonic-gate ((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_2)) 6037c478bd9Sstevel@tonic-gate nwords += 4; 6047c478bd9Sstevel@tonic-gate pci_fill_buf(confhdl, cap_ptr, regbuf, nwords); 6057c478bd9Sstevel@tonic-gate 6067c478bd9Sstevel@tonic-gate return (nwords); 6077c478bd9Sstevel@tonic-gate } 6087c478bd9Sstevel@tonic-gate 6097c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 6107c478bd9Sstevel@tonic-gate static uint32_t 6117c478bd9Sstevel@tonic-gate pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 6127c478bd9Sstevel@tonic-gate uint32_t notused) 6137c478bd9Sstevel@tonic-gate { 6147c478bd9Sstevel@tonic-gate return (0); 6157c478bd9Sstevel@tonic-gate } 6167c478bd9Sstevel@tonic-gate 6177c478bd9Sstevel@tonic-gate static void 6187c478bd9Sstevel@tonic-gate pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf, 6197c478bd9Sstevel@tonic-gate uint16_t pmcap_offset) 6207c478bd9Sstevel@tonic-gate { 6217c478bd9Sstevel@tonic-gate uint16_t pmcsr; 6227c478bd9Sstevel@tonic-gate uint16_t pmcsr_offset = pmcap_offset + PCI_PMCSR; 6237c478bd9Sstevel@tonic-gate uint32_t *saved_pmcsrp = (uint32_t *)((caddr_t)regbuf + PCI_PMCSR); 6247c478bd9Sstevel@tonic-gate 6257c478bd9Sstevel@tonic-gate /* 6267c478bd9Sstevel@tonic-gate * Copy the power state bits from the PMCSR to our saved copy. 6277c478bd9Sstevel@tonic-gate * This is to make sure that we don't change the D state when 6287c478bd9Sstevel@tonic-gate * we restore config space of the device. 6297c478bd9Sstevel@tonic-gate */ 6307c478bd9Sstevel@tonic-gate pmcsr = pci_config_get16(confhdl, pmcsr_offset); 6317c478bd9Sstevel@tonic-gate (*saved_pmcsrp) &= ~PCI_PMCSR_STATE_MASK; 6327c478bd9Sstevel@tonic-gate (*saved_pmcsrp) |= (pmcsr & PCI_PMCSR_STATE_MASK); 6337c478bd9Sstevel@tonic-gate } 6347c478bd9Sstevel@tonic-gate 6357c478bd9Sstevel@tonic-gate static void 6367c478bd9Sstevel@tonic-gate pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 6377c478bd9Sstevel@tonic-gate pci_cap_save_desc_t *cap_descp, uint32_t elements) 6387c478bd9Sstevel@tonic-gate { 6397c478bd9Sstevel@tonic-gate int i, j; 6407c478bd9Sstevel@tonic-gate uint16_t offset; 6417c478bd9Sstevel@tonic-gate 6427c478bd9Sstevel@tonic-gate for (i = 0; i < (elements / sizeof (pci_cap_save_desc_t)); i++) { 6437c478bd9Sstevel@tonic-gate offset = cap_descp->cap_offset; 6447c478bd9Sstevel@tonic-gate if (cap_descp->cap_id == PCI_CAP_ID_PM) 6457c478bd9Sstevel@tonic-gate pci_pmcap_check(confhdl, regbuf, offset); 6467c478bd9Sstevel@tonic-gate for (j = 0; j < cap_descp->cap_nregs; j++) { 6477c478bd9Sstevel@tonic-gate pci_config_put32(confhdl, offset, *regbuf); 6487c478bd9Sstevel@tonic-gate regbuf++; 6497c478bd9Sstevel@tonic-gate offset += 4; 6507c478bd9Sstevel@tonic-gate } 6517c478bd9Sstevel@tonic-gate cap_descp++; 6527c478bd9Sstevel@tonic-gate } 6537c478bd9Sstevel@tonic-gate } 6547c478bd9Sstevel@tonic-gate 6557c478bd9Sstevel@tonic-gate /* 6567c478bd9Sstevel@tonic-gate * Restore config_regs from a single devinfo node. 6577c478bd9Sstevel@tonic-gate */ 6587c478bd9Sstevel@tonic-gate int 6597c478bd9Sstevel@tonic-gate pci_restore_config_regs(dev_info_t *dip) 6607c478bd9Sstevel@tonic-gate { 6617c478bd9Sstevel@tonic-gate ddi_acc_handle_t confhdl; 6627c478bd9Sstevel@tonic-gate pci_config_header_state_t *chs_p; 6637c478bd9Sstevel@tonic-gate pci_cap_save_desc_t *cap_descp; 6647c478bd9Sstevel@tonic-gate uint32_t elements, i; 6657c478bd9Sstevel@tonic-gate uint8_t *maskbuf; 6667c478bd9Sstevel@tonic-gate uint32_t *regbuf, *p; 6677c478bd9Sstevel@tonic-gate off_t offset = 0; 6687c478bd9Sstevel@tonic-gate 6697c478bd9Sstevel@tonic-gate if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) { 6707c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d can't get config handle", 6717c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip)); 6727c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 6737c478bd9Sstevel@tonic-gate } 6747c478bd9Sstevel@tonic-gate 6757c478bd9Sstevel@tonic-gate if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 6767c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS_MASK, 6777c478bd9Sstevel@tonic-gate (uchar_t **)&maskbuf, &elements) == DDI_PROP_SUCCESS) { 6787c478bd9Sstevel@tonic-gate 6797c478bd9Sstevel@tonic-gate if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 6807c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS, 6817c478bd9Sstevel@tonic-gate (uchar_t **)®buf, &elements) != DDI_PROP_SUCCESS) { 6827c478bd9Sstevel@tonic-gate goto restoreconfig_err; 6837c478bd9Sstevel@tonic-gate } 6847c478bd9Sstevel@tonic-gate ASSERT(elements == PCIE_CONF_HDR_SIZE); 6857c478bd9Sstevel@tonic-gate /* pcie device and has 4k config space saved */ 6867c478bd9Sstevel@tonic-gate p = regbuf; 6877c478bd9Sstevel@tonic-gate for (i = 0; i < PCIE_CONF_HDR_SIZE / sizeof (uint32_t); i++) { 6887c478bd9Sstevel@tonic-gate /* If the word is readable then restore it */ 6897c478bd9Sstevel@tonic-gate if (maskbuf[i >> INDEX_SHIFT] & 6907c478bd9Sstevel@tonic-gate (uint8_t)(1 << (i & BITMASK))) 6917c478bd9Sstevel@tonic-gate pci_config_put32(confhdl, offset, *p); 6927c478bd9Sstevel@tonic-gate p++; 6937c478bd9Sstevel@tonic-gate offset += sizeof (uint32_t); 6947c478bd9Sstevel@tonic-gate } 6957c478bd9Sstevel@tonic-gate ddi_prop_free(regbuf); 6967c478bd9Sstevel@tonic-gate ddi_prop_free(maskbuf); 6977c478bd9Sstevel@tonic-gate if (ndi_prop_remove(DDI_DEV_T_NONE, dip, 6987c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS_MASK) != DDI_PROP_SUCCESS) { 6997c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d can't remove prop %s", 7007c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 7017c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS_MASK); 7027c478bd9Sstevel@tonic-gate } 7037c478bd9Sstevel@tonic-gate } else { 7047c478bd9Sstevel@tonic-gate if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 7057c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS, 7067c478bd9Sstevel@tonic-gate (uchar_t **)®buf, &elements) != DDI_PROP_SUCCESS) { 7077c478bd9Sstevel@tonic-gate 7087c478bd9Sstevel@tonic-gate pci_config_teardown(&confhdl); 709*abee7076Sgs return (DDI_SUCCESS); 7107c478bd9Sstevel@tonic-gate } 7117c478bd9Sstevel@tonic-gate 7127c478bd9Sstevel@tonic-gate chs_p = (pci_config_header_state_t *)regbuf; 7137c478bd9Sstevel@tonic-gate pci_config_put16(confhdl, PCI_CONF_COMM, 7147c478bd9Sstevel@tonic-gate chs_p->chs_command); 7157c478bd9Sstevel@tonic-gate if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) == 7167c478bd9Sstevel@tonic-gate PCI_HEADER_ONE) { 7177c478bd9Sstevel@tonic-gate pci_config_put16(confhdl, PCI_BCNF_BCNTRL, 7187c478bd9Sstevel@tonic-gate chs_p->chs_bridge_control); 7197c478bd9Sstevel@tonic-gate } 7207c478bd9Sstevel@tonic-gate pci_config_put8(confhdl, PCI_CONF_CACHE_LINESZ, 7217c478bd9Sstevel@tonic-gate chs_p->chs_cache_line_size); 7227c478bd9Sstevel@tonic-gate pci_config_put8(confhdl, PCI_CONF_LATENCY_TIMER, 7237c478bd9Sstevel@tonic-gate chs_p->chs_latency_timer); 7247c478bd9Sstevel@tonic-gate if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) == 7257c478bd9Sstevel@tonic-gate PCI_HEADER_ONE) 7267c478bd9Sstevel@tonic-gate pci_config_put8(confhdl, PCI_BCNF_LATENCY_TIMER, 7277c478bd9Sstevel@tonic-gate chs_p->chs_sec_latency_timer); 7287c478bd9Sstevel@tonic-gate 7297c478bd9Sstevel@tonic-gate pci_config_put32(confhdl, PCI_CONF_BASE0, chs_p->chs_base0); 7307c478bd9Sstevel@tonic-gate pci_config_put32(confhdl, PCI_CONF_BASE1, chs_p->chs_base1); 7317c478bd9Sstevel@tonic-gate pci_config_put32(confhdl, PCI_CONF_BASE2, chs_p->chs_base2); 7327c478bd9Sstevel@tonic-gate pci_config_put32(confhdl, PCI_CONF_BASE3, chs_p->chs_base3); 7337c478bd9Sstevel@tonic-gate pci_config_put32(confhdl, PCI_CONF_BASE4, chs_p->chs_base4); 7347c478bd9Sstevel@tonic-gate pci_config_put32(confhdl, PCI_CONF_BASE5, chs_p->chs_base5); 7357c478bd9Sstevel@tonic-gate 7367c478bd9Sstevel@tonic-gate if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 7377c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 7387c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS_CAPINFO, 7397c478bd9Sstevel@tonic-gate (uchar_t **)&cap_descp, &elements) == DDI_PROP_SUCCESS) { 7407c478bd9Sstevel@tonic-gate /* 7417c478bd9Sstevel@tonic-gate * PCI capability related regsiters are saved. 7427c478bd9Sstevel@tonic-gate * Restore them based on the description. 7437c478bd9Sstevel@tonic-gate */ 7447c478bd9Sstevel@tonic-gate p = (uint32_t *)((caddr_t)regbuf + 7457c478bd9Sstevel@tonic-gate sizeof (pci_config_header_state_t)); 7467c478bd9Sstevel@tonic-gate pci_restore_caps(confhdl, p, cap_descp, elements); 7477c478bd9Sstevel@tonic-gate ddi_prop_free(cap_descp); 7487c478bd9Sstevel@tonic-gate } 7497c478bd9Sstevel@tonic-gate 7507c478bd9Sstevel@tonic-gate ddi_prop_free(regbuf); 7517c478bd9Sstevel@tonic-gate } 7527c478bd9Sstevel@tonic-gate 7537c478bd9Sstevel@tonic-gate /* 7547c478bd9Sstevel@tonic-gate * Make sure registers are flushed 7557c478bd9Sstevel@tonic-gate */ 7567c478bd9Sstevel@tonic-gate (void) pci_config_get32(confhdl, PCI_CONF_BASE5); 7577c478bd9Sstevel@tonic-gate 7587c478bd9Sstevel@tonic-gate 7597c478bd9Sstevel@tonic-gate if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS) != 7607c478bd9Sstevel@tonic-gate DDI_PROP_SUCCESS) { 7617c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d can't remove prop %s", 7627c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 7637c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS); 7647c478bd9Sstevel@tonic-gate } 7657c478bd9Sstevel@tonic-gate 7667c478bd9Sstevel@tonic-gate pci_config_teardown(&confhdl); 7677c478bd9Sstevel@tonic-gate 7687c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 7697c478bd9Sstevel@tonic-gate 7707c478bd9Sstevel@tonic-gate restoreconfig_err: 7717c478bd9Sstevel@tonic-gate ddi_prop_free(maskbuf); 7727c478bd9Sstevel@tonic-gate if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS_MASK) != 7737c478bd9Sstevel@tonic-gate DDI_PROP_SUCCESS) { 7747c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d can't remove prop %s", 7757c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 7767c478bd9Sstevel@tonic-gate SAVED_CONFIG_REGS_MASK); 7777c478bd9Sstevel@tonic-gate } 7787c478bd9Sstevel@tonic-gate pci_config_teardown(&confhdl); 7797c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 7807c478bd9Sstevel@tonic-gate } 7812df1fe9cSrandyf 7822df1fe9cSrandyf /*ARGSUSED*/ 7832df1fe9cSrandyf static int 7842df1fe9cSrandyf pci_lookup_pmcap(dev_info_t *dip, ddi_acc_handle_t conf_hdl, 7852df1fe9cSrandyf uint16_t *pmcap_offsetp) 7862df1fe9cSrandyf { 7872df1fe9cSrandyf uint8_t cap_ptr; 7882df1fe9cSrandyf uint8_t cap_id; 7892df1fe9cSrandyf uint8_t header_type; 7902df1fe9cSrandyf uint16_t status; 7912df1fe9cSrandyf 7922df1fe9cSrandyf header_type = pci_config_get8(conf_hdl, PCI_CONF_HEADER); 7932df1fe9cSrandyf header_type &= PCI_HEADER_TYPE_M; 7942df1fe9cSrandyf 7952df1fe9cSrandyf /* we don't deal with bridges, etc here */ 7962df1fe9cSrandyf if (header_type != PCI_HEADER_ZERO) { 7972df1fe9cSrandyf return (DDI_FAILURE); 7982df1fe9cSrandyf } 7992df1fe9cSrandyf 8002df1fe9cSrandyf status = pci_config_get16(conf_hdl, PCI_CONF_STAT); 8012df1fe9cSrandyf if ((status & PCI_STAT_CAP) == 0) { 8022df1fe9cSrandyf return (DDI_FAILURE); 8032df1fe9cSrandyf } 8042df1fe9cSrandyf 8052df1fe9cSrandyf cap_ptr = pci_config_get8(conf_hdl, PCI_CONF_CAP_PTR); 8062df1fe9cSrandyf 8072df1fe9cSrandyf /* 8082df1fe9cSrandyf * Walk the capabilities searching for a PM entry. 8092df1fe9cSrandyf */ 8102df1fe9cSrandyf while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 8112df1fe9cSrandyf cap_id = pci_config_get8(conf_hdl, cap_ptr + PCI_CAP_ID); 8122df1fe9cSrandyf if (cap_id == PCI_CAP_ID_PM) { 8132df1fe9cSrandyf break; 8142df1fe9cSrandyf } 8152df1fe9cSrandyf cap_ptr = pci_config_get8(conf_hdl, 8162df1fe9cSrandyf cap_ptr + PCI_CAP_NEXT_PTR); 8172df1fe9cSrandyf } 8182df1fe9cSrandyf 8192df1fe9cSrandyf if (cap_ptr == PCI_CAP_NEXT_PTR_NULL) { 8202df1fe9cSrandyf return (DDI_FAILURE); 8212df1fe9cSrandyf } 8222df1fe9cSrandyf *pmcap_offsetp = cap_ptr; 8232df1fe9cSrandyf return (DDI_SUCCESS); 8242df1fe9cSrandyf } 8252df1fe9cSrandyf 8262df1fe9cSrandyf /* 8272df1fe9cSrandyf * Do common pci-specific suspend actions: 8282df1fe9cSrandyf * - enable wakeup if appropriate for the device 8292df1fe9cSrandyf * - put device in lowest D-state that supports wakeup, or D3 if none 8302df1fe9cSrandyf * - turn off bus mastering in control register 8312df1fe9cSrandyf * For lack of per-dip storage (parent private date is pretty busy) 8322df1fe9cSrandyf * we use properties to store the necessary context 8332df1fe9cSrandyf * To avoid grotting through pci config space on every suspend, 8342df1fe9cSrandyf * we leave the prop in existence after resume, cause we know that 8352df1fe9cSrandyf * the detach framework code will dispose of it for us. 8362df1fe9cSrandyf */ 8372df1fe9cSrandyf 8382df1fe9cSrandyf typedef struct pci_pm_context { 8392df1fe9cSrandyf int ppc_flags; 8402df1fe9cSrandyf uint16_t ppc_cap_offset; /* offset in config space to pm cap */ 8412df1fe9cSrandyf uint16_t ppc_pmcsr; /* need this too */ 8422df1fe9cSrandyf uint16_t ppc_suspend_level; 8432df1fe9cSrandyf } pci_pm_context_t; 8442df1fe9cSrandyf 8452df1fe9cSrandyf #define SAVED_PM_CONTEXT "pci-pm-context" 8462df1fe9cSrandyf 8472df1fe9cSrandyf /* values for ppc_flags */ 8482df1fe9cSrandyf #define PPCF_NOPMCAP 1 8492df1fe9cSrandyf 8502df1fe9cSrandyf /* 8512df1fe9cSrandyf * Handle pci-specific suspend processing 8522df1fe9cSrandyf * PM CSR and PCI CMD are saved by pci_save_config_regs(). 8532df1fe9cSrandyf * If device can wake up system via PME, enable it to do so 8542df1fe9cSrandyf * Set device power level to lowest that can generate PME, or D3 if none can 8552df1fe9cSrandyf * Turn off bus master enable in pci command register 8562df1fe9cSrandyf */ 8572df1fe9cSrandyf #if defined(__x86) 8582df1fe9cSrandyf extern int acpi_ddi_setwake(dev_info_t *dip, int level); 8592df1fe9cSrandyf #endif 8602df1fe9cSrandyf 8612df1fe9cSrandyf int 8622df1fe9cSrandyf pci_post_suspend(dev_info_t *dip) 8632df1fe9cSrandyf { 8642df1fe9cSrandyf pci_pm_context_t *p; 8652df1fe9cSrandyf uint16_t pmcap, pmcsr, pcicmd; 8662df1fe9cSrandyf uint_t length; 8672df1fe9cSrandyf int ret; 8682df1fe9cSrandyf int fromprop = 1; /* source of memory *p */ 8692df1fe9cSrandyf ddi_acc_handle_t hdl; 8702df1fe9cSrandyf 8712df1fe9cSrandyf PMD(PMD_SX, ("pci_post_suspend %s:%d\n", 8722df1fe9cSrandyf ddi_driver_name(dip), ddi_get_instance(dip))) 8732df1fe9cSrandyf 8742df1fe9cSrandyf if (pci_save_config_regs(dip) != DDI_SUCCESS) { 8752df1fe9cSrandyf return (DDI_FAILURE); 8762df1fe9cSrandyf } 8772df1fe9cSrandyf 8782df1fe9cSrandyf if (pci_config_setup(dip, &hdl) != DDI_SUCCESS) { 8792df1fe9cSrandyf return (DDI_FAILURE); 8802df1fe9cSrandyf } 8812df1fe9cSrandyf 8822df1fe9cSrandyf if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 8832df1fe9cSrandyf DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 8842df1fe9cSrandyf SAVED_PM_CONTEXT, (uchar_t **)&p, &length) != DDI_PROP_SUCCESS) { 8852df1fe9cSrandyf p = (pci_pm_context_t *)kmem_zalloc(sizeof (*p), KM_SLEEP); 8862df1fe9cSrandyf fromprop = 0; 8872df1fe9cSrandyf if (pci_lookup_pmcap(dip, hdl, 8882df1fe9cSrandyf &p->ppc_cap_offset) != DDI_SUCCESS) { 8892df1fe9cSrandyf p->ppc_flags |= PPCF_NOPMCAP; 8902df1fe9cSrandyf ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 8912df1fe9cSrandyf SAVED_PM_CONTEXT, (uchar_t *)p, 8922df1fe9cSrandyf sizeof (pci_pm_context_t)); 8932df1fe9cSrandyf if (ret != DDI_PROP_SUCCESS) { 8942df1fe9cSrandyf (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 8952df1fe9cSrandyf SAVED_PM_CONTEXT); 8962df1fe9cSrandyf ret = DDI_FAILURE; 8972df1fe9cSrandyf } else { 8982df1fe9cSrandyf ret = DDI_SUCCESS; 8992df1fe9cSrandyf } 9002df1fe9cSrandyf kmem_free(p, sizeof (*p)); 9012df1fe9cSrandyf pci_config_teardown(&hdl); 9022df1fe9cSrandyf return (DDI_SUCCESS); 9032df1fe9cSrandyf } 9042df1fe9cSrandyf /* 9052df1fe9cSrandyf * Upon suspend, set the power level to the lowest that can 9062df1fe9cSrandyf * wake the system. If none can, then set to lowest. 9072df1fe9cSrandyf * XXX later we will need to check policy to see if this 9082df1fe9cSrandyf * XXX device has had wakeup disabled 9092df1fe9cSrandyf */ 9102df1fe9cSrandyf pmcap = pci_config_get16(hdl, p->ppc_cap_offset + PCI_PMCAP); 9112df1fe9cSrandyf if ((pmcap & PCI_PMCAP_D3COLD_PME) != 0) 9122df1fe9cSrandyf p->ppc_suspend_level = 9132df1fe9cSrandyf (PCI_PMCSR_PME_EN | PCI_PMCSR_D3HOT); 9142df1fe9cSrandyf else if ((pmcap & (PCI_PMCAP_D3HOT_PME | PCI_PMCAP_D2_PME)) != 9152df1fe9cSrandyf 0) 9162df1fe9cSrandyf p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D2; 9172df1fe9cSrandyf else if ((pmcap & PCI_PMCAP_D1_PME) != 0) 9182df1fe9cSrandyf p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D1; 9192df1fe9cSrandyf else if ((pmcap & PCI_PMCAP_D0_PME) != 0) 9202df1fe9cSrandyf p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D0; 9212df1fe9cSrandyf else 9222df1fe9cSrandyf p->ppc_suspend_level = PCI_PMCSR_D3HOT; 9232df1fe9cSrandyf 9242df1fe9cSrandyf /* 9252df1fe9cSrandyf * we defer updating the property to catch the saved 9262df1fe9cSrandyf * register values as well 9272df1fe9cSrandyf */ 9282df1fe9cSrandyf } 9292df1fe9cSrandyf /* If we set this in kmem_zalloc'd memory, we already returned above */ 9302df1fe9cSrandyf if ((p->ppc_flags & PPCF_NOPMCAP) != 0) { 9312df1fe9cSrandyf ddi_prop_free(p); 9322df1fe9cSrandyf pci_config_teardown(&hdl); 9332df1fe9cSrandyf return (DDI_SUCCESS); 9342df1fe9cSrandyf } 9352df1fe9cSrandyf 9362df1fe9cSrandyf 9372df1fe9cSrandyf /* 9382df1fe9cSrandyf * Turn off (Bus) Master Enable, since acpica will be turning off 9392df1fe9cSrandyf * bus master aribitration 9402df1fe9cSrandyf */ 9412df1fe9cSrandyf pcicmd = pci_config_get16(hdl, PCI_CONF_COMM); 9422df1fe9cSrandyf pcicmd &= ~PCI_COMM_ME; 9432df1fe9cSrandyf pci_config_put16(hdl, PCI_CONF_COMM, pcicmd); 9442df1fe9cSrandyf 9452df1fe9cSrandyf /* 9462df1fe9cSrandyf * set pm csr 9472df1fe9cSrandyf */ 9482df1fe9cSrandyf pmcsr = pci_config_get16(hdl, p->ppc_cap_offset + PCI_PMCSR); 9492df1fe9cSrandyf p->ppc_pmcsr = pmcsr; 9502df1fe9cSrandyf pmcsr &= (PCI_PMCSR_STATE_MASK); 9512df1fe9cSrandyf pmcsr |= (PCI_PMCSR_PME_STAT | p->ppc_suspend_level); 9522df1fe9cSrandyf pci_config_put16(hdl, p->ppc_cap_offset + PCI_PMCSR, pmcsr); 9532df1fe9cSrandyf 9542df1fe9cSrandyf #if defined(__x86) 9552df1fe9cSrandyf /* 9562df1fe9cSrandyf * Arrange for platform wakeup enabling 9572df1fe9cSrandyf */ 9582df1fe9cSrandyf if ((p->ppc_suspend_level & PCI_PMCSR_PME_EN) != 0) { 9592df1fe9cSrandyf int retval; 9602df1fe9cSrandyf 9612df1fe9cSrandyf retval = acpi_ddi_setwake(dip, 3); /* XXX 3 for now */ 9622df1fe9cSrandyf if (retval) { 9632df1fe9cSrandyf PMD(PMD_SX, ("pci_post_suspend, setwake %s@%s rets " 9642df1fe9cSrandyf "%x\n", PM_NAME(dip), PM_ADDR(dip), retval)); 9652df1fe9cSrandyf } 9662df1fe9cSrandyf } 9672df1fe9cSrandyf #endif 9682df1fe9cSrandyf 9692df1fe9cSrandyf /* 9702df1fe9cSrandyf * Push out saved register values 9712df1fe9cSrandyf */ 9722df1fe9cSrandyf ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, SAVED_PM_CONTEXT, 9732df1fe9cSrandyf (uchar_t *)p, sizeof (pci_pm_context_t)); 9742df1fe9cSrandyf if (ret == DDI_PROP_SUCCESS) { 9752df1fe9cSrandyf if (fromprop) 9762df1fe9cSrandyf ddi_prop_free(p); 9772df1fe9cSrandyf else 9782df1fe9cSrandyf kmem_free(p, sizeof (*p)); 9792df1fe9cSrandyf pci_config_teardown(&hdl); 9802df1fe9cSrandyf return (DDI_SUCCESS); 9812df1fe9cSrandyf } 9822df1fe9cSrandyf /* Failed; put things back the way we found them */ 9832df1fe9cSrandyf (void) pci_restore_config_regs(dip); 9842df1fe9cSrandyf if (fromprop) 9852df1fe9cSrandyf ddi_prop_free(p); 9862df1fe9cSrandyf else 9872df1fe9cSrandyf kmem_free(p, sizeof (*p)); 9882df1fe9cSrandyf (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_PM_CONTEXT); 9892df1fe9cSrandyf pci_config_teardown(&hdl); 9902df1fe9cSrandyf return (DDI_FAILURE); 9912df1fe9cSrandyf } 9922df1fe9cSrandyf 9932df1fe9cSrandyf /* 9942df1fe9cSrandyf * The inverse of pci_post_suspend; handle pci-specific resume processing 9952df1fe9cSrandyf * First, turn device back on, then restore config space. 9962df1fe9cSrandyf */ 9972df1fe9cSrandyf 9982df1fe9cSrandyf int 9992df1fe9cSrandyf pci_pre_resume(dev_info_t *dip) 10002df1fe9cSrandyf { 10012df1fe9cSrandyf ddi_acc_handle_t hdl; 10022df1fe9cSrandyf pci_pm_context_t *p; 10032df1fe9cSrandyf /* E_FUNC_SET_NOT_USED */ 10042df1fe9cSrandyf uint16_t pmcap, pmcsr; 10052df1fe9cSrandyf int flags; 10062df1fe9cSrandyf uint_t length; 10072df1fe9cSrandyf clock_t drv_usectohz(clock_t microsecs); 10082df1fe9cSrandyf #if defined(__x86) 10092df1fe9cSrandyf uint16_t suspend_level; 10102df1fe9cSrandyf #endif 10112df1fe9cSrandyf 10122df1fe9cSrandyf PMD(PMD_SX, ("pci_pre_resume %s:%d\n", ddi_driver_name(dip), 10132df1fe9cSrandyf ddi_get_instance(dip))) 10142df1fe9cSrandyf if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 10152df1fe9cSrandyf DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 10162df1fe9cSrandyf SAVED_PM_CONTEXT, (uchar_t **)&p, &length) != DDI_PROP_SUCCESS) { 10172df1fe9cSrandyf return (DDI_FAILURE); 10182df1fe9cSrandyf } 10192df1fe9cSrandyf flags = p->ppc_flags; 10202df1fe9cSrandyf pmcap = p->ppc_cap_offset; 10212df1fe9cSrandyf pmcsr = p->ppc_pmcsr; 10222df1fe9cSrandyf #if defined(__x86) 10232df1fe9cSrandyf suspend_level = p->ppc_suspend_level; 10242df1fe9cSrandyf #endif 10252df1fe9cSrandyf ddi_prop_free(p); 1026*abee7076Sgs if ((flags & PPCF_NOPMCAP) != 0) 1027*abee7076Sgs goto done; 10282df1fe9cSrandyf #if defined(__x86) 10292df1fe9cSrandyf /* 10302df1fe9cSrandyf * Turn platform wake enable back off 10312df1fe9cSrandyf */ 10322df1fe9cSrandyf if ((suspend_level & PCI_PMCSR_PME_EN) != 0) { 10332df1fe9cSrandyf int retval; 10342df1fe9cSrandyf 10352df1fe9cSrandyf retval = acpi_ddi_setwake(dip, 0); /* 0 for now */ 10362df1fe9cSrandyf if (retval) { 10372df1fe9cSrandyf PMD(PMD_SX, ("pci_pre_resume, setwake %s@%s rets " 10382df1fe9cSrandyf "%x\n", PM_NAME(dip), PM_ADDR(dip), retval)); 10392df1fe9cSrandyf } 10402df1fe9cSrandyf } 10412df1fe9cSrandyf #endif 10422df1fe9cSrandyf if (pci_config_setup(dip, &hdl) != DDI_SUCCESS) { 10432df1fe9cSrandyf return (DDI_FAILURE); 10442df1fe9cSrandyf } 10452df1fe9cSrandyf pci_config_put16(hdl, pmcap + PCI_PMCSR, pmcsr); 10462df1fe9cSrandyf delay(drv_usectohz(10000)); /* PCI PM spec D3->D0 (10ms) */ 10472df1fe9cSrandyf pci_config_teardown(&hdl); 1048*abee7076Sgs done: 10492df1fe9cSrandyf (void) pci_restore_config_regs(dip); /* fudges D-state! */ 10502df1fe9cSrandyf return (DDI_SUCCESS); 10512df1fe9cSrandyf } 1052