1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  *
21  * Copyright (c) 2002-2006 Neterion, Inc.
22  */
23 
24 /*
25  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
26  * Use is subject to license terms.
27  */
28 
29 #include "xgehal-device.h"
30 #include "xgehal-channel.h"
31 #include "xgehal-fifo.h"
32 #include "xgehal-ring.h"
33 #include "xgehal-driver.h"
34 #include "xgehal-mgmt.h"
35 
36 #define SWITCH_SIGN	0xA5A5A5A5A5A5A5A5ULL
37 #define	END_SIGN	0x0
38 
39 #ifdef XGE_HAL_HERC_EMULATION
40 #undef XGE_HAL_PROCESS_LINK_INT_IN_ISR
41 #endif
42 
43 /*
44  * Jenkins hash key length(in bytes)
45  */
46 #define XGE_HAL_JHASH_MSG_LEN 50
47 
48 /*
49  * mix(a,b,c) used in Jenkins hash algorithm
50  */
51 #define mix(a,b,c) { \
52 	a -= b; a -= c; a ^= (c>>13); \
53 	b -= c; b -= a; b ^= (a<<8);  \
54 	c -= a; c -= b; c ^= (b>>13); \
55 	a -= b; a -= c; a ^= (c>>12); \
56 	b -= c; b -= a; b ^= (a<<16); \
57 	c -= a; c -= b; c ^= (b>>5);  \
58 	a -= b; a -= c; a ^= (c>>3);  \
59 	b -= c; b -= a; b ^= (a<<10); \
60 	c -= a; c -= b; c ^= (b>>15); \
61 }
62 
63 
64 /*
65  * __hal_device_event_queued
66  * @data: pointer to xge_hal_device_t structure
67  *
68  * Will be called when new event succesfully queued.
69  */
70 void
__hal_device_event_queued(void * data,int event_type)71 __hal_device_event_queued(void *data, int event_type)
72 {
73 	xge_assert(((xge_hal_device_t*)data)->magic == XGE_HAL_MAGIC);
74 	if (g_xge_hal_driver->uld_callbacks.event_queued) {
75 		g_xge_hal_driver->uld_callbacks.event_queued(data, event_type);
76 	}
77 }
78 
79 /*
80  * __hal_pio_mem_write32_upper
81  *
82  * Endiann-aware implementation of xge_os_pio_mem_write32().
83  * Since Xframe has 64bit registers, we differintiate uppper and lower
84  * parts.
85  */
86 void
__hal_pio_mem_write32_upper(pci_dev_h pdev,pci_reg_h regh,u32 val,void * addr)87 __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val, void *addr)
88 {
89 #if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN)
90 	xge_os_pio_mem_write32(pdev, regh, val, addr);
91 #else
92 	xge_os_pio_mem_write32(pdev, regh, val, (void *)((char *)addr + 4));
93 #endif
94 }
95 
96 /*
97  * __hal_pio_mem_write32_upper
98  *
99  * Endiann-aware implementation of xge_os_pio_mem_write32().
100  * Since Xframe has 64bit registers, we differintiate uppper and lower
101  * parts.
102  */
103 void
__hal_pio_mem_write32_lower(pci_dev_h pdev,pci_reg_h regh,u32 val,void * addr)104 __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val,
105                             void *addr)
106 {
107 #if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN)
108 	xge_os_pio_mem_write32(pdev, regh, val,
109                                (void *) ((char *)addr +	4));
110 #else
111 	xge_os_pio_mem_write32(pdev, regh, val, addr);
112 #endif
113 }
114 
115 /*
116  * __hal_device_register_poll
117  * @hldev: pointer to xge_hal_device_t structure
118  * @reg: register to poll for
119  * @op: 0 - bit reset, 1 - bit set
120  * @mask: mask for logical "and" condition based on %op
121  * @max_millis: maximum time to try to poll in milliseconds
122  *
123  * Will poll certain register for specified amount of time.
124  * Will poll until masked bit is not cleared.
125  */
126 xge_hal_status_e
__hal_device_register_poll(xge_hal_device_t * hldev,u64 * reg,int op,u64 mask,int max_millis)127 __hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg,
128 			   int op, u64 mask, int max_millis)
129 {
130 	u64 val64;
131 	int i = 0;
132 	xge_hal_status_e ret = XGE_HAL_FAIL;
133 
134 	xge_os_udelay(10);
135 
136 	do {
137 		val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, reg);
138 		if (op == 0 && !(val64 & mask))
139 			return XGE_HAL_OK;
140 		else if (op == 1 && (val64 & mask) == mask)
141 			return XGE_HAL_OK;
142 		xge_os_udelay(100);
143 	} while (++i <= 9);
144 
145 	do {
146 		val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, reg);
147 		if (op == 0 && !(val64 & mask))
148 			return XGE_HAL_OK;
149 		else if (op == 1 && (val64 & mask) == mask)
150 			return XGE_HAL_OK;
151 		xge_os_udelay(1000);
152 	} while (++i < max_millis);
153 
154 	return ret;
155 }
156 
157 /*
158  * __hal_device_wait_quiescent
159  * @hldev: the device
160  * @hw_status: hw_status in case of error
161  *
162  * Will wait until device is quiescent for some blocks.
163  */
164 static xge_hal_status_e
__hal_device_wait_quiescent(xge_hal_device_t * hldev,u64 * hw_status)165 __hal_device_wait_quiescent(xge_hal_device_t *hldev, u64 *hw_status)
166 {
167 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
168 
169 	/* poll and wait first */
170 #ifdef XGE_HAL_HERC_EMULATION
171 	(void) __hal_device_register_poll(hldev, &bar0->adapter_status, 1,
172 			(XGE_HAL_ADAPTER_STATUS_TDMA_READY |
173 			 XGE_HAL_ADAPTER_STATUS_RDMA_READY |
174 			 XGE_HAL_ADAPTER_STATUS_PFC_READY |
175 			 XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY |
176 			 XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT |
177 			 XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY |
178 			 XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY |
179 			 XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK),
180 			 XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS);
181 #else
182 	(void) __hal_device_register_poll(hldev, &bar0->adapter_status, 1,
183 			(XGE_HAL_ADAPTER_STATUS_TDMA_READY |
184 			 XGE_HAL_ADAPTER_STATUS_RDMA_READY |
185 			 XGE_HAL_ADAPTER_STATUS_PFC_READY |
186 			 XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY |
187 			 XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT |
188 			 XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY |
189 			 XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY |
190 			 XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK |
191 			 XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK),
192 			 XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS);
193 #endif
194 
195 	return xge_hal_device_status(hldev, hw_status);
196 }
197 
198 /**
199  * xge_hal_device_is_slot_freeze
200  * @devh: the device
201  *
202  * Returns non-zero if the slot is freezed.
203  * The determination is made based on the adapter_status
204  * register which will never give all FFs, unless PCI read
205  * cannot go through.
206  */
207 int
xge_hal_device_is_slot_freeze(xge_hal_device_h devh)208 xge_hal_device_is_slot_freeze(xge_hal_device_h devh)
209 {
210 	xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
211 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
212 	u16 device_id;
213 	u64 adapter_status =
214 		xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
215 				      &bar0->adapter_status);
216 	xge_os_pci_read16(hldev->pdev,hldev->cfgh,
217 			xge_offsetof(xge_hal_pci_config_le_t, device_id),
218 			&device_id);
219 #ifdef TX_DEBUG
220 	if (adapter_status == XGE_HAL_ALL_FOXES)
221 	{
222 		u64 dummy;
223 		dummy = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
224 						&bar0->pcc_enable);
225 		printf(">>> Slot is frozen!\n");
226 		brkpoint(0);
227 	}
228 #endif
229 	return((adapter_status == XGE_HAL_ALL_FOXES) || (device_id == 0xffff));
230 }
231 
232 
233 /*
234  * __hal_device_led_actifity_fix
235  * @hldev: pointer to xge_hal_device_t structure
236  *
237  * SXE-002: Configure link and activity LED to turn it off
238  */
239 static void
__hal_device_led_actifity_fix(xge_hal_device_t * hldev)240 __hal_device_led_actifity_fix(xge_hal_device_t *hldev)
241 {
242 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
243 	u16 subid;
244 	u64 val64;
245 
246 	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
247 		xge_offsetof(xge_hal_pci_config_le_t, subsystem_id), &subid);
248 
249 	/*
250 	 *  In the case of Herc, there is a new register named beacon control
251 	 *  is added which was not present in Xena.
252 	 *  Beacon control register in Herc is at the same offset as
253 	 *  gpio control register in Xena.  It means they are one and same in
254 	 *  the case of Xena. Also, gpio control register offset in Herc and
255 	 *  Xena is different.
256 	 *  The current register map represents Herc(It means we have
257 	 *  both beacon  and gpio control registers in register map).
258 	 *  WRT transition from Xena to Herc, all the code in Xena which was
259 	 *  using  gpio control register for LED handling would  have to
260 	 *  use beacon control register in Herc and the rest of the code
261 	 *  which uses gpio control in Xena  would use the same register
262 	 *  in Herc.
263 	 *  WRT LED handling(following code), In the case of Herc, beacon
264 	 *  control register has to be used. This is applicable for Xena also,
265 	 *  since it represents the gpio control register in Xena.
266 	 */
267 	if ((subid & 0xFF) >= 0x07) {
268 		val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
269 		                            &bar0->beacon_control);
270 		val64 |= 0x0000800000000000ULL;
271 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
272 				     val64, &bar0->beacon_control);
273 		val64 = 0x0411040400000000ULL;
274 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
275 				    (void *) ((u8 *)bar0 + 0x2700));
276 	}
277 }
278 
279 /* Constants for Fixing the MacAddress problem seen mostly on
280  * Alpha machines.
281  */
282 static u64 xena_fix_mac[] = {
283 	0x0060000000000000ULL, 0x0060600000000000ULL,
284 	0x0040600000000000ULL, 0x0000600000000000ULL,
285 	0x0020600000000000ULL, 0x0060600000000000ULL,
286 	0x0020600000000000ULL, 0x0060600000000000ULL,
287 	0x0020600000000000ULL, 0x0060600000000000ULL,
288 	0x0020600000000000ULL, 0x0060600000000000ULL,
289 	0x0020600000000000ULL, 0x0060600000000000ULL,
290 	0x0020600000000000ULL, 0x0060600000000000ULL,
291 	0x0020600000000000ULL, 0x0060600000000000ULL,
292 	0x0020600000000000ULL, 0x0060600000000000ULL,
293 	0x0020600000000000ULL, 0x0060600000000000ULL,
294 	0x0020600000000000ULL, 0x0060600000000000ULL,
295 	0x0020600000000000ULL, 0x0000600000000000ULL,
296 	0x0040600000000000ULL, 0x0060600000000000ULL,
297 	END_SIGN
298 };
299 
300 /*
301  * __hal_device_fix_mac
302  * @hldev: HAL device handle.
303  *
304  * Fix for all "FFs" MAC address problems observed on Alpha platforms.
305  */
306 static void
__hal_device_xena_fix_mac(xge_hal_device_t * hldev)307 __hal_device_xena_fix_mac(xge_hal_device_t *hldev)
308 {
309 	int i = 0;
310 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
311 
312 	/*
313 	 *  In the case of Herc, there is a new register named beacon control
314 	 *  is added which was not present in Xena.
315 	 *  Beacon control register in Herc is at the same offset as
316 	 *  gpio control register in Xena.  It means they are one and same in
317 	 *  the case of Xena. Also, gpio control register offset in Herc and
318 	 *  Xena is different.
319 	 *  The current register map represents Herc(It means we have
320 	 *  both beacon  and gpio control registers in register map).
321 	 *  WRT transition from Xena to Herc, all the code in Xena which was
322 	 *  using  gpio control register for LED handling would  have to
323 	 *  use beacon control register in Herc and the rest of the code
324 	 *  which uses gpio control in Xena  would use the same register
325 	 *  in Herc.
326 	 *  In the following code(xena_fix_mac), beacon control register has
327 	 *  to be used in the case of Xena, since it represents gpio control
328 	 *  register. In the case of Herc, there is no change required.
329 	 */
330 	while (xena_fix_mac[i] != END_SIGN) {
331 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
332 				xena_fix_mac[i++], &bar0->beacon_control);
333 		xge_os_mdelay(1);
334 	}
335 }
336 
337 /*
338  * xge_hal_device_bcast_enable
339  * @hldev: HAL device handle.
340  *
341  * Enable receiving broadcasts.
342  * The host must first write RMAC_CFG_KEY "key"
343  * register, and then - MAC_CFG register.
344  */
345 void
xge_hal_device_bcast_enable(xge_hal_device_h devh)346 xge_hal_device_bcast_enable(xge_hal_device_h devh)
347 {
348 	xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
349 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
350 	u64 val64;
351 
352 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
353 	&bar0->mac_cfg);
354 		val64 |= XGE_HAL_MAC_RMAC_BCAST_ENABLE;
355 
356 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
357 		XGE_HAL_RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
358 
359     __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0,
360 		(u32)(val64 >> 32), &bar0->mac_cfg);
361 
362 	xge_debug_device(XGE_TRACE, "mac_cfg 0x"XGE_OS_LLXFMT": broadcast %s",
363 		(unsigned long long)val64,
364 		hldev->config.mac.rmac_bcast_en ? "enabled" : "disabled");
365 }
366 
367 /*
368  * xge_hal_device_bcast_disable
369  * @hldev: HAL device handle.
370  *
371  * Disable receiving broadcasts.
372  * The host must first write RMAC_CFG_KEY "key"
373  * register, and then - MAC_CFG register.
374  */
375 void
xge_hal_device_bcast_disable(xge_hal_device_h devh)376 xge_hal_device_bcast_disable(xge_hal_device_h devh)
377 {
378 	xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
379 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
380 	u64 val64;
381 
382 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
383 	&bar0->mac_cfg);
384 
385 	val64 &= ~(XGE_HAL_MAC_RMAC_BCAST_ENABLE);
386 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
387 		     XGE_HAL_RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
388 
389         __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0,
390 		    (u32)(val64 >> 32), &bar0->mac_cfg);
391 
392 	xge_debug_device(XGE_TRACE, "mac_cfg 0x"XGE_OS_LLXFMT": broadcast %s",
393 		(unsigned long long)val64,
394 		hldev->config.mac.rmac_bcast_en ? "enabled" : "disabled");
395 }
396 
397 /*
398  * __hal_device_shared_splits_configure
399  * @hldev: HAL device handle.
400  *
401  * TxDMA will stop Read request if the number of read split had exceeded
402  * the limit set by shared_splits
403  */
404 static void
__hal_device_shared_splits_configure(xge_hal_device_t * hldev)405 __hal_device_shared_splits_configure(xge_hal_device_t *hldev)
406 {
407 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
408 	u64 val64;
409 
410 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
411 	                            &bar0->pic_control);
412 	val64 |=
413 	XGE_HAL_PIC_CNTL_SHARED_SPLITS(hldev->config.shared_splits);
414 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
415 			     &bar0->pic_control);
416 	xge_debug_device(XGE_TRACE, "%s", "shared splits configured");
417 }
418 
419 /*
420  * __hal_device_rmac_padding_configure
421  * @hldev: HAL device handle.
422  *
423  * Configure RMAC frame padding. Depends on configuration, it
424  * can be send to host or removed by MAC.
425  */
426 static void
__hal_device_rmac_padding_configure(xge_hal_device_t * hldev)427 __hal_device_rmac_padding_configure(xge_hal_device_t *hldev)
428 {
429 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
430 	u64 val64;
431 
432 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
433 		    XGE_HAL_RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
434 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
435 	&bar0->mac_cfg);
436 	val64 &= ( ~XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE );
437 	val64 &= ( ~XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE );
438 	val64 |= XGE_HAL_MAC_CFG_TMAC_APPEND_PAD;
439 
440 	/*
441 	 * If the RTH enable bit is not set, strip the FCS
442 	 */
443 	if (!hldev->config.rth_en ||
444 	    !(xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
445 			   &bar0->rts_rth_cfg) & XGE_HAL_RTS_RTH_EN)) {
446 		val64 |= XGE_HAL_MAC_CFG_RMAC_STRIP_FCS;
447 	}
448 
449 	val64 &= ( ~XGE_HAL_MAC_CFG_RMAC_STRIP_PAD );
450 	val64 |= XGE_HAL_MAC_RMAC_DISCARD_PFRM;
451 
452 	__hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0,
453 		    (u32)(val64 >> 32), (char*)&bar0->mac_cfg);
454 	xge_os_mdelay(1);
455 
456 	xge_debug_device(XGE_TRACE,
457 		  "mac_cfg 0x"XGE_OS_LLXFMT": frame padding configured",
458 		  (unsigned long long)val64);
459 }
460 
461 /*
462  * __hal_device_pause_frames_configure
463  * @hldev: HAL device handle.
464  *
465  * Set Pause threshold.
466  *
467  * Pause frame is generated if the amount of data outstanding
468  * on any queue exceeded the ratio of
469  * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
470  */
471 static void
__hal_device_pause_frames_configure(xge_hal_device_t * hldev)472 __hal_device_pause_frames_configure(xge_hal_device_t *hldev)
473 {
474 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
475 	int i;
476 	u64 val64;
477 
478 	switch (hldev->config.mac.media) {
479 		case XGE_HAL_MEDIA_SR:
480 		case XGE_HAL_MEDIA_SW:
481 			val64=0xfffbfffbfffbfffbULL;
482 			break;
483 		case XGE_HAL_MEDIA_LR:
484 		case XGE_HAL_MEDIA_LW:
485 			val64=0xffbbffbbffbbffbbULL;
486 			break;
487 		case XGE_HAL_MEDIA_ER:
488 		case XGE_HAL_MEDIA_EW:
489 		default:
490 			val64=0xffbbffbbffbbffbbULL;
491 			break;
492 	}
493 
494 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
495 			val64, &bar0->mc_pause_thresh_q0q3);
496 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
497 			val64, &bar0->mc_pause_thresh_q4q7);
498 
499 	/* Set the time value  to be inserted in the pause frame generated
500 	 * by Xframe */
501 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
502 	                            &bar0->rmac_pause_cfg);
503 	if (hldev->config.mac.rmac_pause_gen_en)
504 		val64 |= XGE_HAL_RMAC_PAUSE_GEN_EN;
505 	else
506 		val64 &= ~(XGE_HAL_RMAC_PAUSE_GEN_EN);
507 	if (hldev->config.mac.rmac_pause_rcv_en)
508 		val64 |= XGE_HAL_RMAC_PAUSE_RCV_EN;
509 	else
510 		val64 &= ~(XGE_HAL_RMAC_PAUSE_RCV_EN);
511 	val64 &= ~(XGE_HAL_RMAC_PAUSE_HG_PTIME(0xffff));
512 	val64 |= XGE_HAL_RMAC_PAUSE_HG_PTIME(hldev->config.mac.rmac_pause_time);
513 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
514 			     &bar0->rmac_pause_cfg);
515 
516 	val64 = 0;
517 	for (i = 0; i<4; i++) {
518 		val64 |=
519 		     (((u64)0xFF00|hldev->config.mac.mc_pause_threshold_q0q3)
520 							<<(i*2*8));
521 	}
522 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
523 			     &bar0->mc_pause_thresh_q0q3);
524 
525 	val64 = 0;
526 	for (i = 0; i<4; i++) {
527 		val64 |=
528 		     (((u64)0xFF00|hldev->config.mac.mc_pause_threshold_q4q7)
529 							<<(i*2*8));
530 	}
531 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
532 			     &bar0->mc_pause_thresh_q4q7);
533 	xge_debug_device(XGE_TRACE, "%s", "pause frames configured");
534 }
535 
536 /*
537  * Herc's clock rate doubled, unless the slot is 33MHz.
538  */
__hal_fix_time_ival_herc(xge_hal_device_t * hldev,unsigned int time_ival)539 unsigned int __hal_fix_time_ival_herc(xge_hal_device_t *hldev,
540 				      unsigned int time_ival)
541 {
542 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA)
543 		return time_ival;
544 
545 	xge_assert(xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC);
546 
547 	if (hldev->bus_frequency != XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN &&
548 	    hldev->bus_frequency != XGE_HAL_PCI_BUS_FREQUENCY_33MHZ)
549 		time_ival *= 2;
550 
551 	return time_ival;
552 }
553 
554 
555 /*
556  * __hal_device_bus_master_disable
557  * @hldev: HAL device handle.
558  *
559  * Disable bus mastership.
560  */
561 static void
__hal_device_bus_master_disable(xge_hal_device_t * hldev)562 __hal_device_bus_master_disable (xge_hal_device_t *hldev)
563 {
564 	u16 cmd;
565 	u16 bus_master = 4;
566 
567 	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
568 			xge_offsetof(xge_hal_pci_config_le_t, command), &cmd);
569 	cmd &= ~bus_master;
570 	xge_os_pci_write16(hldev->pdev, hldev->cfgh,
571 			 xge_offsetof(xge_hal_pci_config_le_t, command), cmd);
572 }
573 
574 /*
575  * __hal_device_bus_master_enable
576  * @hldev: HAL device handle.
577  *
578  * Disable bus mastership.
579  */
580 static void
__hal_device_bus_master_enable(xge_hal_device_t * hldev)581 __hal_device_bus_master_enable (xge_hal_device_t *hldev)
582 {
583 	u16 cmd;
584 	u16 bus_master = 4;
585 
586 	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
587 			xge_offsetof(xge_hal_pci_config_le_t, command), &cmd);
588 
589 	/* already enabled? do nothing */
590 	if (cmd & bus_master)
591 		return;
592 
593 	cmd |= bus_master;
594 	xge_os_pci_write16(hldev->pdev, hldev->cfgh,
595 			 xge_offsetof(xge_hal_pci_config_le_t, command), cmd);
596 }
597 /*
598  * __hal_device_intr_mgmt
599  * @hldev: HAL device handle.
600  * @mask: mask indicating which Intr block must be modified.
601  * @flag: if true - enable, otherwise - disable interrupts.
602  *
603  * Disable or enable device interrupts. Mask is used to specify
604  * which hardware blocks should produce interrupts. For details
605  * please refer to Xframe User Guide.
606  */
607 static void
__hal_device_intr_mgmt(xge_hal_device_t * hldev,u64 mask,int flag)608 __hal_device_intr_mgmt(xge_hal_device_t *hldev, u64 mask, int flag)
609 {
610 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
611 	u64 val64 = 0, temp64 = 0;
612 	u64 gim, gim_saved;
613 
614 	gim_saved = gim = xge_os_pio_mem_read64(hldev->pdev,
615                               hldev->regh0, &bar0->general_int_mask);
616 
617 	/* Top level interrupt classification */
618 	/* PIC Interrupts */
619 	if ((mask & (XGE_HAL_TX_PIC_INTR/* | XGE_HAL_RX_PIC_INTR*/))) {
620 		/* Enable PIC Intrs in the general intr mask register */
621 		val64 = XGE_HAL_TXPIC_INT_M/* | XGE_HAL_PIC_RX_INT_M*/;
622 		if (flag) {
623 			gim &= ~((u64) val64);
624 			temp64 = xge_os_pio_mem_read64(hldev->pdev,
625 					hldev->regh0, &bar0->pic_int_mask);
626 
627 			temp64 &= ~XGE_HAL_PIC_INT_TX;
628 #ifdef  XGE_HAL_PROCESS_LINK_INT_IN_ISR
629 			if (xge_hal_device_check_id(hldev) ==
630 							XGE_HAL_CARD_HERC) {
631 				temp64 &= ~XGE_HAL_PIC_INT_MISC;
632 			}
633 #endif
634 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
635 					     temp64, &bar0->pic_int_mask);
636 #ifdef  XGE_HAL_PROCESS_LINK_INT_IN_ISR
637 			if (xge_hal_device_check_id(hldev) ==
638 							XGE_HAL_CARD_HERC) {
639 				/*
640 				 * Unmask only Link Up interrupt
641 				 */
642 				temp64 = xge_os_pio_mem_read64(hldev->pdev,
643 					hldev->regh0, &bar0->misc_int_mask);
644 				temp64 &= ~XGE_HAL_MISC_INT_REG_LINK_UP_INT;
645 				xge_os_pio_mem_write64(hldev->pdev,
646 					      hldev->regh0, temp64,
647 					      &bar0->misc_int_mask);
648 				xge_debug_device(XGE_TRACE,
649 					"unmask link up flag "XGE_OS_LLXFMT,
650 					(unsigned long long)temp64);
651 			}
652 #endif
653 		} else { /* flag == 0 */
654 
655 #ifdef  XGE_HAL_PROCESS_LINK_INT_IN_ISR
656 			if (xge_hal_device_check_id(hldev) ==
657 							XGE_HAL_CARD_HERC) {
658 				/*
659 				 * Mask both Link Up and Down interrupts
660 				 */
661 				temp64 = xge_os_pio_mem_read64(hldev->pdev,
662 					hldev->regh0, &bar0->misc_int_mask);
663 				temp64 |= XGE_HAL_MISC_INT_REG_LINK_UP_INT;
664 				temp64 |= XGE_HAL_MISC_INT_REG_LINK_DOWN_INT;
665 				xge_os_pio_mem_write64(hldev->pdev,
666 					      hldev->regh0, temp64,
667 					      &bar0->misc_int_mask);
668 				xge_debug_device(XGE_TRACE,
669 					"mask link up/down flag "XGE_OS_LLXFMT,
670 					(unsigned long long)temp64);
671 			}
672 #endif
673 			/* Disable PIC Intrs in the general intr mask
674 			 * register */
675 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
676 					     XGE_HAL_ALL_INTRS_DIS,
677 			                     &bar0->pic_int_mask);
678 			gim |= val64;
679 		}
680 	}
681 
682 	/*  DMA Interrupts */
683 	/*  Enabling/Disabling Tx DMA interrupts */
684 	if (mask & XGE_HAL_TX_DMA_INTR) {
685 		/*  Enable TxDMA Intrs in the general intr mask register */
686 		val64 = XGE_HAL_TXDMA_INT_M;
687 		if (flag) {
688 			gim &= ~((u64) val64);
689 			/* Enable all TxDMA interrupts */
690 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
691 					     0x0, &bar0->txdma_int_mask);
692 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
693 					     0x0, &bar0->pfc_err_mask);
694 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
695 					     0x0, &bar0->tda_err_mask);
696 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
697 					     0x0, &bar0->pcc_err_mask);
698 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
699 					     0x0, &bar0->tti_err_mask);
700 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
701 					     0x0, &bar0->lso_err_mask);
702 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
703 					     0x0, &bar0->tpa_err_mask);
704 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
705 					     0x0, &bar0->sm_err_mask);
706 
707 		} else { /* flag == 0 */
708 
709 			/*  Disable TxDMA Intrs in the general intr mask
710 			 *  register */
711 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
712 					     XGE_HAL_ALL_INTRS_DIS,
713 			                     &bar0->txdma_int_mask);
714 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
715 					     XGE_HAL_ALL_INTRS_DIS,
716 			                     &bar0->pfc_err_mask);
717 
718 			gim |= val64;
719 		}
720 	}
721 
722 	/*  Enabling/Disabling Rx DMA interrupts */
723 	if (mask & XGE_HAL_RX_DMA_INTR) {
724 		/*  Enable RxDMA Intrs in the general intr mask register */
725 		val64 = XGE_HAL_RXDMA_INT_M;
726 		if (flag) {
727 
728 			gim &= ~((u64) val64);
729 			/* All RxDMA block interrupts are disabled for now
730 			 * TODO */
731 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
732 					     XGE_HAL_ALL_INTRS_DIS,
733 			                     &bar0->rxdma_int_mask);
734 
735 		} else { /* flag == 0 */
736 
737 			/*  Disable RxDMA Intrs in the general intr mask
738 			 *  register */
739 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
740 					     XGE_HAL_ALL_INTRS_DIS,
741 			                     &bar0->rxdma_int_mask);
742 
743 			gim |= val64;
744 		}
745 	}
746 
747 	/*  MAC Interrupts */
748 	/*  Enabling/Disabling MAC interrupts */
749 	if (mask & (XGE_HAL_TX_MAC_INTR | XGE_HAL_RX_MAC_INTR)) {
750 		val64 = XGE_HAL_TXMAC_INT_M | XGE_HAL_RXMAC_INT_M;
751 		if (flag) {
752 
753 			gim &= ~((u64) val64);
754 
755 			/* All MAC block error inter. are disabled for now. */
756 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
757 			     XGE_HAL_ALL_INTRS_DIS, &bar0->mac_int_mask);
758 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
759 			     XGE_HAL_ALL_INTRS_DIS, &bar0->mac_rmac_err_mask);
760 
761 		} else { /* flag == 0 */
762 
763 			/* Disable MAC Intrs in the general intr mask
764 			 * register */
765 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
766 			     XGE_HAL_ALL_INTRS_DIS, &bar0->mac_int_mask);
767 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
768 			     XGE_HAL_ALL_INTRS_DIS, &bar0->mac_rmac_err_mask);
769 
770 			gim |= val64;
771 		}
772 	}
773 
774 	/*  XGXS Interrupts */
775 	if (mask & (XGE_HAL_TX_XGXS_INTR | XGE_HAL_RX_XGXS_INTR)) {
776 		val64 = XGE_HAL_TXXGXS_INT_M | XGE_HAL_RXXGXS_INT_M;
777 		if (flag) {
778 
779 			gim &= ~((u64) val64);
780 			/* All XGXS block error interrupts are disabled for now
781 			 * TODO */
782 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
783 			     XGE_HAL_ALL_INTRS_DIS, &bar0->xgxs_int_mask);
784 
785 		} else { /* flag == 0 */
786 
787 			/* Disable MC Intrs in the general intr mask register */
788 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
789 				XGE_HAL_ALL_INTRS_DIS, &bar0->xgxs_int_mask);
790 
791 			gim |= val64;
792 		}
793 	}
794 
795 	/*  Memory Controller(MC) interrupts */
796 	if (mask & XGE_HAL_MC_INTR) {
797 		val64 = XGE_HAL_MC_INT_M;
798 		if (flag) {
799 
800 			gim &= ~((u64) val64);
801 
802 			/* Enable all MC blocks error interrupts */
803 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
804 				     0x0ULL, &bar0->mc_int_mask);
805 
806 		} else { /* flag == 0 */
807 
808 			/* Disable MC Intrs in the general intr mask
809 			 * register */
810 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
811 				     XGE_HAL_ALL_INTRS_DIS, &bar0->mc_int_mask);
812 
813 			gim |= val64;
814 		}
815 	}
816 
817 
818 	/*  Tx traffic interrupts */
819 	if (mask & XGE_HAL_TX_TRAFFIC_INTR) {
820 		val64 = XGE_HAL_TXTRAFFIC_INT_M;
821 		if (flag) {
822 
823 			gim &= ~((u64) val64);
824 
825 			/* Enable all the Tx side interrupts */
826 			/* '0' Enables all 64 TX interrupt levels. */
827 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0x0,
828 			                    &bar0->tx_traffic_mask);
829 
830 		} else { /* flag == 0 */
831 
832 			/* Disable Tx Traffic Intrs in the general intr mask
833 			 * register. */
834 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
835 			                     XGE_HAL_ALL_INTRS_DIS,
836 			                     &bar0->tx_traffic_mask);
837 			gim |= val64;
838 		}
839 	}
840 
841 	/*  Rx traffic interrupts */
842 	if (mask & XGE_HAL_RX_TRAFFIC_INTR) {
843 		val64 = XGE_HAL_RXTRAFFIC_INT_M;
844 		if (flag) {
845 			gim &= ~((u64) val64);
846 			/* '0' Enables all 8 RX interrupt levels. */
847 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0x0,
848 			                    &bar0->rx_traffic_mask);
849 
850 		} else { /* flag == 0 */
851 
852 			/* Disable Rx Traffic Intrs in the general intr mask
853 			 * register.
854 			 */
855 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
856 			                     XGE_HAL_ALL_INTRS_DIS,
857 			                     &bar0->rx_traffic_mask);
858 
859 			gim |= val64;
860 		}
861 	}
862 
863 	/* Sched Timer interrupt */
864 	if (mask & XGE_HAL_SCHED_INTR) {
865 		if (flag) {
866 			temp64 = xge_os_pio_mem_read64(hldev->pdev,
867 					hldev->regh0, &bar0->txpic_int_mask);
868 			temp64 &= ~XGE_HAL_TXPIC_INT_SCHED_INTR;
869 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
870 					temp64, &bar0->txpic_int_mask);
871 
872 			xge_hal_device_sched_timer(hldev,
873 					hldev->config.sched_timer_us,
874 					hldev->config.sched_timer_one_shot);
875 		} else {
876 			temp64 = xge_os_pio_mem_read64(hldev->pdev,
877 					hldev->regh0, &bar0->txpic_int_mask);
878 			temp64 |= XGE_HAL_TXPIC_INT_SCHED_INTR;
879 
880 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
881 					temp64, &bar0->txpic_int_mask);
882 
883 			xge_hal_device_sched_timer(hldev,
884 					XGE_HAL_SCHED_TIMER_DISABLED,
885 					XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE);
886 		}
887 	}
888 
889 	if (gim != gim_saved) {
890 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, gim,
891 			&bar0->general_int_mask);
892 		xge_debug_device(XGE_TRACE, "general_int_mask updated "
893 			 XGE_OS_LLXFMT" => "XGE_OS_LLXFMT,
894 			(unsigned long long)gim_saved, (unsigned long long)gim);
895 	}
896 }
897 
898 /*
899  * __hal_device_bimodal_configure
900  * @hldev: HAL device handle.
901  *
902  * Bimodal parameters initialization.
903  */
904 static void
__hal_device_bimodal_configure(xge_hal_device_t * hldev)905 __hal_device_bimodal_configure(xge_hal_device_t *hldev)
906 {
907 	int i;
908 
909 	for (i=0; i<XGE_HAL_MAX_RING_NUM; i++) {
910 		xge_hal_tti_config_t *tti;
911 		xge_hal_rti_config_t *rti;
912 
913 		if (!hldev->config.ring.queue[i].configured)
914 			continue;
915 		rti = &hldev->config.ring.queue[i].rti;
916 		tti = &hldev->bimodal_tti[i];
917 
918 		tti->enabled = 1;
919 		tti->urange_a = hldev->bimodal_urange_a_en * 10;
920 		tti->urange_b = 20;
921 		tti->urange_c = 30;
922 		tti->ufc_a = hldev->bimodal_urange_a_en * 8;
923 		tti->ufc_b = 16;
924 		tti->ufc_c = 32;
925 		tti->ufc_d = 64;
926 		tti->timer_val_us = hldev->bimodal_timer_val_us;
927 		tti->timer_ac_en = 1;
928 		tti->timer_ci_en = 0;
929 
930 		rti->urange_a = 10;
931 		rti->urange_b = 20;
932 		rti->urange_c = 30;
933 		rti->ufc_a = 1; /* <= for netpipe type of tests */
934 		rti->ufc_b = 4;
935 		rti->ufc_c = 4;
936 		rti->ufc_d = 4; /* <= 99% of a bandwidth traffic counts here */
937 		rti->timer_ac_en = 1;
938 		rti->timer_val_us = 5; /* for optimal bus efficiency usage */
939 	}
940 }
941 
942 /*
943  * __hal_device_tti_apply
944  * @hldev: HAL device handle.
945  *
946  * apply TTI configuration.
947  */
948 static xge_hal_status_e
__hal_device_tti_apply(xge_hal_device_t * hldev,xge_hal_tti_config_t * tti,int num,int runtime)949 __hal_device_tti_apply(xge_hal_device_t *hldev, xge_hal_tti_config_t *tti,
950 		       int num, int runtime)
951 {
952 	u64 val64, data1 = 0, data2 = 0;
953 	xge_hal_pci_bar0_t *bar0;
954 
955 	if (runtime)
956 		bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0;
957 	else
958 		bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
959 
960 	if (tti->timer_val_us) {
961 		unsigned int tx_interval;
962 
963 		if (hldev->config.pci_freq_mherz) {
964 			tx_interval = hldev->config.pci_freq_mherz *
965 					tti->timer_val_us / 64;
966 			tx_interval =
967 				__hal_fix_time_ival_herc(hldev,
968 							 tx_interval);
969 		} else {
970 			tx_interval = tti->timer_val_us;
971 		}
972 		data1 |= XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(tx_interval);
973 		if (tti->timer_ac_en) {
974 			data1 |= XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN;
975 		}
976 		if (tti->timer_ci_en) {
977 			data1 |= XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN;
978 		}
979 
980 		if (!runtime) {
981 			xge_debug_device(XGE_TRACE, "TTI[%d] timer enabled to %d, ci %s",
982 				  num, tx_interval, tti->timer_ci_en ?
983 				  "enabled": "disabled");
984 		}
985 	}
986 
987 	if (tti->urange_a ||
988 	    tti->urange_b ||
989 	    tti->urange_c ||
990 	    tti->ufc_a ||
991 	    tti->ufc_b ||
992 	    tti->ufc_c ||
993 	    tti->ufc_d ) {
994 		data1 |= XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(tti->urange_a) |
995 			 XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(tti->urange_b) |
996 			 XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(tti->urange_c);
997 
998 		data2 |= XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(tti->ufc_a) |
999 			 XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(tti->ufc_b) |
1000 			 XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(tti->ufc_c) |
1001 			 XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(tti->ufc_d);
1002 	}
1003 
1004 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
1005 	    data1, &bar0->tti_data1_mem);
1006 	(void)xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
1007 	    &bar0->tti_data1_mem);
1008 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
1009 	    data2, &bar0->tti_data2_mem);
1010 	(void)xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
1011 	    &bar0->tti_data2_mem);
1012 	xge_os_wmb();
1013 
1014 	val64 = XGE_HAL_TTI_CMD_MEM_WE | XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD |
1015 	      XGE_HAL_TTI_CMD_MEM_OFFSET(num);
1016 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
1017 		&bar0->tti_command_mem);
1018 
1019 	if (!runtime && __hal_device_register_poll(hldev, &bar0->tti_command_mem,
1020 		   0, XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD,
1021 		   XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) {
1022 		/* upper layer may require to repeat */
1023 		return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING;
1024 	}
1025 
1026 	if (!runtime) {
1027 		xge_debug_device(XGE_TRACE, "TTI[%d] configured: tti_data1_mem 0x"
1028 		   XGE_OS_LLXFMT, num,
1029 		   (unsigned long long)xge_os_pio_mem_read64(hldev->pdev,
1030 		   hldev->regh0, &bar0->tti_data1_mem));
1031 	}
1032 
1033 	return XGE_HAL_OK;
1034 }
1035 
1036 /*
1037  * __hal_device_tti_configure
1038  * @hldev: HAL device handle.
1039  *
1040  * TTI Initialization.
1041  * Initialize Transmit Traffic Interrupt Scheme.
1042  */
1043 static xge_hal_status_e
__hal_device_tti_configure(xge_hal_device_t * hldev,int runtime)1044 __hal_device_tti_configure(xge_hal_device_t *hldev, int runtime)
1045 {
1046 	int i;
1047 
1048 	for (i=0; i<XGE_HAL_MAX_FIFO_NUM; i++) {
1049 		int j;
1050 
1051 		if (!hldev->config.fifo.queue[i].configured)
1052 			continue;
1053 
1054 		for (j=0; j<XGE_HAL_MAX_FIFO_TTI_NUM; j++) {
1055 			xge_hal_status_e status;
1056 
1057 			if (!hldev->config.fifo.queue[i].tti[j].enabled)
1058 				continue;
1059 
1060 			/* at least some TTI enabled. Record it. */
1061 			hldev->tti_enabled = 1;
1062 
1063 			status = __hal_device_tti_apply(hldev,
1064 				&hldev->config.fifo.queue[i].tti[j],
1065 				i * XGE_HAL_MAX_FIFO_TTI_NUM + j, runtime);
1066 			if (status != XGE_HAL_OK)
1067 				return status;
1068 		}
1069 	}
1070 
1071 	/* processing bimodal TTIs */
1072 	for (i=0; i<XGE_HAL_MAX_RING_NUM; i++) {
1073 		xge_hal_status_e status;
1074 
1075 		if (!hldev->bimodal_tti[i].enabled)
1076 			continue;
1077 
1078 		/* at least some bimodal TTI enabled. Record it. */
1079 		hldev->tti_enabled = 1;
1080 
1081 		status = __hal_device_tti_apply(hldev, &hldev->bimodal_tti[i],
1082 				XGE_HAL_MAX_FIFO_TTI_RING_0 + i, runtime);
1083 		if (status != XGE_HAL_OK)
1084 			return status;
1085 
1086 	}
1087 
1088 	return XGE_HAL_OK;
1089 }
1090 
1091 /*
1092  * __hal_device_rti_configure
1093  * @hldev: HAL device handle.
1094  *
1095  * RTI Initialization.
1096  * Initialize Receive Traffic Interrupt Scheme.
1097  */
1098 xge_hal_status_e
__hal_device_rti_configure(xge_hal_device_t * hldev,int runtime)1099 __hal_device_rti_configure(xge_hal_device_t *hldev, int runtime)
1100 {
1101 	xge_hal_pci_bar0_t *bar0;
1102 	u64 val64, data1 = 0, data2 = 0;
1103 	int i;
1104 
1105 	if (runtime) {
1106 		/*
1107 		 * we don't want to re-configure RTI in case when
1108 		 * bimodal interrupts are in use. Instead reconfigure TTI
1109 		 * with new RTI values.
1110 		 */
1111 		if (hldev->config.bimodal_interrupts) {
1112 			__hal_device_bimodal_configure(hldev);
1113 			return __hal_device_tti_configure(hldev, 1);
1114 		}
1115 		bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0;
1116 	} else
1117 		bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
1118 
1119 	for (i=0; i<XGE_HAL_MAX_RING_NUM; i++) {
1120 		xge_hal_rti_config_t *rti = &hldev->config.ring.queue[i].rti;
1121 
1122 		if (!hldev->config.ring.queue[i].configured)
1123 			continue;
1124 
1125 		if (rti->timer_val_us) {
1126 			unsigned int rx_interval;
1127 
1128 			if (hldev->config.pci_freq_mherz) {
1129 				rx_interval = hldev->config.pci_freq_mherz *
1130 						rti->timer_val_us / 8;
1131 				rx_interval =
1132 					__hal_fix_time_ival_herc(hldev,
1133 								 rx_interval);
1134 			} else {
1135 				rx_interval = rti->timer_val_us;
1136 			}
1137 			data1 |=XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(rx_interval);
1138 			if (rti->timer_ac_en) {
1139 				data1 |= XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN;
1140 			}
1141 			data1 |= XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN;
1142 		}
1143 
1144 		if (rti->urange_a ||
1145 		    rti->urange_b ||
1146 		    rti->urange_c ||
1147 		    rti->ufc_a ||
1148 		    rti->ufc_b ||
1149 		    rti->ufc_c ||
1150 		    rti->ufc_d) {
1151 			data1 |=XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(rti->urange_a) |
1152 				XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(rti->urange_b) |
1153 				XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(rti->urange_c);
1154 
1155 			data2 |= XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(rti->ufc_a) |
1156 				 XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(rti->ufc_b) |
1157 				 XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(rti->ufc_c) |
1158 				 XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(rti->ufc_d);
1159 		}
1160 
1161 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
1162 		    data1, &bar0->rti_data1_mem);
1163 		(void)xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
1164 		    &bar0->rti_data1_mem);
1165 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
1166 		    data2, &bar0->rti_data2_mem);
1167 		(void)xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
1168 		    &bar0->rti_data2_mem);
1169 
1170 		xge_os_wmb();
1171 
1172 		val64 = XGE_HAL_RTI_CMD_MEM_WE |
1173 		XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD;
1174 		val64 |= XGE_HAL_RTI_CMD_MEM_OFFSET(i);
1175 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
1176 		                    &bar0->rti_command_mem);
1177 
1178 		if (!runtime && __hal_device_register_poll(hldev,
1179 			&bar0->rti_command_mem, 0,
1180 			XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD,
1181 			XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) {
1182 			/* upper layer may require to repeat */
1183 			return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING;
1184 		}
1185 
1186 		if (!runtime) {
1187 			xge_debug_device(XGE_TRACE,
1188 			  "RTI[%d] configured: rti_data1_mem 0x"XGE_OS_LLXFMT,
1189 			  i,
1190 			  (unsigned long long)xge_os_pio_mem_read64(hldev->pdev,
1191 					  hldev->regh0, &bar0->rti_data1_mem));
1192 		}
1193 	}
1194 
1195 	return XGE_HAL_OK;
1196 }
1197 
1198 
1199 /* Constants to be programmed into the Xena's registers to configure
1200  * the XAUI. */
1201 static u64 default_xena_mdio_cfg[] = {
1202 	/* Reset PMA PLL */
1203 	0xC001010000000000ULL, 0xC0010100000000E0ULL,
1204 	0xC0010100008000E4ULL,
1205 	/* Remove Reset from PMA PLL */
1206 	0xC001010000000000ULL, 0xC0010100000000E0ULL,
1207 	0xC0010100000000E4ULL,
1208 	END_SIGN
1209 };
1210 
1211 static u64 default_herc_mdio_cfg[] = {
1212 	END_SIGN
1213 };
1214 
1215 static u64 default_xena_dtx_cfg[] = {
1216 	0x8000051500000000ULL, 0x80000515000000E0ULL,
1217 	0x80000515D93500E4ULL, 0x8001051500000000ULL,
1218 	0x80010515000000E0ULL, 0x80010515001E00E4ULL,
1219 	0x8002051500000000ULL, 0x80020515000000E0ULL,
1220 	0x80020515F21000E4ULL,
1221 	/* Set PADLOOPBACKN */
1222 	0x8002051500000000ULL, 0x80020515000000E0ULL,
1223 	0x80020515B20000E4ULL, 0x8003051500000000ULL,
1224 	0x80030515000000E0ULL, 0x80030515B20000E4ULL,
1225 	0x8004051500000000ULL, 0x80040515000000E0ULL,
1226 	0x80040515B20000E4ULL, 0x8005051500000000ULL,
1227 	0x80050515000000E0ULL, 0x80050515B20000E4ULL,
1228 	SWITCH_SIGN,
1229 	/* Remove PADLOOPBACKN */
1230 	0x8002051500000000ULL, 0x80020515000000E0ULL,
1231 	0x80020515F20000E4ULL, 0x8003051500000000ULL,
1232 	0x80030515000000E0ULL, 0x80030515F20000E4ULL,
1233 	0x8004051500000000ULL, 0x80040515000000E0ULL,
1234 	0x80040515F20000E4ULL, 0x8005051500000000ULL,
1235 	0x80050515000000E0ULL, 0x80050515F20000E4ULL,
1236 	END_SIGN
1237 };
1238 
1239 /*
1240 static u64 default_herc_dtx_cfg[] = {
1241 	0x80000515BA750000ULL, 0x80000515BA7500E0ULL,
1242 	0x80000515BA750004ULL, 0x80000515BA7500E4ULL,
1243 	0x80010515003F0000ULL, 0x80010515003F00E0ULL,
1244 	0x80010515003F0004ULL, 0x80010515003F00E4ULL,
1245 	0x80020515F2100000ULL, 0x80020515F21000E0ULL,
1246 	0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1247 	END_SIGN
1248 };
1249 */
1250 
1251 static u64 default_herc_dtx_cfg[] = {
1252     0x8000051536750000ULL, 0x80000515367500E0ULL,
1253     0x8000051536750004ULL, 0x80000515367500E4ULL,
1254 
1255     0x80010515003F0000ULL, 0x80010515003F00E0ULL,
1256     0x80010515003F0004ULL, 0x80010515003F00E4ULL,
1257 
1258     0x801205150D440000ULL, 0x801205150D4400E0ULL,
1259     0x801205150D440004ULL, 0x801205150D4400E4ULL,
1260 
1261     0x80020515F2100000ULL, 0x80020515F21000E0ULL,
1262     0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1263     END_SIGN
1264 };
1265 
1266 
1267 void
__hal_serial_mem_write64(xge_hal_device_t * hldev,u64 value,u64 * reg)1268 __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg)
1269 {
1270 	__hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0,
1271 		    (u32)(value>>32), reg);
1272 	xge_os_wmb();
1273 	__hal_pio_mem_write32_lower(hldev->pdev, hldev->regh0,
1274 		    (u32)value, reg);
1275 	xge_os_wmb();
1276 	xge_os_mdelay(1);
1277 }
1278 
1279 u64
__hal_serial_mem_read64(xge_hal_device_t * hldev,u64 * reg)1280 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg)
1281 {
1282 	u64 val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
1283 			reg);
1284 	xge_os_mdelay(1);
1285 	return val64;
1286 }
1287 
1288 /*
1289  * __hal_device_xaui_configure
1290  * @hldev: HAL device handle.
1291  *
1292  * Configure XAUI Interface of Xena.
1293  *
1294  * To Configure the Xena's XAUI, one has to write a series
1295  * of 64 bit values into two registers in a particular
1296  * sequence. Hence a macro 'SWITCH_SIGN' has been defined
1297  * which will be defined in the array of configuration values
1298  * (default_dtx_cfg & default_mdio_cfg) at appropriate places
1299  * to switch writing from one regsiter to another. We continue
1300  * writing these values until we encounter the 'END_SIGN' macro.
1301  * For example, After making a series of 21 writes into
1302  * dtx_control register the 'SWITCH_SIGN' appears and hence we
1303  * start writing into mdio_control until we encounter END_SIGN.
1304  */
1305 static void
__hal_device_xaui_configure(xge_hal_device_t * hldev)1306 __hal_device_xaui_configure(xge_hal_device_t *hldev)
1307 {
1308 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
1309 	int mdio_cnt = 0, dtx_cnt = 0;
1310 	u64 *default_dtx_cfg = NULL, *default_mdio_cfg = NULL;
1311 
1312 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) {
1313 		default_dtx_cfg = default_xena_dtx_cfg;
1314 		default_mdio_cfg = default_xena_mdio_cfg;
1315 	} else if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) {
1316 		default_dtx_cfg = default_herc_dtx_cfg;
1317 		default_mdio_cfg = default_herc_mdio_cfg;
1318 	} else {
1319 		xge_assert(default_dtx_cfg);
1320     return;
1321   }
1322 
1323 	do {
1324 	    dtx_cfg:
1325 		while (default_dtx_cfg[dtx_cnt] != END_SIGN) {
1326 			if (default_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
1327 				dtx_cnt++;
1328 				goto mdio_cfg;
1329 			}
1330 			__hal_serial_mem_write64(hldev, default_dtx_cfg[dtx_cnt],
1331 					       &bar0->dtx_control);
1332 			dtx_cnt++;
1333 		}
1334 	    mdio_cfg:
1335 		while (default_mdio_cfg[mdio_cnt] != END_SIGN) {
1336 			if (default_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
1337 				mdio_cnt++;
1338 				goto dtx_cfg;
1339 			}
1340 			__hal_serial_mem_write64(hldev, default_mdio_cfg[mdio_cnt],
1341 				&bar0->mdio_control);
1342 			mdio_cnt++;
1343 		}
1344 	} while ( !((default_dtx_cfg[dtx_cnt] == END_SIGN) &&
1345 		    (default_mdio_cfg[mdio_cnt] == END_SIGN)) );
1346 
1347 	xge_debug_device(XGE_TRACE, "%s", "XAUI interface configured");
1348 }
1349 
1350 /*
1351  * __hal_device_mac_link_util_set
1352  * @hldev: HAL device handle.
1353  *
1354  * Set sampling rate to calculate link utilization.
1355  */
1356 static void
__hal_device_mac_link_util_set(xge_hal_device_t * hldev)1357 __hal_device_mac_link_util_set(xge_hal_device_t *hldev)
1358 {
1359 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
1360 	u64 val64;
1361 
1362 	val64 = XGE_HAL_MAC_TX_LINK_UTIL_VAL(
1363 			hldev->config.mac.tmac_util_period) |
1364 		XGE_HAL_MAC_RX_LINK_UTIL_VAL(
1365 			hldev->config.mac.rmac_util_period);
1366 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
1367 	                     &bar0->mac_link_util);
1368 	xge_debug_device(XGE_TRACE, "%s",
1369 			  "bandwidth link utilization configured");
1370 }
1371 
1372 /*
1373  * __hal_device_set_swapper
1374  * @hldev: HAL device handle.
1375  *
1376  * Set the Xframe's byte "swapper" in accordance with
1377  * endianness of the host.
1378  */
1379 xge_hal_status_e
__hal_device_set_swapper(xge_hal_device_t * hldev)1380 __hal_device_set_swapper(xge_hal_device_t *hldev)
1381 {
1382 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
1383 	u64 val64;
1384 
1385 	/*
1386 	 * from 32bit errarta:
1387 	 *
1388 	 * The SWAPPER_CONTROL register determines how the adapter accesses
1389 	 * host memory as well as how it responds to read and write requests
1390 	 * from the host system. Writes to this register should be performed
1391 	 * carefully, since the byte swappers could reverse the order of bytes.
1392 	 * When configuring this register keep in mind that writes to the PIF
1393 	 * read and write swappers could reverse the order of the upper and
1394 	 * lower 32-bit words. This means that the driver may have to write
1395 	 * to the upper 32 bits of the SWAPPER_CONTROL twice in order to
1396 	 * configure the entire register. */
1397 
1398 	/*
1399 	 * The device by default set to a big endian format, so a big endian
1400 	 * driver need not set anything.
1401 	 */
1402 
1403 #if defined(XGE_HAL_CUSTOM_HW_SWAPPER)
1404 
1405 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
1406 			0xffffffffffffffffULL, &bar0->swapper_ctrl);
1407 
1408 	val64 = XGE_HAL_CUSTOM_HW_SWAPPER;
1409 
1410 	xge_os_wmb();
1411 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
1412 			     &bar0->swapper_ctrl);
1413 
1414 	xge_debug_device(XGE_TRACE, "using custom HW swapper 0x"XGE_OS_LLXFMT,
1415 			(unsigned long long)val64);
1416 
1417 #elif !defined(XGE_OS_HOST_BIG_ENDIAN)
1418 
1419 	/*
1420 	 * Initially we enable all bits to make it accessible by the driver,
1421 	 * then we selectively enable only those bits that we want to set.
1422 	 * i.e. force swapper to swap for the first time since second write
1423 	 * will overwrite with the final settings.
1424 	 *
1425 	 * Use only for little endian platforms.
1426 	 */
1427 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
1428 			0xffffffffffffffffULL, &bar0->swapper_ctrl);
1429 	xge_os_wmb();
1430 	val64 = (XGE_HAL_SWAPPER_CTRL_PIF_R_FE |
1431 		 XGE_HAL_SWAPPER_CTRL_PIF_R_SE |
1432 		 XGE_HAL_SWAPPER_CTRL_PIF_W_FE |
1433 		 XGE_HAL_SWAPPER_CTRL_PIF_W_SE |
1434 		 XGE_HAL_SWAPPER_CTRL_RTH_FE |
1435 		 XGE_HAL_SWAPPER_CTRL_RTH_SE |
1436 		 XGE_HAL_SWAPPER_CTRL_TXP_FE |
1437 		 XGE_HAL_SWAPPER_CTRL_TXP_SE |
1438 		 XGE_HAL_SWAPPER_CTRL_TXD_R_FE |
1439 		 XGE_HAL_SWAPPER_CTRL_TXD_R_SE |
1440 		 XGE_HAL_SWAPPER_CTRL_TXD_W_FE |
1441 		 XGE_HAL_SWAPPER_CTRL_TXD_W_SE |
1442 		 XGE_HAL_SWAPPER_CTRL_TXF_R_FE |
1443 		 XGE_HAL_SWAPPER_CTRL_RXD_R_FE |
1444 		 XGE_HAL_SWAPPER_CTRL_RXD_R_SE |
1445 		 XGE_HAL_SWAPPER_CTRL_RXD_W_FE |
1446 		 XGE_HAL_SWAPPER_CTRL_RXD_W_SE |
1447 		 XGE_HAL_SWAPPER_CTRL_RXF_W_FE |
1448 		 XGE_HAL_SWAPPER_CTRL_XMSI_FE |
1449 		 XGE_HAL_SWAPPER_CTRL_STATS_FE | XGE_HAL_SWAPPER_CTRL_STATS_SE);
1450 
1451 	/*
1452 	if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX) {
1453 		 val64 |= XGE_HAL_SWAPPER_CTRL_XMSI_SE;
1454 	} */
1455 	__hal_pio_mem_write32_lower(hldev->pdev, hldev->regh0, (u32)val64,
1456 	                     &bar0->swapper_ctrl);
1457 	xge_os_wmb();
1458 	__hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, (u32)(val64>>32),
1459 	                     &bar0->swapper_ctrl);
1460 	xge_os_wmb();
1461 	__hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, (u32)(val64>>32),
1462 	                     &bar0->swapper_ctrl);
1463 	xge_debug_device(XGE_TRACE, "%s", "using little endian set");
1464 #endif
1465 
1466 	/*  Verifying if endian settings are accurate by reading a feedback
1467 	 *  register.  */
1468 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
1469 	                            &bar0->pif_rd_swapper_fb);
1470 	if (val64 != XGE_HAL_IF_RD_SWAPPER_FB) {
1471 		xge_debug_device(XGE_ERR, "pif_rd_swapper_fb read "XGE_OS_LLXFMT,
1472 			  (unsigned long long) val64);
1473 		return XGE_HAL_ERR_SWAPPER_CTRL;
1474 	}
1475 
1476 	xge_debug_device(XGE_TRACE, "%s", "be/le swapper enabled");
1477 
1478 	return XGE_HAL_OK;
1479 }
1480 
1481 /*
1482  * __hal_device_rts_mac_configure - Configure RTS steering based on
1483  * destination mac address.
1484  * @hldev: HAL device handle.
1485  *
1486  */
1487 xge_hal_status_e
__hal_device_rts_mac_configure(xge_hal_device_t * hldev)1488 __hal_device_rts_mac_configure(xge_hal_device_t *hldev)
1489 {
1490 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
1491 	u64 val64;
1492 
1493 	if (!hldev->config.rts_mac_en) {
1494 		return XGE_HAL_OK;
1495 	}
1496 
1497 	/*
1498 	* Set the receive traffic steering mode from default(classic)
1499 	* to enhanced.
1500 	*/
1501 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
1502 					&bar0->rts_ctrl);
1503 	val64 |=  XGE_HAL_RTS_CTRL_ENHANCED_MODE;
1504 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
1505 				val64, &bar0->rts_ctrl);
1506 	return XGE_HAL_OK;
1507 }
1508 
1509 /*
1510  * __hal_device_rts_port_configure - Configure RTS steering based on
1511  * destination or source port number.
1512  * @hldev: HAL device handle.
1513  *
1514  */
1515 xge_hal_status_e
__hal_device_rts_port_configure(xge_hal_device_t * hldev)1516 __hal_device_rts_port_configure(xge_hal_device_t *hldev)
1517 {
1518 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
1519 	u64 val64;
1520 	int rnum;
1521 
1522 	if (!hldev->config.rts_port_en) {
1523 		return XGE_HAL_OK;
1524 	}
1525 
1526 	/*
1527 	 * Set the receive traffic steering mode from default(classic)
1528 	 * to enhanced.
1529 	 */
1530 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
1531 					&bar0->rts_ctrl);
1532 	val64 |=  XGE_HAL_RTS_CTRL_ENHANCED_MODE;
1533 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
1534 				val64, &bar0->rts_ctrl);
1535 
1536 	/*
1537 	 * Initiate port steering according to per-ring configuration
1538 	 */
1539 	for (rnum = 0; rnum < XGE_HAL_MAX_RING_NUM; rnum++) {
1540 		int pnum;
1541 		xge_hal_ring_queue_t *queue = &hldev->config.ring.queue[rnum];
1542 
1543 		if (!queue->configured || queue->rts_port_en)
1544 			continue;
1545 
1546 		for (pnum = 0; pnum < XGE_HAL_MAX_STEERABLE_PORTS; pnum++) {
1547 			xge_hal_rts_port_t *port = &queue->rts_ports[pnum];
1548 
1549 			/*
1550 			 * Skip and clear empty ports
1551 			 */
1552 			if (!port->num) {
1553 				/*
1554 				 * Clear CAM memory
1555 				 */
1556 				xge_os_pio_mem_write64(hldev->pdev,
1557 				       hldev->regh0, 0ULL,
1558 				       &bar0->rts_pn_cam_data);
1559 
1560 				val64 = BIT(7) | BIT(15);
1561 			} else {
1562 				/*
1563 				 * Assign new Port values according
1564 				 * to configuration
1565 				 */
1566 				val64 = vBIT(port->num,8,16) |
1567 					vBIT(rnum,37,3) | BIT(63);
1568 				if (port->src)
1569 					val64 = BIT(47);
1570 				if (!port->udp)
1571 					val64 = BIT(7);
1572 				xge_os_pio_mem_write64(hldev->pdev,
1573 					       hldev->regh0, val64,
1574 					       &bar0->rts_pn_cam_data);
1575 
1576 				val64 = BIT(7) | BIT(15) | vBIT(pnum,24,8);
1577 			}
1578 
1579 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
1580 					       val64, &bar0->rts_pn_cam_ctrl);
1581 
1582 			/* poll until done */
1583 			if (__hal_device_register_poll(hldev,
1584 			       &bar0->rts_pn_cam_ctrl, 0,
1585 			       XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED,
1586 			       XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) !=
1587 								XGE_HAL_OK) {
1588 				/* upper layer may require to repeat */
1589 				return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING;
1590 			}
1591 		}
1592 	}
1593 	return XGE_HAL_OK;
1594 }
1595 
1596 /*
1597  * __hal_device_rts_qos_configure - Configure RTS steering based on
1598  * qos.
1599  * @hldev: HAL device handle.
1600  *
1601  */
1602 xge_hal_status_e
__hal_device_rts_qos_configure(xge_hal_device_t * hldev)1603 __hal_device_rts_qos_configure(xge_hal_device_t *hldev)
1604 {
1605 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
1606 	u64 val64;
1607 	int j, rx_ring_num;
1608 
1609 	if (!hldev->config.rts_qos_en) {
1610 		return XGE_HAL_OK;
1611 	}
1612 
1613 	/* First clear the RTS_DS_MEM_DATA */
1614 	val64 = 0;
1615 	for (j = 0; j < 64; j++ )
1616 	{
1617 		/* First clear the value */
1618 		val64 = XGE_HAL_RTS_DS_MEM_DATA(0);
1619 
1620 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
1621 				       &bar0->rts_ds_mem_data);
1622 
1623 		val64 = XGE_HAL_RTS_DS_MEM_CTRL_WE |
1624 			XGE_HAL_RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
1625 			XGE_HAL_RTS_DS_MEM_CTRL_OFFSET ( j );
1626 
1627 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
1628 				       &bar0->rts_ds_mem_ctrl);
1629 
1630 
1631 		/* poll until done */
1632 		if (__hal_device_register_poll(hldev,
1633 		       &bar0->rts_ds_mem_ctrl, 0,
1634 		       XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
1635 		       XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) {
1636 			/* upper layer may require to repeat */
1637 			return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING;
1638 		}
1639 
1640 	}
1641 
1642 	rx_ring_num = 0;
1643 	for (j = 0; j < XGE_HAL_MAX_RING_NUM; j++) {
1644 		if (hldev->config.ring.queue[j].configured)
1645 			rx_ring_num++;
1646 	}
1647 
1648 	switch (rx_ring_num) {
1649 	case 1:
1650 		val64 = 0x0;
1651 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0);
1652 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1);
1653 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2);
1654 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3);
1655 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4);
1656 		break;
1657 	case 2:
1658 		val64 = 0x0001000100010001ULL;
1659 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0);
1660 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1);
1661 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2);
1662 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3);
1663 		val64 = 0x0001000100000000ULL;
1664 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4);
1665 		break;
1666 	case 3:
1667 		val64 = 0x0001020001020001ULL;
1668 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0);
1669 		val64 = 0x0200010200010200ULL;
1670 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1);
1671 		val64 = 0x0102000102000102ULL;
1672 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2);
1673 		val64 = 0x0001020001020001ULL;
1674 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3);
1675 		val64 = 0x0200010200000000ULL;
1676 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4);
1677 		break;
1678 	case 4:
1679 		val64 = 0x0001020300010203ULL;
1680 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0);
1681 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1);
1682 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2);
1683 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3);
1684 		val64 = 0x0001020300000000ULL;
1685 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4);
1686 		break;
1687 	case 5:
1688 		val64 = 0x0001020304000102ULL;
1689 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0);
1690 		val64 = 0x0304000102030400ULL;
1691 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1);
1692 		val64 = 0x0102030400010203ULL;
1693 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2);
1694 		val64 = 0x0400010203040001ULL;
1695 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3);
1696 		val64 = 0x0203040000000000ULL;
1697 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4);
1698 		break;
1699 	case 6:
1700 		val64 = 0x0001020304050001ULL;
1701 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0);
1702 		val64 = 0x0203040500010203ULL;
1703 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1);
1704 		val64 = 0x0405000102030405ULL;
1705 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2);
1706 		val64 = 0x0001020304050001ULL;
1707 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3);
1708 		val64 = 0x0203040500000000ULL;
1709 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4);
1710 		break;
1711 	case 7:
1712 		val64 = 0x0001020304050600ULL;
1713 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0);
1714 		val64 = 0x0102030405060001ULL;
1715 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1);
1716 		val64 = 0x0203040506000102ULL;
1717 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2);
1718 		val64 = 0x0304050600010203ULL;
1719 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3);
1720 		val64 = 0x0405060000000000ULL;
1721 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4);
1722 		break;
1723 	case 8:
1724 		val64 = 0x0001020304050607ULL;
1725 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0);
1726 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1);
1727 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2);
1728 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3);
1729 		val64 = 0x0001020300000000ULL;
1730 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4);
1731 		break;
1732 	}
1733 
1734 	return XGE_HAL_OK;
1735 }
1736 
1737 /*
1738  * xge__hal_device_rts_mac_enable
1739  *
1740  * @devh: HAL device handle.
1741  * @index: index number where the MAC addr will be stored
1742  * @macaddr: MAC address
1743  *
1744  * - Enable RTS steering for the given MAC address. This function has to be
1745  * called with lock acquired.
1746  *
1747  * NOTE:
1748  * 1. ULD has to call this function with the index value which
1749  *    statisfies the following condition:
1750  *	ring_num = (index % 8)
1751  * 2.ULD also needs to make sure that the index is not
1752  *   occupied by any MAC address. If that index has any MAC address
1753  *   it will be overwritten and HAL will not check for it.
1754  *
1755  */
1756 xge_hal_status_e
xge_hal_device_rts_mac_enable(xge_hal_device_h devh,int index,macaddr_t macaddr)1757 xge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr)
1758 {
1759 	int max_addr = XGE_HAL_MAX_MAC_ADDRESSES;
1760 	xge_hal_status_e status;
1761 
1762 	xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
1763 
1764 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)
1765 		max_addr = XGE_HAL_MAX_MAC_ADDRESSES_HERC;
1766 
1767 	if ( index >= max_addr )
1768 		return XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES;
1769 
1770 	/*
1771 	 * Set the MAC address at the given location marked by index.
1772 	 */
1773 	status = xge_hal_device_macaddr_set(hldev, index, macaddr);
1774 	if (status != XGE_HAL_OK) {
1775 		xge_debug_device(XGE_ERR, "%s",
1776 			"Not able to set the mac addr");
1777 		return status;
1778 	}
1779 
1780 	return xge_hal_device_rts_section_enable(hldev, index);
1781 }
1782 
1783 /*
1784  * xge__hal_device_rts_mac_disable
1785  * @hldev: HAL device handle.
1786  * @index: index number where to disable the MAC addr
1787  *
1788  * Disable RTS Steering based on the MAC address.
1789  * This function should be called with lock acquired.
1790  *
1791  */
1792 xge_hal_status_e
xge_hal_device_rts_mac_disable(xge_hal_device_h devh,int index)1793 xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index)
1794 {
1795 	xge_hal_status_e status;
1796 	u8 macaddr[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
1797 	int max_addr = XGE_HAL_MAX_MAC_ADDRESSES;
1798 
1799 	xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
1800 
1801 	xge_debug_ll(XGE_TRACE, "the index value is %d ", index);
1802 
1803 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)
1804 		max_addr = XGE_HAL_MAX_MAC_ADDRESSES_HERC;
1805 
1806 	if ( index >= max_addr )
1807 		return XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES;
1808 
1809 	/*
1810 	 * Disable MAC address @ given index location
1811 	 */
1812 	status = xge_hal_device_macaddr_set(hldev, index, macaddr);
1813 	if (status != XGE_HAL_OK) {
1814 		xge_debug_device(XGE_ERR, "%s",
1815 			"Not able to set the mac addr");
1816 		return status;
1817 	}
1818 
1819 	return XGE_HAL_OK;
1820 }
1821 
1822 
1823 /*
1824  * __hal_device_rth_configure - Configure RTH for the device
1825  * @hldev: HAL device handle.
1826  *
1827  * Using IT (Indirection Table).
1828  */
1829 xge_hal_status_e
__hal_device_rth_it_configure(xge_hal_device_t * hldev)1830 __hal_device_rth_it_configure(xge_hal_device_t *hldev)
1831 {
1832 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
1833 	u64 val64;
1834 	int rings[XGE_HAL_MAX_RING_NUM]={0};
1835 	int rnum;
1836 	int rmax;
1837 	int buckets_num;
1838 	int bucket;
1839 
1840 	if (!hldev->config.rth_en) {
1841 		return XGE_HAL_OK;
1842 	}
1843 
1844 	/*
1845 	 * Set the receive traffic steering mode from default(classic)
1846 	 * to enhanced.
1847 	 */
1848 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
1849 				      &bar0->rts_ctrl);
1850 	val64 |=  XGE_HAL_RTS_CTRL_ENHANCED_MODE;
1851 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
1852 			       val64, &bar0->rts_ctrl);
1853 
1854 	buckets_num = (1 << hldev->config.rth_bucket_size);
1855 
1856 	rmax=0;
1857 	for (rnum = 0; rnum < XGE_HAL_MAX_RING_NUM; rnum++) {
1858 		if (hldev->config.ring.queue[rnum].configured &&
1859 				hldev->config.ring.queue[rnum].rth_en)
1860 				rings[rmax++] = rnum;
1861 	}
1862 
1863 	rnum = 0;
1864 	/* for starters: fill in all the buckets with rings "equally" */
1865 	for (bucket = 0; bucket < buckets_num; bucket++) {
1866 
1867 	    if (rnum == rmax)
1868            rnum = 0;
1869 
1870 		/* write data */
1871 		val64 = XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN |
1872 		        XGE_HAL_RTS_RTH_MAP_MEM_DATA(rings[rnum]);
1873 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
1874 				     &bar0->rts_rth_map_mem_data);
1875 
1876 		/* execute */
1877 		val64 = XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE |
1878 			XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE |
1879 			XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(bucket);
1880 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
1881 				     &bar0->rts_rth_map_mem_ctrl);
1882 
1883 		/* poll until done */
1884 		if (__hal_device_register_poll(hldev,
1885 			&bar0->rts_rth_map_mem_ctrl, 0,
1886 			XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE,
1887 			XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) {
1888 			return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING;
1889 		}
1890 
1891         rnum++;
1892 	}
1893 
1894 	val64 = XGE_HAL_RTS_RTH_EN;
1895 	val64 |= XGE_HAL_RTS_RTH_BUCKET_SIZE(hldev->config.rth_bucket_size);
1896 	val64 |= XGE_HAL_RTS_RTH_TCP_IPV4_EN | XGE_HAL_RTS_RTH_UDP_IPV4_EN | XGE_HAL_RTS_RTH_IPV4_EN |
1897 			 XGE_HAL_RTS_RTH_TCP_IPV6_EN |XGE_HAL_RTS_RTH_UDP_IPV6_EN | XGE_HAL_RTS_RTH_IPV6_EN |
1898 			 XGE_HAL_RTS_RTH_TCP_IPV6_EX_EN | XGE_HAL_RTS_RTH_UDP_IPV6_EX_EN | XGE_HAL_RTS_RTH_IPV6_EX_EN;
1899 
1900 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
1901 			     &bar0->rts_rth_cfg);
1902 
1903 	xge_debug_device(XGE_TRACE, "RTH configured, bucket_size %d",
1904 			  hldev->config.rth_bucket_size);
1905 
1906 	return XGE_HAL_OK;
1907 }
1908 
1909 
1910 /*
1911  * __hal_spdm_entry_add - Add a new entry to the SPDM table.
1912  *
1913  * Add a new entry to the SPDM table
1914  *
1915  * This function add a new entry to the SPDM table.
1916  *
1917  * Note:
1918  *   This function should be called with spdm_lock.
1919  *
1920  * See also: xge_hal_spdm_entry_add , xge_hal_spdm_entry_remove.
1921  */
1922 static xge_hal_status_e
__hal_spdm_entry_add(xge_hal_device_t * hldev,xge_hal_ipaddr_t * src_ip,xge_hal_ipaddr_t * dst_ip,u16 l4_sp,u16 l4_dp,u8 is_tcp,u8 is_ipv4,u8 tgt_queue,u32 jhash_value,u16 spdm_entry)1923 __hal_spdm_entry_add(xge_hal_device_t *hldev, xge_hal_ipaddr_t *src_ip,
1924 		xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, u8 is_tcp,
1925 		u8 is_ipv4, u8 tgt_queue, u32 jhash_value, u16 spdm_entry)
1926 {
1927 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
1928 	u64 val64;
1929 	u64 spdm_line_arr[8];
1930 	u8 line_no;
1931 
1932 	/*
1933 	 * Clear the SPDM READY bit
1934 	 */
1935 	val64 = XGE_HAL_RX_PIC_INT_REG_SPDM_READY;
1936 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
1937 			       &bar0->rxpic_int_reg);
1938 
1939 	xge_debug_device(XGE_TRACE,
1940 			"L4 SP %x:DP %x: hash %x tgt_queue %d ",
1941 			l4_sp, l4_dp, jhash_value, tgt_queue);
1942 
1943 	xge_os_memzero(&spdm_line_arr, sizeof(spdm_line_arr));
1944 
1945 	/*
1946 	 * Construct the SPDM entry.
1947 	 */
1948 	spdm_line_arr[0] = vBIT(l4_sp,0,16) |
1949 			   vBIT(l4_dp,16,32) |
1950 			   vBIT(tgt_queue,53,3)	|
1951 			   vBIT(is_tcp,59,1) |
1952 			   vBIT(is_ipv4,63,1);
1953 
1954 
1955 	if (is_ipv4) {
1956 		spdm_line_arr[1] = vBIT(src_ip->ipv4.addr,0,32) |
1957 				   vBIT(dst_ip->ipv4.addr,32,32);
1958 
1959 	} else {
1960 		xge_os_memcpy(&spdm_line_arr[1], &src_ip->ipv6.addr[0], 8);
1961 		xge_os_memcpy(&spdm_line_arr[2], &src_ip->ipv6.addr[1], 8);
1962 		xge_os_memcpy(&spdm_line_arr[3], &dst_ip->ipv6.addr[0], 8);
1963 		xge_os_memcpy(&spdm_line_arr[4], &dst_ip->ipv6.addr[1], 8);
1964 	}
1965 
1966 	spdm_line_arr[7] = vBIT(jhash_value,0,32) |
1967 				BIT(63);  /* entry enable bit */
1968 
1969 	/*
1970 	 * Add the entry to the SPDM table
1971 	 */
1972 	for(line_no = 0; line_no < 8; line_no++) {
1973 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
1974 				spdm_line_arr[line_no],
1975 				(void *)((char *)hldev->spdm_mem_base +
1976 						(spdm_entry * 64) +
1977 						(line_no * 8)));
1978 	}
1979 
1980 	/*
1981 	 * Wait for the operation to be completed.
1982 	 */
1983 	if (__hal_device_register_poll(hldev, &bar0->rxpic_int_reg, 1,
1984 			XGE_HAL_RX_PIC_INT_REG_SPDM_READY,
1985 			XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) {
1986 		return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING;
1987 	}
1988 
1989 	/*
1990 	 * Add this information to a local SPDM table. The purpose of
1991 	 * maintaining a local SPDM table is to avoid a search in the
1992 	 * adapter SPDM table for spdm entry lookup which is very costly
1993 	 * in terms of time.
1994 	 */
1995 	hldev->spdm_table[spdm_entry]->in_use = 1;
1996 	xge_os_memcpy(&hldev->spdm_table[spdm_entry]->src_ip, src_ip,
1997 		    sizeof(xge_hal_ipaddr_t));
1998 	xge_os_memcpy(&hldev->spdm_table[spdm_entry]->dst_ip, dst_ip,
1999 		    sizeof(xge_hal_ipaddr_t));
2000 	hldev->spdm_table[spdm_entry]->l4_sp = l4_sp;
2001 	hldev->spdm_table[spdm_entry]->l4_dp = l4_dp;
2002 	hldev->spdm_table[spdm_entry]->is_tcp = is_tcp;
2003 	hldev->spdm_table[spdm_entry]->is_ipv4 = is_ipv4;
2004 	hldev->spdm_table[spdm_entry]->tgt_queue = tgt_queue;
2005 	hldev->spdm_table[spdm_entry]->jhash_value = jhash_value;
2006 	hldev->spdm_table[spdm_entry]->spdm_entry = spdm_entry;
2007 
2008 	return XGE_HAL_OK;
2009 }
2010 
2011 /*
2012  * __hal_device_rth_spdm_configure - Configure RTH for the device
2013  * @hldev: HAL device handle.
2014  *
2015  * Using SPDM (Socket-Pair Direct Match).
2016  */
2017 xge_hal_status_e
__hal_device_rth_spdm_configure(xge_hal_device_t * hldev)2018 __hal_device_rth_spdm_configure(xge_hal_device_t *hldev)
2019 {
2020 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0;
2021 	u64 val64;
2022 	u8 spdm_bar_num;
2023 	u32 spdm_bar_offset;
2024 	int spdm_table_size;
2025 	int i;
2026 
2027 	if (!hldev->config.rth_spdm_en) {
2028 		return XGE_HAL_OK;
2029 	}
2030 
2031 	/*
2032 	 * Retrieve the base address of SPDM Table.
2033 	 */
2034 	val64 = xge_os_pio_mem_read64(hldev->pdev,
2035 			hldev->regh0, &bar0->spdm_bir_offset);
2036 
2037 	spdm_bar_num	= XGE_HAL_SPDM_PCI_BAR_NUM(val64);
2038 	spdm_bar_offset	= XGE_HAL_SPDM_PCI_BAR_OFFSET(val64);
2039 
2040 
2041 	/*
2042 	 * spdm_bar_num specifies the PCI bar num register used to
2043 	 * address the memory space. spdm_bar_offset specifies the offset
2044 	 * of the SPDM memory with in the bar num memory space.
2045 	 */
2046 	switch (spdm_bar_num) {
2047 		case 0:
2048 		{
2049 			hldev->spdm_mem_base = (char *)bar0 +
2050 						(spdm_bar_offset * 8);
2051 			break;
2052 		}
2053 		case 1:
2054 		{
2055 			char *bar1 = (char *)hldev->bar1;
2056 			hldev->spdm_mem_base = bar1 + (spdm_bar_offset * 8);
2057 			break;
2058 		}
2059 		default:
2060 			xge_assert(((spdm_bar_num != 0) && (spdm_bar_num != 1)));
2061 	}
2062 
2063 	/*
2064 	 * Retrieve the size of SPDM table(number of entries).
2065 	 */
2066 	val64 = xge_os_pio_mem_read64(hldev->pdev,
2067 			hldev->regh0, &bar0->spdm_structure);
2068 	hldev->spdm_max_entries = XGE_HAL_SPDM_MAX_ENTRIES(val64);
2069 
2070 
2071 	spdm_table_size = hldev->spdm_max_entries *
2072 					sizeof(xge_hal_spdm_entry_t);
2073 	if (hldev->spdm_table == NULL) {
2074 		void *mem;
2075 
2076 		/*
2077 		 * Allocate memory to hold the copy of SPDM table.
2078 		 */
2079 		if ((hldev->spdm_table = (xge_hal_spdm_entry_t **)
2080 					xge_os_malloc(
2081 					 hldev->pdev,
2082 					 (sizeof(xge_hal_spdm_entry_t *) *
2083 					 hldev->spdm_max_entries))) == NULL) {
2084 			return XGE_HAL_ERR_OUT_OF_MEMORY;
2085 		}
2086 
2087 		if ((mem = xge_os_malloc(hldev->pdev, spdm_table_size)) == NULL)
2088 		{
2089 			xge_os_free(hldev->pdev, hldev->spdm_table,
2090 				  (sizeof(xge_hal_spdm_entry_t *) *
2091 					 hldev->spdm_max_entries));
2092 			return XGE_HAL_ERR_OUT_OF_MEMORY;
2093 		}
2094 
2095 		xge_os_memzero(mem, spdm_table_size);
2096 		for (i = 0; i < hldev->spdm_max_entries; i++) {
2097 			hldev->spdm_table[i] = (xge_hal_spdm_entry_t *)
2098 					((char *)mem +
2099 					 i * sizeof(xge_hal_spdm_entry_t));
2100 		}
2101 		xge_os_spin_lock_init(&hldev->spdm_lock, hldev->pdev);
2102 	} else {
2103 		/*
2104 		 * We are here because the host driver tries to
2105 		 * do a soft reset on the device.
2106 		 * Since the device soft reset clears the SPDM table, copy
2107 		 * the entries from the local SPDM table to the actual one.
2108 		 */
2109 		xge_os_spin_lock(&hldev->spdm_lock);
2110 		for (i = 0; i < hldev->spdm_max_entries; i++) {
2111 			xge_hal_spdm_entry_t *spdm_entry = hldev->spdm_table[i];
2112 
2113 			if (spdm_entry->in_use) {
2114 				if (__hal_spdm_entry_add(hldev,
2115 							 &spdm_entry->src_ip,
2116 							 &spdm_entry->dst_ip,
2117 							 spdm_entry->l4_sp,
2118 							 spdm_entry->l4_dp,
2119 							 spdm_entry->is_tcp,
2120 							 spdm_entry->is_ipv4,
2121 							 spdm_entry->tgt_queue,
2122 							 spdm_entry->jhash_value,
2123 							 spdm_entry->spdm_entry)
2124 						!= XGE_HAL_OK) {
2125 					/* Log an warning */
2126 					xge_debug_device(XGE_ERR,
2127 						"SPDM table update from local"
2128 						" memory failed");
2129 				}
2130 			}
2131 		}
2132 		xge_os_spin_unlock(&hldev->spdm_lock);
2133 	}
2134 
2135 	/*
2136 	 * Set the receive traffic steering mode from default(classic)
2137 	 * to enhanced.
2138 	 */
2139 	val64 = xge_os_pio_mem_read64(hldev->pdev,
2140 				    hldev->regh0, &bar0->rts_ctrl);
2141 	val64 |=  XGE_HAL_RTS_CTRL_ENHANCED_MODE;
2142 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
2143 			     val64, &bar0->rts_ctrl);
2144 
2145 	/*
2146 	 * We may not need to configure rts_rth_jhash_cfg register as the
2147 	 * default values are good enough to calculate the hash.
2148 	 */
2149 
2150 	/*
2151 	 * As of now, set all the rth mask registers to zero. TODO.
2152 	 */
2153 	for(i = 0; i < 5; i++) {
2154 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
2155 				     0, &bar0->rts_rth_hash_mask[i]);
2156 	}
2157 
2158 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
2159 			     0, &bar0->rts_rth_hash_mask_5);
2160 
2161 	if (hldev->config.rth_spdm_use_l4) {
2162 		val64 = XGE_HAL_RTH_STATUS_SPDM_USE_L4;
2163 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
2164 				     val64, &bar0->rts_rth_status);
2165 	}
2166 
2167 	val64 = XGE_HAL_RTS_RTH_EN;
2168 	val64 |= XGE_HAL_RTS_RTH_IPV4_EN | XGE_HAL_RTS_RTH_TCP_IPV4_EN;
2169 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
2170 			     &bar0->rts_rth_cfg);
2171 
2172 
2173 	return XGE_HAL_OK;
2174 }
2175 
2176 /*
2177  * __hal_device_pci_init
2178  * @hldev: HAL device handle.
2179  *
2180  * Initialize certain PCI/PCI-X configuration registers
2181  * with recommended values. Save config space for future hw resets.
2182  */
2183 static void
__hal_device_pci_init(xge_hal_device_t * hldev)2184 __hal_device_pci_init(xge_hal_device_t *hldev)
2185 {
2186 	int i, pcisize = 0;
2187 	u16 cmd = 0;
2188 	u8  val;
2189 
2190 	/* Store PCI device ID and revision for future references where in we
2191 	 * decide Xena revision using PCI sub system ID */
2192 	xge_os_pci_read16(hldev->pdev,hldev->cfgh,
2193 			xge_offsetof(xge_hal_pci_config_le_t, device_id),
2194 			&hldev->device_id);
2195 	xge_os_pci_read8(hldev->pdev,hldev->cfgh,
2196 			xge_offsetof(xge_hal_pci_config_le_t, revision),
2197 			&hldev->revision);
2198 
2199 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)
2200 		pcisize = XGE_HAL_PCISIZE_HERC;
2201 	else if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA)
2202 		pcisize = XGE_HAL_PCISIZE_XENA;
2203 
2204 	/* save original PCI config space to restore it on device_terminate() */
2205 	for (i = 0; i < pcisize; i++) {
2206 		xge_os_pci_read32(hldev->pdev, hldev->cfgh, i*4,
2207 		                (u32*)&hldev->pci_config_space_bios + i);
2208 	}
2209 
2210 	/* Set the PErr Repconse bit and SERR in PCI command register. */
2211 	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
2212 			xge_offsetof(xge_hal_pci_config_le_t, command), &cmd);
2213 	cmd |= 0x140;
2214 	xge_os_pci_write16(hldev->pdev, hldev->cfgh,
2215 			 xge_offsetof(xge_hal_pci_config_le_t, command), cmd);
2216 
2217 	/* Set user spcecified value for the PCI Latency Timer */
2218 	if (hldev->config.latency_timer &&
2219 	    hldev->config.latency_timer != XGE_HAL_USE_BIOS_DEFAULT_LATENCY) {
2220 		xge_os_pci_write8(hldev->pdev, hldev->cfgh,
2221 	                 xge_offsetof(xge_hal_pci_config_le_t,
2222 	                 latency_timer),
2223 			 (u8)hldev->config.latency_timer);
2224 	}
2225 	/* Read back latency timer to reflect it into user level */
2226 	xge_os_pci_read8(hldev->pdev, hldev->cfgh,
2227 		xge_offsetof(xge_hal_pci_config_le_t, latency_timer), &val);
2228 	hldev->config.latency_timer = val;
2229 
2230 	/* Enable Data Parity Error Recovery in PCI-X command register. */
2231 	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
2232 		xge_offsetof(xge_hal_pci_config_le_t, pcix_command), &cmd);
2233 	cmd |= 1;
2234 	xge_os_pci_write16(hldev->pdev, hldev->cfgh,
2235 		 xge_offsetof(xge_hal_pci_config_le_t, pcix_command), cmd);
2236 
2237 	/* Set MMRB count in PCI-X command register. */
2238 	if (hldev->config.mmrb_count != XGE_HAL_DEFAULT_BIOS_MMRB_COUNT) {
2239 		cmd &= 0xFFF3;
2240 		cmd |= hldev->config.mmrb_count << 2;
2241 		xge_os_pci_write16(hldev->pdev, hldev->cfgh,
2242 		       xge_offsetof(xge_hal_pci_config_le_t, pcix_command),
2243 		       cmd);
2244 	}
2245 	/* Read back MMRB count to reflect it into user level */
2246 	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
2247 		        xge_offsetof(xge_hal_pci_config_le_t, pcix_command),
2248 		        &cmd);
2249 	cmd &= 0x000C;
2250 	hldev->config.mmrb_count = cmd>>2;
2251 
2252 	/*  Setting Maximum outstanding splits based on system type. */
2253 	if (hldev->config.max_splits_trans != XGE_HAL_USE_BIOS_DEFAULT_SPLITS)  {
2254 		xge_os_pci_read16(hldev->pdev, hldev->cfgh,
2255 			xge_offsetof(xge_hal_pci_config_le_t, pcix_command),
2256 			&cmd);
2257 		cmd &= 0xFF8F;
2258 		cmd |= hldev->config.max_splits_trans << 4;
2259 		xge_os_pci_write16(hldev->pdev, hldev->cfgh,
2260 			xge_offsetof(xge_hal_pci_config_le_t, pcix_command),
2261 			cmd);
2262 	}
2263 
2264 	/* Read back max split trans to reflect it into user level */
2265 	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
2266 		xge_offsetof(xge_hal_pci_config_le_t, pcix_command), &cmd);
2267 	cmd &= 0x0070;
2268 	hldev->config.max_splits_trans = cmd>>4;
2269 
2270 	/* Forcibly disabling relaxed ordering capability of the card. */
2271 	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
2272 		xge_offsetof(xge_hal_pci_config_le_t, pcix_command), &cmd);
2273 	cmd &= 0xFFFD;
2274 	xge_os_pci_write16(hldev->pdev, hldev->cfgh,
2275 		 xge_offsetof(xge_hal_pci_config_le_t, pcix_command), cmd);
2276 
2277 	/* save PCI config space for future resets */
2278 	for (i = 0; i < pcisize; i++) {
2279 		xge_os_pci_read32(hldev->pdev, hldev->cfgh, i*4,
2280 		                (u32*)&hldev->pci_config_space + i);
2281 	}
2282 }
2283 
2284 /*
2285  * __hal_device_pci_info_get - Get PCI bus informations such as width, frequency
2286  *                               and mode.
2287  * @devh: HAL device handle.
2288  * @pci_mode:		pointer to a variable of enumerated type
2289  *			xge_hal_pci_mode_e{}.
2290  * @bus_frequency:	pointer to a variable of enumerated type
2291  *			xge_hal_pci_bus_frequency_e{}.
2292  * @bus_width:		pointer to a variable of enumerated type
2293  *			xge_hal_pci_bus_width_e{}.
2294  *
2295  * Get pci mode, frequency, and PCI bus width.
2296  *
2297  * Returns: one of the xge_hal_status_e{} enumerated types.
2298  * XGE_HAL_OK			- for success.
2299  * XGE_HAL_ERR_INVALID_PCI_INFO - for invalid PCI information from the card.
2300  * XGE_HAL_ERR_BAD_DEVICE_ID	- for invalid card.
2301  *
2302  * See Also: xge_hal_pci_mode_e, xge_hal_pci_mode_e, xge_hal_pci_width_e.
2303  */
2304 static xge_hal_status_e
__hal_device_pci_info_get(xge_hal_device_h devh,xge_hal_pci_mode_e * pci_mode,xge_hal_pci_bus_frequency_e * bus_frequency,xge_hal_pci_bus_width_e * bus_width)2305 __hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode,
2306 		xge_hal_pci_bus_frequency_e *bus_frequency,
2307 		xge_hal_pci_bus_width_e *bus_width)
2308 {
2309 	xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
2310 	xge_hal_status_e rc_status = XGE_HAL_OK;
2311 	xge_hal_card_e card_id	   = xge_hal_device_check_id (devh);
2312 
2313 #ifdef XGE_HAL_HERC_EMULATION
2314 	hldev->config.pci_freq_mherz =
2315 		XGE_HAL_PCI_BUS_FREQUENCY_66MHZ;
2316 	*bus_frequency	=
2317 		XGE_HAL_PCI_BUS_FREQUENCY_66MHZ;
2318 	*pci_mode = XGE_HAL_PCI_66MHZ_MODE;
2319 #else
2320 	if (card_id == XGE_HAL_CARD_HERC) {
2321 		xge_hal_pci_bar0_t *bar0 =
2322 		(xge_hal_pci_bar0_t *)(void *)hldev->bar0;
2323 		u64 pci_info = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2324 				    &bar0->pci_info);
2325 		if (XGE_HAL_PCI_32_BIT & pci_info)
2326 			*bus_width = XGE_HAL_PCI_BUS_WIDTH_32BIT;
2327 		else
2328 			*bus_width = XGE_HAL_PCI_BUS_WIDTH_64BIT;
2329 		switch((pci_info & XGE_HAL_PCI_INFO)>>60)
2330 		{
2331 			case XGE_HAL_PCI_33MHZ_MODE:
2332 				 *bus_frequency	=
2333 					 XGE_HAL_PCI_BUS_FREQUENCY_33MHZ;
2334 				 *pci_mode = XGE_HAL_PCI_33MHZ_MODE;
2335 				 break;
2336 			case XGE_HAL_PCI_66MHZ_MODE:
2337 				 *bus_frequency	=
2338 					 XGE_HAL_PCI_BUS_FREQUENCY_66MHZ;
2339 				 *pci_mode = XGE_HAL_PCI_66MHZ_MODE;
2340 				 break;
2341 			case XGE_HAL_PCIX_M1_66MHZ_MODE:
2342 				 *bus_frequency	=
2343 					 XGE_HAL_PCI_BUS_FREQUENCY_66MHZ;
2344 				 *pci_mode = XGE_HAL_PCIX_M1_66MHZ_MODE;
2345 				 break;
2346 			case XGE_HAL_PCIX_M1_100MHZ_MODE:
2347 				 *bus_frequency	=
2348 					 XGE_HAL_PCI_BUS_FREQUENCY_100MHZ;
2349 				 *pci_mode = XGE_HAL_PCIX_M1_100MHZ_MODE;
2350 				 break;
2351 			case XGE_HAL_PCIX_M1_133MHZ_MODE:
2352 				 *bus_frequency	=
2353 					 XGE_HAL_PCI_BUS_FREQUENCY_133MHZ;
2354 				 *pci_mode = XGE_HAL_PCIX_M1_133MHZ_MODE;
2355 				 break;
2356 			case XGE_HAL_PCIX_M2_66MHZ_MODE:
2357 				 *bus_frequency	=
2358 					 XGE_HAL_PCI_BUS_FREQUENCY_133MHZ;
2359 				 *pci_mode = XGE_HAL_PCIX_M2_66MHZ_MODE;
2360 				 break;
2361 			case XGE_HAL_PCIX_M2_100MHZ_MODE:
2362 				 *bus_frequency	=
2363 					 XGE_HAL_PCI_BUS_FREQUENCY_200MHZ;
2364 				 *pci_mode = XGE_HAL_PCIX_M2_100MHZ_MODE;
2365 				 break;
2366 			case XGE_HAL_PCIX_M2_133MHZ_MODE:
2367 				 *bus_frequency	=
2368 					 XGE_HAL_PCI_BUS_FREQUENCY_266MHZ;
2369 				 *pci_mode = XGE_HAL_PCIX_M2_133MHZ_MODE;
2370 				  break;
2371 			case XGE_HAL_PCIX_M1_RESERVED:
2372 			case XGE_HAL_PCIX_M1_66MHZ_NS:
2373 			case XGE_HAL_PCIX_M1_100MHZ_NS:
2374 			case XGE_HAL_PCIX_M1_133MHZ_NS:
2375 			case XGE_HAL_PCIX_M2_RESERVED:
2376 			case XGE_HAL_PCIX_533_RESERVED:
2377 			default:
2378 				 rc_status = XGE_HAL_ERR_INVALID_PCI_INFO;
2379 				 xge_debug_device(XGE_ERR,
2380 					  "invalid pci info "XGE_OS_LLXFMT,
2381 					 (unsigned long long)pci_info);
2382 				 break;
2383 		}
2384 		if (rc_status != XGE_HAL_ERR_INVALID_PCI_INFO)
2385 			xge_debug_device(XGE_TRACE, "PCI info: mode %d width "
2386 				"%d frequency %d", *pci_mode, *bus_width,
2387 				*bus_frequency);
2388 		if (hldev->config.pci_freq_mherz ==
2389 				XGE_HAL_DEFAULT_USE_HARDCODE) {
2390 			hldev->config.pci_freq_mherz = *bus_frequency;
2391 		}
2392 	}
2393 	/* for XENA, we report PCI mode, only. PCI bus frequency, and bus width
2394 	 * are set to unknown */
2395 	else if (card_id == XGE_HAL_CARD_XENA) {
2396 		u32 pcix_status;
2397 		u8 dev_num, bus_num;
2398 		/* initialize defaults for XENA */
2399 		*bus_frequency	= XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN;
2400 		*bus_width	= XGE_HAL_PCI_BUS_WIDTH_UNKNOWN;
2401 		xge_os_pci_read32(hldev->pdev, hldev->cfgh,
2402 			xge_offsetof(xge_hal_pci_config_le_t, pcix_status),
2403 			&pcix_status);
2404 		dev_num = (u8)((pcix_status & 0xF8) >> 3);
2405 		bus_num = (u8)((pcix_status & 0xFF00) >> 8);
2406 		if (dev_num == 0 && bus_num == 0)
2407 			*pci_mode = XGE_HAL_PCI_BASIC_MODE;
2408 		else
2409 			*pci_mode = XGE_HAL_PCIX_BASIC_MODE;
2410 		xge_debug_device(XGE_TRACE, "PCI info: mode %d", *pci_mode);
2411 		if (hldev->config.pci_freq_mherz ==
2412 				XGE_HAL_DEFAULT_USE_HARDCODE) {
2413 			/*
2414 			 * There is no way to detect BUS frequency on Xena,
2415 			 * so, in case of automatic configuration we hopelessly
2416 			 * assume 133MHZ.
2417 			 */
2418 			hldev->config.pci_freq_mherz =
2419 				XGE_HAL_PCI_BUS_FREQUENCY_133MHZ;
2420 		}
2421 	} else if (card_id == XGE_HAL_CARD_TITAN) {
2422 		*bus_width = XGE_HAL_PCI_BUS_WIDTH_64BIT;
2423 		*bus_frequency	= XGE_HAL_PCI_BUS_FREQUENCY_250MHZ;
2424 		if (hldev->config.pci_freq_mherz ==
2425 				XGE_HAL_DEFAULT_USE_HARDCODE) {
2426 			hldev->config.pci_freq_mherz = *bus_frequency;
2427 		}
2428 	} else{
2429 		rc_status =  XGE_HAL_ERR_BAD_DEVICE_ID;
2430 		xge_debug_device(XGE_ERR, "invalid device id %d", card_id);
2431 	}
2432 #endif
2433 
2434 	return rc_status;
2435 }
2436 
2437 /*
2438  * __hal_device_handle_link_up_ind
2439  * @hldev: HAL device handle.
2440  *
2441  * Link up indication handler. The function is invoked by HAL when
2442  * Xframe indicates that the link is up for programmable amount of time.
2443  */
2444 static int
__hal_device_handle_link_up_ind(xge_hal_device_t * hldev)2445 __hal_device_handle_link_up_ind(xge_hal_device_t *hldev)
2446 {
2447 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
2448 	u64 val64;
2449 
2450 	/*
2451 	 * If the previous link state is not down, return.
2452 	 */
2453 	if (hldev->link_state == XGE_HAL_LINK_UP) {
2454 #ifdef XGE_HAL_PROCESS_LINK_INT_IN_ISR
2455 		if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC){
2456 			val64 = xge_os_pio_mem_read64(
2457 				hldev->pdev, hldev->regh0,
2458 				&bar0->misc_int_mask);
2459 			val64 |= XGE_HAL_MISC_INT_REG_LINK_UP_INT;
2460 			val64 &= ~XGE_HAL_MISC_INT_REG_LINK_DOWN_INT;
2461 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
2462 				val64, &bar0->misc_int_mask);
2463 		}
2464 #endif
2465 		xge_debug_device(XGE_TRACE,
2466 			"link up indication while link is up, ignoring..");
2467 		return 0;
2468 	}
2469 
2470 	/* Now re-enable it as due to noise, hardware turned it off */
2471 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2472 				     &bar0->adapter_control);
2473 	val64 |= XGE_HAL_ADAPTER_CNTL_EN;
2474 	val64 = val64 & (~XGE_HAL_ADAPTER_ECC_EN); /* ECC enable */
2475 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
2476 			     &bar0->adapter_control);
2477 
2478 	/* Turn on the Laser */
2479 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2480 				    &bar0->adapter_control);
2481 	val64 = val64|(XGE_HAL_ADAPTER_EOI_TX_ON |
2482 			XGE_HAL_ADAPTER_LED_ON);
2483 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
2484 			     &bar0->adapter_control);
2485 
2486 #ifdef XGE_HAL_PROCESS_LINK_INT_IN_ISR
2487 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) {
2488 	        val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2489 				              &bar0->adapter_status);
2490 	        if (val64 & (XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT |
2491 		             XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT)) {
2492 		        xge_debug_device(XGE_TRACE, "%s",
2493 				          "fail to transition link to up...");
2494 			return 0;
2495 	        }
2496 	        else {
2497 		        /*
2498 		         * Mask the Link Up interrupt and unmask the Link Down
2499 		         * interrupt.
2500 		         */
2501 		        val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2502 					              &bar0->misc_int_mask);
2503 		        val64 |= XGE_HAL_MISC_INT_REG_LINK_UP_INT;
2504 		        val64 &= ~XGE_HAL_MISC_INT_REG_LINK_DOWN_INT;
2505 		        xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
2506 				               &bar0->misc_int_mask);
2507 		        xge_debug_device(XGE_TRACE, "calling link up..");
2508 		        hldev->link_state = XGE_HAL_LINK_UP;
2509 
2510 		        /* notify ULD */
2511 		        if (g_xge_hal_driver->uld_callbacks.link_up) {
2512 			        g_xge_hal_driver->uld_callbacks.link_up(
2513 					        hldev->upper_layer_info);
2514 		        }
2515 			return 1;
2516 	        }
2517         }
2518 #endif
2519 	xge_os_mdelay(1);
2520 	if (__hal_device_register_poll(hldev, &bar0->adapter_status, 0,
2521 			(XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT |
2522 			XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT),
2523 			XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS) == XGE_HAL_OK) {
2524 
2525 		/* notify ULD */
2526 		(void) xge_queue_produce_context(hldev->queueh,
2527 						 XGE_HAL_EVENT_LINK_IS_UP, hldev);
2528 		/* link is up after been enabled */
2529 		return 1;
2530 	} else {
2531 		xge_debug_device(XGE_TRACE, "%s",
2532 				  "fail to transition link to up...");
2533 		return 0;
2534 	}
2535 }
2536 
2537 /*
2538  * __hal_device_handle_link_down_ind
2539  * @hldev: HAL device handle.
2540  *
2541  * Link down indication handler. The function is invoked by HAL when
2542  * Xframe indicates that the link is down.
2543  */
2544 static int
__hal_device_handle_link_down_ind(xge_hal_device_t * hldev)2545 __hal_device_handle_link_down_ind(xge_hal_device_t *hldev)
2546 {
2547 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
2548 	u64 val64;
2549 
2550 	/*
2551 	 * If the previous link state is not up, return.
2552 	 */
2553 	if (hldev->link_state == XGE_HAL_LINK_DOWN) {
2554 #ifdef	XGE_HAL_PROCESS_LINK_INT_IN_ISR
2555 		if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC){
2556 			val64 = xge_os_pio_mem_read64(
2557 				hldev->pdev, hldev->regh0,
2558 				&bar0->misc_int_mask);
2559 			val64 |= XGE_HAL_MISC_INT_REG_LINK_DOWN_INT;
2560 			val64 &= ~XGE_HAL_MISC_INT_REG_LINK_UP_INT;
2561 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
2562 				val64, &bar0->misc_int_mask);
2563 		}
2564 #endif
2565 		xge_debug_device(XGE_TRACE,
2566 			"link down indication while link is down, ignoring..");
2567 		return 0;
2568 	}
2569 	xge_os_mdelay(1);
2570 
2571 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2572 				      &bar0->adapter_control);
2573 
2574 	/* try to debounce the link only if the adapter is enabled. */
2575 	if (val64 & XGE_HAL_ADAPTER_CNTL_EN) {
2576 		if (__hal_device_register_poll(hldev, &bar0->adapter_status, 0,
2577 			(XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT |
2578 			XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT),
2579 			XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS) == XGE_HAL_OK) {
2580 			xge_debug_device(XGE_TRACE,
2581 				"link is actually up (possible noisy link?), ignoring.");
2582 			return(0);
2583 		}
2584 	}
2585 
2586 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2587 				    &bar0->adapter_control);
2588 	/* turn off LED */
2589 	val64 = val64 & (~XGE_HAL_ADAPTER_LED_ON);
2590 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
2591 			       &bar0->adapter_control);
2592 
2593 #ifdef  XGE_HAL_PROCESS_LINK_INT_IN_ISR
2594 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) {
2595 		/*
2596 		 * Mask the Link Down interrupt and unmask the Link up
2597 		 * interrupt
2598 		 */
2599 		val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2600 					      &bar0->misc_int_mask);
2601 		val64 |= XGE_HAL_MISC_INT_REG_LINK_DOWN_INT;
2602 		val64 &= ~XGE_HAL_MISC_INT_REG_LINK_UP_INT;
2603 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
2604 				       &bar0->misc_int_mask);
2605 
2606 		/* link is down */
2607 		xge_debug_device(XGE_TRACE, "calling link down..");
2608 		hldev->link_state = XGE_HAL_LINK_DOWN;
2609 
2610 		/* notify ULD */
2611 		if (g_xge_hal_driver->uld_callbacks.link_down) {
2612 				g_xge_hal_driver->uld_callbacks.link_down(
2613 					hldev->upper_layer_info);
2614 		}
2615 		return 1;
2616 	}
2617 #endif
2618 	/* notify ULD */
2619 	(void) xge_queue_produce_context(hldev->queueh,
2620 					 XGE_HAL_EVENT_LINK_IS_DOWN, hldev);
2621 	/* link is down */
2622 	return 1;
2623 }
2624 /*
2625  * __hal_device_handle_link_state_change
2626  * @hldev: HAL device handle.
2627  *
2628  * Link state change handler. The function is invoked by HAL when
2629  * Xframe indicates link state change condition. The code here makes sure to
2630  * 1) ignore redundant state change indications;
2631  * 2) execute link-up sequence, and handle the failure to bring the link up;
2632  * 3) generate XGE_HAL_LINK_UP/DOWN event for the subsequent handling by
2633  *    upper-layer driver (ULD).
2634  */
2635 static int
__hal_device_handle_link_state_change(xge_hal_device_t * hldev)2636 __hal_device_handle_link_state_change(xge_hal_device_t *hldev)
2637 {
2638 	u64 hw_status;
2639 	int hw_link_state;
2640 	int retcode;
2641 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
2642 	u64 val64;
2643 	int i = 0;
2644 
2645 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2646 					&bar0->adapter_control);
2647 
2648 	/* If the adapter is not enabled but the hal thinks we are in the up
2649 	 * state then transition to the down state.
2650 	 */
2651 	if ( !(val64 & XGE_HAL_ADAPTER_CNTL_EN) &&
2652 	     (hldev->link_state == XGE_HAL_LINK_UP) ) {
2653 		return(__hal_device_handle_link_down_ind(hldev));
2654 	}
2655 
2656 	do {
2657 		xge_os_mdelay(1);
2658 		(void) xge_hal_device_status(hldev, &hw_status);
2659 		hw_link_state = (hw_status &
2660 			(XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT |
2661 				XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT)) ?
2662 				XGE_HAL_LINK_DOWN : XGE_HAL_LINK_UP;
2663 
2664 		/* check if the current link state is still considered
2665 		 * to be changed. This way we will make sure that this is
2666 		 * not a noise which needs to be filtered out */
2667 		if (hldev->link_state == hw_link_state)
2668 			break;
2669 	} while (i++ < hldev->config.link_valid_cnt);
2670 
2671 	/* If the current link state is same as previous, just return */
2672 	if (hldev->link_state == hw_link_state)
2673 		retcode = 0;
2674 	/* detected state change */
2675 	else if (hw_link_state == XGE_HAL_LINK_UP)
2676 		retcode = __hal_device_handle_link_up_ind(hldev);
2677 	else
2678 		retcode = __hal_device_handle_link_down_ind(hldev);
2679 	return retcode;
2680 }
2681 
2682 /*
2683  *
2684  */
2685 static void
__hal_device_handle_serr(xge_hal_device_t * hldev,char * reg,u64 value)2686 __hal_device_handle_serr(xge_hal_device_t *hldev, char *reg, u64 value)
2687 {
2688 	hldev->stats.sw_dev_err_stats.serr_cnt++;
2689 	if (hldev->config.dump_on_serr) {
2690 #ifdef XGE_HAL_USE_MGMT_AUX
2691 		(void) xge_hal_aux_device_dump(hldev);
2692 #endif
2693 	}
2694 
2695 	(void) xge_queue_produce(hldev->queueh, XGE_HAL_EVENT_SERR, hldev,
2696 			   1, sizeof(u64), (void *)&value);
2697 
2698 	xge_debug_device(XGE_ERR, "%s: read "XGE_OS_LLXFMT, reg,
2699 				  (unsigned long long) value);
2700 }
2701 
2702 /*
2703  *
2704  */
2705 static void
__hal_device_handle_eccerr(xge_hal_device_t * hldev,char * reg,u64 value)2706 __hal_device_handle_eccerr(xge_hal_device_t *hldev, char *reg, u64 value)
2707 {
2708 	if (hldev->config.dump_on_eccerr) {
2709 #ifdef XGE_HAL_USE_MGMT_AUX
2710 		(void) xge_hal_aux_device_dump(hldev);
2711 #endif
2712 	}
2713 
2714 	/* Herc smart enough to recover on its own! */
2715 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) {
2716 		(void) xge_queue_produce(hldev->queueh,
2717 			XGE_HAL_EVENT_ECCERR, hldev,
2718 			1, sizeof(u64), (void *)&value);
2719 	}
2720 
2721         xge_debug_device(XGE_ERR, "%s: read "XGE_OS_LLXFMT, reg,
2722                                   (unsigned long long) value);
2723 }
2724 
2725 /*
2726  *
2727  */
2728 static void
__hal_device_handle_parityerr(xge_hal_device_t * hldev,char * reg,u64 value)2729 __hal_device_handle_parityerr(xge_hal_device_t *hldev, char *reg, u64 value)
2730 {
2731 	if (hldev->config.dump_on_parityerr) {
2732 #ifdef XGE_HAL_USE_MGMT_AUX
2733 		(void) xge_hal_aux_device_dump(hldev);
2734 #endif
2735 	}
2736 	(void) xge_queue_produce_context(hldev->queueh,
2737 			XGE_HAL_EVENT_PARITYERR, hldev);
2738 
2739         xge_debug_device(XGE_ERR, "%s: read "XGE_OS_LLXFMT, reg,
2740                                   (unsigned long long) value);
2741 }
2742 
2743 /*
2744  *
2745  */
2746 static void
__hal_device_handle_targetabort(xge_hal_device_t * hldev)2747 __hal_device_handle_targetabort(xge_hal_device_t *hldev)
2748 {
2749 	(void) xge_queue_produce_context(hldev->queueh,
2750 			XGE_HAL_EVENT_TARGETABORT, hldev);
2751 }
2752 
2753 
2754 /*
2755  * __hal_device_hw_initialize
2756  * @hldev: HAL device handle.
2757  *
2758  * Initialize Xframe hardware.
2759  */
2760 static xge_hal_status_e
__hal_device_hw_initialize(xge_hal_device_t * hldev)2761 __hal_device_hw_initialize(xge_hal_device_t *hldev)
2762 {
2763 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
2764 	xge_hal_status_e status;
2765 	u64 val64;
2766 
2767 	/* Set proper endian settings and verify the same by reading the PIF
2768 	 * Feed-back register. */
2769 	status = __hal_device_set_swapper(hldev);
2770 	if (status != XGE_HAL_OK) {
2771 		return status;
2772 	}
2773 
2774 	/* update the pci mode, frequency, and width */
2775 	if (__hal_device_pci_info_get(hldev, &hldev->pci_mode,
2776 		&hldev->bus_frequency, &hldev->bus_width) != XGE_HAL_OK){
2777 		hldev->pci_mode	= XGE_HAL_PCI_INVALID_MODE;
2778 		hldev->bus_frequency = XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN;
2779 		hldev->bus_width = XGE_HAL_PCI_BUS_WIDTH_UNKNOWN;
2780 		/*
2781 		 * FIXME: this cannot happen.
2782 		 * But if it happens we cannot continue just like that
2783 		 */
2784 		xge_debug_device(XGE_ERR, "unable to get pci info");
2785 	}
2786 
2787 	if ((hldev->pci_mode == XGE_HAL_PCI_33MHZ_MODE) ||
2788 		(hldev->pci_mode == XGE_HAL_PCI_66MHZ_MODE) ||
2789 		(hldev->pci_mode == XGE_HAL_PCI_BASIC_MODE)) {
2790 		/* PCI optimization: set TxReqTimeOut
2791 		 * register (0x800+0x120) to 0x1ff or
2792 		 * something close to this.
2793 		 * Note: not to be used for PCI-X! */
2794 
2795 		val64 = XGE_HAL_TXREQTO_VAL(0x1FF);
2796 		val64 |= XGE_HAL_TXREQTO_EN;
2797 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
2798 				     &bar0->txreqtimeout);
2799 
2800 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0ULL,
2801 				     &bar0->read_retry_delay);
2802 
2803 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0ULL,
2804 				     &bar0->write_retry_delay);
2805 
2806 		xge_debug_device(XGE_TRACE, "%s", "optimizing for PCI mode");
2807 	}
2808 
2809 	if (hldev->bus_frequency == XGE_HAL_PCI_BUS_FREQUENCY_266MHZ ||
2810 	    hldev->bus_frequency == XGE_HAL_PCI_BUS_FREQUENCY_250MHZ) {
2811 
2812 		/* Optimizing for PCI-X 266/250 */
2813 
2814 		val64 = XGE_HAL_TXREQTO_VAL(0x7F);
2815 		val64 |= XGE_HAL_TXREQTO_EN;
2816 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
2817 				     &bar0->txreqtimeout);
2818 
2819 		xge_debug_device(XGE_TRACE, "%s", "optimizing for PCI-X 266/250 modes");
2820 	}
2821 
2822 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) {
2823 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0x4000000000000ULL,
2824 				     &bar0->read_retry_delay);
2825 
2826 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0x4000000000000ULL,
2827 				     &bar0->write_retry_delay);
2828 	}
2829 
2830 	/* added this to set the no of bytes used to update lso_bytes_sent
2831 	   returned TxD0 */
2832 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2833 				      &bar0->pic_control_2);
2834 	val64 &= ~XGE_HAL_TXD_WRITE_BC(0x2);
2835 	val64 |= XGE_HAL_TXD_WRITE_BC(0x4);
2836 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
2837 			       &bar0->pic_control_2);
2838 	/* added this to clear the EOI_RESET field while leaving XGXS_RESET
2839 	 * in reset, then a 1-second delay */
2840 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
2841 			XGE_HAL_SW_RESET_XGXS, &bar0->sw_reset);
2842 	xge_os_mdelay(1000);
2843 
2844 	/* Clear the XGXS_RESET field of the SW_RESET register in order to
2845 	 * release the XGXS from reset. Its reset value is 0xA5; write 0x00
2846 	 * to activate the XGXS. The core requires a minimum 500 us reset.*/
2847         xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0, &bar0->sw_reset);
2848 	(void) xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2849 				&bar0->sw_reset);
2850 	xge_os_mdelay(1);
2851 
2852 	/* read registers in all blocks */
2853 	(void) xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2854 				   &bar0->mac_int_mask);
2855 	(void) xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2856 				   &bar0->mc_int_mask);
2857 	(void) xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2858 				   &bar0->xgxs_int_mask);
2859 
2860 	/* set default MTU and steer based on length*/
2861 	__hal_ring_mtu_set(hldev, hldev->config.mtu+22); // Alway set 22 bytes extra for steering to work
2862 
2863 	if (hldev->config.mac.rmac_bcast_en) {
2864         xge_hal_device_bcast_enable(hldev);
2865 	} else {
2866 	    xge_hal_device_bcast_disable(hldev);
2867 	}
2868 
2869 #ifndef XGE_HAL_HERC_EMULATION
2870 	__hal_device_xaui_configure(hldev);
2871 #endif
2872 	__hal_device_mac_link_util_set(hldev);
2873 
2874 	__hal_device_mac_link_util_set(hldev);
2875 
2876 	/*
2877 	 * Keep its PCI REQ# line asserted during a write
2878 	 * transaction up to the end of the transaction
2879 	 */
2880 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2881 				&bar0->misc_control);
2882 
2883 	val64 |= XGE_HAL_MISC_CONTROL_EXT_REQ_EN;
2884 
2885 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
2886 				val64, &bar0->misc_control);
2887 
2888 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) {
2889 		val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
2890 					&bar0->misc_control);
2891 
2892 		val64 |= XGE_HAL_MISC_CONTROL_LINK_FAULT;
2893 
2894 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
2895 					val64, &bar0->misc_control);
2896 	}
2897 
2898 	/*
2899 	 * bimodal interrupts is when all Rx traffic interrupts
2900 	 * will go to TTI, so we need to adjust RTI settings and
2901 	 * use adaptive TTI timer. We need to make sure RTI is
2902 	 * properly configured to sane value which will not
2903 	 * distrupt bimodal behavior.
2904 	 */
2905 	if (hldev->config.bimodal_interrupts) {
2906 		int i;
2907 
2908 		/* force polling_cnt to be "0", otherwise
2909 		 * IRQ workload statistics will be screwed. This could
2910 		 * be worked out in TXPIC handler later. */
2911 		hldev->config.isr_polling_cnt = 0;
2912 		hldev->config.sched_timer_us = 10000;
2913 
2914 		/* disable all TTI < 56 */
2915 		for (i=0; i<XGE_HAL_MAX_FIFO_NUM; i++) {
2916 			int j;
2917 			if (!hldev->config.fifo.queue[i].configured)
2918 				continue;
2919 			for (j=0; j<XGE_HAL_MAX_FIFO_TTI_NUM; j++) {
2920 			    if (hldev->config.fifo.queue[i].tti[j].enabled)
2921 				hldev->config.fifo.queue[i].tti[j].enabled = 0;
2922 			}
2923 		}
2924 
2925 		/* now configure bimodal interrupts */
2926 		__hal_device_bimodal_configure(hldev);
2927 	}
2928 
2929 	status = __hal_device_tti_configure(hldev, 0);
2930 	if (status != XGE_HAL_OK)
2931 		return status;
2932 
2933 	status = __hal_device_rti_configure(hldev, 0);
2934 	if (status != XGE_HAL_OK)
2935 		return status;
2936 
2937 	status = __hal_device_rth_it_configure(hldev);
2938 	if (status != XGE_HAL_OK)
2939 		return status;
2940 
2941 	status = __hal_device_rth_spdm_configure(hldev);
2942 	if (status != XGE_HAL_OK)
2943 		return status;
2944 
2945 	status = __hal_device_rts_mac_configure(hldev);
2946 	if (status != XGE_HAL_OK) {
2947 		xge_debug_device(XGE_ERR, "__hal_device_rts_mac_configure Failed ");
2948 		return status;
2949 	}
2950 
2951 	status = __hal_device_rts_port_configure(hldev);
2952 	if (status != XGE_HAL_OK) {
2953 		xge_debug_device(XGE_ERR, "__hal_device_rts_port_configure Failed ");
2954 		return status;
2955 	}
2956 
2957 	status = __hal_device_rts_qos_configure(hldev);
2958 	if (status != XGE_HAL_OK) {
2959 		xge_debug_device(XGE_ERR, "__hal_device_rts_qos_configure Failed ");
2960 		return status;
2961 	}
2962 
2963 	__hal_device_pause_frames_configure(hldev);
2964 	__hal_device_rmac_padding_configure(hldev);
2965 	__hal_device_shared_splits_configure(hldev);
2966 
2967 	/* make sure all interrupts going to be disabled at the moment */
2968 	__hal_device_intr_mgmt(hldev, XGE_HAL_ALL_INTRS, 0);
2969 
2970 	/* SXE-008 Transmit DMA arbitration issue */
2971 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA &&
2972 	    hldev->revision < 4) {
2973 		xge_os_pio_mem_write64(hldev->pdev,hldev->regh0,
2974 				XGE_HAL_ADAPTER_PCC_ENABLE_FOUR,
2975 				&bar0->pcc_enable);
2976 	}
2977 	__hal_fifo_hw_initialize(hldev);
2978 	__hal_ring_hw_initialize(hldev);
2979 
2980 	if (__hal_device_wait_quiescent(hldev, &val64)) {
2981 		return XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT;
2982 	}
2983 
2984 	if (__hal_device_register_poll(hldev, &bar0->adapter_status, 1,
2985 		XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT,
2986 		 XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS) != XGE_HAL_OK) {
2987 		xge_debug_device(XGE_TRACE, "%s", "PRC is not QUIESCENT!");
2988 		return XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT;
2989 	}
2990 
2991 	xge_debug_device(XGE_TRACE, "device 0x"XGE_OS_LLXFMT" is quiescent",
2992 			  (unsigned long long)(ulong_t)hldev);
2993 
2994 	if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX ||
2995 	    hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSI) {
2996 		/*
2997 		 * If MSI is enabled, ensure that One Shot for MSI in PCI_CTRL
2998 		 * is disabled.
2999 		 */
3000 		val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
3001 					    &bar0->pic_control);
3002 		val64 &= ~(XGE_HAL_PIC_CNTL_ONE_SHOT_TINT);
3003 		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
3004 					    &bar0->pic_control);
3005 	}
3006 
3007 	hldev->hw_is_initialized = 1;
3008 	hldev->terminating = 0;
3009 	return XGE_HAL_OK;
3010 }
3011 
3012 /*
3013  * __hal_device_reset - Reset device only.
3014  * @hldev: HAL device handle.
3015  *
3016  * Reset the device, and subsequently restore
3017  * the previously saved PCI configuration space.
3018  */
3019 #define XGE_HAL_MAX_PCI_CONFIG_SPACE_REINIT 50
3020 static xge_hal_status_e
__hal_device_reset(xge_hal_device_t * hldev)3021 __hal_device_reset(xge_hal_device_t *hldev)
3022 {
3023 	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
3024 	int i, j, swap_done, pcisize = 0;
3025 	u64 val64, rawval = 0ULL;
3026 
3027 	if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX) {
3028 		if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) {
3029 			if ( hldev->bar2 ) {
3030 			    u64 *msix_vetor_table = (u64 *)hldev->bar2;
3031 
3032 			    // 2 64bit words for each entry
3033 			    for (i = 0; i < XGE_HAL_MAX_MSIX_MESSAGES * 2;
3034 			         i++) {
3035 			          hldev->msix_vector_table[i] =
3036 				       xge_os_pio_mem_read64(hldev->pdev,
3037 			                  hldev->regh2, &msix_vetor_table[i]);
3038 			    }
3039 			}
3040 		}
3041 	}
3042 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
3043 	                            &bar0->pif_rd_swapper_fb);
3044 	swap_done = (val64 == XGE_HAL_IF_RD_SWAPPER_FB);
3045 
3046 	if (swap_done) {
3047 		__hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0,
3048 		     (u32)(XGE_HAL_SW_RESET_ALL>>32), (char *)&bar0->sw_reset);
3049 	} else {
3050 		u32 val = (u32)(XGE_HAL_SW_RESET_ALL >> 32);
3051 #if defined(XGE_OS_HOST_LITTLE_ENDIAN) || defined(XGE_OS_PIO_LITTLE_ENDIAN)
3052 		/* swap it */
3053 		val = (((val & (u32)0x000000ffUL) << 24) |
3054 		       ((val & (u32)0x0000ff00UL) <<  8) |
3055 		       ((val & (u32)0x00ff0000UL) >>  8) |
3056 		       ((val & (u32)0xff000000UL) >> 24));
3057 #endif
3058 		xge_os_pio_mem_write32(hldev->pdev, hldev->regh0, val,
3059 				     &bar0->sw_reset);
3060 	}
3061 
3062 	pcisize = (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)?
3063 			   XGE_HAL_PCISIZE_HERC : XGE_HAL_PCISIZE_XENA;
3064 
3065 	xge_os_mdelay(20); /* Wait for 20 ms after reset */
3066 
3067 	{
3068 		/* Poll for no more than 1 second */
3069 		for (i = 0; i < XGE_HAL_MAX_PCI_CONFIG_SPACE_REINIT; i++)
3070 		{
3071 			for (j = 0; j < pcisize; j++) {
3072 				xge_os_pci_write32(hldev->pdev, hldev->cfgh, j * 4,
3073 					*((u32*)&hldev->pci_config_space + j));
3074 			}
3075 
3076 			xge_os_pci_read16(hldev->pdev,hldev->cfgh,
3077 				xge_offsetof(xge_hal_pci_config_le_t, device_id),
3078 				&hldev->device_id);
3079 
3080 			if (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_UNKNOWN)
3081 				break;
3082 			xge_os_mdelay(20);
3083 		}
3084 	}
3085 
3086 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_UNKNOWN)
3087 	{
3088 		xge_debug_device(XGE_ERR, "device reset failed");
3089 			return XGE_HAL_ERR_RESET_FAILED;
3090 	}
3091 
3092 	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) {
3093 		int cnt = 0;
3094 
3095 		rawval = XGE_HAL_SW_RESET_RAW_VAL_HERC;
3096 		pcisize = XGE_HAL_PCISIZE_HERC;
3097 		xge_os_mdelay(1);
3098 		do {
3099 			val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
3100 				&bar0->sw_reset);
3101 			if (val64 != rawval) {
3102 				break;
3103 			}
3104 			cnt++;
3105 			xge_os_mdelay(1); /* Wait for 1ms before retry */
3106 		} while(cnt < 20);
3107 	} else if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) {
3108 		rawval = XGE_HAL_SW_RESET_RAW_VAL_XENA;
3109 		pcisize = XGE_HAL_PCISIZE_XENA;
3110 		xge_os_mdelay(XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS);
3111 	}
3112 
3113 	/* Restore MSI-X vector table */
3114 	if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX) {
3115 		if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) {
3116 			if ( hldev->bar2 ) {
3117 			    /*
3118 			     * 94: MSIXTable 00000004  ( BIR:4  Offset:0x0 )
3119 			     * 98: PBATable  00000404  ( BIR:4  Offset:0x400 )
3120 			     */
3121 			     u64 *msix_vetor_table = (u64 *)hldev->bar2;
3122 
3123 			     /* 2 64bit words for each entry */
3124 			     for (i = 0; i < XGE_HAL_MAX_MSIX_MESSAGES * 2;
3125 				  i++) {
3126 			         xge_os_pio_mem_write64(hldev->pdev,
3127 					hldev->regh2,
3128 					hldev->msix_vector_table[i],
3129 					&msix_vetor_table[i]);
3130 			     }
3131 			}
3132 		}
3133 	}
3134 
3135 	hldev->link_state = XGE_HAL_LINK_DOWN;
3136 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
3137                                       &bar0->sw_reset);
3138 
3139 	if (val64 != rawval) {
3140 		xge_debug_device(XGE_ERR, "device has not been reset "
3141 			"got 0x"XGE_OS_LLXFMT", expected 0x"XGE_OS_LLXFMT,
3142 			(unsigned long long)val64, (unsigned long long)rawval);
3143 	        return XGE_HAL_ERR_RESET_FAILED;
3144 	}
3145 
3146 	hldev->hw_is_initialized = 0;
3147 	return XGE_HAL_OK;
3148 }
3149 
3150 /*
3151  * __hal_device_poll - General private routine to poll the device.
3152  * @hldev: HAL device handle.
3153  *
3154  * Returns: one of the xge_hal_status_e{} enumerated types.
3155  * XGE_HAL_OK			- for success.
3156  * XGE_HAL_ERR_CRITICAL         - when encounters critical error.
3157  */
3158 static xge_hal_status_e
__hal_device_poll(xge_hal_device_t * hldev)3159 __hal_device_poll(xge_hal_device_t *hldev)
3160 {
3161 	xge_hal_pci_bar0_t *bar0;
3162 	u64 err_reg;
3163 
3164 	bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
3165 
3166 	/* Handling SERR errors by forcing a H/W reset. */
3167 	err_reg = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
3168 				      &bar0->serr_source);
3169 	if (err_reg & XGE_HAL_SERR_SOURCE_ANY) {
3170 		__hal_device_handle_serr(hldev, "serr_source", err_reg);
3171 		return XGE_HAL_ERR_CRITICAL;
3172 	}
3173 
3174 	err_reg = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
3175 					&bar0->misc_int_reg);
3176 
3177 	if (err_reg & XGE_HAL_MISC_INT_REG_DP_ERR_INT) {
3178 		hldev->stats.sw_dev_err_stats.parity_err_cnt++;
3179 		__hal_device_handle_parityerr(hldev, "misc_int_reg", err_reg);
3180 		return XGE_HAL_ERR_CRITICAL;
3181 	}
3182 
3183 #ifdef  XGE_HAL_PROCESS_LINK_INT_IN_ISR
3184 	if ((xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) ||
3185 		(hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX))
3186 #endif
3187 	{
3188 
3189 		/* Handling link status change error Intr */
3190 		err_reg = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
3191 						&bar0->mac_rmac_err_reg);
3192 		if (__hal_device_handle_link_state_change(hldev))
3193 			xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
3194 				       err_reg, &bar0->mac_rmac_err_reg);
3195 	}
3196 
3197 	if (hldev->inject_serr != 0) {
3198 		err_reg = hldev->inject_serr;
3199 		hldev->inject_serr = 0;
3200 		__hal_device_handle_serr(hldev, "inject_serr", err_reg);
3201 		return XGE_HAL_ERR_CRITICAL;
3202         }
3203 
3204         if (hldev->inject_ecc != 0) {
3205                 err_reg = hldev->inject_ecc;
3206                 hldev->inject_ecc = 0;
3207 		hldev->stats.sw_dev_err_stats.ecc_err_cnt++;
3208                 __hal_device_handle_eccerr(hldev, "inject_ecc", err_reg);
3209 		return XGE_HAL_ERR_CRITICAL;
3210         }
3211 
3212 	if (hldev->inject_bad_tcode != 0) {
3213 		u8 t_code = hldev->inject_bad_tcode;
3214 		xge_hal_channel_t channel;
3215 		xge_hal_fifo_txd_t txd;
3216