1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24 #ifndef XGE_HAL_TYPES_H 25 #define XGE_HAL_TYPES_H 26 27 #include "xge-os-pal.h" 28 29 __EXTERN_BEGIN_DECLS 30 31 /* 32 * BIT(loc) - set bit at offset 33 */ 34 #define BIT(loc) (0x8000000000000000ULL >> (loc)) 35 36 /* 37 * vBIT(val, loc, sz) - set bits at offset 38 */ 39 #define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) 40 #define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) 41 42 /* 43 * bVALx(bits, loc) - Get the value of x bits at location 44 */ 45 #define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1) 46 #define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3) 47 #define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7) 48 #define bVAL4(bits, loc) ((((u64)bits) >> (64-(loc+4))) & 0xF) 49 #define bVAL5(bits, loc) ((((u64)bits) >> (64-(loc+5))) & 0x1F) 50 #define bVAL6(bits, loc) ((((u64)bits) >> (64-(loc+6))) & 0x3F) 51 #define bVAL7(bits, loc) ((((u64)bits) >> (64-(loc+7))) & 0x7F) 52 #define bVAL8(bits, loc) ((((u64)bits) >> (64-(loc+8))) & 0xFF) 53 #define bVAL12(bits, loc) ((((u64)bits) >> (64-(loc+12))) & 0xFFF) 54 #define bVAL16(bits, loc) ((((u64)bits) >> (64-(loc+16))) & 0xFFFF) 55 #define bVAL20(bits, loc) ((((u64)bits) >> (64-(loc+20))) & 0xFFFFF) 56 #define bVAL22(bits, loc) ((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF) 57 #define bVAL24(bits, loc) ((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF) 58 #define bVAL28(bits, loc) ((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF) 59 #define bVAL32(bits, loc) ((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF) 60 #define bVAL36(bits, loc) ((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFF) 61 #define bVAL40(bits, loc) ((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFF) 62 #define bVAL44(bits, loc) ((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFF) 63 #define bVAL48(bits, loc) ((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFF) 64 #define bVAL52(bits, loc) ((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFF) 65 #define bVAL56(bits, loc) ((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFF) 66 #define bVAL60(bits, loc) ((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFF) 67 68 #define XGE_HAL_BASE_INF 100 69 #define XGE_HAL_BASE_ERR 200 70 #define XGE_HAL_BASE_BADCFG 300 71 72 #define XGE_HAL_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL 73 74 /** 75 * enum xge_hal_status_e - HAL return codes. 76 * @XGE_HAL_OK: Success. 77 * @XGE_HAL_FAIL: Failure. 78 * @XGE_HAL_COMPLETIONS_REMAIN: There are more completions on a channel. 79 * (specific to polling mode completion processing). 80 * @XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS: No more completed 81 * descriptors. See xge_hal_fifo_dtr_next_completed(). 82 * @XGE_HAL_INF_OUT_OF_DESCRIPTORS: Out of descriptors. Channel 83 * descriptors 84 * are reserved (via xge_hal_fifo_dtr_reserve(), 85 * xge_hal_fifo_dtr_reserve()) 86 * and not yet freed (via xge_hal_fifo_dtr_free(), 87 * xge_hal_ring_dtr_free()). 88 * @XGE_HAL_INF_CHANNEL_IS_NOT_READY: Channel is not ready for 89 * operation. 90 * @XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING: Indicates that host needs to 91 * poll until PIO is executed. 92 * @XGE_HAL_INF_STATS_IS_NOT_READY: Cannot retrieve statistics because 93 * HAL and/or device is not yet initialized. 94 * @XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS: No descriptors left to 95 * reserve. Internal use only. 96 * @XGE_HAL_INF_IRQ_POLLING_CONTINUE: Returned by the ULD channel 97 * callback when instructed to exit descriptor processing loop 98 * prematurely. Typical usage: polling mode of processing completed 99 * descriptors. 100 * Upon getting LRO_ISED, ll driver shall 101 * 1) initialise lro struct with mbuf if sg_num == 1. 102 * 2) else it will update m_data_ptr_of_mbuf to tcp pointer and 103 * append the new mbuf to the tail of mbuf chain in lro struct. 104 * 105 * @XGE_HAL_INF_LRO_BEGIN: Returned by ULD LRO module, when new LRO is 106 * being initiated. 107 * @XGE_HAL_INF_LRO_CONT: Returned by ULD LRO module, when new frame 108 * is appended at the end of existing LRO. 109 * @XGE_HAL_INF_LRO_UNCAPABLE: Returned by ULD LRO module, when new 110 * frame is not LRO capable. 111 * @XGE_HAL_INF_LRO_END_1: Returned by ULD LRO module, when new frame 112 * triggers LRO flush. 113 * @XGE_HAL_INF_LRO_END_2: Returned by ULD LRO module, when new 114 * frame triggers LRO flush. Lro frame should be flushed first then 115 * new frame should be flushed next. 116 * @XGE_HAL_INF_LRO_END_3: Returned by ULD LRO module, when new 117 * frame triggers close of current LRO session and opening of new LRO session 118 * with the frame. 119 * @XGE_HAL_INF_LRO_SESSIONS_XCDED: Returned by ULD LRO module, when no 120 * more LRO sessions can be added. 121 * @XGE_HAL_INF_NOT_ENOUGH_HW_CQES: TBD 122 * @XGE_HAL_ERR_DRIVER_NOT_INITIALIZED: HAL is not initialized. 123 * @XGE_HAL_ERR_OUT_OF_MEMORY: Out of memory (example, when and 124 * allocating descriptors). 125 * @XGE_HAL_ERR_CHANNEL_NOT_FOUND: xge_hal_channel_open will return this 126 * error if corresponding channel is not configured. 127 * @XGE_HAL_ERR_WRONG_IRQ: Returned by HAL's ISR when the latter is 128 * invoked not because of the Xframe-generated interrupt. 129 * @XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES: Returned when user tries to 130 * configure more than XGE_HAL_MAX_MAC_ADDRESSES mac addresses. 131 * @XGE_HAL_ERR_BAD_DEVICE_ID: Unknown device PCI ID. 132 * @XGE_HAL_ERR_OUT_ALIGNED_FRAGS: Too many unaligned fragments 133 * in a scatter-gather list. 134 * @XGE_HAL_ERR_DEVICE_NOT_INITIALIZED: Device is not initialized. 135 * Typically means wrong sequence of API calls. 136 * @XGE_HAL_ERR_SWAPPER_CTRL: Error during device initialization: failed 137 * to set Xframe byte swapper in accordnace with the host 138 * endian-ness. 139 * @XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT: Failed to restore the device to 140 * a "quiescent" state. 141 * @XGE_HAL_ERR_INVALID_MTU_SIZE: Returned when MTU size specified by 142 * caller is not in the (64, 9600) range. 143 * @XGE_HAL_ERR_OUT_OF_MAPPING: Failed to map DMA-able memory. 144 * @XGE_HAL_ERR_BAD_SUBSYSTEM_ID: Bad PCI subsystem ID. (Currently we 145 * check for zero/non-zero only.) 146 * @XGE_HAL_ERR_INVALID_BAR_ID: Invalid BAR ID. Xframe supports two Base 147 * Address Register Spaces: BAR0 (id=0) and BAR1 (id=1). 148 * @XGE_HAL_ERR_INVALID_OFFSET: Invalid offset. Example, attempt to read 149 * register value (with offset) outside of the BAR0 space. 150 * @XGE_HAL_ERR_INVALID_DEVICE: Invalid device. The HAL device handle 151 * (passed by ULD) is invalid. 152 * @XGE_HAL_ERR_OUT_OF_SPACE: Out-of-provided-buffer-space. Returned by 153 * management "get" routines when the retrieved information does 154 * not fit into the provided buffer. 155 * @XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE: Invalid bit size. 156 * @XGE_HAL_ERR_VERSION_CONFLICT: Upper-layer driver and HAL (versions) 157 * are not compatible. 158 * @XGE_HAL_ERR_INVALID_MAC_ADDRESS: Invalid MAC address. 159 * @XGE_HAL_ERR_SPDM_NOT_ENABLED: SPDM support is not enabled. 160 * @XGE_HAL_ERR_SPDM_TABLE_FULL: SPDM table is full. 161 * @XGE_HAL_ERR_SPDM_INVALID_ENTRY: Invalid SPDM entry. 162 * @XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND: Unable to locate the entry in the 163 * SPDM table. 164 * @XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT: Local SPDM table is not in 165 * synch ith the actual one. 166 * @XGE_HAL_ERR_INVALID_PCI_INFO: Invalid or unrecognized PCI frequency, 167 * and or width, and or mode (Xframe-II only, see UG on PCI_INFO register). 168 * @XGE_HAL_ERR_CRITICAL: Critical error. Returned by HAL APIs 169 * (including xge_hal_device_handle_tcode()) on: ECC, parity, SERR. 170 * Also returned when PIO read does not go through ("all-foxes") 171 * because of "slot-freeze". 172 * @XGE_HAL_ERR_RESET_FAILED: Failed to soft-reset the device. 173 * Returned by xge_hal_device_reset(). One circumstance when it could 174 * happen: slot freeze by the system (see @XGE_HAL_ERR_CRITICAL). 175 * @XGE_HAL_BADCFG_TX_URANGE_A: Invalid Tx link utilization range A. See 176 * the structure xge_hal_tti_config_t{} for valid values. 177 * @XGE_HAL_BADCFG_TX_UFC_A: Invalid frame count for Tx link utilization 178 * range A. See the structure xge_hal_tti_config_t{} for valid values. 179 * @XGE_HAL_BADCFG_TX_URANGE_B: Invalid Tx link utilization range B. See 180 * the structure xge_hal_tti_config_t{} for valid values. 181 * @XGE_HAL_BADCFG_TX_UFC_B: Invalid frame count for Tx link utilization 182 * range B. See the strucuture xge_hal_tti_config_t{} for valid values. 183 * @XGE_HAL_BADCFG_TX_URANGE_C: Invalid Tx link utilization range C. See 184 * the structure xge_hal_tti_config_t{} for valid values. 185 * @XGE_HAL_BADCFG_TX_UFC_C: Invalid frame count for Tx link utilization 186 * range C. See the structure xge_hal_tti_config_t{} for valid values. 187 * @XGE_HAL_BADCFG_TX_UFC_D: Invalid frame count for Tx link utilization 188 * range D. See the structure xge_hal_tti_config_t{} for valid values. 189 * @XGE_HAL_BADCFG_TX_TIMER_VAL: Invalid Tx timer value. See the 190 * structure xge_hal_tti_config_t{} for valid values. 191 * @XGE_HAL_BADCFG_TX_TIMER_CI_EN: Invalid Tx timer continuous interrupt 192 * enable. See the structure xge_hal_tti_config_t{} for valid values. 193 * @XGE_HAL_BADCFG_RX_URANGE_A: Invalid Rx link utilization range A. See 194 * the structure xge_hal_rti_config_t{} for valid values. 195 * @XGE_HAL_BADCFG_RX_UFC_A: Invalid frame count for Rx link utilization 196 * range A. See the structure xge_hal_rti_config_t{} for valid values. 197 * @XGE_HAL_BADCFG_RX_URANGE_B: Invalid Rx link utilization range B. See 198 * the structure xge_hal_rti_config_t{} for valid values. 199 * @XGE_HAL_BADCFG_RX_UFC_B: Invalid frame count for Rx link utilization 200 * range B. See the structure xge_hal_rti_config_t{} for valid values. 201 * @XGE_HAL_BADCFG_RX_URANGE_C: Invalid Rx link utilization range C. See 202 * the structure xge_hal_rti_config_t{} for valid values. 203 * @XGE_HAL_BADCFG_RX_UFC_C: Invalid frame count for Rx link utilization 204 * range C. See the structure xge_hal_rti_config_t{} for valid values. 205 * @XGE_HAL_BADCFG_RX_UFC_D: Invalid frame count for Rx link utilization 206 * range D. See the structure xge_hal_rti_config_t{} for valid values. 207 * @XGE_HAL_BADCFG_RX_TIMER_VAL: Invalid Rx timer value. See the 208 * structure xge_hal_rti_config_t{} for valid values. 209 * @XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH: Invalid initial fifo queue 210 * length. See the structure xge_hal_fifo_queue_t for valid values. 211 * @XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH: Invalid fifo queue max length. 212 * See the structure xge_hal_fifo_queue_t for valid values. 213 * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR: Invalid fifo queue interrupt mode. 214 * See the structure xge_hal_fifo_queue_t for valid values. 215 * @XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS: Invalid Initial number of 216 * RxD blocks for the ring. See the structure xge_hal_ring_queue_t for 217 * valid values. 218 * @XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS: Invalid maximum number of RxD 219 * blocks for the ring. See the structure xge_hal_ring_queue_t for 220 * valid values. 221 * @XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE: Invalid ring buffer mode. See 222 * the structure xge_hal_ring_queue_t for valid values. 223 * @XGE_HAL_BADCFG_RING_QUEUE_SIZE: Invalid ring queue size. See the 224 * structure xge_hal_ring_queue_t for valid values. 225 * @XGE_HAL_BADCFG_BACKOFF_INTERVAL_US: Invalid backoff timer interval 226 * for the ring. See the structure xge_hal_ring_queue_t for valid values. 227 * @XGE_HAL_BADCFG_MAX_FRM_LEN: Invalid ring max frame length. See the 228 * structure xge_hal_ring_queue_t for valid values. 229 * @XGE_HAL_BADCFG_RING_PRIORITY: Invalid ring priority. See the 230 * structure xge_hal_ring_queue_t for valid values. 231 * @XGE_HAL_BADCFG_TMAC_UTIL_PERIOD: Invalid tmac util period. See the 232 * structure xge_hal_mac_config_t{} for valid values. 233 * @XGE_HAL_BADCFG_RMAC_UTIL_PERIOD: Invalid rmac util period. See the 234 * structure xge_hal_mac_config_t{} for valid values. 235 * @XGE_HAL_BADCFG_RMAC_BCAST_EN: Invalid rmac brodcast enable. See the 236 * structure xge_hal_mac_config_t{} for valid values. 237 * @XGE_HAL_BADCFG_RMAC_HIGH_PTIME: Invalid rmac pause time. See the 238 * structure xge_hal_mac_config_t{} for valid values. 239 * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3: Invalid threshold for pause 240 * frame generation for queues 0 through 3. See the structure 241 * xge_hal_mac_config_t{} for valid values. 242 * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7:Invalid threshold for pause 243 * frame generation for queues 4 through 7. See the structure 244 * xge_hal_mac_config_t{} for valid values. 245 * @XGE_HAL_BADCFG_FIFO_FRAGS: Invalid fifo max fragments length. See 246 * the structure xge_hal_fifo_config_t{} for valid values. 247 * @XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD: Invalid fifo reserve 248 * threshold. See the structure xge_hal_fifo_config_t{} for valid values. 249 * @XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE: Invalid fifo descriptors memblock 250 * size. See the structure xge_hal_fifo_config_t{} for valid values. 251 * @XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE: Invalid ring descriptors memblock 252 * size. See the structure xge_hal_ring_config_t{} for valid values. 253 * @XGE_HAL_BADCFG_MAX_MTU: Invalid max mtu for the device. See the 254 * structure xge_hal_device_config_t{} for valid values. 255 * @XGE_HAL_BADCFG_ISR_POLLING_CNT: Invalid isr polling count. See the 256 * structure xge_hal_device_config_t{} for valid values. 257 * @XGE_HAL_BADCFG_LATENCY_TIMER: Invalid Latency timer. See the 258 * structure xge_hal_device_config_t{} for valid values. 259 * @XGE_HAL_BADCFG_MAX_SPLITS_TRANS: Invalid maximum number of pci-x 260 * split transactions. See the structure xge_hal_device_config_t{} for valid 261 * values. 262 * @XGE_HAL_BADCFG_MMRB_COUNT: Invalid mmrb count. See the structure 263 * xge_hal_device_config_t{} for valid values. 264 * @XGE_HAL_BADCFG_SHARED_SPLITS: Invalid number of outstanding split 265 * transactions that is shared by Tx and Rx requests. See the structure 266 * xge_hal_device_config_t{} for valid values. 267 * @XGE_HAL_BADCFG_STATS_REFRESH_TIME: Invalid time interval for 268 * automatic statistics transfer to the host. See the structure 269 * xge_hal_device_config_t{} for valid values. 270 * @XGE_HAL_BADCFG_PCI_FREQ_MHERZ: Invalid pci clock frequency. See the 271 * structure xge_hal_device_config_t{} for valid values. 272 * @XGE_HAL_BADCFG_PCI_MODE: Invalid pci mode. See the structure 273 * xge_hal_device_config_t{} for valid values. 274 * @XGE_HAL_BADCFG_INTR_MODE: Invalid interrupt mode. See the structure 275 * xge_hal_device_config_t{} for valid values. 276 * @XGE_HAL_BADCFG_SCHED_TIMER_US: Invalid scheduled timer interval to 277 * generate interrupt. See the structure xge_hal_device_config_t{} 278 * for valid values. 279 * @XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT: Invalid scheduled timer one 280 * shot. See the structure xge_hal_device_config_t{} for valid values. 281 * @XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL: Invalid driver queue initial 282 * size. See the structure xge_hal_driver_config_t{} for valid values. 283 * @XGE_HAL_BADCFG_QUEUE_SIZE_MAX: Invalid driver queue max size. See 284 * the structure xge_hal_driver_config_t{} for valid values. 285 * @XGE_HAL_BADCFG_RING_RTH_EN: Invalid value of RTH-enable. See 286 * the structure xge_hal_ring_queue_t for valid values. 287 * @XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS: Invalid value configured for 288 * indicate_max_pkts variable. 289 * @XGE_HAL_BADCFG_TX_TIMER_AC_EN: Invalid value for Tx timer 290 * auto-cancel. See xge_hal_tti_config_t{}. 291 * @XGE_HAL_BADCFG_RX_TIMER_AC_EN: Invalid value for Rx timer 292 * auto-cancel. See xge_hal_rti_config_t{}. 293 * @XGE_HAL_BADCFG_RXUFCA_INTR_THRES: TODO 294 * @XGE_HAL_BADCFG_RXUFCA_LO_LIM: TODO 295 * @XGE_HAL_BADCFG_RXUFCA_HI_LIM: TODO 296 * @XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD: TODO 297 * @XGE_HAL_BADCFG_TRACEBUF_SIZE: Bad configuration: the size of the circular 298 * (in memory) trace buffer either too large or too small. See the 299 * the corresponding header file or README for the acceptable range. 300 * @XGE_HAL_BADCFG_LINK_VALID_CNT: Bad configuration: the link-valid 301 * counter cannot have the specified value. Note that the link-valid 302 * counting is done only at device-open time, to determine with the 303 * specified certainty that the link is up. See the 304 * the corresponding header file or README for the acceptable range. 305 * See also @XGE_HAL_BADCFG_LINK_RETRY_CNT. 306 * @XGE_HAL_BADCFG_LINK_RETRY_CNT: Bad configuration: the specified 307 * link-up retry count is out of the valid range. Note that the link-up 308 * retry counting is done only at device-open time. 309 * See also xge_hal_device_config_t{}. 310 * @XGE_HAL_BADCFG_LINK_STABILITY_PERIOD: Invalid link stability period. 311 * @XGE_HAL_BADCFG_DEVICE_POLL_MILLIS: Invalid device poll interval. 312 * @XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN: TBD 313 * @XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN: TBD 314 * @XGE_HAL_BADCFG_MEDIA: TBD 315 * @XGE_HAL_BADCFG_NO_ISR_EVENTS: TBD 316 * See the structure xge_hal_device_config_t{} for valid values. 317 * @XGE_HAL_EOF_TRACE_BUF: End of the circular (in memory) trace buffer. 318 * Returned by xge_hal_mgmt_trace_read(), when user tries to read the trace 319 * past the buffer limits. Used to enable user to load the trace in two 320 * or more reads. 321 * @XGE_HAL_BADCFG_RING_RTS_MAC_EN: Invalid value of RTS_MAC_EN enable. See 322 * the structure xge_hal_ring_queue_t for valid values. 323 * @XGE_HAL_BADCFG_LRO_SG_SIZE : Invalid value of LRO scatter gatter size. 324 * See the structure xge_hal_device_config_t for valid values. 325 * @XGE_HAL_BADCFG_LRO_FRM_LEN : Invalid value of LRO frame length. 326 * See the structure xge_hal_device_config_t for valid values. 327 * @XGE_HAL_BADCFG_WQE_NUM_ODS: TBD 328 * @XGE_HAL_BADCFG_BIMODAL_INTR: Invalid value to configure bimodal interrupts 329 * Enumerates status and error codes returned by HAL public 330 * API functions. 331 */ 332 typedef enum xge_hal_status_e { 333 XGE_HAL_OK = 0, 334 XGE_HAL_FAIL = 1, 335 XGE_HAL_COMPLETIONS_REMAIN = 2, 336 337 XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS = XGE_HAL_BASE_INF + 1, 338 XGE_HAL_INF_OUT_OF_DESCRIPTORS = XGE_HAL_BASE_INF + 2, 339 XGE_HAL_INF_CHANNEL_IS_NOT_READY = XGE_HAL_BASE_INF + 3, 340 XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING = XGE_HAL_BASE_INF + 4, 341 XGE_HAL_INF_STATS_IS_NOT_READY = XGE_HAL_BASE_INF + 5, 342 XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS = XGE_HAL_BASE_INF + 6, 343 XGE_HAL_INF_IRQ_POLLING_CONTINUE = XGE_HAL_BASE_INF + 7, 344 XGE_HAL_INF_LRO_BEGIN = XGE_HAL_BASE_INF + 8, 345 XGE_HAL_INF_LRO_CONT = XGE_HAL_BASE_INF + 9, 346 XGE_HAL_INF_LRO_UNCAPABLE = XGE_HAL_BASE_INF + 10, 347 XGE_HAL_INF_LRO_END_1 = XGE_HAL_BASE_INF + 11, 348 XGE_HAL_INF_LRO_END_2 = XGE_HAL_BASE_INF + 12, 349 XGE_HAL_INF_LRO_END_3 = XGE_HAL_BASE_INF + 13, 350 XGE_HAL_INF_LRO_SESSIONS_XCDED = XGE_HAL_BASE_INF + 14, 351 XGE_HAL_INF_NOT_ENOUGH_HW_CQES = XGE_HAL_BASE_INF + 15, 352 XGE_HAL_ERR_DRIVER_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 1, 353 XGE_HAL_ERR_OUT_OF_MEMORY = XGE_HAL_BASE_ERR + 4, 354 XGE_HAL_ERR_CHANNEL_NOT_FOUND = XGE_HAL_BASE_ERR + 5, 355 XGE_HAL_ERR_WRONG_IRQ = XGE_HAL_BASE_ERR + 6, 356 XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES = XGE_HAL_BASE_ERR + 7, 357 XGE_HAL_ERR_SWAPPER_CTRL = XGE_HAL_BASE_ERR + 8, 358 XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT = XGE_HAL_BASE_ERR + 9, 359 XGE_HAL_ERR_INVALID_MTU_SIZE = XGE_HAL_BASE_ERR + 10, 360 XGE_HAL_ERR_OUT_OF_MAPPING = XGE_HAL_BASE_ERR + 11, 361 XGE_HAL_ERR_BAD_SUBSYSTEM_ID = XGE_HAL_BASE_ERR + 12, 362 XGE_HAL_ERR_INVALID_BAR_ID = XGE_HAL_BASE_ERR + 13, 363 XGE_HAL_ERR_INVALID_OFFSET = XGE_HAL_BASE_ERR + 14, 364 XGE_HAL_ERR_INVALID_DEVICE = XGE_HAL_BASE_ERR + 15, 365 XGE_HAL_ERR_OUT_OF_SPACE = XGE_HAL_BASE_ERR + 16, 366 XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE = XGE_HAL_BASE_ERR + 17, 367 XGE_HAL_ERR_VERSION_CONFLICT = XGE_HAL_BASE_ERR + 18, 368 XGE_HAL_ERR_INVALID_MAC_ADDRESS = XGE_HAL_BASE_ERR + 19, 369 XGE_HAL_ERR_BAD_DEVICE_ID = XGE_HAL_BASE_ERR + 20, 370 XGE_HAL_ERR_OUT_ALIGNED_FRAGS = XGE_HAL_BASE_ERR + 21, 371 XGE_HAL_ERR_DEVICE_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 22, 372 XGE_HAL_ERR_SPDM_NOT_ENABLED = XGE_HAL_BASE_ERR + 23, 373 XGE_HAL_ERR_SPDM_TABLE_FULL = XGE_HAL_BASE_ERR + 24, 374 XGE_HAL_ERR_SPDM_INVALID_ENTRY = XGE_HAL_BASE_ERR + 25, 375 XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND = XGE_HAL_BASE_ERR + 26, 376 XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT= XGE_HAL_BASE_ERR + 27, 377 XGE_HAL_ERR_INVALID_PCI_INFO = XGE_HAL_BASE_ERR + 28, 378 XGE_HAL_ERR_CRITICAL = XGE_HAL_BASE_ERR + 29, 379 XGE_HAL_ERR_RESET_FAILED = XGE_HAL_BASE_ERR + 30, 380 XGE_HAL_ERR_INVALID_WR = XGE_HAL_BASE_ERR + 31, 381 XGE_HAL_ERR_TOO_MANY = XGE_HAL_BASE_ERR + 32, 382 383 XGE_HAL_BADCFG_TX_URANGE_A = XGE_HAL_BASE_BADCFG + 1, 384 XGE_HAL_BADCFG_TX_UFC_A = XGE_HAL_BASE_BADCFG + 2, 385 XGE_HAL_BADCFG_TX_URANGE_B = XGE_HAL_BASE_BADCFG + 3, 386 XGE_HAL_BADCFG_TX_UFC_B = XGE_HAL_BASE_BADCFG + 4, 387 XGE_HAL_BADCFG_TX_URANGE_C = XGE_HAL_BASE_BADCFG + 5, 388 XGE_HAL_BADCFG_TX_UFC_C = XGE_HAL_BASE_BADCFG + 6, 389 XGE_HAL_BADCFG_TX_UFC_D = XGE_HAL_BASE_BADCFG + 8, 390 XGE_HAL_BADCFG_TX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 9, 391 XGE_HAL_BADCFG_TX_TIMER_CI_EN = XGE_HAL_BASE_BADCFG + 10, 392 XGE_HAL_BADCFG_RX_URANGE_A = XGE_HAL_BASE_BADCFG + 11, 393 XGE_HAL_BADCFG_RX_UFC_A = XGE_HAL_BASE_BADCFG + 12, 394 XGE_HAL_BADCFG_RX_URANGE_B = XGE_HAL_BASE_BADCFG + 13, 395 XGE_HAL_BADCFG_RX_UFC_B = XGE_HAL_BASE_BADCFG + 14, 396 XGE_HAL_BADCFG_RX_URANGE_C = XGE_HAL_BASE_BADCFG + 15, 397 XGE_HAL_BADCFG_RX_UFC_C = XGE_HAL_BASE_BADCFG + 16, 398 XGE_HAL_BADCFG_RX_UFC_D = XGE_HAL_BASE_BADCFG + 17, 399 XGE_HAL_BADCFG_RX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 18, 400 XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH= XGE_HAL_BASE_BADCFG + 19, 401 XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH = XGE_HAL_BASE_BADCFG + 20, 402 XGE_HAL_BADCFG_FIFO_QUEUE_INTR = XGE_HAL_BASE_BADCFG + 21, 403 XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS=XGE_HAL_BASE_BADCFG + 22, 404 XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS = XGE_HAL_BASE_BADCFG + 23, 405 XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE = XGE_HAL_BASE_BADCFG + 24, 406 XGE_HAL_BADCFG_RING_QUEUE_SIZE = XGE_HAL_BASE_BADCFG + 25, 407 XGE_HAL_BADCFG_BACKOFF_INTERVAL_US = XGE_HAL_BASE_BADCFG + 26, 408 XGE_HAL_BADCFG_MAX_FRM_LEN = XGE_HAL_BASE_BADCFG + 27, 409 XGE_HAL_BADCFG_RING_PRIORITY = XGE_HAL_BASE_BADCFG + 28, 410 XGE_HAL_BADCFG_TMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 29, 411 XGE_HAL_BADCFG_RMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 30, 412 XGE_HAL_BADCFG_RMAC_BCAST_EN = XGE_HAL_BASE_BADCFG + 31, 413 XGE_HAL_BADCFG_RMAC_HIGH_PTIME = XGE_HAL_BASE_BADCFG + 32, 414 XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3 = XGE_HAL_BASE_BADCFG +33, 415 XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7 = XGE_HAL_BASE_BADCFG + 34, 416 XGE_HAL_BADCFG_FIFO_FRAGS = XGE_HAL_BASE_BADCFG + 35, 417 XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD = XGE_HAL_BASE_BADCFG + 37, 418 XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 38, 419 XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 39, 420 XGE_HAL_BADCFG_MAX_MTU = XGE_HAL_BASE_BADCFG + 40, 421 XGE_HAL_BADCFG_ISR_POLLING_CNT = XGE_HAL_BASE_BADCFG + 41, 422 XGE_HAL_BADCFG_LATENCY_TIMER = XGE_HAL_BASE_BADCFG + 42, 423 XGE_HAL_BADCFG_MAX_SPLITS_TRANS = XGE_HAL_BASE_BADCFG + 43, 424 XGE_HAL_BADCFG_MMRB_COUNT = XGE_HAL_BASE_BADCFG + 44, 425 XGE_HAL_BADCFG_SHARED_SPLITS = XGE_HAL_BASE_BADCFG + 45, 426 XGE_HAL_BADCFG_STATS_REFRESH_TIME = XGE_HAL_BASE_BADCFG + 46, 427 XGE_HAL_BADCFG_PCI_FREQ_MHERZ = XGE_HAL_BASE_BADCFG + 47, 428 XGE_HAL_BADCFG_PCI_MODE = XGE_HAL_BASE_BADCFG + 48, 429 XGE_HAL_BADCFG_INTR_MODE = XGE_HAL_BASE_BADCFG + 49, 430 XGE_HAL_BADCFG_SCHED_TIMER_US = XGE_HAL_BASE_BADCFG + 50, 431 XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT = XGE_HAL_BASE_BADCFG + 51, 432 XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL = XGE_HAL_BASE_BADCFG + 52, 433 XGE_HAL_BADCFG_QUEUE_SIZE_MAX = XGE_HAL_BASE_BADCFG + 53, 434 XGE_HAL_BADCFG_RING_RTH_EN = XGE_HAL_BASE_BADCFG + 54, 435 XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS = XGE_HAL_BASE_BADCFG + 55, 436 XGE_HAL_BADCFG_TX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 56, 437 XGE_HAL_BADCFG_RX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 57, 438 XGE_HAL_BADCFG_RXUFCA_INTR_THRES = XGE_HAL_BASE_BADCFG + 58, 439 XGE_HAL_BADCFG_RXUFCA_LO_LIM = XGE_HAL_BASE_BADCFG + 59, 440 XGE_HAL_BADCFG_RXUFCA_HI_LIM = XGE_HAL_BASE_BADCFG + 60, 441 XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD = XGE_HAL_BASE_BADCFG + 61, 442 XGE_HAL_BADCFG_TRACEBUF_SIZE = XGE_HAL_BASE_BADCFG + 62, 443 XGE_HAL_BADCFG_LINK_VALID_CNT = XGE_HAL_BASE_BADCFG + 63, 444 XGE_HAL_BADCFG_LINK_RETRY_CNT = XGE_HAL_BASE_BADCFG + 64, 445 XGE_HAL_BADCFG_LINK_STABILITY_PERIOD = XGE_HAL_BASE_BADCFG + 65, 446 XGE_HAL_BADCFG_DEVICE_POLL_MILLIS = XGE_HAL_BASE_BADCFG + 66, 447 XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN = XGE_HAL_BASE_BADCFG + 67, 448 XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN = XGE_HAL_BASE_BADCFG + 68, 449 XGE_HAL_BADCFG_MEDIA = XGE_HAL_BASE_BADCFG + 69, 450 XGE_HAL_BADCFG_NO_ISR_EVENTS = XGE_HAL_BASE_BADCFG + 70, 451 XGE_HAL_BADCFG_RING_RTS_MAC_EN = XGE_HAL_BASE_BADCFG + 71, 452 XGE_HAL_BADCFG_LRO_SG_SIZE = XGE_HAL_BASE_BADCFG + 72, 453 XGE_HAL_BADCFG_LRO_FRM_LEN = XGE_HAL_BASE_BADCFG + 73, 454 XGE_HAL_BADCFG_WQE_NUM_ODS = XGE_HAL_BASE_BADCFG + 74, 455 XGE_HAL_BADCFG_BIMODAL_INTR = XGE_HAL_BASE_BADCFG + 75, 456 XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US = XGE_HAL_BASE_BADCFG + 76, 457 XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US = XGE_HAL_BASE_BADCFG + 77, 458 XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED = XGE_HAL_BASE_BADCFG + 78, 459 XGE_HAL_BADCFG_RTS_QOS_STEERING_CONFIG = XGE_HAL_BASE_BADCFG + 79, 460 XGE_HAL_EOF_TRACE_BUF = -1 461 } xge_hal_status_e; 462 463 #define XGE_HAL_ETH_ALEN 6 464 typedef u8 macaddr_t[XGE_HAL_ETH_ALEN]; 465 466 #define XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE 0x100 467 468 /* frames sizes */ 469 #define XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE 14 470 #define XGE_HAL_HEADER_802_2_SIZE 3 471 #define XGE_HAL_HEADER_SNAP_SIZE 5 472 #define XGE_HAL_HEADER_VLAN_SIZE 4 473 #define XGE_HAL_MAC_HEADER_MAX_SIZE \ 474 (XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \ 475 XGE_HAL_HEADER_802_2_SIZE + \ 476 XGE_HAL_HEADER_SNAP_SIZE) 477 478 #define XGE_HAL_TCPIP_HEADER_MAX_SIZE (64 + 64) 479 480 /* 32bit alignments */ 481 #define XGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN 2 482 #define XGE_HAL_HEADER_802_2_SNAP_ALIGN 2 483 #define XGE_HAL_HEADER_802_2_ALIGN 3 484 #define XGE_HAL_HEADER_SNAP_ALIGN 1 485 486 #define XGE_HAL_L3_CKSUM_OK 0xFFFF 487 #define XGE_HAL_L4_CKSUM_OK 0xFFFF 488 #define XGE_HAL_MIN_MTU 46 489 #define XGE_HAL_MAX_MTU 9600 490 #define XGE_HAL_DEFAULT_MTU 1500 491 492 #define XGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE 81920 493 494 #define XGE_HAL_PCISIZE_XENA 26 /* multiples of dword */ 495 #define XGE_HAL_PCISIZE_HERC 64 /* multiples of dword */ 496 497 /* Highest level interrupt blocks */ 498 #define XGE_HAL_TX_PIC_INTR (0x0001<<0) 499 #define XGE_HAL_TX_DMA_INTR (0x0001<<1) 500 #define XGE_HAL_TX_MAC_INTR (0x0001<<2) 501 #define XGE_HAL_TX_XGXS_INTR (0x0001<<3) 502 #define XGE_HAL_TX_TRAFFIC_INTR (0x0001<<4) 503 #define XGE_HAL_RX_PIC_INTR (0x0001<<5) 504 #define XGE_HAL_RX_DMA_INTR (0x0001<<6) 505 #define XGE_HAL_RX_MAC_INTR (0x0001<<7) 506 #define XGE_HAL_RX_XGXS_INTR (0x0001<<8) 507 #define XGE_HAL_RX_TRAFFIC_INTR (0x0001<<9) 508 #define XGE_HAL_MC_INTR (0x0001<<10) 509 #define XGE_HAL_SCHED_INTR (0x0001<<11) 510 #define XGE_HAL_ALL_INTRS (XGE_HAL_TX_PIC_INTR | \ 511 XGE_HAL_TX_DMA_INTR | \ 512 XGE_HAL_TX_MAC_INTR | \ 513 XGE_HAL_TX_XGXS_INTR | \ 514 XGE_HAL_TX_TRAFFIC_INTR | \ 515 XGE_HAL_RX_PIC_INTR | \ 516 XGE_HAL_RX_DMA_INTR | \ 517 XGE_HAL_RX_MAC_INTR | \ 518 XGE_HAL_RX_XGXS_INTR | \ 519 XGE_HAL_RX_TRAFFIC_INTR | \ 520 XGE_HAL_MC_INTR | \ 521 XGE_HAL_SCHED_INTR) 522 #define XGE_HAL_GEN_MASK_INTR (0x0001<<12) 523 524 /* Interrupt masks for the general interrupt mask register */ 525 #define XGE_HAL_ALL_INTRS_DIS 0xFFFFFFFFFFFFFFFFULL 526 527 #define XGE_HAL_TXPIC_INT_M BIT(0) 528 #define XGE_HAL_TXDMA_INT_M BIT(1) 529 #define XGE_HAL_TXMAC_INT_M BIT(2) 530 #define XGE_HAL_TXXGXS_INT_M BIT(3) 531 #define XGE_HAL_TXTRAFFIC_INT_M BIT(8) 532 #define XGE_HAL_PIC_RX_INT_M BIT(32) 533 #define XGE_HAL_RXDMA_INT_M BIT(33) 534 #define XGE_HAL_RXMAC_INT_M BIT(34) 535 #define XGE_HAL_MC_INT_M BIT(35) 536 #define XGE_HAL_RXXGXS_INT_M BIT(36) 537 #define XGE_HAL_RXTRAFFIC_INT_M BIT(40) 538 539 /* MSI level Interrupts */ 540 #define XGE_HAL_MAX_MSIX_VECTORS (16) 541 542 /* 543 * xge_hal_msix_vector_t 544 * 545 * Represents MSI-X vector. 546 * 547 */ 548 typedef struct xge_hal_msix_vector_t { 549 int idx; 550 int num; 551 void *data; 552 char desc[16]; 553 u64 msi_addr; 554 u64 msi_data; 555 } xge_hal_msix_vector_t; 556 557 558 typedef struct xge_hal_ipv4 { 559 u32 addr; 560 }xge_hal_ipv4; 561 562 typedef struct xge_hal_ipv6 { 563 u64 addr[2]; 564 }xge_hal_ipv6; 565 566 typedef union xge_hal_ipaddr_t { 567 xge_hal_ipv4 ipv4; 568 xge_hal_ipv6 ipv6; 569 }xge_hal_ipaddr_t; 570 571 /* DMA level Interrupts */ 572 #define XGE_HAL_TXDMA_PFC_INT_M BIT(0) 573 574 /* PFC block interrupts */ 575 #define XGE_HAL_PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO 576 full */ 577 578 /* basic handles */ 579 typedef void* xge_hal_device_h; 580 typedef void* xge_hal_dtr_h; 581 typedef void* xge_hal_channel_h; 582 #ifdef XGEHAL_RNIC 583 typedef void* xge_hal_towi_h; 584 typedef void* xge_hal_hw_wqe_h; 585 typedef void* xge_hal_hw_cqe_h; 586 typedef void* xge_hal_lro_wqe_h; 587 typedef void* xge_hal_lro_cqe_h; 588 typedef void* xge_hal_up_msg_h; 589 typedef void* xge_hal_down_msg_h; 590 #endif 591 /* 592 * I2C device id. Used in I2C control register for accessing EEPROM device 593 * memory. 594 */ 595 #define XGE_DEV_ID 5 596 597 typedef enum xge_hal_xpak_alarm_type_e { 598 XGE_HAL_XPAK_ALARM_EXCESS_TEMP = 1, 599 XGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT = 2, 600 XGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT = 3, 601 } xge_hal_xpak_alarm_type_e; 602 603 604 __EXTERN_END_DECLS 605 606 #endif /* XGE_HAL_TYPES_H */ 607