1 /* 2 xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 * 22 * Copyright (c) 2002-2006 Neterion, Inc. 23 */ 24 25 #ifndef XGE_HAL_STATS_H 26 #define XGE_HAL_STATS_H 27 28 #include "xge-os-pal.h" 29 #include "xge-debug.h" 30 #include "xgehal-types.h" 31 #include "xgehal-config.h" 32 33 __EXTERN_BEGIN_DECLS 34 35 /** 36 * struct xge_hal_stats_hw_info_t - Xframe hardware statistics. 37 * Transmit MAC Statistics: 38 * 39 * @tmac_frms: Count of successfully transmitted MAC 40 * frames Note that this statistic may be inaccurate. The correct statistic may 41 * be derived by calcualating (tmac_ttl_octets - tmac_ttl_less_fb_octets) / 8 42 * 43 * @tmac_data_octets: Count of data and padding octets of successfully 44 * transmitted frames. 45 * 46 * @tmac_drop_frms: Count of frames that could not be sent for no other reason 47 * than internal MAC processing. Increments once whenever the 48 * transmit buffer is flushed (due to an ECC error on a memory descriptor). 49 * 50 * @tmac_mcst_frms: Count of successfully transmitted frames to a multicast 51 * address. Does not include frames sent to the broadcast address. 52 * 53 * @tmac_bcst_frms: Count of successfully transmitted frames to the broadcast 54 * address. 55 * 56 * @tmac_pause_ctrl_frms: Count of MAC PAUSE control frames that are 57 * transmitted. Since, the only control frames supported by this device 58 * are PAUSE frames, this register is a count of all transmitted MAC control 59 * frames. 60 * 61 * @tmac_ttl_octets: Count of total octets of transmitted frames, including 62 * framing characters. 63 * 64 * @tmac_ucst_frms: Count of transmitted frames containing a unicast address. 65 * @tmac_nucst_frms: Count of transmitted frames containing a non-unicast 66 * (broadcast, multicast) address. 67 * 68 * @tmac_any_err_frms: Count of transmitted frames containing any error that 69 * prevents them from being passed to the network. Increments if there is an ECC 70 * while reading the frame out of the transmit buffer. 71 * 72 * @tmac_ttl_less_fb_octets: Count of total octets of transmitted 73 * frames, not including framing characters (i.e. less framing bits) 74 * 75 * @tmac_vld_ip_octets: Count of total octets of transmitted IP datagrams that 76 * were passed to the network. Frames that are padded by the host have 77 * their padding counted as part of the IP datagram. 78 * 79 * @tmac_vld_ip: Count of transmitted IP datagrams that were passed to the 80 * network. 81 * 82 * @tmac_drop_ip: Count of transmitted IP datagrams that could not be passed to 83 * the network. Increments because of 1) an internal processing error (such as 84 * an uncorrectable ECC error); 2) a frame parsing error during IP checksum 85 * calculation. 86 * 87 * @tmac_icmp: Count of transmitted ICMP messages. Includes messages not sent 88 * due to problems within ICMP. 89 * 90 * @tmac_rst_tcp: Count of transmitted TCP segments containing the RST flag. 91 * 92 * @tmac_tcp: Count of transmitted TCP segments. Note that Xena has 93 * no knowledge of retransmission. 94 * 95 * @tmac_udp: Count of transmitted UDP datagrams. 96 * @reserved_0: Reserved. 97 * 98 * Receive MAC Statistics: 99 * @rmac_vld_frms: Count of successfully received MAC frames. Does not include 100 * frames received with frame-too-long, FCS, or length errors. 101 * 102 * @rmac_data_octets: Count of data and padding octets of successfully received 103 * frames. Does not include frames received with frame-too-long, FCS, or length 104 * errors. 105 * 106 * @rmac_fcs_err_frms: Count of received MAC frames that do not pass FCS. Does 107 * not include frames received with frame-too-long or frame-too-short error. 108 * 109 * @rmac_drop_frms: Count of received frames that could not be passed to the 110 * host because of 1) Random Early Discard (RED); 2) Frame steering algorithm 111 * found no available queue; 3) Receive ingress buffer overflow. 112 * 113 * @rmac_vld_mcst_frms: Count of successfully received MAC frames containing a 114 * multicast address. Does not include frames received with frame-too-long, FCS, 115 * or length errors. 116 * 117 * @rmac_vld_bcst_frms: Count of successfully received MAC frames containing a 118 * broadcast address. Does not include frames received with frame-too-long, FCS, 119 * or length errors. 120 * 121 * @rmac_in_rng_len_err_frms: Count of received frames with a length/type field 122 * value between 46 (42 for VLANtagged frames) and 1500 (also 1500 for 123 * VLAN-tagged frames), inclusive, that does not match the number of data octets 124 * (including pad) received. Also contains a count of received frames with a 125 * length/type field less than 46 (42 for VLAN-tagged frames) and the number of 126 * data octets (including pad) received is greater than 46 (42 for VLAN-tagged 127 * frames). 128 * 129 * @rmac_out_rng_len_err_frms: Count of received frames with length/type field 130 * between 1501 and 1535 decimal, inclusive. 131 * 132 * @rmac_long_frms: Count of received frames that are longer than 133 * rmac_max_pyld_len + 18 bytes (+22 bytes if VLAN-tagged). 134 * 135 * @rmac_pause_ctrl_frms: Count of received MAC PAUSE control frames. 136 * 137 * @rmac_unsup_ctrl_frms: Count of received MAC control frames 138 * that do not contain the PAUSE opcode. The sum of MAC_PAUSE_CTRL_FRMS and this 139 * register is a count of all received MAC control frames. 140 * 141 * @rmac_ttl_octets: Count of total octets of received frames, including framing 142 * characters. 143 * 144 * @rmac_accepted_ucst_frms: Count of successfully received frames 145 * containing a unicast address. Only includes frames that are passed to the 146 * system. 147 * 148 * @rmac_accepted_nucst_frms: Count of successfully received frames 149 * containing a non-unicast (broadcast or multicast) address. Only includes 150 * frames that are passed to the system. Could include, for instance, 151 * non-unicast frames that contain FCS errors if the MAC_ERROR_CFG register is 152 * set to pass FCSerrored frames to the host. 153 * 154 * @rmac_discarded_frms: Count of received frames containing any error that 155 * prevents them from being passed to the system. Includes, for example, 156 * received pause frames that are discarded by the MAC and frames discarded 157 * because of their destination address. 158 * 159 * @rmac_drop_events: Because the RMAC drops one frame at a time, this stat 160 * matches rmac_drop_frms. 161 * 162 * @reserved_1: Reserved. 163 * @rmac_ttl_less_fb_octets: Count of total octets of received frames, 164 * not including framing characters (i.e. less framing bits). 165 * 166 * @rmac_ttl_frms: Count of all received MAC frames, including frames received 167 * with frame-too-long, FCS, or length errors. 168 * 169 * @reserved_2: Reserved. 170 * @reserved_3: Reserved. 171 * @rmac_usized_frms: Count of received frames of length (including FCS, but not 172 * framing bits) less than 64 octets, that are otherwise well-formed. 173 * 174 * @rmac_osized_frms: Count of received frames of length (including FCS, but not 175 * framing bits) more than 1518 octets, that are otherwise well-formed. 176 * 177 * @rmac_frag_frms: Count of received frames of length (including FCS, but not 178 * framing bits) less than 64 octets that had bad FCS. In other words, counts 179 * fragments (i.e. runts). 180 * 181 * @rmac_jabber_frms: Count of received frames of length (including FCS, but not 182 * framing bits) more than MTU octets that had bad FCS. In other words, counts 183 * jabbers. 184 * 185 * @reserved_4: Reserved. 186 * @rmac_ttl_64_frms: Count of all received MAC frames with length (including 187 * FCS, but not framing bits) of exactly 64 octets. Includes frames received 188 * with frame-too-long, FCS, or length errors. 189 * 190 * @rmac_ttl_65_127_frms: Count of all received MAC frames with length 191 * (including FCS, but not framing bits) of between 65 and 127 octets 192 * inclusive. Includes frames received with frame-too-long, FCS, or length 193 * errors. 194 * @reserved_5: Reserved. 195 * @rmac_ttl_128_255_frms: Count of all received MAC frames with length 196 * (including FCS, but not framing bits) of between 128 and 255 octets 197 * inclusive. Includes frames received with frame-too-long, FCS, or length 198 * errors. 199 * 200 * @rmac_ttl_256_511_frms: Count of all received MAC frames with length 201 * (including FCS, but not framing bits) of between 256 and 511 octets 202 * inclusive. Includes frames received with frame-too-long, FCS, or length 203 * errors. 204 * 205 * @reserved_6: Reserved. 206 * @rmac_ttl_512_1023_frms: Count of all received MAC frames with length 207 * (including FCS, but not framing bits) of between 512 and 1023 octets 208 * inclusive. Includes frames received with frame-too-long, FCS, or length 209 * errors. 210 * 211 * @rmac_ttl_1024_1518_frms: Count of all received MAC frames with length 212 * (including FCS, but not framing bits) of between 1024 and 1518 octets 213 * inclusive. Includes frames received with frame-too-long, FCS, or length 214 * errors. 215 * @reserved_7: Reserved. 216 * @rmac_ip: Count of received IP datagrams. Includes errored IP datagrams. 217 * 218 * @rmac_ip_octets: Count of number of octets in received IP datagrams. Includes 219 * errored IP datagrams. 220 * 221 * @rmac_hdr_err_ip: Count of received IP datagrams that are discarded due to IP 222 * header errors. 223 * 224 * @rmac_drop_ip: Count of received IP datagrams that could not be passed to the 225 * host because of 1) Random Early Discard (RED); 2) Frame steering algorithm 226 * found no available queue; 3) Receive ingress buffer overflow. 227 * @rmac_icmp: Count of received ICMP messages. Includes errored ICMP messages 228 * (due to ICMP checksum fail). 229 * 230 * @reserved_8: Reserved. 231 * @rmac_tcp: Count of received TCP segments. Since Xena is unaware of 232 * connection context, counts all received TCP segments, regardless of whether 233 * or not they pertain to an established connection. 234 * 235 * @rmac_udp: Count of received UDP datagrams. 236 * @rmac_err_drp_udp: Count of received UDP datagrams that were not delivered to 237 * the system because of 1) Random Early Discard (RED); 2) Frame steering 238 * algorithm found no available queue; 3) Receive ingress buffer overflow. 239 * 240 * @rmac_xgmii_err_sym: Count of the number of symbol errors in the received 241 * XGMII data (i.e. PHY indicates "Receive Error" on the XGMII). Only includes 242 * symbol errors that are observed between the XGMII Start Frame Delimiter 243 * and End Frame Delimiter, inclusive. And only increments the count by one for 244 * each frame. 245 * 246 * @rmac_frms_q0: Count of number of frames that pass through queue 0 of receive 247 * buffer. 248 * @rmac_frms_q1: Count of number of frames that pass through queue 1 of receive 249 * buffer. 250 * @rmac_frms_q2: Count of number of frames that pass through queue 2 of receive 251 * buffer. 252 * @rmac_frms_q3: Count of number of frames that pass through queue 3 of receive 253 * buffer. 254 * @rmac_frms_q4: Count of number of frames that pass through queue 4 of receive 255 * buffer. 256 * @rmac_frms_q5: Count of number of frames that pass through queue 5 of receive 257 * buffer. 258 * @rmac_frms_q6: Count of number of frames that pass through queue 6 of receive 259 * buffer. 260 * @rmac_frms_q7: Count of number of frames that pass through queue 7 of receive 261 * buffer. 262 * @rmac_full_q0: Count of number of times that receive buffer queue 0 has 263 * filled up. If a queue is size 0, then this stat is incremented to a value of 264 * 1 when MAC receives its first frame. 265 * 266 * @rmac_full_q1: Count of number of times that receive buffer queue 1 has 267 * filled up. If a queue is size 0, then this stat is incremented to a value of 268 * 1 when MAC receives its first frame. 269 * 270 * @rmac_full_q2: Count of number of times that receive buffer queue 2 has 271 * filled up. If a queue is size 0, then this stat is incremented to a value of 272 * 1 when MAC receives its first frame. 273 * 274 * @rmac_full_q3: Count of number of times that receive buffer queue 3 has 275 * filled up. If a queue is size 0, then this stat is incremented to a value of 276 * 1 when MAC receives its first frame. 277 * 278 * @rmac_full_q4: Count of number of times that receive buffer queue 4 has 279 * filled up. If a queue is size 0, then this stat is incremented to a value of 280 * 1 when MAC receives its first frame. 281 * 282 * @rmac_full_q5: Count of number of times that receive buffer queue 5 has 283 * filled up. If a queue is size 0, then this stat is incremented to a value of 284 * 1 when MAC receives its first frame. 285 * 286 * @rmac_full_q6: Count of number of times that receive buffer queue 6 has 287 * filled up. If a queue is size 0, then this stat is incremented to a value of 288 * 1 when MAC receives its first frame. 289 * 290 * @rmac_full_q7: Count of number of times that receive buffer queue 7 has 291 * filled up. If a queue is size 0, then this stat is incremented to a value of 292 * 1 when MAC receives its first frame. 293 * 294 * @rmac_pause_cnt: Count of number of pause quanta that the MAC has been in the 295 * paused state. Recall, one pause quantum equates to 512 bit times. 296 * @reserved_9: Reserved. 297 * @rmac_xgmii_data_err_cnt: This counter is incremented when either 1) The 298 * Reconcilliation Sublayer (RS) is expecting one control character and gets 299 * another (i.e. expecting Start control character and gets another control 300 * character); 2) Start control character is not in lane 0 or lane 4; 3) The RS 301 * gets a Start control character, but the start frame delimiter is not found in 302 * the correct location. 303 * @rmac_xgmii_ctrl_err_cnt: Maintains a count of unexpected or 304 * misplaced control characters occuring outside of normal data transmission 305 * (i.e. not included in RMAC_XGMII_DATA_ERR_CNT). 306 * 307 * @rmac_accepted_ip: Count of received IP datagrams that were passed to the 308 * system. 309 * 310 * @rmac_err_tcp: Count of received TCP segments containing errors. For example, 311 * bad TCP checksum. 312 * 313 * PCI (bus) Statistics: 314 * @rd_req_cnt: Counts the total number of read requests made by the device. 315 * @new_rd_req_cnt: Counts the requests made for a new read sequence (request 316 * made for the same sequence after a retry or disconnect response are not 317 * counted). 318 * @new_rd_req_rtry_cnt: Counts the Retry responses received on the start of 319 * the new read sequences. 320 * @rd_rtry_cnt: Counts the Retry responses received for read requests. 321 * @wr_rtry_rd_ack_cnt: Increments whenever a read request is accepted by 322 * the target after a write request was terminated with retry. 323 * @wr_req_cnt: Counts the total number of Write requests made by the device. 324 * @new_wr_req_cnt: Counts the requests made for a new write sequence (request 325 * made for the same sequence after a retry or disconnect response are not 326 * counted). 327 * @new_wr_req_rtry_cnt: Counts the requests made for a new write sequence 328 * (request made for the same sequence after a retry or disconnect response are 329 * not counted). 330 * 331 * @wr_rtry_cnt: Counts the Retry responses received for write requests. 332 * @wr_disc_cnt: Write Disconnect. Counts the target initiated disconnects 333 * on write transactions. 334 * @rd_rtry_wr_ack_cnt: Increments whenever a write request is accepted by the 335 * target after a read request was terminated with retry. 336 * 337 * @txp_wr_cnt: Counts the host write transactions to the Tx Pointer 338 * FIFOs. 339 * @txd_rd_cnt: Count of the Transmit Descriptor (TxD) read requests. 340 * @txd_wr_cnt: Count of the TxD write requests. 341 * @rxd_rd_cnt: Count of the Receive Descriptor (RxD) read requests. 342 * @rxd_wr_cnt: Count of the RxD write requests. 343 * @txf_rd_cnt: Count of transmit frame read requests. This will not 344 * equal the number of frames transmitted, as frame data is typically spread 345 * across multiple PCI transactions. 346 * @rxf_wr_cnt: Count of receive frame write requests. 347 * 348 * @tmac_frms_oflow: tbd 349 * @tmac_data_octets_oflow: tbd 350 * @tmac_mcst_frms_oflow: tbd 351 * @tmac_bcst_frms_oflow: tbd 352 * @tmac_ttl_octets_oflow: tbd 353 * @tmac_ucst_frms_oflow: tbd 354 * @tmac_nucst_frms_oflow: tbd 355 * @tmac_any_err_frms_oflow: tbd 356 * @tmac_vlan_frms: tbd 357 * @tmac_vld_ip_oflow: tbd 358 * @tmac_drop_ip_oflow: tbd 359 * @tmac_icmp_oflow: tbd 360 * @tmac_rst_tcp_oflow: tbd 361 * @tmac_udp_oflow: tbd 362 * @tpa_unknown_protocol: tbd 363 * @tpa_parse_failure: tbd 364 * @rmac_vld_frms_oflow: tbd 365 * @rmac_data_octets_oflow: tbd 366 * @rmac_vld_mcst_frms_oflow: tbd 367 * @rmac_vld_bcst_frms_oflow: tbd 368 * @rmac_ttl_octets_oflow: tbd 369 * @rmac_accepted_ucst_frms_oflow: tbd 370 * @rmac_accepted_nucst_frms_oflow: tbd 371 * @rmac_discarded_frms_oflow: tbd 372 * @rmac_drop_events_oflow: tbd 373 * @rmac_usized_frms_oflow: tbd 374 * @rmac_osized_frms_oflow: tbd 375 * @rmac_frag_frms_oflow: tbd 376 * @rmac_jabber_frms_oflow: tbd 377 * @rmac_ip_oflow: tbd 378 * @rmac_drop_ip_oflow: tbd 379 * @rmac_icmp_oflow: tbd 380 * @rmac_udp_oflow: tbd 381 * @rmac_err_drp_udp_oflow: tbd 382 * @rmac_pause_cnt_oflow: tbd 383 * @rmac_ttl_1519_4095_frms: tbd 384 * @rmac_ttl_4096_8191_frms: tbd 385 * @rmac_ttl_8192_max_frms: tbd 386 * @rmac_ttl_gt_max_frms: tbd 387 * @rmac_osized_alt_frms: tbd 388 * @rmac_jabber_alt_frms: tbd 389 * @rmac_gt_max_alt_frms: tbd 390 * @rmac_vlan_frms: tbd 391 * @rmac_fcs_discard: tbd 392 * @rmac_len_discard: tbd 393 * @rmac_da_discard: tbd 394 * @rmac_pf_discard: tbd 395 * @rmac_rts_discard: tbd 396 * @rmac_red_discard: tbd 397 * @rmac_ingm_full_discard: tbd 398 * @rmac_accepted_ip_oflow: tbd 399 * @link_fault_cnt: TBD 400 * Xframe hardware statistics. 401 */ 402 typedef struct xge_hal_stats_hw_info_t { 403 #ifdef XGE_OS_HOST_BIG_ENDIAN 404 /* Tx MAC statistics counters. */ 405 u32 tmac_frms; 406 u32 tmac_data_octets; 407 u64 tmac_drop_frms; 408 u32 tmac_mcst_frms; 409 u32 tmac_bcst_frms; 410 u64 tmac_pause_ctrl_frms; 411 u32 tmac_ttl_octets; 412 u32 tmac_ucst_frms; 413 u32 tmac_nucst_frms; 414 u32 tmac_any_err_frms; 415 u64 tmac_ttl_less_fb_octets; 416 u64 tmac_vld_ip_octets; 417 u32 tmac_vld_ip; 418 u32 tmac_drop_ip; 419 u32 tmac_icmp; 420 u32 tmac_rst_tcp; 421 u64 tmac_tcp; 422 u32 tmac_udp; 423 u32 reserved_0; 424 425 /* Rx MAC Statistics counters. */ 426 u32 rmac_vld_frms; 427 u32 rmac_data_octets; 428 u64 rmac_fcs_err_frms; 429 u64 rmac_drop_frms; 430 u32 rmac_vld_mcst_frms; 431 u32 rmac_vld_bcst_frms; 432 u32 rmac_in_rng_len_err_frms; 433 u32 rmac_out_rng_len_err_frms; 434 u64 rmac_long_frms; 435 u64 rmac_pause_ctrl_frms; 436 u64 rmac_unsup_ctrl_frms; 437 u32 rmac_ttl_octets; 438 u32 rmac_accepted_ucst_frms; 439 u32 rmac_accepted_nucst_frms; 440 u32 rmac_discarded_frms; 441 u32 rmac_drop_events; 442 u32 reserved_1; 443 u64 rmac_ttl_less_fb_octets; 444 u64 rmac_ttl_frms; 445 u64 reserved_2; 446 u32 reserved_3; 447 u32 rmac_usized_frms; 448 u32 rmac_osized_frms; 449 u32 rmac_frag_frms; 450 u32 rmac_jabber_frms; 451 u32 reserved_4; 452 u64 rmac_ttl_64_frms; 453 u64 rmac_ttl_65_127_frms; 454 u64 reserved_5; 455 u64 rmac_ttl_128_255_frms; 456 u64 rmac_ttl_256_511_frms; 457 u64 reserved_6; 458 u64 rmac_ttl_512_1023_frms; 459 u64 rmac_ttl_1024_1518_frms; 460 u32 reserved_7; 461 u32 rmac_ip; 462 u64 rmac_ip_octets; 463 u32 rmac_hdr_err_ip; 464 u32 rmac_drop_ip; 465 u32 rmac_icmp; 466 u32 reserved_8; 467 u64 rmac_tcp; 468 u32 rmac_udp; 469 u32 rmac_err_drp_udp; 470 u64 rmac_xgmii_err_sym; 471 u64 rmac_frms_q0; 472 u64 rmac_frms_q1; 473 u64 rmac_frms_q2; 474 u64 rmac_frms_q3; 475 u64 rmac_frms_q4; 476 u64 rmac_frms_q5; 477 u64 rmac_frms_q6; 478 u64 rmac_frms_q7; 479 u16 rmac_full_q0; 480 u16 rmac_full_q1; 481 u16 rmac_full_q2; 482 u16 rmac_full_q3; 483 u16 rmac_full_q4; 484 u16 rmac_full_q5; 485 u16 rmac_full_q6; 486 u16 rmac_full_q7; 487 u32 rmac_pause_cnt; 488 u32 reserved_9; 489 u64 rmac_xgmii_data_err_cnt; 490 u64 rmac_xgmii_ctrl_err_cnt; 491 u32 rmac_accepted_ip; 492 u32 rmac_err_tcp; 493 494 /* PCI/PCI-X Read transaction statistics. */ 495 u32 rd_req_cnt; 496 u32 new_rd_req_cnt; 497 u32 new_rd_req_rtry_cnt; 498 u32 rd_rtry_cnt; 499 u32 wr_rtry_rd_ack_cnt; 500 501 /* PCI/PCI-X write transaction statistics. */ 502 u32 wr_req_cnt; 503 u32 new_wr_req_cnt; 504 u32 new_wr_req_rtry_cnt; 505 u32 wr_rtry_cnt; 506 u32 wr_disc_cnt; 507 u32 rd_rtry_wr_ack_cnt; 508 509 /* DMA Transaction statistics. */ 510 u32 txp_wr_cnt; 511 u32 txd_rd_cnt; 512 u32 txd_wr_cnt; 513 u32 rxd_rd_cnt; 514 u32 rxd_wr_cnt; 515 u32 txf_rd_cnt; 516 u32 rxf_wr_cnt; 517 518 /* Enhanced Herc statistics */ 519 u32 tmac_frms_oflow; 520 u32 tmac_data_octets_oflow; 521 u32 tmac_mcst_frms_oflow; 522 u32 tmac_bcst_frms_oflow; 523 u32 tmac_ttl_octets_oflow; 524 u32 tmac_ucst_frms_oflow; 525 u32 tmac_nucst_frms_oflow; 526 u32 tmac_any_err_frms_oflow; 527 u64 tmac_vlan_frms; 528 u32 tmac_vld_ip_oflow; 529 u32 tmac_drop_ip_oflow; 530 u32 tmac_icmp_oflow; 531 u32 tmac_rst_tcp_oflow; 532 u32 tmac_udp_oflow; 533 u32 tpa_unknown_protocol; 534 u32 tpa_parse_failure; 535 u32 reserved_10; 536 u32 rmac_vld_frms_oflow; 537 u32 rmac_data_octets_oflow; 538 u32 rmac_vld_mcst_frms_oflow; 539 u32 rmac_vld_bcst_frms_oflow; 540 u32 rmac_ttl_octets_oflow; 541 u32 rmac_accepted_ucst_frms_oflow; 542 u32 rmac_accepted_nucst_frms_oflow; 543 u32 rmac_discarded_frms_oflow; 544 u32 rmac_drop_events_oflow; 545 u32 rmac_usized_frms_oflow; 546 u32 rmac_osized_frms_oflow; 547 u32 rmac_frag_frms_oflow; 548 u32 rmac_jabber_frms_oflow; 549 u32 rmac_ip_oflow; 550 u32 rmac_drop_ip_oflow; 551 u32 rmac_icmp_oflow; 552 u32 rmac_udp_oflow; 553 u32 rmac_err_drp_udp_oflow; 554 u32 rmac_pause_cnt_oflow; 555 u32 reserved_11; 556 u64 rmac_ttl_1519_4095_frms; 557 u64 rmac_ttl_4096_8191_frms; 558 u64 rmac_ttl_8192_max_frms; 559 u64 rmac_ttl_gt_max_frms; 560 u64 rmac_osized_alt_frms; 561 u64 rmac_jabber_alt_frms; 562 u64 rmac_gt_max_alt_frms; 563 u64 rmac_vlan_frms; 564 u32 rmac_fcs_discard; 565 u32 rmac_len_discard; 566 u32 rmac_da_discard; 567 u32 rmac_pf_discard; 568 u32 rmac_rts_discard; 569 u32 rmac_wol_discard; 570 u32 rmac_red_discard; 571 u32 rmac_ingm_full_discard; 572 u32 rmac_accepted_ip_oflow; 573 u32 reserved_12; 574 u32 link_fault_cnt; 575 u32 reserved_13; 576 #else 577 /* Tx MAC statistics counters. */ 578 u32 tmac_data_octets; 579 u32 tmac_frms; 580 u64 tmac_drop_frms; 581 u32 tmac_bcst_frms; 582 u32 tmac_mcst_frms; 583 u64 tmac_pause_ctrl_frms; 584 u32 tmac_ucst_frms; 585 u32 tmac_ttl_octets; 586 u32 tmac_any_err_frms; 587 u32 tmac_nucst_frms; 588 u64 tmac_ttl_less_fb_octets; 589 u64 tmac_vld_ip_octets; 590 u32 tmac_drop_ip; 591 u32 tmac_vld_ip; 592 u32 tmac_rst_tcp; 593 u32 tmac_icmp; 594 u64 tmac_tcp; 595 u32 reserved_0; 596 u32 tmac_udp; 597 598 /* Rx MAC Statistics counters. */ 599 u32 rmac_data_octets; 600 u32 rmac_vld_frms; 601 u64 rmac_fcs_err_frms; 602 u64 rmac_drop_frms; 603 u32 rmac_vld_bcst_frms; 604 u32 rmac_vld_mcst_frms; 605 u32 rmac_out_rng_len_err_frms; 606 u32 rmac_in_rng_len_err_frms; 607 u64 rmac_long_frms; 608 u64 rmac_pause_ctrl_frms; 609 u64 rmac_unsup_ctrl_frms; 610 u32 rmac_accepted_ucst_frms; 611 u32 rmac_ttl_octets; 612 u32 rmac_discarded_frms; 613 u32 rmac_accepted_nucst_frms; 614 u32 reserved_1; 615 u32 rmac_drop_events; 616 u64 rmac_ttl_less_fb_octets; 617 u64 rmac_ttl_frms; 618 u64 reserved_2; 619 u32 rmac_usized_frms; 620 u32 reserved_3; 621 u32 rmac_frag_frms; 622 u32 rmac_osized_frms; 623 u32 reserved_4; 624 u32 rmac_jabber_frms; 625 u64 rmac_ttl_64_frms; 626 u64 rmac_ttl_65_127_frms; 627 u64 reserved_5; 628 u64 rmac_ttl_128_255_frms; 629 u64 rmac_ttl_256_511_frms; 630 u64 reserved_6; 631 u64 rmac_ttl_512_1023_frms; 632 u64 rmac_ttl_1024_1518_frms; 633 u32 rmac_ip; 634 u32 reserved_7; 635 u64 rmac_ip_octets; 636 u32 rmac_drop_ip; 637 u32 rmac_hdr_err_ip; 638 u32 reserved_8; 639 u32 rmac_icmp; 640 u64 rmac_tcp; 641 u32 rmac_err_drp_udp; 642 u32 rmac_udp; 643 u64 rmac_xgmii_err_sym; 644 u64 rmac_frms_q0; 645 u64 rmac_frms_q1; 646 u64 rmac_frms_q2; 647 u64 rmac_frms_q3; 648 u64 rmac_frms_q4; 649 u64 rmac_frms_q5; 650 u64 rmac_frms_q6; 651 u64 rmac_frms_q7; 652 u16 rmac_full_q3; 653 u16 rmac_full_q2; 654 u16 rmac_full_q1; 655 u16 rmac_full_q0; 656 u16 rmac_full_q7; 657 u16 rmac_full_q6; 658 u16 rmac_full_q5; 659 u16 rmac_full_q4; 660 u32 reserved_9; 661 u32 rmac_pause_cnt; 662 u64 rmac_xgmii_data_err_cnt; 663 u64 rmac_xgmii_ctrl_err_cnt; 664 u32 rmac_err_tcp; 665 u32 rmac_accepted_ip; 666 667 /* PCI/PCI-X Read transaction statistics. */ 668 u32 new_rd_req_cnt; 669 u32 rd_req_cnt; 670 u32 rd_rtry_cnt; 671 u32 new_rd_req_rtry_cnt; 672 673 /* PCI/PCI-X Write/Read transaction statistics. */ 674 u32 wr_req_cnt; 675 u32 wr_rtry_rd_ack_cnt; 676 u32 new_wr_req_rtry_cnt; 677 u32 new_wr_req_cnt; 678 u32 wr_disc_cnt; 679 u32 wr_rtry_cnt; 680 681 /* PCI/PCI-X Write / DMA Transaction statistics. */ 682 u32 txp_wr_cnt; 683 u32 rd_rtry_wr_ack_cnt; 684 u32 txd_wr_cnt; 685 u32 txd_rd_cnt; 686 u32 rxd_wr_cnt; 687 u32 rxd_rd_cnt; 688 u32 rxf_wr_cnt; 689 u32 txf_rd_cnt; 690 691 /* Enhanced Herc statistics */ 692 u32 tmac_data_octets_oflow; 693 u32 tmac_frms_oflow; 694 u32 tmac_bcst_frms_oflow; 695 u32 tmac_mcst_frms_oflow; 696 u32 tmac_ucst_frms_oflow; 697 u32 tmac_ttl_octets_oflow; 698 u32 tmac_any_err_frms_oflow; 699 u32 tmac_nucst_frms_oflow; 700 u64 tmac_vlan_frms; 701 u32 tmac_drop_ip_oflow; 702 u32 tmac_vld_ip_oflow; 703 u32 tmac_rst_tcp_oflow; 704 u32 tmac_icmp_oflow; 705 u32 tpa_unknown_protocol; 706 u32 tmac_udp_oflow; 707 u32 reserved_10; 708 u32 tpa_parse_failure; 709 u32 rmac_data_octets_oflow; 710 u32 rmac_vld_frms_oflow; 711 u32 rmac_vld_bcst_frms_oflow; 712 u32 rmac_vld_mcst_frms_oflow; 713 u32 rmac_accepted_ucst_frms_oflow; 714 u32 rmac_ttl_octets_oflow; 715 u32 rmac_discarded_frms_oflow; 716 u32 rmac_accepted_nucst_frms_oflow; 717 u32 rmac_usized_frms_oflow; 718 u32 rmac_drop_events_oflow; 719 u32 rmac_frag_frms_oflow; 720 u32 rmac_osized_frms_oflow; 721 u32 rmac_ip_oflow; 722 u32 rmac_jabber_frms_oflow; 723 u32 rmac_icmp_oflow; 724 u32 rmac_drop_ip_oflow; 725 u32 rmac_err_drp_udp_oflow; 726 u32 rmac_udp_oflow; 727 u32 reserved_11; 728 u32 rmac_pause_cnt_oflow; 729 u64 rmac_ttl_1519_4095_frms; 730 u64 rmac_ttl_4096_8191_frms; 731 u64 rmac_ttl_8192_max_frms; 732 u64 rmac_ttl_gt_max_frms; 733 u64 rmac_osized_alt_frms; 734 u64 rmac_jabber_alt_frms; 735 u64 rmac_gt_max_alt_frms; 736 u64 rmac_vlan_frms; 737 u32 rmac_len_discard; 738 u32 rmac_fcs_discard; 739 u32 rmac_pf_discard; 740 u32 rmac_da_discard; 741 u32 rmac_wol_discard; 742 u32 rmac_rts_discard; 743 u32 rmac_ingm_full_discard; 744 u32 rmac_red_discard; 745 u32 reserved_12; 746 u32 rmac_accepted_ip_oflow; 747 u32 reserved_13; 748 u32 link_fault_cnt; 749 #endif 750 } xge_hal_stats_hw_info_t; 751 752 /** 753 * struct xge_hal_stats_channel_into_t - HAL channel statistics. 754 * @out_of_dtrs_cnt: Number of times caller failed to reserve descriptors, 755 * that is, number of xge_hal_fifo/ring_dtr_reserve failures. 756 * @reserve_free_swaps_cnt: Reserve/free swap counter. Internal usage. 757 * @max_compl_per_intr_cnt: Maximum number of completions per interrupt. 758 * @avg_compl_per_intr_cnt: Average number of completions per interrupt. 759 * Note that a total number of completed descriptors 760 * for the given channel can be calculated as 761 * (@traffic_intr_cnt * @avg_compl_per_intr_cnt). 762 * @total_compl_cnt: Total completion count. 763 * @total_compl_cnt == (@traffic_intr_cnt * @avg_compl_per_intr_cnt). 764 * @total_posts: Total number of descriptor postings on the channel. 765 * Counts the number of xge_hal_ring_dtr_post() 766 * or xge_hal_fifo_dtr_post() calls by ULD, for ring and fifo 767 * channel, respectively. 768 * @total_posts_many: Total number of posts on the channel that involved 769 * more than one descriptor. Counts the number of 770 * xge_hal_fifo_dtr_post_many() calls performed by ULD. 771 * @total_buffers: Total number of buffers posted on the channel. 772 * @avg_buffers_per_post: Average number of buffers transferred in a single 773 * post operation. 774 * Calculated as @total_buffers/@total_posts. 775 * @avg_buffer_size: Average buffer size transferred by a single post 776 * operation on a fifo channel. The counter is not supported for a ring 777 * channel. Calculated as a total number of transmitted octets divided 778 * by @total_buffers. 779 * @avg_post_size: Average amount of data transferred by a single post. 780 * Calculated as a total number of transmitted octets divided by 781 * @total_posts. 782 * @ring_bump_cnt: Ring "bump" count. Number of times the hardware could 783 * not post receive data (and had to continue keeping it on-board) 784 * because of unavailable receive descriptor(s). 785 * @total_posts_dtrs_many: Total number of posts on the channel that involving 786 * more than one descriptor. 787 * @total_posts_frags_many: Total number of fragments posted on the channel 788 * during post requests of multiple descriptors. 789 * @total_posts_dang_dtrs: Total number of posts on the channel involving 790 * dangling descriptors. 791 * @total_posts_dang_frags: Total number of dangling fragments posted on the channel 792 * during post request containing multiple descriptors. 793 * 794 * HAL channel counters. 795 * See also: xge_hal_stats_device_info_t{}. 796 */ 797 typedef struct xge_hal_stats_channel_info_t { 798 u32 full_cnt; 799 u32 usage_max; 800 u32 reserve_free_swaps_cnt; 801 u32 avg_compl_per_intr_cnt; 802 u32 total_compl_cnt; 803 u32 total_posts; 804 u32 total_posts_many; 805 u32 total_buffers; 806 u32 copied_frags; 807 u32 copied_buffers; 808 u32 avg_buffers_per_post; 809 u32 avg_buffer_size; 810 u32 avg_post_size; 811 u32 ring_bump_cnt; 812 u32 total_posts_dtrs_many; 813 u32 total_posts_frags_many; 814 u32 total_posts_dang_dtrs; 815 u32 total_posts_dang_frags; 816 } xge_hal_stats_channel_info_t; 817 818 /** 819 * struct xge_hal_xpak_counter_t - HAL xpak error counters 820 * @excess_temp: excess transceiver_temperature count 821 * @excess_bias_current: excess laser_bias_current count 822 * @excess_laser_output: excess laser_output_power count 823 * @tick_period: tick count for each cycle 824 */ 825 typedef struct xge_hal_xpak_counter_t { 826 u32 excess_temp; 827 u32 excess_bias_current; 828 u32 excess_laser_output; 829 u32 tick_period; 830 } xge_hal_xpak_counter_t; 831 832 /** 833 * struct xge_hal_stats_xpak_t - HAL xpak stats 834 * @alarm_transceiver_temp_high: alarm_transceiver_temp_high count value 835 * @alarm_transceiver_temp_low : alarm_transceiver_temp_low count value 836 * @alarm_laser_bias_current_high: alarm_laser_bias_current_high count value 837 * @alarm_laser_bias_current_low: alarm_laser_bias_current_low count value 838 * @alarm_laser_output_power_high: alarm_laser_output_power_high count value 839 * @alarm_laser_output_power_low: alarm_laser_output_power_low count value 840 * @warn_transceiver_temp_high: warn_transceiver_temp_high count value 841 * @warn_transceiver_temp_low: warn_transceiver_temp_low count value 842 * @warn_laser_bias_current_high: warn_laser_bias_current_high count value 843 * @warn_laser_bias_current_low: warn_laser_bias_current_low count value 844 * @warn_laser_output_power_high: warn_laser_output_power_high count value 845 * @warn_laser_output_power_low: warn_laser_output_power_low count value 846 */ 847 typedef struct xge_hal_stats_xpak_t { 848 u16 alarm_transceiver_temp_high; 849 u16 alarm_transceiver_temp_low; 850 u16 alarm_laser_bias_current_high; 851 u16 alarm_laser_bias_current_low; 852 u16 alarm_laser_output_power_high; 853 u16 alarm_laser_output_power_low; 854 u16 warn_transceiver_temp_high; 855 u16 warn_transceiver_temp_low; 856 u16 warn_laser_bias_current_high; 857 u16 warn_laser_bias_current_low; 858 u16 warn_laser_output_power_high; 859 u16 warn_laser_output_power_low; 860 } xge_hal_stats_xpak_t; 861 862 863 864 /** 865 * struct xge_hal_stats_sw_err_t - HAL device error statistics. 866 * @sm_err_cnt: TBD 867 * @single_ecc_err_cnt: TBD 868 * @double_ecc_err_cnt: TBD 869 * @ecc_err_cnt: ECC error count. 870 * @parity_err_cnt: Parity error count. 871 * @serr_cnt: Number of exceptions indicated to the host via PCI SERR#. 872 * @rxd_t_code_err_cnt: Array of receive transfer codes. The position 873 * (index) in this array reflects the transfer code type, for instance 874 * 0x7 - for "invalid receive buffer size", or 0x8 - for ECC. 875 * Value rxd_t_code_err_cnt[i] reflects the 876 * number of times the corresponding transfer code was encountered. 877 * 878 * @txd_t_code_err_cnt: Array of transmit transfer codes. The position 879 * (index) in this array reflects the transfer code type, for instance 880 * 0xA - "loss of link". 881 * Value txd_t_code_err_cnt[i] reflects the 882 * number of times the corresponding transfer code was encountered. 883 */ 884 typedef struct xge_hal_stats_sw_err_t { 885 u32 sm_err_cnt; 886 u32 single_ecc_err_cnt; 887 u32 double_ecc_err_cnt; 888 u32 ecc_err_cnt; 889 u32 parity_err_cnt; 890 u32 serr_cnt; 891 u32 rxd_t_code_err_cnt[16]; 892 u32 txd_t_code_err_cnt[16]; 893 xge_hal_stats_xpak_t stats_xpak; 894 xge_hal_xpak_counter_t xpak_counter; 895 } xge_hal_stats_sw_err_t; 896 897 /** 898 * struct xge_hal_stats_device_info_t - HAL own per-device statistics. 899 * 900 * @rx_traffic_intr_cnt: TBD 901 * @tx_traffic_intr_cnt: TBD 902 * @txpic_intr_cnt: TBD 903 * @txdma_intr_cnt: TBD 904 * @txmac_intr_cnt: TBD 905 * @txxgxs_intr_cnt: TBD 906 * @rxpic_intr_cnt: TBD 907 * @rxdma_intr_cnt: TBD 908 * @rxmac_intr_cnt: TBD 909 * @rxxgxs_intr_cnt: TBD 910 * @mc_intr_cnt: TBD 911 * @not_traffic_intr_cnt: Number of times the host was interrupted 912 * without new completions. 913 * "Non-traffic interrupt counter". 914 * @traffic_intr_cnt: Number of traffic interrupts for the device. 915 * @total_intr_cnt: Total number of traffic interrupts for the device. 916 * @total_intr_cnt == @traffic_intr_cnt + 917 * @not_traffic_intr_cnt 918 * @soft_reset_cnt: Number of times soft reset is done on this device. 919 * @rxufca_hi_adjust_cnt: TODO 920 * @rxufca_lo_adjust_cnt: TODO 921 * 922 * @tot_frms_lroised: TBD 923 * @tot_lro_sessions: TBD 924 * @lro_frm_len_exceed_cnt: TBD 925 * @lro_sg_exceed_cnt: TBD 926 * @lro_out_of_seq_pkt_cnt: TBD 927 * @lro_dup_pkt_cnt: TBD 928 * 929 * HAL per-device statistics. 930 * See also: xge_hal_stats_channel_info_t{}. 931 */ 932 typedef struct xge_hal_stats_device_info_t { 933 u32 rx_traffic_intr_cnt; 934 u32 tx_traffic_intr_cnt; 935 u32 txpic_intr_cnt; 936 u32 txdma_intr_cnt; 937 u32 txmac_intr_cnt; 938 u32 txxgxs_intr_cnt; 939 u32 rxpic_intr_cnt; 940 u32 rxdma_intr_cnt; 941 u32 rxmac_intr_cnt; 942 u32 rxxgxs_intr_cnt; 943 u32 mc_intr_cnt; 944 u32 not_traffic_intr_cnt; 945 u32 traffic_intr_cnt; 946 u32 total_intr_cnt; 947 u32 soft_reset_cnt; 948 u32 rxufca_hi_adjust_cnt; 949 u32 rxufca_lo_adjust_cnt; 950 u32 bimodal_hi_adjust_cnt; 951 u32 bimodal_lo_adjust_cnt; 952 #ifdef XGE_HAL_CONFIG_LRO 953 u32 tot_frms_lroised; 954 u32 tot_lro_sessions; 955 u32 lro_frm_len_exceed_cnt; 956 u32 lro_sg_exceed_cnt; 957 u32 lro_out_of_seq_pkt_cnt; 958 u32 lro_dup_pkt_cnt; 959 #endif 960 } xge_hal_stats_device_info_t; 961 962 /** 963 * struct xge_hal_stats_t - Contains HAL per-device statistics, 964 * including hw. 965 * @devh: HAL device handle. 966 * @dma_addr: DMA addres of the %hw_info. Given to device to fill-in the stats. 967 * @hw_info_dmah: DMA handle used to map hw statistics onto the device memory 968 * space. 969 * @hw_info_dma_acch: One more DMA handle used subsequently to free the 970 * DMA object. Note that this and the previous handle have 971 * physical meaning for Solaris; on Windows and Linux the 972 * corresponding value will be simply pointer to PCI device. 973 * 974 * @hw_info: Xframe statistics maintained by the hardware. 975 * @hw_info_saved: TBD 976 * @hw_info_latest: TBD 977 * @sw_dev_info_stats: HAL's "soft" device informational statistics, e.g. number 978 * of completions per interrupt. 979 * @sw_dev_err_stats: HAL's "soft" device error statistics. 980 * 981 * @is_initialized: True, if all the subordinate structures are allocated and 982 * initialized. 983 * @is_enabled: True, if device stats collection is enabled. 984 * 985 * Structure-container of HAL per-device statistics. Note that per-channel 986 * statistics are kept in separate structures under HAL's fifo and ring 987 * channels. 988 * See also: xge_hal_stats_hw_info_t{}, xge_hal_stats_sw_err_t{}, 989 * xge_hal_stats_device_info_t{}. 990 * See also: xge_hal_stats_channel_info_t{}. 991 */ 992 typedef struct xge_hal_stats_t { 993 /* handles */ 994 xge_hal_device_h devh; 995 dma_addr_t dma_addr; 996 pci_dma_h hw_info_dmah; 997 pci_dma_acc_h hw_info_dma_acch; 998 999 /* HAL device hardware statistics */ 1000 xge_hal_stats_hw_info_t *hw_info; 1001 xge_hal_stats_hw_info_t hw_info_saved; 1002 xge_hal_stats_hw_info_t hw_info_latest; 1003 1004 /* HAL device "soft" stats */ 1005 xge_hal_stats_sw_err_t sw_dev_err_stats; 1006 xge_hal_stats_device_info_t sw_dev_info_stats; 1007 1008 /* flags */ 1009 int is_initialized; 1010 int is_enabled; 1011 } xge_hal_stats_t; 1012 1013 /* ========================== STATS PRIVATE API ========================= */ 1014 1015 xge_hal_status_e __hal_stats_initialize(xge_hal_stats_t *stats, 1016 xge_hal_device_h devh); 1017 1018 void __hal_stats_terminate(xge_hal_stats_t *stats); 1019 1020 void __hal_stats_enable(xge_hal_stats_t *stats); 1021 1022 void __hal_stats_disable(xge_hal_stats_t *stats); 1023 1024 void __hal_stats_soft_reset(xge_hal_device_h devh, int reset_all); 1025 1026 /* ========================== STATS PUBLIC API ========================= */ 1027 1028 xge_hal_status_e xge_hal_stats_hw(xge_hal_device_h devh, 1029 xge_hal_stats_hw_info_t **hw_info); 1030 1031 xge_hal_status_e xge_hal_stats_device(xge_hal_device_h devh, 1032 xge_hal_stats_device_info_t **device_info); 1033 1034 xge_hal_status_e xge_hal_stats_channel(xge_hal_channel_h channelh, 1035 xge_hal_stats_channel_info_t **channel_info); 1036 1037 xge_hal_status_e xge_hal_stats_reset(xge_hal_device_h devh); 1038 1039 __EXTERN_END_DECLS 1040 1041 #endif /* XGE_HAL_STATS_H */ 1042