1a23fd118Syl /* 2a23fd118Syl * CDDL HEADER START 3a23fd118Syl * 4a23fd118Syl * The contents of this file are subject to the terms of the 5a23fd118Syl * Common Development and Distribution License (the "License"). 6a23fd118Syl * You may not use this file except in compliance with the License. 7a23fd118Syl * 8a23fd118Syl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9a23fd118Syl * or http://www.opensolaris.org/os/licensing. 10a23fd118Syl * See the License for the specific language governing permissions 11a23fd118Syl * and limitations under the License. 12a23fd118Syl * 13a23fd118Syl * When distributing Covered Code, include this CDDL HEADER in each 14a23fd118Syl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15a23fd118Syl * If applicable, add the following below this CDDL HEADER, with the 16a23fd118Syl * fields enclosed by brackets "[]" replaced with your own identifying 17a23fd118Syl * information: Portions Copyright [yyyy] [name of copyright owner] 18a23fd118Syl * 19a23fd118Syl * CDDL HEADER END 20a23fd118Syl */ 21a23fd118Syl 22a23fd118Syl /* 23*0dc2366fSVenugopal Iyer * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24a23fd118Syl * Use is subject to license terms. 25a23fd118Syl */ 26a23fd118Syl 27a23fd118Syl /* 28a23fd118Syl * Copyright (c) 2002-2005 Neterion, Inc. 29a23fd118Syl * All right Reserved. 30a23fd118Syl * 31a23fd118Syl * FileName : xgell.h 32a23fd118Syl * 33a23fd118Syl * Description: Link Layer driver declaration 34a23fd118Syl * 35a23fd118Syl */ 36a23fd118Syl 37a23fd118Syl #ifndef _SYS_XGELL_H 38a23fd118Syl #define _SYS_XGELL_H 39a23fd118Syl 40a23fd118Syl #include <sys/types.h> 41a23fd118Syl #include <sys/errno.h> 42a23fd118Syl #include <sys/param.h> 43a23fd118Syl #include <sys/stropts.h> 44a23fd118Syl #include <sys/stream.h> 45a23fd118Syl #include <sys/strsubr.h> 46a23fd118Syl #include <sys/kmem.h> 47a23fd118Syl #include <sys/conf.h> 48a23fd118Syl #include <sys/devops.h> 49a23fd118Syl #include <sys/ksynch.h> 50a23fd118Syl #include <sys/stat.h> 51a23fd118Syl #include <sys/modctl.h> 52a23fd118Syl #include <sys/debug.h> 53a23fd118Syl #include <sys/pci.h> 54a23fd118Syl #include <sys/ethernet.h> 55a23fd118Syl #include <sys/vlan.h> 56a23fd118Syl #include <sys/dlpi.h> 57a23fd118Syl #include <sys/taskq.h> 58a23fd118Syl #include <sys/cyclic.h> 59a23fd118Syl 60a23fd118Syl #include <sys/pattr.h> 61a23fd118Syl #include <sys/strsun.h> 62a23fd118Syl 63da14cebeSEric Cheng #include <sys/mac_provider.h> 64ba2e4443Sseb #include <sys/mac_ether.h> 65a23fd118Syl 66a23fd118Syl #ifdef __cplusplus 67a23fd118Syl extern "C" { 68a23fd118Syl #endif 69a23fd118Syl 7019397407SSherry Moore #define XGELL_DESC "Xframe I/II 10Gb Ethernet" 71a23fd118Syl #define XGELL_IFNAME "xge" 72a23fd118Syl 73a23fd118Syl #include <xgehal.h> 74a23fd118Syl 757eced415Sxw /* 767eced415Sxw * The definition of XGELL_RX_BUFFER_RECYCLE_CACHE is an experimental value. 777eced415Sxw * With this value, the lock contention between xgell_rx_buffer_recycle() 787eced415Sxw * and xgell_rx_1b_compl() is reduced to great extent. And multiple rx rings 797eced415Sxw * alleviate the lock contention further since each rx ring has its own mutex. 807eced415Sxw */ 817eced415Sxw #define XGELL_RX_BUFFER_RECYCLE_CACHE XGE_HAL_RING_RXDS_PER_BLOCK(1) * 2 827eced415Sxw #define MSG_SIZE 64 837eced415Sxw 848347601bSyl /* 858347601bSyl * These default values can be overridden by vaules in xge.conf. 868347601bSyl * In xge.conf user has to specify actual (not percentages) values. 878347601bSyl */ 888347601bSyl #define XGELL_RX_BUFFER_TOTAL XGE_HAL_RING_RXDS_PER_BLOCK(1) * 6 898347601bSyl #define XGELL_RX_BUFFER_POST_HIWAT XGE_HAL_RING_RXDS_PER_BLOCK(1) * 5 90a23fd118Syl 91da14cebeSEric Cheng /* 92da14cebeSEric Cheng * Multiple rings configuration 93da14cebeSEric Cheng */ 94da14cebeSEric Cheng #define XGELL_RX_RING_MAIN 0 95da14cebeSEric Cheng #define XGELL_TX_RING_MAIN 0 96da14cebeSEric Cheng 97da14cebeSEric Cheng #define XGELL_RX_RING_NUM_MIN 1 98da14cebeSEric Cheng #define XGELL_TX_RING_NUM_MIN 1 99da14cebeSEric Cheng #define XGELL_RX_RING_NUM_MAX 8 100da14cebeSEric Cheng #define XGELL_TX_RING_NUM_MAX 1 /* TODO */ 101da14cebeSEric Cheng #define XGELL_RX_RING_NUM_DEFAULT XGELL_RX_RING_NUM_MAX 102da14cebeSEric Cheng #define XGELL_TX_RING_NUM_DEFAULT XGELL_TX_RING_NUM_MAX 103da14cebeSEric Cheng 104da14cebeSEric Cheng #define XGELL_MINTR_NUM_MIN 1 105da14cebeSEric Cheng #define XGELL_MINTR_NUM_MAX \ 106da14cebeSEric Cheng (XGELL_RX_RING_NUM_MAX + XGELL_TX_RING_NUM_MAX + 1) 107da14cebeSEric Cheng #define XGELL_MINTR_NUM_DEFAULT XGELL_MINTR_NUM_MAX 108da14cebeSEric Cheng 109da14cebeSEric Cheng #define XGELL_CONF_GROUP_POLICY_BASIC 0 110da14cebeSEric Cheng #define XGELL_CONF_GROUP_POLICY_VIRT 1 111da14cebeSEric Cheng #define XGELL_CONF_GROUP_POLICY_PERF 2 112da14cebeSEric Cheng #if 0 113da14cebeSEric Cheng #if defined(__sparc) 114da14cebeSEric Cheng #define XGELL_CONF_GROUP_POLICY_DEFAULT XGELL_CONF_GROUP_POLICY_PERF 115da14cebeSEric Cheng #else 116da14cebeSEric Cheng #define XGELL_CONF_GROUP_POLICY_DEFAULT XGELL_CONF_GROUP_POLICY_VIRT 117da14cebeSEric Cheng #endif 118da14cebeSEric Cheng #else 119da14cebeSEric Cheng /* 120da14cebeSEric Cheng * The _PERF configuration enable a fat group of all rx rings, as approachs 121da14cebeSEric Cheng * better fanout performance of the primary interface. 122da14cebeSEric Cheng */ 123da14cebeSEric Cheng #define XGELL_CONF_GROUP_POLICY_DEFAULT XGELL_CONF_GROUP_POLICY_PERF 124da14cebeSEric Cheng #endif 125a23fd118Syl 126da14cebeSEric Cheng #define XGELL_TX_LEVEL_LOW 8 127da14cebeSEric Cheng #define XGELL_TX_LEVEL_HIGH 32 128da14cebeSEric Cheng #define XGELL_TX_LEVEL_CHECK 3 129da14cebeSEric Cheng #define XGELL_MAX_RING_DEFAULT 8 130da14cebeSEric Cheng #define XGELL_MAX_FIFO_DEFAULT 1 131a23fd118Syl 132da14cebeSEric Cheng /* Control driver to copy or DMA inbound/outbound packets */ 133da14cebeSEric Cheng #if defined(__sparc) 134da14cebeSEric Cheng #define XGELL_RX_DMA_LOWAT 256 135da14cebeSEric Cheng #define XGELL_TX_DMA_LOWAT 512 1368347601bSyl #else 137da14cebeSEric Cheng #define XGELL_RX_DMA_LOWAT 256 138da14cebeSEric Cheng #define XGELL_TX_DMA_LOWAT 128 1398347601bSyl #endif 1408347601bSyl 1418347601bSyl /* 1428347601bSyl * Try to collapse up to XGELL_RX_PKT_BURST packets into single mblk 1438347601bSyl * sequence before mac_rx() is called. 1448347601bSyl */ 145da14cebeSEric Cheng #define XGELL_RX_PKT_BURST 32 1468347601bSyl 147a23fd118Syl /* About 1s */ 148da14cebeSEric Cheng #define XGE_DEV_POLL_TICKS drv_usectohz(1000000) 149a23fd118Syl 1508347601bSyl #define XGELL_LSO_MAXLEN 65535 1518347601bSyl #define XGELL_CONF_ENABLE_BY_DEFAULT 1 1528347601bSyl #define XGELL_CONF_DISABLE_BY_DEFAULT 0 1538347601bSyl 1548347601bSyl /* LRO configuration */ 1557eced415Sxw #define XGE_HAL_DEFAULT_LRO_SG_SIZE 2 /* <=2 LRO fix not required */ 1568347601bSyl #define XGE_HAL_DEFAULT_LRO_FRM_LEN 65535 1578347601bSyl 158a23fd118Syl /* 1597eced415Sxw * Default values for tunables used in HAL. Please refer to xgehal-config.h 1607eced415Sxw * for more details. 161a23fd118Syl */ 162a23fd118Syl #define XGE_HAL_DEFAULT_USE_HARDCODE -1 163a23fd118Syl 1647eced415Sxw /* Bimodal adaptive schema defaults - ENABLED */ 1658347601bSyl #define XGE_HAL_DEFAULT_BIMODAL_INTERRUPTS -1 1668347601bSyl #define XGE_HAL_DEFAULT_BIMODAL_TIMER_LO_US 24 1678347601bSyl #define XGE_HAL_DEFAULT_BIMODAL_TIMER_HI_US 256 1688347601bSyl 1697eced415Sxw /* Interrupt moderation/utilization defaults */ 1708347601bSyl #define XGE_HAL_DEFAULT_TX_URANGE_A 5 1718347601bSyl #define XGE_HAL_DEFAULT_TX_URANGE_B 15 1728347601bSyl #define XGE_HAL_DEFAULT_TX_URANGE_C 30 1738347601bSyl #define XGE_HAL_DEFAULT_TX_UFC_A 15 1748347601bSyl #define XGE_HAL_DEFAULT_TX_UFC_B 30 1758347601bSyl #define XGE_HAL_DEFAULT_TX_UFC_C 45 1768347601bSyl #define XGE_HAL_DEFAULT_TX_UFC_D 60 177a23fd118Syl #define XGE_HAL_DEFAULT_TX_TIMER_CI_EN 1 178a23fd118Syl #define XGE_HAL_DEFAULT_TX_TIMER_AC_EN 1 1798347601bSyl #define XGE_HAL_DEFAULT_TX_TIMER_VAL 10000 1808347601bSyl #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_B 512 /* bimodal */ 1818347601bSyl #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_N 256 /* normal UFC */ 182a23fd118Syl #define XGE_HAL_DEFAULT_RX_URANGE_A 10 1838347601bSyl #define XGE_HAL_DEFAULT_RX_URANGE_B 30 184a23fd118Syl #define XGE_HAL_DEFAULT_RX_URANGE_C 50 1858347601bSyl #define XGE_HAL_DEFAULT_RX_UFC_A 1 1868347601bSyl #define XGE_HAL_DEFAULT_RX_UFC_B_J 2 1878347601bSyl #define XGE_HAL_DEFAULT_RX_UFC_B_N 8 1888347601bSyl #define XGE_HAL_DEFAULT_RX_UFC_C_J 4 1898347601bSyl #define XGE_HAL_DEFAULT_RX_UFC_C_N 16 1908347601bSyl #define XGE_HAL_DEFAULT_RX_UFC_D 32 191a23fd118Syl #define XGE_HAL_DEFAULT_RX_TIMER_AC_EN 1 1928347601bSyl #define XGE_HAL_DEFAULT_RX_TIMER_VAL 384 193a23fd118Syl 194da14cebeSEric Cheng #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_A 1024 195a23fd118Syl #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_J 2048 196a23fd118Syl #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_N 4096 197a23fd118Syl #define XGE_HAL_DEFAULT_FIFO_QUEUE_INTR 0 198a23fd118Syl #define XGE_HAL_DEFAULT_FIFO_RESERVE_THRESHOLD 0 199a23fd118Syl #define XGE_HAL_DEFAULT_FIFO_MEMBLOCK_SIZE PAGESIZE 200a23fd118Syl 2018347601bSyl /* 2027eced415Sxw * This will force HAL to allocate extra copied buffer per TXDL which 2038347601bSyl * size calculated by formula: 2048347601bSyl * 2058347601bSyl * (ALIGNMENT_SIZE * ALIGNED_FRAGS) 2068347601bSyl */ 2078347601bSyl #define XGE_HAL_DEFAULT_FIFO_ALIGNMENT_SIZE 4096 208a23fd118Syl #define XGE_HAL_DEFAULT_FIFO_MAX_ALIGNED_FRAGS 1 209da14cebeSEric Cheng #if defined(__sparc) 2108347601bSyl #define XGE_HAL_DEFAULT_FIFO_FRAGS 64 211da14cebeSEric Cheng #else 212da14cebeSEric Cheng #define XGE_HAL_DEFAULT_FIFO_FRAGS 128 213a23fd118Syl #endif 2148347601bSyl #define XGE_HAL_DEFAULT_FIFO_FRAGS_THRESHOLD 18 215a23fd118Syl 216da14cebeSEric Cheng #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS 2 217a23fd118Syl #define XGE_HAL_RING_QUEUE_BUFFER_MODE_DEFAULT 1 2188347601bSyl #define XGE_HAL_DEFAULT_BACKOFF_INTERVAL_US 64 219a23fd118Syl #define XGE_HAL_DEFAULT_RING_PRIORITY 0 220a23fd118Syl #define XGE_HAL_DEFAULT_RING_MEMBLOCK_SIZE PAGESIZE 221a23fd118Syl 222a23fd118Syl #define XGE_HAL_DEFAULT_RING_NUM 8 223a23fd118Syl #define XGE_HAL_DEFAULT_TMAC_UTIL_PERIOD 5 224a23fd118Syl #define XGE_HAL_DEFAULT_RMAC_UTIL_PERIOD 5 225a23fd118Syl #define XGE_HAL_DEFAULT_RMAC_HIGH_PTIME 65535 226a23fd118Syl #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q0Q3 187 227a23fd118Syl #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q4Q7 187 2288347601bSyl #define XGE_HAL_DEFAULT_RMAC_PAUSE_GEN_EN 1 2298347601bSyl #define XGE_HAL_DEFAULT_RMAC_PAUSE_GEN_DIS 0 2308347601bSyl #define XGE_HAL_DEFAULT_RMAC_PAUSE_RCV_EN 1 2318347601bSyl #define XGE_HAL_DEFAULT_RMAC_PAUSE_RCV_DIS 0 232a23fd118Syl #define XGE_HAL_DEFAULT_INITIAL_MTU XGE_HAL_DEFAULT_MTU /* 1500 */ 2338347601bSyl #define XGE_HAL_DEFAULT_ISR_POLLING_CNT 0 234a23fd118Syl #define XGE_HAL_DEFAULT_LATENCY_TIMER 255 2357eced415Sxw #define XGE_HAL_DEFAULT_SHARED_SPLITS 0 236a23fd118Syl #define XGE_HAL_DEFAULT_STATS_REFRESH_TIME 1 237a23fd118Syl 2387eced415Sxw #if defined(__sparc) 239da14cebeSEric Cheng #define XGE_HAL_DEFAULT_MMRB_COUNT XGE_HAL_MAX_MMRB_COUNT 240da14cebeSEric Cheng #define XGE_HAL_DEFAULT_SPLIT_TRANSACTION XGE_HAL_EIGHT_SPLIT_TRANSACTION 2417eced415Sxw #else 2427eced415Sxw #define XGE_HAL_DEFAULT_MMRB_COUNT 1 /* 1k */ 243da14cebeSEric Cheng #define XGE_HAL_DEFAULT_SPLIT_TRANSACTION XGE_HAL_TWO_SPLIT_TRANSACTION 2447eced415Sxw #endif 2457eced415Sxw 246a23fd118Syl /* 247da14cebeSEric Cheng * Default the size of buffers allocated for ndd interface functions 248a23fd118Syl */ 2497eced415Sxw #define XGELL_STATS_BUFSIZE 8192 250a23fd118Syl #define XGELL_PCICONF_BUFSIZE 2048 251a23fd118Syl #define XGELL_ABOUT_BUFSIZE 512 252a23fd118Syl #define XGELL_IOCTL_BUFSIZE 64 2537eced415Sxw #define XGELL_DEVCONF_BUFSIZE 8192 254a23fd118Syl 255a23fd118Syl /* 256da14cebeSEric Cheng * Multiple mac address definitions 257a23fd118Syl * 258da14cebeSEric Cheng * We'll use whole MAC Addresses Configuration Memory for unicast addresses, 259da14cebeSEric Cheng * since current multicast implementation in HAL is by enabling promise mode. 260a23fd118Syl */ 261da14cebeSEric Cheng #define XGE_RX_MULTI_MAC_ADDRESSES_MAX 8 /* per ring group */ 262a23fd118Syl 263a23fd118Syl typedef struct { 2648347601bSyl int rx_pkt_burst; 265a23fd118Syl int rx_buffer_total; 266a23fd118Syl int rx_buffer_post_hiwat; 2678347601bSyl int rx_dma_lowat; 2688347601bSyl int tx_dma_lowat; 2698347601bSyl int lso_enable; 270da14cebeSEric Cheng int msix_enable; 271da14cebeSEric Cheng int grouping; 272a23fd118Syl } xgell_config_t; 273a23fd118Syl 274da14cebeSEric Cheng typedef struct xgell_multi_mac xgell_multi_mac_t; 275da14cebeSEric Cheng typedef struct xgell_rx_ring xgell_rx_ring_t; 276da14cebeSEric Cheng typedef struct xgell_tx_ring xgell_tx_ring_t; 277da14cebeSEric Cheng typedef struct xgelldev xgelldev_t; 2787eced415Sxw 279a23fd118Syl typedef struct xgell_rx_buffer_t { 280da14cebeSEric Cheng struct xgell_rx_buffer_t *next; 281da14cebeSEric Cheng void *vaddr; 282da14cebeSEric Cheng dma_addr_t dma_addr; 283da14cebeSEric Cheng ddi_dma_handle_t dma_handle; 284da14cebeSEric Cheng ddi_acc_handle_t dma_acch; 285da14cebeSEric Cheng xgell_rx_ring_t *ring; 286da14cebeSEric Cheng frtn_t frtn; 287a23fd118Syl } xgell_rx_buffer_t; 288a23fd118Syl 289da14cebeSEric Cheng /* Buffer pool for one rx ring */ 290a23fd118Syl typedef struct xgell_rx_buffer_pool_t { 291a23fd118Syl uint_t total; /* total buffers */ 292a23fd118Syl uint_t size; /* buffer size */ 293a23fd118Syl xgell_rx_buffer_t *head; /* header pointer */ 294a23fd118Syl uint_t free; /* free buffers */ 295a23fd118Syl uint_t post; /* posted buffers */ 296a23fd118Syl uint_t post_hiwat; /* hiwat to stop post */ 297a23fd118Syl spinlock_t pool_lock; /* buffer pool lock */ 298da14cebeSEric Cheng boolean_t live; /* pool status */ 2997eced415Sxw xgell_rx_buffer_t *recycle_head; /* recycle list's head */ 3007eced415Sxw xgell_rx_buffer_t *recycle_tail; /* recycle list's tail */ 3017eced415Sxw uint_t recycle; /* # of rx buffers recycled */ 3027eced415Sxw spinlock_t recycle_lock; /* buffer recycle lock */ 303a23fd118Syl } xgell_rx_buffer_pool_t; 304a23fd118Syl 305da14cebeSEric Cheng struct xgell_multi_mac { 306da14cebeSEric Cheng int naddr; /* total supported addresses */ 307da14cebeSEric Cheng int naddrfree; /* free addresses slots */ 308da14cebeSEric Cheng ether_addr_t mac_addr[XGE_RX_MULTI_MAC_ADDRESSES_MAX]; 309da14cebeSEric Cheng boolean_t mac_addr_set[XGE_RX_MULTI_MAC_ADDRESSES_MAX]; 310da14cebeSEric Cheng }; 311ba2e4443Sseb 312da14cebeSEric Cheng typedef uint_t (*intr_func_t)(caddr_t, caddr_t); 313da14cebeSEric Cheng 314da14cebeSEric Cheng typedef struct xgell_intr { 315da14cebeSEric Cheng uint_t index; 316da14cebeSEric Cheng ddi_intr_handle_t *handle; /* DDI interrupt handle */ 317da14cebeSEric Cheng intr_func_t *function; /* interrupt function */ 318da14cebeSEric Cheng caddr_t arg; /* interrupt source */ 319da14cebeSEric Cheng } xgell_intr_t; 320da14cebeSEric Cheng 321da14cebeSEric Cheng struct xgell_rx_ring { 322da14cebeSEric Cheng int index; 323da14cebeSEric Cheng boolean_t live; /* ring active status */ 324da14cebeSEric Cheng xge_hal_channel_h channelh; /* hardware channel */ 325da14cebeSEric Cheng xgelldev_t *lldev; /* driver device */ 326da14cebeSEric Cheng mac_ring_handle_t ring_handle; /* call back ring handle */ 327da14cebeSEric Cheng mac_group_handle_t group_handle; /* call back group handle */ 328da14cebeSEric Cheng uint64_t ring_gen_num; 329da14cebeSEric Cheng 330da14cebeSEric Cheng xgell_multi_mac_t mmac; /* per group multiple addrs */ 331da14cebeSEric Cheng xgell_rx_buffer_pool_t bf_pool; /* per ring buffer pool */ 332*0dc2366fSVenugopal Iyer uint64_t rx_pkts; /* total received packets */ 333*0dc2366fSVenugopal Iyer uint64_t rx_bytes; /* total received bytes */ 334da14cebeSEric Cheng int poll_bytes; /* bytes to be polled up */ 335da14cebeSEric Cheng int polled_bytes; /* total polled bytes */ 336da14cebeSEric Cheng mblk_t *poll_mp; /* polled messages */ 337da14cebeSEric Cheng 338da14cebeSEric Cheng spinlock_t ring_lock; /* per ring lock */ 3397eced415Sxw }; 3407eced415Sxw 341da14cebeSEric Cheng struct xgell_tx_ring { 342da14cebeSEric Cheng int index; 343da14cebeSEric Cheng boolean_t live; /* ring active status */ 344da14cebeSEric Cheng xge_hal_channel_h channelh; /* hardware channel */ 345da14cebeSEric Cheng xgelldev_t *lldev; /* driver device */ 346da14cebeSEric Cheng mac_ring_handle_t ring_handle; /* call back ring handle */ 347*0dc2366fSVenugopal Iyer uint64_t tx_pkts; /* packets sent */ 348*0dc2366fSVenugopal Iyer uint64_t tx_bytes; /* bytes sent though the ring */ 349da14cebeSEric Cheng 350da14cebeSEric Cheng boolean_t need_resched; 3517eced415Sxw }; 352a23fd118Syl 353ba2e4443Sseb struct xgelldev { 354da14cebeSEric Cheng volatile int is_initialized; 355da14cebeSEric Cheng volatile int in_reset; 356da14cebeSEric Cheng kmutex_t genlock; 357ba2e4443Sseb mac_handle_t mh; 358a23fd118Syl int instance; 359a23fd118Syl dev_info_t *dev_info; 360a23fd118Syl xge_hal_device_h devh; 361da14cebeSEric Cheng caddr_t ndp; 362a23fd118Syl timeout_id_t timeout_id; 363da14cebeSEric Cheng 364da14cebeSEric Cheng int init_rx_rings; 365da14cebeSEric Cheng int init_tx_rings; 366da14cebeSEric Cheng int init_rx_groups; 367da14cebeSEric Cheng 368da14cebeSEric Cheng int live_rx_rings; 369da14cebeSEric Cheng int live_tx_rings; 370da14cebeSEric Cheng xgell_rx_ring_t rx_ring[XGELL_RX_RING_NUM_DEFAULT]; 371da14cebeSEric Cheng xgell_tx_ring_t tx_ring[XGELL_TX_RING_NUM_DEFAULT]; 372da14cebeSEric Cheng 373da14cebeSEric Cheng int tx_copied_max; 374da14cebeSEric Cheng 375da14cebeSEric Cheng xgell_intr_t intrs[XGELL_MINTR_NUM_DEFAULT]; 376da14cebeSEric Cheng 3777eced415Sxw ddi_intr_handle_t *intr_table; 3787eced415Sxw uint_t intr_table_size; 3797eced415Sxw int intr_type; 3807eced415Sxw int intr_cnt; 3817eced415Sxw uint_t intr_pri; 3827eced415Sxw int intr_cap; 383da14cebeSEric Cheng 384da14cebeSEric Cheng xgell_config_t config; 385ba2e4443Sseb }; 386a23fd118Syl 387a23fd118Syl typedef struct { 388a23fd118Syl mblk_t *mblk; 389a23fd118Syl ddi_dma_handle_t dma_handles[XGE_HAL_DEFAULT_FIFO_FRAGS]; 390a23fd118Syl int handle_cnt; 391a23fd118Syl } xgell_txd_priv_t; 392a23fd118Syl 393a23fd118Syl typedef struct { 394a23fd118Syl xgell_rx_buffer_t *rx_buffer; 395a23fd118Syl } xgell_rxd_priv_t; 396a23fd118Syl 397a23fd118Syl int xgell_device_alloc(xge_hal_device_h devh, dev_info_t *dev_info, 398a23fd118Syl xgelldev_t **lldev_out); 399a23fd118Syl 400a23fd118Syl void xgell_device_free(xgelldev_t *lldev); 401a23fd118Syl 402a23fd118Syl int xgell_device_register(xgelldev_t *lldev, xgell_config_t *config); 403a23fd118Syl 404a23fd118Syl int xgell_device_unregister(xgelldev_t *lldev); 405a23fd118Syl 406a23fd118Syl void xgell_callback_link_up(void *userdata); 407a23fd118Syl 408a23fd118Syl void xgell_callback_link_down(void *userdata); 409a23fd118Syl 410a23fd118Syl int xgell_onerr_reset(xgelldev_t *lldev); 411a23fd118Syl 412a23fd118Syl void xge_device_poll_now(void *data); 413a23fd118Syl 4147eced415Sxw int xge_add_intrs(xgelldev_t *lldev); 4157eced415Sxw 4167eced415Sxw int xge_enable_intrs(xgelldev_t *lldev); 4177eced415Sxw 4187eced415Sxw void xge_disable_intrs(xgelldev_t *lldev); 4197eced415Sxw 4207eced415Sxw void xge_rem_intrs(xgelldev_t *lldev); 4217eced415Sxw 422*0dc2366fSVenugopal Iyer int xgell_rx_ring_stat(mac_ring_driver_t rh, uint_t stat, uint64_t *val); 4237eced415Sxw 424*0dc2366fSVenugopal Iyer int xgell_tx_ring_stat(mac_ring_driver_t rh, uint_t stat, uint64_t *val); 4257eced415Sxw 426a23fd118Syl #ifdef __cplusplus 427a23fd118Syl } 428a23fd118Syl #endif 429a23fd118Syl 430a23fd118Syl #endif /* _SYS_XGELL_H */ 431