1a23fd118Syl /*
2a23fd118Syl * CDDL HEADER START
3a23fd118Syl *
4a23fd118Syl * The contents of this file are subject to the terms of the
5a23fd118Syl * Common Development and Distribution License (the "License").
6a23fd118Syl * You may not use this file except in compliance with the License.
7a23fd118Syl *
8a23fd118Syl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9a23fd118Syl * or http://www.opensolaris.org/os/licensing.
10a23fd118Syl * See the License for the specific language governing permissions
11a23fd118Syl * and limitations under the License.
12a23fd118Syl *
13a23fd118Syl * When distributing Covered Code, include this CDDL HEADER in each
14a23fd118Syl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15a23fd118Syl * If applicable, add the following below this CDDL HEADER, with the
16a23fd118Syl * fields enclosed by brackets "[]" replaced with your own identifying
17a23fd118Syl * information: Portions Copyright [yyyy] [name of copyright owner]
18a23fd118Syl *
19a23fd118Syl * CDDL HEADER END
20a23fd118Syl */
21a23fd118Syl
22a23fd118Syl /*
237eced415Sxw * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
24a23fd118Syl * Use is subject to license terms.
25a23fd118Syl */
26a23fd118Syl
27a23fd118Syl /*
28a23fd118Syl * Copyright (c) 2002-2005 Neterion, Inc.
29a23fd118Syl * All right Reserved.
30a23fd118Syl *
31a23fd118Syl * FileName : xge_osdep.h
32a23fd118Syl *
33a23fd118Syl * Description: OSPAL - Solaris
34a23fd118Syl *
35a23fd118Syl */
36a23fd118Syl
37a23fd118Syl #ifndef _SYS_XGE_OSDEP_H
38a23fd118Syl #define _SYS_XGE_OSDEP_H
39a23fd118Syl
40a23fd118Syl #include <sys/ddi.h>
41a23fd118Syl #include <sys/sunddi.h>
42a23fd118Syl #include <sys/varargs.h>
43a23fd118Syl #include <sys/atomic.h>
44a23fd118Syl #include <sys/policy.h>
45a23fd118Syl #include <sys/int_fmtio.h>
46a23fd118Syl #include <sys/thread.h>
47a23fd118Syl #include <sys/cpuvar.h>
48a23fd118Syl
49a23fd118Syl #include <inet/common.h>
50a23fd118Syl #include <inet/ip.h>
51a23fd118Syl #include <inet/mi.h>
52a23fd118Syl #include <inet/nd.h>
53a23fd118Syl
54a23fd118Syl #ifdef __cplusplus
55a23fd118Syl extern "C" {
56a23fd118Syl #endif
57a23fd118Syl
58a23fd118Syl /* ------------------------- includes and defines ------------------------- */
59a23fd118Syl
60a23fd118Syl #define XGE_HAL_TX_MULTI_POST_IRQ 1
61a23fd118Syl #define XGE_HAL_TX_MULTI_RESERVE_IRQ 1
62a23fd118Syl #define XGE_HAL_TX_MULTI_FREE_IRQ 1
63a23fd118Syl #define XGE_HAL_DMA_DTR_CONSISTENT 1
64a23fd118Syl #define XGE_HAL_DMA_STATS_STREAMING 1
65a23fd118Syl
66a23fd118Syl #if defined(__sparc)
67a23fd118Syl #define XGE_OS_DMA_REQUIRES_SYNC 1
68a23fd118Syl #endif
69a23fd118Syl
708347601bSyl #define XGE_HAL_ALIGN_XMIT 1
718347601bSyl
72a23fd118Syl #ifdef _BIG_ENDIAN
73a23fd118Syl #define XGE_OS_HOST_BIG_ENDIAN 1
74a23fd118Syl #else
75a23fd118Syl #define XGE_OS_HOST_LITTLE_ENDIAN 1
76a23fd118Syl #endif
77a23fd118Syl
787eced415Sxw #if defined(__sparc)
797eced415Sxw #define XGE_OS_HOST_PAGE_SIZE 8192
807eced415Sxw #else
817eced415Sxw #define XGE_OS_HOST_PAGE_SIZE 4096
827eced415Sxw #endif
837eced415Sxw
84a23fd118Syl #if defined(_LP64)
85a23fd118Syl #define XGE_OS_PLATFORM_64BIT 1
86a23fd118Syl #else
87a23fd118Syl #define XGE_OS_PLATFORM_32BIT 1
88a23fd118Syl #endif
89a23fd118Syl
90a23fd118Syl #define XGE_OS_HAS_SNPRINTF 1
91a23fd118Syl
928347601bSyl /* LRO defines */
938347601bSyl #define XGE_LL_IP_FAST_CSUM(hdr, len) 0 /* ip_ocsum(hdr, len>>1, 0); */
948347601bSyl
95a23fd118Syl /* ---------------------- fixed size primitive types ----------------------- */
96a23fd118Syl
97a23fd118Syl #define u8 uint8_t
98a23fd118Syl #define u16 uint16_t
99a23fd118Syl #define u32 uint32_t
100a23fd118Syl #define u64 uint64_t
101a23fd118Syl typedef u64 dma_addr_t;
102a23fd118Syl #define ulong_t ulong_t
103a23fd118Syl #define ptrdiff_t ptrdiff_t
104a23fd118Syl typedef kmutex_t spinlock_t;
105a23fd118Syl typedef dev_info_t *pci_dev_h;
106a23fd118Syl typedef ddi_acc_handle_t pci_reg_h;
107a23fd118Syl typedef ddi_acc_handle_t pci_cfg_h;
1087eced415Sxw typedef uint_t pci_irq_h;
109a23fd118Syl typedef ddi_dma_handle_t pci_dma_h;
110a23fd118Syl typedef ddi_acc_handle_t pci_dma_acc_h;
111a23fd118Syl
1128347601bSyl /* LRO types */
1138347601bSyl #define OS_NETSTACK_BUF mblk_t *
1148347601bSyl #define OS_LL_HEADER uint8_t *
1158347601bSyl #define OS_IP_HEADER uint8_t *
1168347601bSyl #define OS_TL_HEADER uint8_t *
1178347601bSyl
118a23fd118Syl /* -------------------------- "libc" functionality ------------------------- */
119a23fd118Syl
1207eced415Sxw #define xge_os_strlcpy (void) strlcpy
121a23fd118Syl #define xge_os_strlen strlen
122a23fd118Syl #define xge_os_snprintf snprintf
123a23fd118Syl #define xge_os_memzero(addr, size) bzero(addr, size)
124a23fd118Syl #define xge_os_memcpy(dst, src, size) bcopy(src, dst, size)
125a23fd118Syl #define xge_os_memcmp(src1, src2, size) bcmp(src1, src2, size)
1268347601bSyl #define xge_os_ntohl ntohl
1278347601bSyl #define xge_os_htons htons
1288347601bSyl #define xge_os_ntohs ntohs
129a23fd118Syl
130a23fd118Syl #ifdef __GNUC__
131a23fd118Syl #define xge_os_printf(fmt...) cmn_err(CE_CONT, fmt)
132a23fd118Syl #define xge_os_sprintf(buf, fmt...) strlen(sprintf(buf, fmt))
133a23fd118Syl #else
134a23fd118Syl #define xge_os_vaprintf(fmt) { \
135a23fd118Syl va_list va; \
136a23fd118Syl va_start(va, fmt); \
137a23fd118Syl vcmn_err(CE_CONT, fmt, va); \
138a23fd118Syl va_end(va); \
139a23fd118Syl }
140a23fd118Syl
xge_os_printf(char * fmt,...)141a23fd118Syl static inline void xge_os_printf(char *fmt, ...) {
142a23fd118Syl xge_os_vaprintf(fmt);
143a23fd118Syl }
144a23fd118Syl
145a23fd118Syl #define xge_os_vasprintf(buf, fmt) { \
146a23fd118Syl va_list va; \
147a23fd118Syl va_start(va, fmt); \
148a23fd118Syl (void) vsprintf(buf, fmt, va); \
149a23fd118Syl va_end(va); \
150a23fd118Syl }
151a23fd118Syl
xge_os_sprintf(char * buf,char * fmt,...)152a23fd118Syl static inline int xge_os_sprintf(char *buf, char *fmt, ...) {
153a23fd118Syl xge_os_vasprintf(buf, fmt);
154a23fd118Syl return (strlen(buf));
155a23fd118Syl }
156a23fd118Syl #endif
157a23fd118Syl
158a23fd118Syl #define xge_os_timestamp(buf) { \
159a23fd118Syl todinfo_t todinfo = utc_to_tod(ddi_get_time()); \
1607eced415Sxw (void) xge_os_sprintf(buf, "%02d/%02d/%02d.%02d:%02d:%02d: ", \
161a23fd118Syl todinfo.tod_day, todinfo.tod_month, \
162a23fd118Syl (1970 + todinfo.tod_year - 70), \
163a23fd118Syl todinfo.tod_hour, todinfo.tod_min, todinfo.tod_sec); \
164a23fd118Syl }
165a23fd118Syl
166a23fd118Syl #define xge_os_println xge_os_printf
167a23fd118Syl
168a23fd118Syl /* -------------------- synchronization primitives ------------------------- */
169a23fd118Syl
170a23fd118Syl #define xge_os_spin_lock_init(lockp, ctxh) \
171a23fd118Syl mutex_init(lockp, NULL, MUTEX_DRIVER, NULL)
172a23fd118Syl #define xge_os_spin_lock_init_irq(lockp, irqh) \
1737eced415Sxw mutex_init(lockp, NULL, MUTEX_DRIVER, DDI_INTR_PRI(irqh))
174a23fd118Syl #define xge_os_spin_lock_destroy(lockp, cthx) \
175a23fd118Syl (cthx = cthx, mutex_destroy(lockp))
176a23fd118Syl #define xge_os_spin_lock_destroy_irq(lockp, cthx) \
177a23fd118Syl (cthx = cthx, mutex_destroy(lockp))
178a23fd118Syl #define xge_os_spin_lock(lockp) mutex_enter(lockp)
179a23fd118Syl #define xge_os_spin_unlock(lockp) mutex_exit(lockp)
180a23fd118Syl #define xge_os_spin_lock_irq(lockp, flags) (flags = flags, mutex_enter(lockp))
181a23fd118Syl #define xge_os_spin_unlock_irq(lockp, flags) mutex_exit(lockp)
182a23fd118Syl
183a23fd118Syl /* x86 arch will never re-order writes, Sparc can */
184a23fd118Syl #define xge_os_wmb() membar_producer()
185a23fd118Syl
186a23fd118Syl #define xge_os_udelay(us) drv_usecwait(us)
187a23fd118Syl #define xge_os_mdelay(ms) drv_usecwait(ms * 1000)
188a23fd118Syl
189a23fd118Syl #define xge_os_cmpxchg(targetp, cmp, newval) \
190a23fd118Syl sizeof (*(targetp)) == 4 ? \
191*75d94465SJosef 'Jeff' Sipek atomic_cas_32((uint32_t *)targetp, cmp, newval) : \
192*75d94465SJosef 'Jeff' Sipek atomic_cas_64((uint64_t *)targetp, cmp, newval)
193a23fd118Syl
194a23fd118Syl /* ------------------------- misc primitives ------------------------------- */
195a23fd118Syl
196a23fd118Syl #define xge_os_unlikely(x) (x)
197a23fd118Syl #define xge_os_prefetch(a) (a = a)
198a23fd118Syl #define xge_os_prefetchw
199a23fd118Syl #ifdef __GNUC__
200a23fd118Syl #define xge_os_bug(fmt...) cmn_err(CE_PANIC, fmt)
201a23fd118Syl #else
xge_os_bug(char * fmt,...)202a23fd118Syl static inline void xge_os_bug(char *fmt, ...) {
203a23fd118Syl va_list ap;
204a23fd118Syl
205a23fd118Syl va_start(ap, fmt);
206a23fd118Syl vcmn_err(CE_PANIC, fmt, ap);
207a23fd118Syl va_end(ap);
208a23fd118Syl }
209a23fd118Syl #endif
210a23fd118Syl
211a23fd118Syl /* -------------------------- compiler stuffs ------------------------------ */
212a23fd118Syl
213a23fd118Syl #if defined(__i386)
214a23fd118Syl #define __xge_os_cacheline_size 64 /* L1-cache line size: x86_64 */
215a23fd118Syl #else
216a23fd118Syl #define __xge_os_cacheline_size 64 /* L1-cache line size: sparcv9 */
217a23fd118Syl #endif
218a23fd118Syl
219a23fd118Syl #ifdef __GNUC__
220a23fd118Syl #define __xge_os_attr_cacheline_aligned \
221a23fd118Syl __attribute__((__aligned__(__xge_os_cacheline_size)))
222a23fd118Syl #else
223a23fd118Syl #define __xge_os_attr_cacheline_aligned
224a23fd118Syl #endif
225a23fd118Syl
226a23fd118Syl /* ---------------------- memory primitives -------------------------------- */
227a23fd118Syl
__xge_os_malloc(pci_dev_h pdev,unsigned long size,char * file,int line)228a23fd118Syl static inline void *__xge_os_malloc(pci_dev_h pdev, unsigned long size,
229a23fd118Syl char *file, int line)
230a23fd118Syl {
231a23fd118Syl void *vaddr = kmem_alloc(size, KM_SLEEP);
232a23fd118Syl
233a23fd118Syl XGE_OS_MEMORY_CHECK_MALLOC(vaddr, size, file, line);
234a23fd118Syl return (vaddr);
235a23fd118Syl }
236a23fd118Syl
xge_os_free(pci_dev_h pdev,const void * vaddr,unsigned long size)237a23fd118Syl static inline void xge_os_free(pci_dev_h pdev, const void *vaddr,
238a23fd118Syl unsigned long size)
239a23fd118Syl {
240a23fd118Syl XGE_OS_MEMORY_CHECK_FREE(vaddr, size);
241a23fd118Syl kmem_free((void*)vaddr, size);
242a23fd118Syl }
243a23fd118Syl
244a23fd118Syl #define xge_os_malloc(pdev, size) \
245a23fd118Syl __xge_os_malloc(pdev, size, __FILE__, __LINE__)
246a23fd118Syl
__xge_os_dma_malloc(pci_dev_h pdev,unsigned long size,int dma_flags,pci_dma_h * p_dmah,pci_dma_acc_h * p_dma_acch,char * file,int line)247a23fd118Syl static inline void *__xge_os_dma_malloc(pci_dev_h pdev, unsigned long size,
248a23fd118Syl int dma_flags, pci_dma_h *p_dmah, pci_dma_acc_h *p_dma_acch, char *file,
249a23fd118Syl int line)
250a23fd118Syl {
251a23fd118Syl void *vaddr;
252a23fd118Syl int ret;
253a23fd118Syl size_t real_size;
254a23fd118Syl extern ddi_device_acc_attr_t *p_xge_dev_attr;
255a23fd118Syl extern struct ddi_dma_attr *p_hal_dma_attr;
256a23fd118Syl
2577eced415Sxw ret = ddi_dma_alloc_handle(pdev, p_hal_dma_attr,
258a23fd118Syl DDI_DMA_DONTWAIT, 0, p_dmah);
259a23fd118Syl if (ret != DDI_SUCCESS) {
260a23fd118Syl return (NULL);
261a23fd118Syl }
262a23fd118Syl
263a23fd118Syl ret = ddi_dma_mem_alloc(*p_dmah, size, p_xge_dev_attr,
264a23fd118Syl (dma_flags & XGE_OS_DMA_CONSISTENT ?
2658347601bSyl DDI_DMA_CONSISTENT : DDI_DMA_STREAMING), DDI_DMA_DONTWAIT, 0,
2668347601bSyl (caddr_t *)&vaddr, &real_size, p_dma_acch);
267a23fd118Syl if (ret != DDI_SUCCESS) {
268a23fd118Syl ddi_dma_free_handle(p_dmah);
269a23fd118Syl return (NULL);
270a23fd118Syl }
271a23fd118Syl
272a23fd118Syl if (size > real_size) {
273a23fd118Syl ddi_dma_mem_free(p_dma_acch);
274a23fd118Syl ddi_dma_free_handle(p_dmah);
275a23fd118Syl return (NULL);
276a23fd118Syl }
277a23fd118Syl
278a23fd118Syl XGE_OS_MEMORY_CHECK_MALLOC(vaddr, size, file, line);
279a23fd118Syl
280a23fd118Syl return (vaddr);
281a23fd118Syl }
282a23fd118Syl
283a23fd118Syl #define xge_os_dma_malloc(pdev, size, dma_flags, p_dmah, p_dma_acch) \
284a23fd118Syl __xge_os_dma_malloc(pdev, size, dma_flags, p_dmah, p_dma_acch, \
285a23fd118Syl __FILE__, __LINE__)
286a23fd118Syl
xge_os_dma_free(pci_dev_h pdev,const void * vaddr,int size,pci_dma_acc_h * p_dma_acch,pci_dma_h * p_dmah)287a23fd118Syl static inline void xge_os_dma_free(pci_dev_h pdev, const void *vaddr, int size,
288a23fd118Syl pci_dma_acc_h *p_dma_acch, pci_dma_h *p_dmah)
289a23fd118Syl {
290a23fd118Syl XGE_OS_MEMORY_CHECK_FREE(vaddr, 0);
291a23fd118Syl ddi_dma_mem_free(p_dma_acch);
292a23fd118Syl ddi_dma_free_handle(p_dmah);
293a23fd118Syl }
294a23fd118Syl
295a23fd118Syl
296a23fd118Syl /* --------------------------- pci primitives ------------------------------ */
297a23fd118Syl
298a23fd118Syl #define xge_os_pci_read8(pdev, cfgh, where, val) \
299a23fd118Syl (*(val) = pci_config_get8(cfgh, where))
300a23fd118Syl
301a23fd118Syl #define xge_os_pci_write8(pdev, cfgh, where, val) \
302a23fd118Syl pci_config_put8(cfgh, where, val)
303a23fd118Syl
304a23fd118Syl #define xge_os_pci_read16(pdev, cfgh, where, val) \
305a23fd118Syl (*(val) = pci_config_get16(cfgh, where))
306a23fd118Syl
307a23fd118Syl #define xge_os_pci_write16(pdev, cfgh, where, val) \
308a23fd118Syl pci_config_put16(cfgh, where, val)
309a23fd118Syl
310a23fd118Syl #define xge_os_pci_read32(pdev, cfgh, where, val) \
311a23fd118Syl (*(val) = pci_config_get32(cfgh, where))
312a23fd118Syl
313a23fd118Syl #define xge_os_pci_write32(pdev, cfgh, where, val) \
314a23fd118Syl pci_config_put32(cfgh, where, val)
315a23fd118Syl
316a23fd118Syl /* --------------------------- io primitives ------------------------------- */
317a23fd118Syl
318a23fd118Syl #define xge_os_pio_mem_read8(pdev, regh, addr) \
319a23fd118Syl (ddi_get8(regh, (uint8_t *)(addr)))
320a23fd118Syl
321a23fd118Syl #define xge_os_pio_mem_write8(pdev, regh, val, addr) \
322a23fd118Syl (ddi_put8(regh, (uint8_t *)(addr), val))
323a23fd118Syl
324a23fd118Syl #define xge_os_pio_mem_read16(pdev, regh, addr) \
325a23fd118Syl (ddi_get16(regh, (uint16_t *)(addr)))
326a23fd118Syl
327a23fd118Syl #define xge_os_pio_mem_write16(pdev, regh, val, addr) \
328a23fd118Syl (ddi_put16(regh, (uint16_t *)(addr), val))
329a23fd118Syl
330a23fd118Syl #define xge_os_pio_mem_read32(pdev, regh, addr) \
331a23fd118Syl (ddi_get32(regh, (uint32_t *)(addr)))
332a23fd118Syl
333a23fd118Syl #define xge_os_pio_mem_write32(pdev, regh, val, addr) \
334a23fd118Syl (ddi_put32(regh, (uint32_t *)(addr), val))
335a23fd118Syl
336a23fd118Syl #define xge_os_pio_mem_read64(pdev, regh, addr) \
337a23fd118Syl (ddi_get64(regh, (uint64_t *)(addr)))
338a23fd118Syl
339a23fd118Syl #define xge_os_pio_mem_write64(pdev, regh, val, addr) \
340a23fd118Syl (ddi_put64(regh, (uint64_t *)(addr), val))
341a23fd118Syl
342a23fd118Syl #define xge_os_flush_bridge xge_os_pio_mem_read64
343a23fd118Syl
344a23fd118Syl /* --------------------------- dma primitives ----------------------------- */
345a23fd118Syl
346a23fd118Syl #define XGE_OS_DMA_DIR_TODEVICE DDI_DMA_SYNC_FORDEV
347a23fd118Syl #define XGE_OS_DMA_DIR_FROMDEVICE DDI_DMA_SYNC_FORKERNEL
348a23fd118Syl #define XGE_OS_DMA_DIR_BIDIRECTIONAL -1
349a23fd118Syl #if defined(__x86)
350a23fd118Syl #define XGE_OS_DMA_USES_IOMMU 0
351a23fd118Syl #else
352a23fd118Syl #define XGE_OS_DMA_USES_IOMMU 1
353a23fd118Syl #endif
354a23fd118Syl
355a23fd118Syl #define XGE_OS_INVALID_DMA_ADDR ((dma_addr_t)0)
356a23fd118Syl
xge_os_dma_map(pci_dev_h pdev,pci_dma_h dmah,void * vaddr,size_t size,int dir,int dma_flags)357a23fd118Syl static inline dma_addr_t xge_os_dma_map(pci_dev_h pdev, pci_dma_h dmah,
358a23fd118Syl void *vaddr, size_t size, int dir, int dma_flags) {
359a23fd118Syl int ret;
360a23fd118Syl uint_t flags;
361a23fd118Syl uint_t ncookies;
362a23fd118Syl ddi_dma_cookie_t dma_cookie;
363a23fd118Syl
364a23fd118Syl switch (dir) {
365a23fd118Syl case XGE_OS_DMA_DIR_TODEVICE:
366a23fd118Syl flags = DDI_DMA_WRITE;
367a23fd118Syl break;
368a23fd118Syl case XGE_OS_DMA_DIR_FROMDEVICE:
369a23fd118Syl flags = DDI_DMA_READ;
370a23fd118Syl break;
371a23fd118Syl case XGE_OS_DMA_DIR_BIDIRECTIONAL:
372a23fd118Syl flags = DDI_DMA_RDWR;
373a23fd118Syl break;
374a23fd118Syl default:
375a23fd118Syl return (0);
376a23fd118Syl }
377a23fd118Syl
378a23fd118Syl flags |= (dma_flags & XGE_OS_DMA_CONSISTENT) ?
379a23fd118Syl DDI_DMA_CONSISTENT : DDI_DMA_STREAMING;
380a23fd118Syl
381a23fd118Syl ret = ddi_dma_addr_bind_handle(dmah, NULL, vaddr, size, flags,
382a23fd118Syl DDI_DMA_SLEEP, 0, &dma_cookie, &ncookies);
383a23fd118Syl if (ret != DDI_SUCCESS) {
384a23fd118Syl return (0);
385a23fd118Syl }
386a23fd118Syl
387a23fd118Syl if (ncookies != 1 || dma_cookie.dmac_size < size) {
388a23fd118Syl (void) ddi_dma_unbind_handle(dmah);
389a23fd118Syl return (0);
390a23fd118Syl }
391a23fd118Syl
392a23fd118Syl return (dma_cookie.dmac_laddress);
393a23fd118Syl }
394a23fd118Syl
xge_os_dma_unmap(pci_dev_h pdev,pci_dma_h dmah,dma_addr_t dma_addr,size_t size,int dir)395a23fd118Syl static inline void xge_os_dma_unmap(pci_dev_h pdev, pci_dma_h dmah,
396a23fd118Syl dma_addr_t dma_addr, size_t size, int dir)
397a23fd118Syl {
398a23fd118Syl (void) ddi_dma_unbind_handle(dmah);
399a23fd118Syl }
400a23fd118Syl
xge_os_dma_sync(pci_dev_h pdev,pci_dma_h dmah,dma_addr_t dma_addr,u64 dma_offset,size_t length,int dir)401a23fd118Syl static inline void xge_os_dma_sync(pci_dev_h pdev, pci_dma_h dmah,
402a23fd118Syl dma_addr_t dma_addr, u64 dma_offset, size_t length, int dir)
403a23fd118Syl {
404a23fd118Syl (void) ddi_dma_sync(dmah, dma_offset, length, dir);
405a23fd118Syl }
406a23fd118Syl
407a23fd118Syl #ifdef __cplusplus
408a23fd118Syl }
409a23fd118Syl #endif
410a23fd118Syl
411a23fd118Syl #endif /* _SYS_XGE_OSDEP_H */
412