1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27 /* 28 * EHCI Host Controller Driver (EHCI) 29 * 30 * The EHCI driver is a software driver which interfaces to the Universal 31 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 32 * the Host Controller is defined by the EHCI Host Controller Interface. 33 * 34 * This module contains the main EHCI driver code which handles all USB 35 * transfers, bandwidth allocations and other general functionalities. 36 */ 37 38 #include <sys/usb/hcd/ehci/ehcid.h> 39 #include <sys/usb/hcd/ehci/ehci_isoch.h> 40 #include <sys/usb/hcd/ehci/ehci_xfer.h> 41 42 /* 43 * EHCI MSI tunable: 44 * 45 * By default MSI is enabled on all supported platforms except for the 46 * EHCI controller of ULI1575 South bridge. 47 */ 48 boolean_t ehci_enable_msi = B_TRUE; 49 50 /* Pointer to the state structure */ 51 extern void *ehci_statep; 52 53 extern void ehci_handle_endpoint_reclaimation(ehci_state_t *); 54 55 extern uint_t ehci_vt62x2_workaround; 56 extern int force_ehci_off; 57 58 /* Adjustable variables for the size of the pools */ 59 int ehci_qh_pool_size = EHCI_QH_POOL_SIZE; 60 int ehci_qtd_pool_size = EHCI_QTD_POOL_SIZE; 61 62 /* 63 * Initialize the values which the order of 32ms intr qh are executed 64 * by the host controller in the lattice tree. 65 */ 66 static uchar_t ehci_index[EHCI_NUM_INTR_QH_LISTS] = 67 {0x00, 0x10, 0x08, 0x18, 68 0x04, 0x14, 0x0c, 0x1c, 69 0x02, 0x12, 0x0a, 0x1a, 70 0x06, 0x16, 0x0e, 0x1e, 71 0x01, 0x11, 0x09, 0x19, 72 0x05, 0x15, 0x0d, 0x1d, 73 0x03, 0x13, 0x0b, 0x1b, 74 0x07, 0x17, 0x0f, 0x1f}; 75 76 /* 77 * Initialize the values which are used to calculate start split mask 78 * for the low/full/high speed interrupt and isochronous endpoints. 79 */ 80 static uint_t ehci_start_split_mask[15] = { 81 /* 82 * For high/full/low speed usb devices. For high speed 83 * device with polling interval greater than or equal 84 * to 8us (125us). 85 */ 86 0x01, /* 00000001 */ 87 0x02, /* 00000010 */ 88 0x04, /* 00000100 */ 89 0x08, /* 00001000 */ 90 0x10, /* 00010000 */ 91 0x20, /* 00100000 */ 92 0x40, /* 01000000 */ 93 0x80, /* 10000000 */ 94 95 /* Only for high speed devices with polling interval 4us */ 96 0x11, /* 00010001 */ 97 0x22, /* 00100010 */ 98 0x44, /* 01000100 */ 99 0x88, /* 10001000 */ 100 101 /* Only for high speed devices with polling interval 2us */ 102 0x55, /* 01010101 */ 103 0xaa, /* 10101010 */ 104 105 /* Only for high speed devices with polling interval 1us */ 106 0xff /* 11111111 */ 107 }; 108 109 /* 110 * Initialize the values which are used to calculate complete split mask 111 * for the low/full speed interrupt and isochronous endpoints. 112 */ 113 static uint_t ehci_intr_complete_split_mask[7] = { 114 /* Only full/low speed devices */ 115 0x1c, /* 00011100 */ 116 0x38, /* 00111000 */ 117 0x70, /* 01110000 */ 118 0xe0, /* 11100000 */ 119 0x00, /* Need FSTN feature */ 120 0x00, /* Need FSTN feature */ 121 0x00 /* Need FSTN feature */ 122 }; 123 124 125 /* 126 * EHCI Internal Function Prototypes 127 */ 128 129 /* Host Controller Driver (HCD) initialization functions */ 130 void ehci_set_dma_attributes(ehci_state_t *ehcip); 131 int ehci_allocate_pools(ehci_state_t *ehcip); 132 void ehci_decode_ddi_dma_addr_bind_handle_result( 133 ehci_state_t *ehcip, 134 int result); 135 int ehci_map_regs(ehci_state_t *ehcip); 136 int ehci_register_intrs_and_init_mutex( 137 ehci_state_t *ehcip); 138 static int ehci_add_intrs(ehci_state_t *ehcip, 139 int intr_type); 140 int ehci_init_ctlr(ehci_state_t *ehcip, 141 int init_type); 142 static int ehci_take_control(ehci_state_t *ehcip); 143 static int ehci_init_periodic_frame_lst_table( 144 ehci_state_t *ehcip); 145 static void ehci_build_interrupt_lattice( 146 ehci_state_t *ehcip); 147 usba_hcdi_ops_t *ehci_alloc_hcdi_ops(ehci_state_t *ehcip); 148 149 /* Host Controller Driver (HCD) deinitialization functions */ 150 int ehci_cleanup(ehci_state_t *ehcip); 151 static void ehci_rem_intrs(ehci_state_t *ehcip); 152 int ehci_cpr_suspend(ehci_state_t *ehcip); 153 int ehci_cpr_resume(ehci_state_t *ehcip); 154 155 /* Bandwidth Allocation functions */ 156 int ehci_allocate_bandwidth(ehci_state_t *ehcip, 157 usba_pipe_handle_data_t *ph, 158 uint_t *pnode, 159 uchar_t *smask, 160 uchar_t *cmask); 161 static int ehci_allocate_high_speed_bandwidth( 162 ehci_state_t *ehcip, 163 usba_pipe_handle_data_t *ph, 164 uint_t *hnode, 165 uchar_t *smask, 166 uchar_t *cmask); 167 static int ehci_allocate_classic_tt_bandwidth( 168 ehci_state_t *ehcip, 169 usba_pipe_handle_data_t *ph, 170 uint_t pnode); 171 void ehci_deallocate_bandwidth(ehci_state_t *ehcip, 172 usba_pipe_handle_data_t *ph, 173 uint_t pnode, 174 uchar_t smask, 175 uchar_t cmask); 176 static void ehci_deallocate_high_speed_bandwidth( 177 ehci_state_t *ehcip, 178 usba_pipe_handle_data_t *ph, 179 uint_t hnode, 180 uchar_t smask, 181 uchar_t cmask); 182 static void ehci_deallocate_classic_tt_bandwidth( 183 ehci_state_t *ehcip, 184 usba_pipe_handle_data_t *ph, 185 uint_t pnode); 186 static int ehci_compute_high_speed_bandwidth( 187 ehci_state_t *ehcip, 188 usb_ep_descr_t *endpoint, 189 usb_port_status_t port_status, 190 uint_t *sbandwidth, 191 uint_t *cbandwidth); 192 static int ehci_compute_classic_bandwidth( 193 usb_ep_descr_t *endpoint, 194 usb_port_status_t port_status, 195 uint_t *bandwidth); 196 int ehci_adjust_polling_interval( 197 ehci_state_t *ehcip, 198 usb_ep_descr_t *endpoint, 199 usb_port_status_t port_status); 200 static int ehci_adjust_high_speed_polling_interval( 201 ehci_state_t *ehcip, 202 usb_ep_descr_t *endpoint); 203 static uint_t ehci_lattice_height(uint_t interval); 204 static uint_t ehci_lattice_parent(uint_t node); 205 static uint_t ehci_find_periodic_node( 206 uint_t leaf, 207 int interval); 208 static uint_t ehci_leftmost_leaf(uint_t node, 209 uint_t height); 210 static uint_t ehci_pow_2(uint_t x); 211 static uint_t ehci_log_2(uint_t x); 212 static int ehci_find_bestfit_hs_mask( 213 ehci_state_t *ehcip, 214 uchar_t *smask, 215 uint_t *pnode, 216 usb_ep_descr_t *endpoint, 217 uint_t bandwidth, 218 int interval); 219 static int ehci_find_bestfit_ls_intr_mask( 220 ehci_state_t *ehcip, 221 uchar_t *smask, 222 uchar_t *cmask, 223 uint_t *pnode, 224 uint_t sbandwidth, 225 uint_t cbandwidth, 226 int interval); 227 static int ehci_find_bestfit_sitd_in_mask( 228 ehci_state_t *ehcip, 229 uchar_t *smask, 230 uchar_t *cmask, 231 uint_t *pnode, 232 uint_t sbandwidth, 233 uint_t cbandwidth, 234 int interval); 235 static int ehci_find_bestfit_sitd_out_mask( 236 ehci_state_t *ehcip, 237 uchar_t *smask, 238 uint_t *pnode, 239 uint_t sbandwidth, 240 int interval); 241 static uint_t ehci_calculate_bw_availability_mask( 242 ehci_state_t *ehcip, 243 uint_t bandwidth, 244 int leaf, 245 int leaf_count, 246 uchar_t *bw_mask); 247 static void ehci_update_bw_availability( 248 ehci_state_t *ehcip, 249 int bandwidth, 250 int leftmost_leaf, 251 int leaf_count, 252 uchar_t mask); 253 254 /* Miscellaneous functions */ 255 ehci_state_t *ehci_obtain_state( 256 dev_info_t *dip); 257 int ehci_state_is_operational( 258 ehci_state_t *ehcip); 259 int ehci_do_soft_reset( 260 ehci_state_t *ehcip); 261 usb_req_attrs_t ehci_get_xfer_attrs(ehci_state_t *ehcip, 262 ehci_pipe_private_t *pp, 263 ehci_trans_wrapper_t *tw); 264 usb_frame_number_t ehci_get_current_frame_number( 265 ehci_state_t *ehcip); 266 static void ehci_cpr_cleanup( 267 ehci_state_t *ehcip); 268 int ehci_wait_for_sof( 269 ehci_state_t *ehcip); 270 void ehci_toggle_scheduler( 271 ehci_state_t *ehcip); 272 void ehci_print_caps(ehci_state_t *ehcip); 273 void ehci_print_regs(ehci_state_t *ehcip); 274 void ehci_print_qh(ehci_state_t *ehcip, 275 ehci_qh_t *qh); 276 void ehci_print_qtd(ehci_state_t *ehcip, 277 ehci_qtd_t *qtd); 278 void ehci_create_stats(ehci_state_t *ehcip); 279 void ehci_destroy_stats(ehci_state_t *ehcip); 280 void ehci_do_intrs_stats(ehci_state_t *ehcip, 281 int val); 282 void ehci_do_byte_stats(ehci_state_t *ehcip, 283 size_t len, 284 uint8_t attr, 285 uint8_t addr); 286 287 /* 288 * check if this ehci controller can support PM 289 */ 290 int 291 ehci_hcdi_pm_support(dev_info_t *dip) 292 { 293 ehci_state_t *ehcip = ddi_get_soft_state(ehci_statep, 294 ddi_get_instance(dip)); 295 296 if (((ehcip->ehci_vendor_id == PCI_VENDOR_NEC_COMBO) && 297 (ehcip->ehci_device_id == PCI_DEVICE_NEC_COMBO)) || 298 299 ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 300 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) || 301 302 (ehcip->ehci_vendor_id == PCI_VENDOR_VIA)) { 303 304 return (USB_SUCCESS); 305 } 306 307 return (USB_FAILURE); 308 } 309 310 void 311 ehci_dma_attr_workaround(ehci_state_t *ehcip) 312 { 313 /* 314 * Some Nvidia chips can not handle qh dma address above 2G. 315 * The bit 31 of the dma address might be omitted and it will 316 * cause system crash or other unpredicable result. So force 317 * the dma address allocated below 2G to make ehci work. 318 */ 319 if (PCI_VENDOR_NVIDIA == ehcip->ehci_vendor_id) { 320 switch (ehcip->ehci_device_id) { 321 case PCI_DEVICE_NVIDIA_CK804: 322 case PCI_DEVICE_NVIDIA_MCP04: 323 USB_DPRINTF_L2(PRINT_MASK_ATTA, 324 ehcip->ehci_log_hdl, 325 "ehci_dma_attr_workaround: NVIDIA dma " 326 "workaround enabled, force dma address " 327 "to be allocated below 2G"); 328 ehcip->ehci_dma_attr.dma_attr_addr_hi = 329 0x7fffffffull; 330 break; 331 default: 332 break; 333 334 } 335 } 336 } 337 338 /* 339 * Host Controller Driver (HCD) initialization functions 340 */ 341 342 /* 343 * ehci_set_dma_attributes: 344 * 345 * Set the limits in the DMA attributes structure. Most of the values used 346 * in the DMA limit structures are the default values as specified by the 347 * Writing PCI device drivers document. 348 */ 349 void 350 ehci_set_dma_attributes(ehci_state_t *ehcip) 351 { 352 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 353 "ehci_set_dma_attributes:"); 354 355 /* Initialize the DMA attributes */ 356 ehcip->ehci_dma_attr.dma_attr_version = DMA_ATTR_V0; 357 ehcip->ehci_dma_attr.dma_attr_addr_lo = 0x00000000ull; 358 ehcip->ehci_dma_attr.dma_attr_addr_hi = 0xfffffffeull; 359 360 /* 32 bit addressing */ 361 ehcip->ehci_dma_attr.dma_attr_count_max = EHCI_DMA_ATTR_COUNT_MAX; 362 363 /* Byte alignment */ 364 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 365 366 /* 367 * Since PCI specification is byte alignment, the 368 * burst size field should be set to 1 for PCI devices. 369 */ 370 ehcip->ehci_dma_attr.dma_attr_burstsizes = 0x1; 371 372 ehcip->ehci_dma_attr.dma_attr_minxfer = 0x1; 373 ehcip->ehci_dma_attr.dma_attr_maxxfer = EHCI_DMA_ATTR_MAX_XFER; 374 ehcip->ehci_dma_attr.dma_attr_seg = 0xffffffffull; 375 ehcip->ehci_dma_attr.dma_attr_sgllen = 1; 376 ehcip->ehci_dma_attr.dma_attr_granular = EHCI_DMA_ATTR_GRANULAR; 377 ehcip->ehci_dma_attr.dma_attr_flags = 0; 378 ehci_dma_attr_workaround(ehcip); 379 } 380 381 382 /* 383 * ehci_allocate_pools: 384 * 385 * Allocate the system memory for the Endpoint Descriptor (QH) and for the 386 * Transfer Descriptor (QTD) pools. Both QH and QTD structures must be aligned 387 * to a 16 byte boundary. 388 */ 389 int 390 ehci_allocate_pools(ehci_state_t *ehcip) 391 { 392 ddi_device_acc_attr_t dev_attr; 393 size_t real_length; 394 int result; 395 uint_t ccount; 396 int i; 397 398 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 399 "ehci_allocate_pools:"); 400 401 /* The host controller will be little endian */ 402 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 403 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 404 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 405 406 /* Byte alignment */ 407 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_TD_QH_ALIGNMENT; 408 409 /* Allocate the QTD pool DMA handle */ 410 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 411 DDI_DMA_SLEEP, 0, 412 &ehcip->ehci_qtd_pool_dma_handle) != DDI_SUCCESS) { 413 414 goto failure; 415 } 416 417 /* Allocate the memory for the QTD pool */ 418 if (ddi_dma_mem_alloc(ehcip->ehci_qtd_pool_dma_handle, 419 ehci_qtd_pool_size * sizeof (ehci_qtd_t), 420 &dev_attr, 421 DDI_DMA_CONSISTENT, 422 DDI_DMA_SLEEP, 423 0, 424 (caddr_t *)&ehcip->ehci_qtd_pool_addr, 425 &real_length, 426 &ehcip->ehci_qtd_pool_mem_handle)) { 427 428 goto failure; 429 } 430 431 /* Map the QTD pool into the I/O address space */ 432 result = ddi_dma_addr_bind_handle( 433 ehcip->ehci_qtd_pool_dma_handle, 434 NULL, 435 (caddr_t)ehcip->ehci_qtd_pool_addr, 436 real_length, 437 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 438 DDI_DMA_SLEEP, 439 NULL, 440 &ehcip->ehci_qtd_pool_cookie, 441 &ccount); 442 443 bzero((void *)ehcip->ehci_qtd_pool_addr, 444 ehci_qtd_pool_size * sizeof (ehci_qtd_t)); 445 446 /* Process the result */ 447 if (result == DDI_DMA_MAPPED) { 448 /* The cookie count should be 1 */ 449 if (ccount != 1) { 450 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 451 "ehci_allocate_pools: More than 1 cookie"); 452 453 goto failure; 454 } 455 } else { 456 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 457 "ehci_allocate_pools: Result = %d", result); 458 459 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 460 461 goto failure; 462 } 463 464 /* 465 * DMA addresses for QTD pools are bound 466 */ 467 ehcip->ehci_dma_addr_bind_flag |= EHCI_QTD_POOL_BOUND; 468 469 /* Initialize the QTD pool */ 470 for (i = 0; i < ehci_qtd_pool_size; i ++) { 471 Set_QTD(ehcip->ehci_qtd_pool_addr[i]. 472 qtd_state, EHCI_QTD_FREE); 473 } 474 475 /* Allocate the QTD pool DMA handle */ 476 if (ddi_dma_alloc_handle(ehcip->ehci_dip, 477 &ehcip->ehci_dma_attr, 478 DDI_DMA_SLEEP, 479 0, 480 &ehcip->ehci_qh_pool_dma_handle) != DDI_SUCCESS) { 481 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 482 "ehci_allocate_pools: ddi_dma_alloc_handle failed"); 483 484 goto failure; 485 } 486 487 /* Allocate the memory for the QH pool */ 488 if (ddi_dma_mem_alloc(ehcip->ehci_qh_pool_dma_handle, 489 ehci_qh_pool_size * sizeof (ehci_qh_t), 490 &dev_attr, 491 DDI_DMA_CONSISTENT, 492 DDI_DMA_SLEEP, 493 0, 494 (caddr_t *)&ehcip->ehci_qh_pool_addr, 495 &real_length, 496 &ehcip->ehci_qh_pool_mem_handle) != DDI_SUCCESS) { 497 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 498 "ehci_allocate_pools: ddi_dma_mem_alloc failed"); 499 500 goto failure; 501 } 502 503 result = ddi_dma_addr_bind_handle(ehcip->ehci_qh_pool_dma_handle, 504 NULL, 505 (caddr_t)ehcip->ehci_qh_pool_addr, 506 real_length, 507 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 508 DDI_DMA_SLEEP, 509 NULL, 510 &ehcip->ehci_qh_pool_cookie, 511 &ccount); 512 513 bzero((void *)ehcip->ehci_qh_pool_addr, 514 ehci_qh_pool_size * sizeof (ehci_qh_t)); 515 516 /* Process the result */ 517 if (result == DDI_DMA_MAPPED) { 518 /* The cookie count should be 1 */ 519 if (ccount != 1) { 520 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 521 "ehci_allocate_pools: More than 1 cookie"); 522 523 goto failure; 524 } 525 } else { 526 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 527 528 goto failure; 529 } 530 531 /* 532 * DMA addresses for QH pools are bound 533 */ 534 ehcip->ehci_dma_addr_bind_flag |= EHCI_QH_POOL_BOUND; 535 536 /* Initialize the QH pool */ 537 for (i = 0; i < ehci_qh_pool_size; i ++) { 538 Set_QH(ehcip->ehci_qh_pool_addr[i].qh_state, EHCI_QH_FREE); 539 } 540 541 /* Byte alignment */ 542 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 543 544 return (DDI_SUCCESS); 545 546 failure: 547 /* Byte alignment */ 548 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 549 550 return (DDI_FAILURE); 551 } 552 553 554 /* 555 * ehci_decode_ddi_dma_addr_bind_handle_result: 556 * 557 * Process the return values of ddi_dma_addr_bind_handle() 558 */ 559 void 560 ehci_decode_ddi_dma_addr_bind_handle_result( 561 ehci_state_t *ehcip, 562 int result) 563 { 564 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ehcip->ehci_log_hdl, 565 "ehci_decode_ddi_dma_addr_bind_handle_result:"); 566 567 switch (result) { 568 case DDI_DMA_PARTIAL_MAP: 569 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 570 "Partial transfers not allowed"); 571 break; 572 case DDI_DMA_INUSE: 573 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 574 "Handle is in use"); 575 break; 576 case DDI_DMA_NORESOURCES: 577 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 578 "No resources"); 579 break; 580 case DDI_DMA_NOMAPPING: 581 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 582 "No mapping"); 583 break; 584 case DDI_DMA_TOOBIG: 585 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 586 "Object is too big"); 587 break; 588 default: 589 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 590 "Unknown dma error"); 591 } 592 } 593 594 595 /* 596 * ehci_map_regs: 597 * 598 * The Host Controller (HC) contains a set of on-chip operational registers 599 * and which should be mapped into a non-cacheable portion of the system 600 * addressable space. 601 */ 602 int 603 ehci_map_regs(ehci_state_t *ehcip) 604 { 605 ddi_device_acc_attr_t attr; 606 uint16_t cmd_reg; 607 uint_t length; 608 609 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_map_regs:"); 610 611 /* Check to make sure we have memory access */ 612 if (pci_config_setup(ehcip->ehci_dip, 613 &ehcip->ehci_config_handle) != DDI_SUCCESS) { 614 615 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 616 "ehci_map_regs: Config error"); 617 618 return (DDI_FAILURE); 619 } 620 621 /* Make sure Memory Access Enable is set */ 622 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 623 624 if (!(cmd_reg & PCI_COMM_MAE)) { 625 626 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 627 "ehci_map_regs: Memory base address access disabled"); 628 629 return (DDI_FAILURE); 630 } 631 632 /* The host controller will be little endian */ 633 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 634 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 635 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 636 637 /* Map in EHCI Capability registers */ 638 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 639 (caddr_t *)&ehcip->ehci_capsp, 0, 640 sizeof (ehci_caps_t), &attr, 641 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 642 643 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 644 "ehci_map_regs: Map setup error"); 645 646 return (DDI_FAILURE); 647 } 648 649 length = ddi_get8(ehcip->ehci_caps_handle, 650 (uint8_t *)&ehcip->ehci_capsp->ehci_caps_length); 651 652 /* Free the original mapping */ 653 ddi_regs_map_free(&ehcip->ehci_caps_handle); 654 655 /* Re-map in EHCI Capability and Operational registers */ 656 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 657 (caddr_t *)&ehcip->ehci_capsp, 0, 658 length + sizeof (ehci_regs_t), &attr, 659 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 660 661 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 662 "ehci_map_regs: Map setup error"); 663 664 return (DDI_FAILURE); 665 } 666 667 /* Get the pointer to EHCI Operational Register */ 668 ehcip->ehci_regsp = (ehci_regs_t *) 669 ((uintptr_t)ehcip->ehci_capsp + length); 670 671 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 672 "ehci_map_regs: Capsp 0x%p Regsp 0x%p\n", 673 (void *)ehcip->ehci_capsp, (void *)ehcip->ehci_regsp); 674 675 return (DDI_SUCCESS); 676 } 677 678 /* 679 * The following simulated polling is for debugging purposes only. 680 * It is activated on x86 by setting usb-polling=true in GRUB or ehci.conf. 681 */ 682 static int 683 ehci_is_polled(dev_info_t *dip) 684 { 685 int ret; 686 char *propval; 687 688 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 689 "usb-polling", &propval) != DDI_SUCCESS) 690 691 return (0); 692 693 ret = (strcmp(propval, "true") == 0); 694 ddi_prop_free(propval); 695 696 return (ret); 697 } 698 699 static void 700 ehci_poll_intr(void *arg) 701 { 702 /* poll every msec */ 703 for (;;) { 704 (void) ehci_intr(arg, NULL); 705 delay(drv_usectohz(1000)); 706 } 707 } 708 709 /* 710 * ehci_register_intrs_and_init_mutex: 711 * 712 * Register interrupts and initialize each mutex and condition variables 713 */ 714 int 715 ehci_register_intrs_and_init_mutex(ehci_state_t *ehcip) 716 { 717 int intr_types; 718 719 #if defined(__x86) 720 uint8_t iline; 721 #endif 722 723 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 724 "ehci_register_intrs_and_init_mutex:"); 725 726 /* 727 * There is a known MSI hardware bug with the EHCI controller 728 * of ULI1575 southbridge. Hence MSI is disabled for this chip. 729 */ 730 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 731 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) { 732 ehcip->ehci_msi_enabled = B_FALSE; 733 } else { 734 /* Set the MSI enable flag from the global EHCI MSI tunable */ 735 ehcip->ehci_msi_enabled = ehci_enable_msi; 736 } 737 738 /* launch polling thread instead of enabling pci interrupt */ 739 if (ehci_is_polled(ehcip->ehci_dip)) { 740 extern pri_t maxclsyspri; 741 742 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 743 "ehci_register_intrs_and_init_mutex: " 744 "running in simulated polled mode"); 745 746 (void) thread_create(NULL, 0, ehci_poll_intr, ehcip, 0, &p0, 747 TS_RUN, maxclsyspri); 748 749 goto skip_intr; 750 } 751 752 #if defined(__x86) 753 /* 754 * Make sure that the interrupt pin is connected to the 755 * interrupt controller on x86. Interrupt line 255 means 756 * "unknown" or "not connected" (PCI spec 6.2.4, footnote 43). 757 * If we would return failure when interrupt line equals 255, then 758 * high speed devices will be routed to companion host controllers. 759 * However, it is not necessary to return failure here, and 760 * o/uhci codes don't check the interrupt line either. 761 * But it's good to log a message here for debug purposes. 762 */ 763 iline = pci_config_get8(ehcip->ehci_config_handle, 764 PCI_CONF_ILINE); 765 766 if (iline == 255) { 767 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 768 "ehci_register_intrs_and_init_mutex: " 769 "interrupt line value out of range (%d)", 770 iline); 771 } 772 #endif /* __x86 */ 773 774 /* Get supported interrupt types */ 775 if (ddi_intr_get_supported_types(ehcip->ehci_dip, 776 &intr_types) != DDI_SUCCESS) { 777 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 778 "ehci_register_intrs_and_init_mutex: " 779 "ddi_intr_get_supported_types failed"); 780 781 return (DDI_FAILURE); 782 } 783 784 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 785 "ehci_register_intrs_and_init_mutex: " 786 "supported interrupt types 0x%x", intr_types); 787 788 if ((intr_types & DDI_INTR_TYPE_MSI) && ehcip->ehci_msi_enabled) { 789 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_MSI) 790 != DDI_SUCCESS) { 791 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 792 "ehci_register_intrs_and_init_mutex: MSI " 793 "registration failed, trying FIXED interrupt \n"); 794 } else { 795 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 796 "ehci_register_intrs_and_init_mutex: " 797 "Using MSI interrupt type\n"); 798 799 ehcip->ehci_intr_type = DDI_INTR_TYPE_MSI; 800 ehcip->ehci_flags |= EHCI_INTR; 801 } 802 } 803 804 if ((!(ehcip->ehci_flags & EHCI_INTR)) && 805 (intr_types & DDI_INTR_TYPE_FIXED)) { 806 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_FIXED) 807 != DDI_SUCCESS) { 808 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 809 "ehci_register_intrs_and_init_mutex: " 810 "FIXED interrupt registration failed\n"); 811 812 return (DDI_FAILURE); 813 } 814 815 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 816 "ehci_register_intrs_and_init_mutex: " 817 "Using FIXED interrupt type\n"); 818 819 ehcip->ehci_intr_type = DDI_INTR_TYPE_FIXED; 820 ehcip->ehci_flags |= EHCI_INTR; 821 } 822 823 skip_intr: 824 /* Create prototype for advance on async schedule */ 825 cv_init(&ehcip->ehci_async_schedule_advance_cv, 826 NULL, CV_DRIVER, NULL); 827 828 return (DDI_SUCCESS); 829 } 830 831 832 /* 833 * ehci_add_intrs: 834 * 835 * Register FIXED or MSI interrupts. 836 */ 837 static int 838 ehci_add_intrs(ehci_state_t *ehcip, 839 int intr_type) 840 { 841 int actual, avail, intr_size, count = 0; 842 int i, flag, ret; 843 844 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 845 "ehci_add_intrs: interrupt type 0x%x", intr_type); 846 847 /* Get number of interrupts */ 848 ret = ddi_intr_get_nintrs(ehcip->ehci_dip, intr_type, &count); 849 if ((ret != DDI_SUCCESS) || (count == 0)) { 850 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 851 "ehci_add_intrs: ddi_intr_get_nintrs() failure, " 852 "ret: %d, count: %d", ret, count); 853 854 return (DDI_FAILURE); 855 } 856 857 /* Get number of available interrupts */ 858 ret = ddi_intr_get_navail(ehcip->ehci_dip, intr_type, &avail); 859 if ((ret != DDI_SUCCESS) || (avail == 0)) { 860 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 861 "ehci_add_intrs: ddi_intr_get_navail() failure, " 862 "ret: %d, count: %d", ret, count); 863 864 return (DDI_FAILURE); 865 } 866 867 if (avail < count) { 868 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 869 "ehci_add_intrs: ehci_add_intrs: nintrs () " 870 "returned %d, navail returned %d\n", count, avail); 871 } 872 873 /* Allocate an array of interrupt handles */ 874 intr_size = count * sizeof (ddi_intr_handle_t); 875 ehcip->ehci_htable = kmem_zalloc(intr_size, KM_SLEEP); 876 877 flag = (intr_type == DDI_INTR_TYPE_MSI) ? 878 DDI_INTR_ALLOC_STRICT:DDI_INTR_ALLOC_NORMAL; 879 880 /* call ddi_intr_alloc() */ 881 ret = ddi_intr_alloc(ehcip->ehci_dip, ehcip->ehci_htable, 882 intr_type, 0, count, &actual, flag); 883 884 if ((ret != DDI_SUCCESS) || (actual == 0)) { 885 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 886 "ehci_add_intrs: ddi_intr_alloc() failed %d", ret); 887 888 kmem_free(ehcip->ehci_htable, intr_size); 889 890 return (DDI_FAILURE); 891 } 892 893 if (actual < count) { 894 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 895 "ehci_add_intrs: Requested: %d, Received: %d\n", 896 count, actual); 897 898 for (i = 0; i < actual; i++) 899 (void) ddi_intr_free(ehcip->ehci_htable[i]); 900 901 kmem_free(ehcip->ehci_htable, intr_size); 902 903 return (DDI_FAILURE); 904 } 905 906 ehcip->ehci_intr_cnt = actual; 907 908 if ((ret = ddi_intr_get_pri(ehcip->ehci_htable[0], 909 &ehcip->ehci_intr_pri)) != DDI_SUCCESS) { 910 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 911 "ehci_add_intrs: ddi_intr_get_pri() failed %d", ret); 912 913 for (i = 0; i < actual; i++) 914 (void) ddi_intr_free(ehcip->ehci_htable[i]); 915 916 kmem_free(ehcip->ehci_htable, intr_size); 917 918 return (DDI_FAILURE); 919 } 920 921 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 922 "ehci_add_intrs: Supported Interrupt priority 0x%x", 923 ehcip->ehci_intr_pri); 924 925 /* Test for high level mutex */ 926 if (ehcip->ehci_intr_pri >= ddi_intr_get_hilevel_pri()) { 927 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 928 "ehci_add_intrs: Hi level interrupt not supported"); 929 930 for (i = 0; i < actual; i++) 931 (void) ddi_intr_free(ehcip->ehci_htable[i]); 932 933 kmem_free(ehcip->ehci_htable, intr_size); 934 935 return (DDI_FAILURE); 936 } 937 938 /* Initialize the mutex */ 939 mutex_init(&ehcip->ehci_int_mutex, NULL, MUTEX_DRIVER, 940 DDI_INTR_PRI(ehcip->ehci_intr_pri)); 941 942 /* Call ddi_intr_add_handler() */ 943 for (i = 0; i < actual; i++) { 944 if ((ret = ddi_intr_add_handler(ehcip->ehci_htable[i], 945 ehci_intr, (caddr_t)ehcip, 946 (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 947 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 948 "ehci_add_intrs:ddi_intr_add_handler() " 949 "failed %d", ret); 950 951 for (i = 0; i < actual; i++) 952 (void) ddi_intr_free(ehcip->ehci_htable[i]); 953 954 mutex_destroy(&ehcip->ehci_int_mutex); 955 kmem_free(ehcip->ehci_htable, intr_size); 956 957 return (DDI_FAILURE); 958 } 959 } 960 961 if ((ret = ddi_intr_get_cap(ehcip->ehci_htable[0], 962 &ehcip->ehci_intr_cap)) != DDI_SUCCESS) { 963 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 964 "ehci_add_intrs: ddi_intr_get_cap() failed %d", ret); 965 966 for (i = 0; i < actual; i++) { 967 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 968 (void) ddi_intr_free(ehcip->ehci_htable[i]); 969 } 970 971 mutex_destroy(&ehcip->ehci_int_mutex); 972 kmem_free(ehcip->ehci_htable, intr_size); 973 974 return (DDI_FAILURE); 975 } 976 977 /* Enable all interrupts */ 978 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 979 /* Call ddi_intr_block_enable() for MSI interrupts */ 980 (void) ddi_intr_block_enable(ehcip->ehci_htable, 981 ehcip->ehci_intr_cnt); 982 } else { 983 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 984 for (i = 0; i < ehcip->ehci_intr_cnt; i++) 985 (void) ddi_intr_enable(ehcip->ehci_htable[i]); 986 } 987 988 return (DDI_SUCCESS); 989 } 990 991 992 /* 993 * ehci_init_hardware 994 * 995 * take control from BIOS, reset EHCI host controller, and check version, etc. 996 */ 997 int 998 ehci_init_hardware(ehci_state_t *ehcip) 999 { 1000 int revision; 1001 uint16_t cmd_reg; 1002 int abort_on_BIOS_take_over_failure; 1003 1004 /* Take control from the BIOS */ 1005 if (ehci_take_control(ehcip) != USB_SUCCESS) { 1006 1007 /* read .conf file properties */ 1008 abort_on_BIOS_take_over_failure = 1009 ddi_prop_get_int(DDI_DEV_T_ANY, 1010 ehcip->ehci_dip, DDI_PROP_DONTPASS, 1011 "abort-on-BIOS-take-over-failure", 0); 1012 1013 if (abort_on_BIOS_take_over_failure) { 1014 1015 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1016 "Unable to take control from BIOS."); 1017 1018 return (DDI_FAILURE); 1019 } 1020 1021 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1022 "Unable to take control from BIOS. Failure is ignored."); 1023 } 1024 1025 /* set Memory Master Enable */ 1026 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 1027 cmd_reg |= (PCI_COMM_MAE | PCI_COMM_ME); 1028 pci_config_put16(ehcip->ehci_config_handle, PCI_CONF_COMM, cmd_reg); 1029 1030 /* Reset the EHCI host controller */ 1031 Set_OpReg(ehci_command, 1032 Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET); 1033 1034 /* Wait 10ms for reset to complete */ 1035 drv_usecwait(EHCI_RESET_TIMEWAIT); 1036 1037 ASSERT(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED); 1038 1039 /* Verify the version number */ 1040 revision = Get_16Cap(ehci_version); 1041 1042 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1043 "ehci_init_hardware: Revision 0x%x", revision); 1044 1045 /* 1046 * EHCI driver supports EHCI host controllers compliant to 1047 * 0.95 and higher revisions of EHCI specifications. 1048 */ 1049 if (revision < EHCI_REVISION_0_95) { 1050 1051 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1052 "Revision 0x%x is not supported", revision); 1053 1054 return (DDI_FAILURE); 1055 } 1056 1057 if (ehcip->ehci_hc_soft_state == EHCI_CTLR_INIT_STATE) { 1058 1059 /* Initialize the Frame list base address area */ 1060 if (ehci_init_periodic_frame_lst_table(ehcip) != DDI_SUCCESS) { 1061 1062 return (DDI_FAILURE); 1063 } 1064 1065 /* 1066 * For performance reasons, do not insert anything into the 1067 * asynchronous list or activate the asynch list schedule until 1068 * there is a valid QH. 1069 */ 1070 ehcip->ehci_head_of_async_sched_list = NULL; 1071 1072 if ((ehcip->ehci_vendor_id == PCI_VENDOR_VIA) && 1073 (ehci_vt62x2_workaround & EHCI_VIA_ASYNC_SCHEDULE)) { 1074 /* 1075 * The driver is unable to reliably stop the asynch 1076 * list schedule on VIA VT6202 controllers, so we 1077 * always keep a dummy QH on the list. 1078 */ 1079 ehci_qh_t *dummy_async_qh = 1080 ehci_alloc_qh(ehcip, NULL, NULL); 1081 1082 Set_QH(dummy_async_qh->qh_link_ptr, 1083 ((ehci_qh_cpu_to_iommu(ehcip, dummy_async_qh) & 1084 EHCI_QH_LINK_PTR) | EHCI_QH_LINK_REF_QH)); 1085 1086 /* Set this QH to be the "head" of the circular list */ 1087 Set_QH(dummy_async_qh->qh_ctrl, 1088 Get_QH(dummy_async_qh->qh_ctrl) | 1089 EHCI_QH_CTRL_RECLAIM_HEAD); 1090 1091 Set_QH(dummy_async_qh->qh_next_qtd, 1092 EHCI_QH_NEXT_QTD_PTR_VALID); 1093 Set_QH(dummy_async_qh->qh_alt_next_qtd, 1094 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1095 1096 ehcip->ehci_head_of_async_sched_list = dummy_async_qh; 1097 ehcip->ehci_open_async_count++; 1098 } 1099 } 1100 1101 return (DDI_SUCCESS); 1102 } 1103 1104 1105 /* 1106 * ehci_init_workaround 1107 * 1108 * some workarounds during initializing ehci 1109 */ 1110 int 1111 ehci_init_workaround(ehci_state_t *ehcip) 1112 { 1113 /* 1114 * Acer Labs Inc. M5273 EHCI controller does not send 1115 * interrupts unless the Root hub ports are routed to the EHCI 1116 * host controller; so route the ports now, before we test for 1117 * the presence of SOFs interrupts. 1118 */ 1119 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1120 /* Route all Root hub ports to EHCI host controller */ 1121 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1122 } 1123 1124 /* 1125 * VIA chips have some issues and may not work reliably. 1126 * Revisions >= 0x80 are part of a southbridge and appear 1127 * to be reliable with the workaround. 1128 * For revisions < 0x80, if we were bound using class 1129 * complain, else proceed. This will allow the user to 1130 * bind ehci specifically to this chip and not have the 1131 * warnings 1132 */ 1133 if (ehcip->ehci_vendor_id == PCI_VENDOR_VIA) { 1134 1135 if (ehcip->ehci_rev_id >= PCI_VIA_REVISION_6212) { 1136 1137 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1138 "ehci_init_workaround: Applying VIA workarounds " 1139 "for the 6212 chip."); 1140 1141 } else if (strcmp(DEVI(ehcip->ehci_dip)->devi_binding_name, 1142 "pciclass,0c0320") == 0) { 1143 1144 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1145 "Due to recently discovered incompatibilities"); 1146 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1147 "with this USB controller, USB2.x transfer"); 1148 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1149 "support has been disabled. This device will"); 1150 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1151 "continue to function as a USB1.x controller."); 1152 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1153 "If you are interested in enabling USB2.x"); 1154 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1155 "support please, refer to the ehci(7D) man page."); 1156 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1157 "Please also refer to www.sun.com/io for"); 1158 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1159 "Solaris Ready products and to"); 1160 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1161 "www.sun.com/bigadmin/hcl for additional"); 1162 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1163 "compatible USB products."); 1164 1165 return (DDI_FAILURE); 1166 1167 } else if (ehci_vt62x2_workaround) { 1168 1169 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1170 "Applying VIA workarounds"); 1171 } 1172 } 1173 1174 return (DDI_SUCCESS); 1175 } 1176 1177 1178 /* 1179 * ehci_init_check_status 1180 * 1181 * Check if EHCI host controller is running 1182 */ 1183 int 1184 ehci_init_check_status(ehci_state_t *ehcip) 1185 { 1186 clock_t sof_time_wait; 1187 1188 /* 1189 * Get the number of clock ticks to wait. 1190 * This is based on the maximum time it takes for a frame list rollover 1191 * and maximum time wait for SOFs to begin. 1192 */ 1193 sof_time_wait = drv_usectohz((EHCI_NUM_PERIODIC_FRAME_LISTS * 1000) + 1194 EHCI_SOF_TIMEWAIT); 1195 1196 /* Tell the ISR to broadcast ehci_async_schedule_advance_cv */ 1197 ehcip->ehci_flags |= EHCI_CV_INTR; 1198 1199 /* We need to add a delay to allow the chip time to start running */ 1200 (void) cv_reltimedwait(&ehcip->ehci_async_schedule_advance_cv, 1201 &ehcip->ehci_int_mutex, sof_time_wait, TR_CLOCK_TICK); 1202 1203 /* 1204 * Check EHCI host controller is running, otherwise return failure. 1205 */ 1206 if ((ehcip->ehci_flags & EHCI_CV_INTR) || 1207 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 1208 1209 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1210 "No SOF interrupts have been received, this USB EHCI host" 1211 "controller is unusable"); 1212 1213 /* 1214 * Route all Root hub ports to Classic host 1215 * controller, in case this is an unusable ALI M5273 1216 * EHCI controller. 1217 */ 1218 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1219 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1220 } 1221 1222 return (DDI_FAILURE); 1223 } 1224 1225 return (DDI_SUCCESS); 1226 } 1227 1228 1229 /* 1230 * ehci_init_ctlr: 1231 * 1232 * Initialize the Host Controller (HC). 1233 */ 1234 int 1235 ehci_init_ctlr(ehci_state_t *ehcip, 1236 int init_type) 1237 { 1238 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_init_ctlr:"); 1239 1240 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1241 1242 if (ehci_init_hardware(ehcip) != DDI_SUCCESS) { 1243 1244 return (DDI_FAILURE); 1245 } 1246 } 1247 1248 /* 1249 * Check for Asynchronous schedule park capability feature. If this 1250 * feature is supported, then, program ehci command register with 1251 * appropriate values.. 1252 */ 1253 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_ASYNC_SCHED_PARK_CAP) { 1254 1255 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1256 "ehci_init_ctlr: Async park mode is supported"); 1257 1258 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1259 (EHCI_CMD_ASYNC_PARK_ENABLE | 1260 EHCI_CMD_ASYNC_PARK_COUNT_3))); 1261 } 1262 1263 /* 1264 * Check for programmable periodic frame list feature. If this 1265 * feature is supported, then, program ehci command register with 1266 * 1024 frame list value. 1267 */ 1268 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_PROG_FRAME_LIST_FLAG) { 1269 1270 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1271 "ehci_init_ctlr: Variable programmable periodic " 1272 "frame list is supported"); 1273 1274 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1275 EHCI_CMD_FRAME_1024_SIZE)); 1276 } 1277 1278 /* 1279 * Currently EHCI driver doesn't support 64 bit addressing. 1280 * 1281 * If we are using 64 bit addressing capability, then, program 1282 * ehci_ctrl_segment register with 4 Gigabyte segment where all 1283 * of the interface data structures are allocated. 1284 */ 1285 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_64BIT_ADDR_CAP) { 1286 1287 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1288 "ehci_init_ctlr: EHCI driver doesn't support " 1289 "64 bit addressing"); 1290 } 1291 1292 /* 64 bit addressing is not support */ 1293 Set_OpReg(ehci_ctrl_segment, 0x00000000); 1294 1295 /* Turn on/off the schedulers */ 1296 ehci_toggle_scheduler(ehcip); 1297 1298 /* Set host controller soft state to operational */ 1299 ehcip->ehci_hc_soft_state = EHCI_CTLR_OPERATIONAL_STATE; 1300 1301 /* 1302 * Set the Periodic Frame List Base Address register with the 1303 * starting physical address of the Periodic Frame List. 1304 */ 1305 Set_OpReg(ehci_periodic_list_base, 1306 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 1307 EHCI_PERIODIC_LIST_BASE)); 1308 1309 /* 1310 * Set ehci_interrupt to enable all interrupts except Root 1311 * Hub Status change interrupt. 1312 */ 1313 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 1314 EHCI_INTR_FRAME_LIST_ROLLOVER | EHCI_INTR_USB_ERROR | 1315 EHCI_INTR_USB); 1316 1317 /* 1318 * Set the desired interrupt threshold and turn on EHCI host controller. 1319 */ 1320 Set_OpReg(ehci_command, 1321 ((Get_OpReg(ehci_command) & ~EHCI_CMD_INTR_THRESHOLD) | 1322 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 1323 1324 ASSERT(Get_OpReg(ehci_command) & EHCI_CMD_HOST_CTRL_RUN); 1325 1326 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1327 1328 if (ehci_init_workaround(ehcip) != DDI_SUCCESS) { 1329 1330 /* Set host controller soft state to error */ 1331 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 1332 1333 return (DDI_FAILURE); 1334 } 1335 1336 if (ehci_init_check_status(ehcip) != DDI_SUCCESS) { 1337 1338 /* Set host controller soft state to error */ 1339 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 1340 1341 return (DDI_FAILURE); 1342 } 1343 1344 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1345 "ehci_init_ctlr: SOF's have started"); 1346 } 1347 1348 /* Route all Root hub ports to EHCI host controller */ 1349 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1350 1351 return (DDI_SUCCESS); 1352 } 1353 1354 /* 1355 * ehci_take_control: 1356 * 1357 * Handshake to take EHCI control from BIOS if necessary. Its only valid for 1358 * x86 machines, because sparc doesn't have a BIOS. 1359 * On x86 machine, the take control process includes 1360 * o get the base address of the extended capability list 1361 * o find out the capability for handoff synchronization in the list. 1362 * o check if BIOS has owned the host controller. 1363 * o set the OS Owned semaphore bit, ask the BIOS to release the ownership. 1364 * o wait for a constant time and check if BIOS has relinquished control. 1365 */ 1366 /* ARGSUSED */ 1367 static int 1368 ehci_take_control(ehci_state_t *ehcip) 1369 { 1370 #if defined(__x86) 1371 uint32_t extended_cap; 1372 uint32_t extended_cap_offset; 1373 uint32_t extended_cap_id; 1374 uint_t retry; 1375 1376 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1377 "ehci_take_control:"); 1378 1379 /* 1380 * According EHCI Spec 2.2.4, get EECP base address from HCCPARAMS 1381 * register. 1382 */ 1383 extended_cap_offset = (Get_Cap(ehci_hcc_params) & EHCI_HCC_EECP) >> 1384 EHCI_HCC_EECP_SHIFT; 1385 1386 /* 1387 * According EHCI Spec 2.2.4, if the extended capability offset is 1388 * less than 40h then its not valid. This means we don't need to 1389 * worry about BIOS handoff. 1390 */ 1391 if (extended_cap_offset < EHCI_HCC_EECP_MIN_OFFSET) { 1392 1393 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1394 "ehci_take_control: Hardware doesn't support legacy."); 1395 1396 goto success; 1397 } 1398 1399 /* 1400 * According EHCI Spec 2.1.7, A zero offset indicates the 1401 * end of the extended capability list. 1402 */ 1403 while (extended_cap_offset) { 1404 1405 /* Get the extended capability value. */ 1406 extended_cap = pci_config_get32(ehcip->ehci_config_handle, 1407 extended_cap_offset); 1408 1409 /* Get the capability ID */ 1410 extended_cap_id = (extended_cap & EHCI_EX_CAP_ID) >> 1411 EHCI_EX_CAP_ID_SHIFT; 1412 1413 /* Check if the card support legacy */ 1414 if (extended_cap_id == EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1415 break; 1416 } 1417 1418 /* Get the offset of the next capability */ 1419 extended_cap_offset = (extended_cap & EHCI_EX_CAP_NEXT_PTR) >> 1420 EHCI_EX_CAP_NEXT_PTR_SHIFT; 1421 } 1422 1423 /* 1424 * Unable to find legacy support in hardware's extended capability list. 1425 * This means we don't need to worry about BIOS handoff. 1426 */ 1427 if (extended_cap_id != EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1428 1429 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1430 "ehci_take_control: Hardware doesn't support legacy"); 1431 1432 goto success; 1433 } 1434 1435 /* Check if BIOS has owned it. */ 1436 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1437 1438 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1439 "ehci_take_control: BIOS does not own EHCI"); 1440 1441 goto success; 1442 } 1443 1444 /* 1445 * According EHCI Spec 5.1, The OS driver initiates an ownership 1446 * request by setting the OS Owned semaphore to a one. The OS 1447 * waits for the BIOS Owned bit to go to a zero before attempting 1448 * to use the EHCI controller. The time that OS must wait for BIOS 1449 * to respond to the request for ownership is beyond the scope of 1450 * this specification. 1451 * It waits up to EHCI_TAKEOVER_WAIT_COUNT*EHCI_TAKEOVER_DELAY ms 1452 * for BIOS to release the ownership. 1453 */ 1454 extended_cap |= EHCI_LEGSUP_OS_OWNED_SEM; 1455 pci_config_put32(ehcip->ehci_config_handle, extended_cap_offset, 1456 extended_cap); 1457 1458 for (retry = 0; retry < EHCI_TAKEOVER_WAIT_COUNT; retry++) { 1459 1460 /* wait a special interval */ 1461 #ifndef __lock_lint 1462 delay(drv_usectohz(EHCI_TAKEOVER_DELAY)); 1463 #endif 1464 /* Check to see if the BIOS has released the ownership */ 1465 extended_cap = pci_config_get32( 1466 ehcip->ehci_config_handle, extended_cap_offset); 1467 1468 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1469 1470 USB_DPRINTF_L3(PRINT_MASK_ATTA, 1471 ehcip->ehci_log_hdl, 1472 "ehci_take_control: BIOS has released " 1473 "the ownership. retry = %d", retry); 1474 1475 goto success; 1476 } 1477 1478 } 1479 1480 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1481 "ehci_take_control: take control from BIOS failed."); 1482 1483 return (USB_FAILURE); 1484 1485 success: 1486 1487 #endif /* __x86 */ 1488 return (USB_SUCCESS); 1489 } 1490 1491 1492 /* 1493 * ehci_init_periodic_frame_list_table : 1494 * 1495 * Allocate the system memory and initialize Host Controller 1496 * Periodic Frame List table area. The starting of the Periodic 1497 * Frame List Table area must be 4096 byte aligned. 1498 */ 1499 static int 1500 ehci_init_periodic_frame_lst_table(ehci_state_t *ehcip) 1501 { 1502 ddi_device_acc_attr_t dev_attr; 1503 size_t real_length; 1504 uint_t ccount; 1505 int result; 1506 1507 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1508 1509 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1510 "ehci_init_periodic_frame_lst_table:"); 1511 1512 /* The host controller will be little endian */ 1513 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1514 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1515 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1516 1517 /* Force the required 4K restrictive alignment */ 1518 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_PFL_ALIGNMENT; 1519 1520 /* Create space for the Periodic Frame List */ 1521 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 1522 DDI_DMA_SLEEP, 0, &ehcip->ehci_pflt_dma_handle) != DDI_SUCCESS) { 1523 1524 goto failure; 1525 } 1526 1527 if (ddi_dma_mem_alloc(ehcip->ehci_pflt_dma_handle, 1528 sizeof (ehci_periodic_frame_list_t), 1529 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 1530 0, (caddr_t *)&ehcip->ehci_periodic_frame_list_tablep, 1531 &real_length, &ehcip->ehci_pflt_mem_handle)) { 1532 1533 goto failure; 1534 } 1535 1536 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1537 "ehci_init_periodic_frame_lst_table: " 1538 "Real length %lu", real_length); 1539 1540 /* Map the whole Periodic Frame List into the I/O address space */ 1541 result = ddi_dma_addr_bind_handle(ehcip->ehci_pflt_dma_handle, 1542 NULL, (caddr_t)ehcip->ehci_periodic_frame_list_tablep, 1543 real_length, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1544 DDI_DMA_SLEEP, NULL, &ehcip->ehci_pflt_cookie, &ccount); 1545 1546 if (result == DDI_DMA_MAPPED) { 1547 /* The cookie count should be 1 */ 1548 if (ccount != 1) { 1549 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1550 "ehci_init_periodic_frame_lst_table: " 1551 "More than 1 cookie"); 1552 1553 goto failure; 1554 } 1555 } else { 1556 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 1557 1558 goto failure; 1559 } 1560 1561 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1562 "ehci_init_periodic_frame_lst_table: virtual 0x%p physical 0x%x", 1563 (void *)ehcip->ehci_periodic_frame_list_tablep, 1564 ehcip->ehci_pflt_cookie.dmac_address); 1565 1566 /* 1567 * DMA addresses for Periodic Frame List are bound. 1568 */ 1569 ehcip->ehci_dma_addr_bind_flag |= EHCI_PFLT_DMA_BOUND; 1570 1571 bzero((void *)ehcip->ehci_periodic_frame_list_tablep, real_length); 1572 1573 /* Initialize the Periodic Frame List */ 1574 ehci_build_interrupt_lattice(ehcip); 1575 1576 /* Reset Byte Alignment to Default */ 1577 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1578 1579 return (DDI_SUCCESS); 1580 failure: 1581 /* Byte alignment */ 1582 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1583 1584 return (DDI_FAILURE); 1585 } 1586 1587 1588 /* 1589 * ehci_build_interrupt_lattice: 1590 * 1591 * Construct the interrupt lattice tree using static Endpoint Descriptors 1592 * (QH). This interrupt lattice tree will have total of 32 interrupt QH 1593 * lists and the Host Controller (HC) processes one interrupt QH list in 1594 * every frame. The Host Controller traverses the periodic schedule by 1595 * constructing an array offset reference from the Periodic List Base Address 1596 * register and bits 12 to 3 of Frame Index register. It fetches the element 1597 * and begins traversing the graph of linked schedule data structures. 1598 */ 1599 static void 1600 ehci_build_interrupt_lattice(ehci_state_t *ehcip) 1601 { 1602 ehci_qh_t *list_array = ehcip->ehci_qh_pool_addr; 1603 ushort_t ehci_index[EHCI_NUM_PERIODIC_FRAME_LISTS]; 1604 ehci_periodic_frame_list_t *periodic_frame_list = 1605 ehcip->ehci_periodic_frame_list_tablep; 1606 ushort_t *temp, num_of_nodes; 1607 uintptr_t addr; 1608 int i, j, k; 1609 1610 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1611 "ehci_build_interrupt_lattice:"); 1612 1613 /* 1614 * Reserve the first 63 Endpoint Descriptor (QH) structures 1615 * in the pool as static endpoints & these are required for 1616 * constructing interrupt lattice tree. 1617 */ 1618 for (i = 0; i < EHCI_NUM_STATIC_NODES; i++) { 1619 Set_QH(list_array[i].qh_state, EHCI_QH_STATIC); 1620 Set_QH(list_array[i].qh_status, EHCI_QH_STS_HALTED); 1621 Set_QH(list_array[i].qh_next_qtd, EHCI_QH_NEXT_QTD_PTR_VALID); 1622 Set_QH(list_array[i].qh_alt_next_qtd, 1623 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1624 } 1625 1626 /* 1627 * Make sure that last Endpoint on the periodic frame list terminates 1628 * periodic schedule. 1629 */ 1630 Set_QH(list_array[0].qh_link_ptr, EHCI_QH_LINK_PTR_VALID); 1631 1632 /* Build the interrupt lattice tree */ 1633 for (i = 0; i < (EHCI_NUM_STATIC_NODES / 2); i++) { 1634 /* 1635 * The next pointer in the host controller endpoint 1636 * descriptor must contain an iommu address. Calculate 1637 * the offset into the cpu address and add this to the 1638 * starting iommu address. 1639 */ 1640 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *)&list_array[i]); 1641 1642 Set_QH(list_array[2*i + 1].qh_link_ptr, 1643 addr | EHCI_QH_LINK_REF_QH); 1644 Set_QH(list_array[2*i + 2].qh_link_ptr, 1645 addr | EHCI_QH_LINK_REF_QH); 1646 } 1647 1648 /* Build the tree bottom */ 1649 temp = (unsigned short *) 1650 kmem_zalloc(EHCI_NUM_PERIODIC_FRAME_LISTS * 2, KM_SLEEP); 1651 1652 num_of_nodes = 1; 1653 1654 /* 1655 * Initialize the values which are used for setting up head pointers 1656 * for the 32ms scheduling lists which starts from the Periodic Frame 1657 * List. 1658 */ 1659 for (i = 0; i < ehci_log_2(EHCI_NUM_PERIODIC_FRAME_LISTS); i++) { 1660 for (j = 0, k = 0; k < num_of_nodes; k++, j++) { 1661 ehci_index[j++] = temp[k]; 1662 ehci_index[j] = temp[k] + ehci_pow_2(i); 1663 } 1664 1665 num_of_nodes *= 2; 1666 for (k = 0; k < num_of_nodes; k++) 1667 temp[k] = ehci_index[k]; 1668 } 1669 1670 kmem_free((void *)temp, (EHCI_NUM_PERIODIC_FRAME_LISTS * 2)); 1671 1672 /* 1673 * Initialize the interrupt list in the Periodic Frame List Table 1674 * so that it points to the bottom of the tree. 1675 */ 1676 for (i = 0, j = 0; i < ehci_pow_2(TREE_HEIGHT); i++) { 1677 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *) 1678 (&list_array[((EHCI_NUM_STATIC_NODES + 1) / 2) + i - 1])); 1679 1680 ASSERT(addr); 1681 1682 for (k = 0; k < ehci_pow_2(TREE_HEIGHT); k++) { 1683 Set_PFLT(periodic_frame_list-> 1684 ehci_periodic_frame_list_table[ehci_index[j++]], 1685 (uint32_t)(addr | EHCI_QH_LINK_REF_QH)); 1686 } 1687 } 1688 } 1689 1690 1691 /* 1692 * ehci_alloc_hcdi_ops: 1693 * 1694 * The HCDI interfaces or entry points are the software interfaces used by 1695 * the Universal Serial Bus Driver (USBA) to access the services of the 1696 * Host Controller Driver (HCD). During HCD initialization, inform USBA 1697 * about all available HCDI interfaces or entry points. 1698 */ 1699 usba_hcdi_ops_t * 1700 ehci_alloc_hcdi_ops(ehci_state_t *ehcip) 1701 { 1702 usba_hcdi_ops_t *usba_hcdi_ops; 1703 1704 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1705 "ehci_alloc_hcdi_ops:"); 1706 1707 usba_hcdi_ops = usba_alloc_hcdi_ops(); 1708 1709 usba_hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION; 1710 1711 usba_hcdi_ops->usba_hcdi_pm_support = ehci_hcdi_pm_support; 1712 usba_hcdi_ops->usba_hcdi_pipe_open = ehci_hcdi_pipe_open; 1713 usba_hcdi_ops->usba_hcdi_pipe_close = ehci_hcdi_pipe_close; 1714 1715 usba_hcdi_ops->usba_hcdi_pipe_reset = ehci_hcdi_pipe_reset; 1716 usba_hcdi_ops->usba_hcdi_pipe_reset_data_toggle = 1717 ehci_hcdi_pipe_reset_data_toggle; 1718 1719 usba_hcdi_ops->usba_hcdi_pipe_ctrl_xfer = ehci_hcdi_pipe_ctrl_xfer; 1720 usba_hcdi_ops->usba_hcdi_pipe_bulk_xfer = ehci_hcdi_pipe_bulk_xfer; 1721 usba_hcdi_ops->usba_hcdi_pipe_intr_xfer = ehci_hcdi_pipe_intr_xfer; 1722 usba_hcdi_ops->usba_hcdi_pipe_isoc_xfer = ehci_hcdi_pipe_isoc_xfer; 1723 1724 usba_hcdi_ops->usba_hcdi_bulk_transfer_size = 1725 ehci_hcdi_bulk_transfer_size; 1726 1727 usba_hcdi_ops->usba_hcdi_pipe_stop_intr_polling = 1728 ehci_hcdi_pipe_stop_intr_polling; 1729 usba_hcdi_ops->usba_hcdi_pipe_stop_isoc_polling = 1730 ehci_hcdi_pipe_stop_isoc_polling; 1731 1732 usba_hcdi_ops->usba_hcdi_get_current_frame_number = 1733 ehci_hcdi_get_current_frame_number; 1734 usba_hcdi_ops->usba_hcdi_get_max_isoc_pkts = 1735 ehci_hcdi_get_max_isoc_pkts; 1736 1737 usba_hcdi_ops->usba_hcdi_console_input_init = 1738 ehci_hcdi_polled_input_init; 1739 usba_hcdi_ops->usba_hcdi_console_input_enter = 1740 ehci_hcdi_polled_input_enter; 1741 usba_hcdi_ops->usba_hcdi_console_read = 1742 ehci_hcdi_polled_read; 1743 usba_hcdi_ops->usba_hcdi_console_input_exit = 1744 ehci_hcdi_polled_input_exit; 1745 usba_hcdi_ops->usba_hcdi_console_input_fini = 1746 ehci_hcdi_polled_input_fini; 1747 1748 usba_hcdi_ops->usba_hcdi_console_output_init = 1749 ehci_hcdi_polled_output_init; 1750 usba_hcdi_ops->usba_hcdi_console_output_enter = 1751 ehci_hcdi_polled_output_enter; 1752 usba_hcdi_ops->usba_hcdi_console_write = 1753 ehci_hcdi_polled_write; 1754 usba_hcdi_ops->usba_hcdi_console_output_exit = 1755 ehci_hcdi_polled_output_exit; 1756 usba_hcdi_ops->usba_hcdi_console_output_fini = 1757 ehci_hcdi_polled_output_fini; 1758 return (usba_hcdi_ops); 1759 } 1760 1761 1762 /* 1763 * Host Controller Driver (HCD) deinitialization functions 1764 */ 1765 1766 /* 1767 * ehci_cleanup: 1768 * 1769 * Cleanup on attach failure or detach 1770 */ 1771 int 1772 ehci_cleanup(ehci_state_t *ehcip) 1773 { 1774 ehci_trans_wrapper_t *tw; 1775 ehci_pipe_private_t *pp; 1776 ehci_qtd_t *qtd; 1777 int i, ctrl, rval; 1778 int flags = ehcip->ehci_flags; 1779 1780 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_cleanup:"); 1781 1782 if (flags & EHCI_RHREG) { 1783 /* Unload the root hub driver */ 1784 if (ehci_unload_root_hub_driver(ehcip) != USB_SUCCESS) { 1785 1786 return (DDI_FAILURE); 1787 } 1788 } 1789 1790 if (flags & EHCI_USBAREG) { 1791 /* Unregister this HCD instance with USBA */ 1792 usba_hcdi_unregister(ehcip->ehci_dip); 1793 } 1794 1795 if (flags & EHCI_INTR) { 1796 1797 mutex_enter(&ehcip->ehci_int_mutex); 1798 1799 /* Disable all EHCI QH list processing */ 1800 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1801 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | 1802 EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1803 1804 /* Disable all EHCI interrupts */ 1805 Set_OpReg(ehci_interrupt, 0); 1806 1807 /* wait for the next SOF */ 1808 (void) ehci_wait_for_sof(ehcip); 1809 1810 /* Route all Root hub ports to Classic host controller */ 1811 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1812 1813 /* Stop the EHCI host controller */ 1814 Set_OpReg(ehci_command, 1815 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1816 1817 mutex_exit(&ehcip->ehci_int_mutex); 1818 1819 /* Wait for sometime */ 1820 delay(drv_usectohz(EHCI_TIMEWAIT)); 1821 1822 ehci_rem_intrs(ehcip); 1823 } 1824 1825 /* Unmap the EHCI registers */ 1826 if (ehcip->ehci_caps_handle) { 1827 ddi_regs_map_free(&ehcip->ehci_caps_handle); 1828 } 1829 1830 if (ehcip->ehci_config_handle) { 1831 pci_config_teardown(&ehcip->ehci_config_handle); 1832 } 1833 1834 /* Free all the buffers */ 1835 if (ehcip->ehci_qtd_pool_addr && ehcip->ehci_qtd_pool_mem_handle) { 1836 for (i = 0; i < ehci_qtd_pool_size; i ++) { 1837 qtd = &ehcip->ehci_qtd_pool_addr[i]; 1838 ctrl = Get_QTD(ehcip-> 1839 ehci_qtd_pool_addr[i].qtd_state); 1840 1841 if ((ctrl != EHCI_QTD_FREE) && 1842 (ctrl != EHCI_QTD_DUMMY) && 1843 (qtd->qtd_trans_wrapper)) { 1844 1845 mutex_enter(&ehcip->ehci_int_mutex); 1846 1847 tw = (ehci_trans_wrapper_t *) 1848 EHCI_LOOKUP_ID((uint32_t) 1849 Get_QTD(qtd->qtd_trans_wrapper)); 1850 1851 /* Obtain the pipe private structure */ 1852 pp = tw->tw_pipe_private; 1853 1854 /* Stop the the transfer timer */ 1855 ehci_stop_xfer_timer(ehcip, tw, 1856 EHCI_REMOVE_XFER_ALWAYS); 1857 1858 ehci_deallocate_tw(ehcip, pp, tw); 1859 1860 mutex_exit(&ehcip->ehci_int_mutex); 1861 } 1862 } 1863 1864 /* 1865 * If EHCI_QTD_POOL_BOUND flag is set, then unbind 1866 * the handle for QTD pools. 1867 */ 1868 if ((ehcip->ehci_dma_addr_bind_flag & 1869 EHCI_QTD_POOL_BOUND) == EHCI_QTD_POOL_BOUND) { 1870 1871 rval = ddi_dma_unbind_handle( 1872 ehcip->ehci_qtd_pool_dma_handle); 1873 1874 ASSERT(rval == DDI_SUCCESS); 1875 } 1876 ddi_dma_mem_free(&ehcip->ehci_qtd_pool_mem_handle); 1877 } 1878 1879 /* Free the QTD pool */ 1880 if (ehcip->ehci_qtd_pool_dma_handle) { 1881 ddi_dma_free_handle(&ehcip->ehci_qtd_pool_dma_handle); 1882 } 1883 1884 if (ehcip->ehci_qh_pool_addr && ehcip->ehci_qh_pool_mem_handle) { 1885 /* 1886 * If EHCI_QH_POOL_BOUND flag is set, then unbind 1887 * the handle for QH pools. 1888 */ 1889 if ((ehcip->ehci_dma_addr_bind_flag & 1890 EHCI_QH_POOL_BOUND) == EHCI_QH_POOL_BOUND) { 1891 1892 rval = ddi_dma_unbind_handle( 1893 ehcip->ehci_qh_pool_dma_handle); 1894 1895 ASSERT(rval == DDI_SUCCESS); 1896 } 1897 1898 ddi_dma_mem_free(&ehcip->ehci_qh_pool_mem_handle); 1899 } 1900 1901 /* Free the QH pool */ 1902 if (ehcip->ehci_qh_pool_dma_handle) { 1903 ddi_dma_free_handle(&ehcip->ehci_qh_pool_dma_handle); 1904 } 1905 1906 /* Free the Periodic frame list table (PFLT) area */ 1907 if (ehcip->ehci_periodic_frame_list_tablep && 1908 ehcip->ehci_pflt_mem_handle) { 1909 /* 1910 * If EHCI_PFLT_DMA_BOUND flag is set, then unbind 1911 * the handle for PFLT. 1912 */ 1913 if ((ehcip->ehci_dma_addr_bind_flag & 1914 EHCI_PFLT_DMA_BOUND) == EHCI_PFLT_DMA_BOUND) { 1915 1916 rval = ddi_dma_unbind_handle( 1917 ehcip->ehci_pflt_dma_handle); 1918 1919 ASSERT(rval == DDI_SUCCESS); 1920 } 1921 1922 ddi_dma_mem_free(&ehcip->ehci_pflt_mem_handle); 1923 } 1924 1925 (void) ehci_isoc_cleanup(ehcip); 1926 1927 if (ehcip->ehci_pflt_dma_handle) { 1928 ddi_dma_free_handle(&ehcip->ehci_pflt_dma_handle); 1929 } 1930 1931 if (flags & EHCI_INTR) { 1932 /* Destroy the mutex */ 1933 mutex_destroy(&ehcip->ehci_int_mutex); 1934 1935 /* Destroy the async schedule advance condition variable */ 1936 cv_destroy(&ehcip->ehci_async_schedule_advance_cv); 1937 } 1938 1939 /* clean up kstat structs */ 1940 ehci_destroy_stats(ehcip); 1941 1942 /* Free ehci hcdi ops */ 1943 if (ehcip->ehci_hcdi_ops) { 1944 usba_free_hcdi_ops(ehcip->ehci_hcdi_ops); 1945 } 1946 1947 if (flags & EHCI_ZALLOC) { 1948 1949 usb_free_log_hdl(ehcip->ehci_log_hdl); 1950 1951 /* Remove all properties that might have been created */ 1952 ddi_prop_remove_all(ehcip->ehci_dip); 1953 1954 /* Free the soft state */ 1955 ddi_soft_state_free(ehci_statep, 1956 ddi_get_instance(ehcip->ehci_dip)); 1957 } 1958 1959 return (DDI_SUCCESS); 1960 } 1961 1962 1963 /* 1964 * ehci_rem_intrs: 1965 * 1966 * Unregister FIXED or MSI interrupts 1967 */ 1968 static void 1969 ehci_rem_intrs(ehci_state_t *ehcip) 1970 { 1971 int i; 1972 1973 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1974 "ehci_rem_intrs: interrupt type 0x%x", ehcip->ehci_intr_type); 1975 1976 /* Disable all interrupts */ 1977 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 1978 (void) ddi_intr_block_disable(ehcip->ehci_htable, 1979 ehcip->ehci_intr_cnt); 1980 } else { 1981 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1982 (void) ddi_intr_disable(ehcip->ehci_htable[i]); 1983 } 1984 } 1985 1986 /* Call ddi_intr_remove_handler() */ 1987 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1988 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 1989 (void) ddi_intr_free(ehcip->ehci_htable[i]); 1990 } 1991 1992 kmem_free(ehcip->ehci_htable, 1993 ehcip->ehci_intr_cnt * sizeof (ddi_intr_handle_t)); 1994 } 1995 1996 1997 /* 1998 * ehci_cpr_suspend 1999 */ 2000 int 2001 ehci_cpr_suspend(ehci_state_t *ehcip) 2002 { 2003 int i; 2004 2005 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2006 "ehci_cpr_suspend:"); 2007 2008 /* Call into the root hub and suspend it */ 2009 if (usba_hubdi_detach(ehcip->ehci_dip, DDI_SUSPEND) != DDI_SUCCESS) { 2010 2011 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2012 "ehci_cpr_suspend: root hub fails to suspend"); 2013 2014 return (DDI_FAILURE); 2015 } 2016 2017 /* Only root hub's intr pipe should be open at this time */ 2018 mutex_enter(&ehcip->ehci_int_mutex); 2019 2020 ASSERT(ehcip->ehci_open_pipe_count == 0); 2021 2022 /* Just wait till all resources are reclaimed */ 2023 i = 0; 2024 while ((ehcip->ehci_reclaim_list != NULL) && (i++ < 3)) { 2025 ehci_handle_endpoint_reclaimation(ehcip); 2026 (void) ehci_wait_for_sof(ehcip); 2027 } 2028 ASSERT(ehcip->ehci_reclaim_list == NULL); 2029 2030 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2031 "ehci_cpr_suspend: Disable HC QH list processing"); 2032 2033 /* Disable all EHCI QH list processing */ 2034 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 2035 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE))); 2036 2037 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2038 "ehci_cpr_suspend: Disable HC interrupts"); 2039 2040 /* Disable all EHCI interrupts */ 2041 Set_OpReg(ehci_interrupt, 0); 2042 2043 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2044 "ehci_cpr_suspend: Wait for the next SOF"); 2045 2046 /* Wait for the next SOF */ 2047 if (ehci_wait_for_sof(ehcip) != USB_SUCCESS) { 2048 2049 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2050 "ehci_cpr_suspend: ehci host controller suspend failed"); 2051 2052 mutex_exit(&ehcip->ehci_int_mutex); 2053 return (DDI_FAILURE); 2054 } 2055 2056 /* 2057 * Stop the ehci host controller 2058 * if usb keyboard is not connected. 2059 */ 2060 if (ehcip->ehci_polled_kbd_count == 0 || force_ehci_off != 0) { 2061 Set_OpReg(ehci_command, 2062 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 2063 2064 drv_usecwait(EHCI_RESET_TIMEWAIT); 2065 } 2066 2067 /* Set host controller soft state to suspend */ 2068 ehcip->ehci_hc_soft_state = EHCI_CTLR_SUSPEND_STATE; 2069 2070 /* Reset the host controller. This can poweroff downstream ports */ 2071 Set_OpReg(ehci_command, 2072 Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET); 2073 2074 mutex_exit(&ehcip->ehci_int_mutex); 2075 2076 return (DDI_SUCCESS); 2077 } 2078 2079 2080 /* 2081 * ehci_cpr_resume 2082 */ 2083 int 2084 ehci_cpr_resume(ehci_state_t *ehcip) 2085 { 2086 mutex_enter(&ehcip->ehci_int_mutex); 2087 2088 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2089 "ehci_cpr_resume: Restart the controller"); 2090 2091 /* Cleanup ehci specific information across cpr */ 2092 ehci_cpr_cleanup(ehcip); 2093 2094 /* Restart the controller */ 2095 if (ehci_init_ctlr(ehcip, EHCI_NORMAL_INITIALIZATION) != DDI_SUCCESS) { 2096 2097 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2098 "ehci_cpr_resume: ehci host controller resume failed "); 2099 2100 mutex_exit(&ehcip->ehci_int_mutex); 2101 2102 return (DDI_FAILURE); 2103 } 2104 2105 mutex_exit(&ehcip->ehci_int_mutex); 2106 2107 /* Now resume the root hub */ 2108 if (usba_hubdi_attach(ehcip->ehci_dip, DDI_RESUME) != DDI_SUCCESS) { 2109 2110 return (DDI_FAILURE); 2111 } 2112 2113 return (DDI_SUCCESS); 2114 } 2115 2116 2117 /* 2118 * Bandwidth Allocation functions 2119 */ 2120 2121 /* 2122 * ehci_allocate_bandwidth: 2123 * 2124 * Figure out whether or not this interval may be supported. Return the index 2125 * into the lattice if it can be supported. Return allocation failure if it 2126 * can not be supported. 2127 */ 2128 int 2129 ehci_allocate_bandwidth( 2130 ehci_state_t *ehcip, 2131 usba_pipe_handle_data_t *ph, 2132 uint_t *pnode, 2133 uchar_t *smask, 2134 uchar_t *cmask) 2135 { 2136 int error = USB_SUCCESS; 2137 2138 /* This routine is protected by the ehci_int_mutex */ 2139 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2140 2141 /* Reset the pnode to the last checked pnode */ 2142 *pnode = 0; 2143 2144 /* Allocate high speed bandwidth */ 2145 if ((error = ehci_allocate_high_speed_bandwidth(ehcip, 2146 ph, pnode, smask, cmask)) != USB_SUCCESS) { 2147 2148 return (error); 2149 } 2150 2151 /* 2152 * For low/full speed usb devices, allocate classic TT bandwidth 2153 * in additional to high speed bandwidth. 2154 */ 2155 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2156 2157 /* Allocate classic TT bandwidth */ 2158 if ((error = ehci_allocate_classic_tt_bandwidth( 2159 ehcip, ph, *pnode)) != USB_SUCCESS) { 2160 2161 /* Deallocate high speed bandwidth */ 2162 ehci_deallocate_high_speed_bandwidth( 2163 ehcip, ph, *pnode, *smask, *cmask); 2164 } 2165 } 2166 2167 return (error); 2168 } 2169 2170 2171 /* 2172 * ehci_allocate_high_speed_bandwidth: 2173 * 2174 * Allocate high speed bandwidth for the low/full/high speed interrupt and 2175 * isochronous endpoints. 2176 */ 2177 static int 2178 ehci_allocate_high_speed_bandwidth( 2179 ehci_state_t *ehcip, 2180 usba_pipe_handle_data_t *ph, 2181 uint_t *pnode, 2182 uchar_t *smask, 2183 uchar_t *cmask) 2184 { 2185 uint_t sbandwidth, cbandwidth; 2186 int interval; 2187 usb_ep_descr_t *endpoint = &ph->p_ep; 2188 usba_device_t *child_ud; 2189 usb_port_status_t port_status; 2190 int error; 2191 2192 /* This routine is protected by the ehci_int_mutex */ 2193 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2194 2195 /* Get child's usba device structure */ 2196 child_ud = ph->p_usba_device; 2197 2198 mutex_enter(&child_ud->usb_mutex); 2199 2200 /* Get the current usb device's port status */ 2201 port_status = ph->p_usba_device->usb_port_status; 2202 2203 mutex_exit(&child_ud->usb_mutex); 2204 2205 /* 2206 * Calculate the length in bytes of a transaction on this 2207 * periodic endpoint. Return failure if maximum packet is 2208 * zero. 2209 */ 2210 error = ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2211 port_status, &sbandwidth, &cbandwidth); 2212 if (error != USB_SUCCESS) { 2213 2214 return (error); 2215 } 2216 2217 /* 2218 * Adjust polling interval to be a power of 2. 2219 * If this interval can't be supported, return 2220 * allocation failure. 2221 */ 2222 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2223 if (interval == USB_FAILURE) { 2224 2225 return (USB_FAILURE); 2226 } 2227 2228 if (port_status == USBA_HIGH_SPEED_DEV) { 2229 /* Allocate bandwidth for high speed devices */ 2230 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2231 USB_EP_ATTR_ISOCH) { 2232 error = USB_SUCCESS; 2233 } else { 2234 2235 error = ehci_find_bestfit_hs_mask(ehcip, smask, pnode, 2236 endpoint, sbandwidth, interval); 2237 } 2238 2239 *cmask = 0x00; 2240 2241 } else { 2242 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2243 USB_EP_ATTR_INTR) { 2244 2245 /* Allocate bandwidth for low speed interrupt */ 2246 error = ehci_find_bestfit_ls_intr_mask(ehcip, 2247 smask, cmask, pnode, sbandwidth, cbandwidth, 2248 interval); 2249 } else { 2250 if ((endpoint->bEndpointAddress & 2251 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2252 2253 /* Allocate bandwidth for sitd in */ 2254 error = ehci_find_bestfit_sitd_in_mask(ehcip, 2255 smask, cmask, pnode, sbandwidth, cbandwidth, 2256 interval); 2257 } else { 2258 2259 /* Allocate bandwidth for sitd out */ 2260 error = ehci_find_bestfit_sitd_out_mask(ehcip, 2261 smask, pnode, sbandwidth, interval); 2262 *cmask = 0x00; 2263 } 2264 } 2265 } 2266 2267 if (error != USB_SUCCESS) { 2268 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2269 "ehci_allocate_high_speed_bandwidth: Reached maximum " 2270 "bandwidth value and cannot allocate bandwidth for a " 2271 "given high-speed periodic endpoint"); 2272 2273 return (USB_NO_BANDWIDTH); 2274 } 2275 2276 return (error); 2277 } 2278 2279 2280 /* 2281 * ehci_allocate_classic_tt_speed_bandwidth: 2282 * 2283 * Allocate classic TT bandwidth for the low/full speed interrupt and 2284 * isochronous endpoints. 2285 */ 2286 static int 2287 ehci_allocate_classic_tt_bandwidth( 2288 ehci_state_t *ehcip, 2289 usba_pipe_handle_data_t *ph, 2290 uint_t pnode) 2291 { 2292 uint_t bandwidth, min; 2293 uint_t height, leftmost, list; 2294 usb_ep_descr_t *endpoint = &ph->p_ep; 2295 usba_device_t *child_ud, *parent_ud; 2296 usb_port_status_t port_status; 2297 int i, interval; 2298 2299 /* This routine is protected by the ehci_int_mutex */ 2300 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2301 2302 /* Get child's usba device structure */ 2303 child_ud = ph->p_usba_device; 2304 2305 mutex_enter(&child_ud->usb_mutex); 2306 2307 /* Get the current usb device's port status */ 2308 port_status = child_ud->usb_port_status; 2309 2310 /* Get the parent high speed hub's usba device structure */ 2311 parent_ud = child_ud->usb_hs_hub_usba_dev; 2312 2313 mutex_exit(&child_ud->usb_mutex); 2314 2315 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2316 "ehci_allocate_classic_tt_bandwidth: " 2317 "child_ud 0x%p parent_ud 0x%p", 2318 (void *)child_ud, (void *)parent_ud); 2319 2320 /* 2321 * Calculate the length in bytes of a transaction on this 2322 * periodic endpoint. Return failure if maximum packet is 2323 * zero. 2324 */ 2325 if (ehci_compute_classic_bandwidth(endpoint, 2326 port_status, &bandwidth) != USB_SUCCESS) { 2327 2328 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2329 "ehci_allocate_classic_tt_bandwidth: Periodic endpoint " 2330 "with zero endpoint maximum packet size is not supported"); 2331 2332 return (USB_NOT_SUPPORTED); 2333 } 2334 2335 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2336 "ehci_allocate_classic_tt_bandwidth: bandwidth %d", bandwidth); 2337 2338 mutex_enter(&parent_ud->usb_mutex); 2339 2340 /* 2341 * If the length in bytes plus the allocated bandwidth exceeds 2342 * the maximum, return bandwidth allocation failure. 2343 */ 2344 if ((parent_ud->usb_hs_hub_min_bandwidth + bandwidth) > 2345 FS_PERIODIC_BANDWIDTH) { 2346 2347 mutex_exit(&parent_ud->usb_mutex); 2348 2349 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2350 "ehci_allocate_classic_tt_bandwidth: Reached maximum " 2351 "bandwidth value and cannot allocate bandwidth for a " 2352 "given low/full speed periodic endpoint"); 2353 2354 return (USB_NO_BANDWIDTH); 2355 } 2356 2357 mutex_exit(&parent_ud->usb_mutex); 2358 2359 /* Adjust polling interval to be a power of 2 */ 2360 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2361 2362 /* Find the height in the tree */ 2363 height = ehci_lattice_height(interval); 2364 2365 /* Find the leftmost leaf in the subtree specified by the node. */ 2366 leftmost = ehci_leftmost_leaf(pnode, height); 2367 2368 mutex_enter(&parent_ud->usb_mutex); 2369 2370 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2371 list = ehci_index[leftmost + i]; 2372 2373 if ((parent_ud->usb_hs_hub_bandwidth[list] + 2374 bandwidth) > FS_PERIODIC_BANDWIDTH) { 2375 2376 mutex_exit(&parent_ud->usb_mutex); 2377 2378 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2379 "ehci_allocate_classic_tt_bandwidth: Reached " 2380 "maximum bandwidth value and cannot allocate " 2381 "bandwidth for low/full periodic endpoint"); 2382 2383 return (USB_NO_BANDWIDTH); 2384 } 2385 } 2386 2387 /* 2388 * All the leaves for this node must be updated with the bandwidth. 2389 */ 2390 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2391 list = ehci_index[leftmost + i]; 2392 parent_ud->usb_hs_hub_bandwidth[list] += bandwidth; 2393 } 2394 2395 /* Find the leaf with the smallest allocated bandwidth */ 2396 min = parent_ud->usb_hs_hub_bandwidth[0]; 2397 2398 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2399 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2400 min = parent_ud->usb_hs_hub_bandwidth[i]; 2401 } 2402 } 2403 2404 /* Save the minimum for later use */ 2405 parent_ud->usb_hs_hub_min_bandwidth = min; 2406 2407 mutex_exit(&parent_ud->usb_mutex); 2408 2409 return (USB_SUCCESS); 2410 } 2411 2412 2413 /* 2414 * ehci_deallocate_bandwidth: 2415 * 2416 * Deallocate bandwidth for the given node in the lattice and the length 2417 * of transfer. 2418 */ 2419 void 2420 ehci_deallocate_bandwidth( 2421 ehci_state_t *ehcip, 2422 usba_pipe_handle_data_t *ph, 2423 uint_t pnode, 2424 uchar_t smask, 2425 uchar_t cmask) 2426 { 2427 /* This routine is protected by the ehci_int_mutex */ 2428 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2429 2430 ehci_deallocate_high_speed_bandwidth(ehcip, ph, pnode, smask, cmask); 2431 2432 /* 2433 * For low/full speed usb devices, deallocate classic TT bandwidth 2434 * in additional to high speed bandwidth. 2435 */ 2436 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2437 2438 /* Deallocate classic TT bandwidth */ 2439 ehci_deallocate_classic_tt_bandwidth(ehcip, ph, pnode); 2440 } 2441 } 2442 2443 2444 /* 2445 * ehci_deallocate_high_speed_bandwidth: 2446 * 2447 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2448 */ 2449 static void 2450 ehci_deallocate_high_speed_bandwidth( 2451 ehci_state_t *ehcip, 2452 usba_pipe_handle_data_t *ph, 2453 uint_t pnode, 2454 uchar_t smask, 2455 uchar_t cmask) 2456 { 2457 uint_t height, leftmost; 2458 uint_t list_count; 2459 uint_t sbandwidth, cbandwidth; 2460 int interval; 2461 usb_ep_descr_t *endpoint = &ph->p_ep; 2462 usba_device_t *child_ud; 2463 usb_port_status_t port_status; 2464 2465 /* This routine is protected by the ehci_int_mutex */ 2466 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2467 2468 /* Get child's usba device structure */ 2469 child_ud = ph->p_usba_device; 2470 2471 mutex_enter(&child_ud->usb_mutex); 2472 2473 /* Get the current usb device's port status */ 2474 port_status = ph->p_usba_device->usb_port_status; 2475 2476 mutex_exit(&child_ud->usb_mutex); 2477 2478 (void) ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2479 port_status, &sbandwidth, &cbandwidth); 2480 2481 /* Adjust polling interval to be a power of 2 */ 2482 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2483 2484 /* Find the height in the tree */ 2485 height = ehci_lattice_height(interval); 2486 2487 /* 2488 * Find the leftmost leaf in the subtree specified by the node 2489 */ 2490 leftmost = ehci_leftmost_leaf(pnode, height); 2491 2492 list_count = EHCI_NUM_INTR_QH_LISTS/interval; 2493 2494 /* Delete the bandwidth from the appropriate lists */ 2495 if (port_status == USBA_HIGH_SPEED_DEV) { 2496 2497 ehci_update_bw_availability(ehcip, -sbandwidth, 2498 leftmost, list_count, smask); 2499 } else { 2500 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2501 USB_EP_ATTR_INTR) { 2502 2503 ehci_update_bw_availability(ehcip, -sbandwidth, 2504 leftmost, list_count, smask); 2505 ehci_update_bw_availability(ehcip, -cbandwidth, 2506 leftmost, list_count, cmask); 2507 } else { 2508 if ((endpoint->bEndpointAddress & 2509 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2510 2511 ehci_update_bw_availability(ehcip, -sbandwidth, 2512 leftmost, list_count, smask); 2513 ehci_update_bw_availability(ehcip, 2514 -MAX_UFRAME_SITD_XFER, leftmost, 2515 list_count, cmask); 2516 } else { 2517 2518 ehci_update_bw_availability(ehcip, 2519 -MAX_UFRAME_SITD_XFER, leftmost, 2520 list_count, smask); 2521 } 2522 } 2523 } 2524 } 2525 2526 /* 2527 * ehci_deallocate_classic_tt_bandwidth: 2528 * 2529 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2530 */ 2531 static void 2532 ehci_deallocate_classic_tt_bandwidth( 2533 ehci_state_t *ehcip, 2534 usba_pipe_handle_data_t *ph, 2535 uint_t pnode) 2536 { 2537 uint_t bandwidth, height, leftmost, list, min; 2538 int i, interval; 2539 usb_ep_descr_t *endpoint = &ph->p_ep; 2540 usba_device_t *child_ud, *parent_ud; 2541 usb_port_status_t port_status; 2542 2543 /* This routine is protected by the ehci_int_mutex */ 2544 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2545 2546 /* Get child's usba device structure */ 2547 child_ud = ph->p_usba_device; 2548 2549 mutex_enter(&child_ud->usb_mutex); 2550 2551 /* Get the current usb device's port status */ 2552 port_status = child_ud->usb_port_status; 2553 2554 /* Get the parent high speed hub's usba device structure */ 2555 parent_ud = child_ud->usb_hs_hub_usba_dev; 2556 2557 mutex_exit(&child_ud->usb_mutex); 2558 2559 /* Obtain the bandwidth */ 2560 (void) ehci_compute_classic_bandwidth(endpoint, 2561 port_status, &bandwidth); 2562 2563 /* Adjust polling interval to be a power of 2 */ 2564 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2565 2566 /* Find the height in the tree */ 2567 height = ehci_lattice_height(interval); 2568 2569 /* Find the leftmost leaf in the subtree specified by the node */ 2570 leftmost = ehci_leftmost_leaf(pnode, height); 2571 2572 mutex_enter(&parent_ud->usb_mutex); 2573 2574 /* Delete the bandwidth from the appropriate lists */ 2575 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2576 list = ehci_index[leftmost + i]; 2577 parent_ud->usb_hs_hub_bandwidth[list] -= bandwidth; 2578 } 2579 2580 /* Find the leaf with the smallest allocated bandwidth */ 2581 min = parent_ud->usb_hs_hub_bandwidth[0]; 2582 2583 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2584 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2585 min = parent_ud->usb_hs_hub_bandwidth[i]; 2586 } 2587 } 2588 2589 /* Save the minimum for later use */ 2590 parent_ud->usb_hs_hub_min_bandwidth = min; 2591 2592 mutex_exit(&parent_ud->usb_mutex); 2593 } 2594 2595 2596 /* 2597 * ehci_compute_high_speed_bandwidth: 2598 * 2599 * Given a periodic endpoint (interrupt or isochronous) determine the total 2600 * bandwidth for one transaction. The EHCI host controller traverses the 2601 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2602 * services an endpoint, only a single transaction attempt is made. The HC 2603 * moves to the next Endpoint Descriptor after the first transaction attempt 2604 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2605 * Transfer Descriptor is inserted into the lattice, we will only count the 2606 * number of bytes for one transaction. 2607 * 2608 * The following are the formulas used for calculating bandwidth in terms 2609 * bytes and it is for the single USB high speed transaction. The protocol 2610 * overheads will be different for each of type of USB transfer & all these 2611 * formulas & protocol overheads are derived from the 5.11.3 section of the 2612 * USB 2.0 Specification. 2613 * 2614 * High-Speed: 2615 * Protocol overhead + ((MaxPktSz * 7)/6) + Host_Delay 2616 * 2617 * Split Transaction: (Low/Full speed devices connected behind usb2.0 hub) 2618 * 2619 * Protocol overhead + Split transaction overhead + 2620 * ((MaxPktSz * 7)/6) + Host_Delay; 2621 */ 2622 /* ARGSUSED */ 2623 static int 2624 ehci_compute_high_speed_bandwidth( 2625 ehci_state_t *ehcip, 2626 usb_ep_descr_t *endpoint, 2627 usb_port_status_t port_status, 2628 uint_t *sbandwidth, 2629 uint_t *cbandwidth) 2630 { 2631 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2632 2633 /* Return failure if endpoint maximum packet is zero */ 2634 if (maxpacketsize == 0) { 2635 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2636 "ehci_allocate_high_speed_bandwidth: Periodic endpoint " 2637 "with zero endpoint maximum packet size is not supported"); 2638 2639 return (USB_NOT_SUPPORTED); 2640 } 2641 2642 /* Add bit-stuffing overhead */ 2643 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2644 2645 /* Add Host Controller specific delay to required bandwidth */ 2646 *sbandwidth = EHCI_HOST_CONTROLLER_DELAY; 2647 2648 /* Add xfer specific protocol overheads */ 2649 if ((endpoint->bmAttributes & 2650 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2651 /* High speed interrupt transaction */ 2652 *sbandwidth += HS_NON_ISOC_PROTO_OVERHEAD; 2653 } else { 2654 /* Isochronous transaction */ 2655 *sbandwidth += HS_ISOC_PROTO_OVERHEAD; 2656 } 2657 2658 /* 2659 * For low/full speed devices, add split transaction specific 2660 * overheads. 2661 */ 2662 if (port_status != USBA_HIGH_SPEED_DEV) { 2663 /* 2664 * Add start and complete split transaction 2665 * tokens overheads. 2666 */ 2667 *cbandwidth = *sbandwidth + COMPLETE_SPLIT_OVERHEAD; 2668 *sbandwidth += START_SPLIT_OVERHEAD; 2669 2670 /* Add data overhead depending on data direction */ 2671 if ((endpoint->bEndpointAddress & 2672 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2673 *cbandwidth += maxpacketsize; 2674 } else { 2675 if ((endpoint->bmAttributes & 2676 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 2677 /* There is no compete splits for out */ 2678 *cbandwidth = 0; 2679 } 2680 *sbandwidth += maxpacketsize; 2681 } 2682 } else { 2683 uint_t xactions; 2684 2685 /* Get the max transactions per microframe */ 2686 xactions = ((maxpacketsize & USB_EP_MAX_XACTS_MASK) >> 2687 USB_EP_MAX_XACTS_SHIFT) + 1; 2688 2689 /* High speed transaction */ 2690 *sbandwidth += maxpacketsize; 2691 2692 /* Calculate bandwidth per micro-frame */ 2693 *sbandwidth *= xactions; 2694 2695 *cbandwidth = 0; 2696 } 2697 2698 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2699 "ehci_allocate_high_speed_bandwidth: " 2700 "Start split bandwidth %d Complete split bandwidth %d", 2701 *sbandwidth, *cbandwidth); 2702 2703 return (USB_SUCCESS); 2704 } 2705 2706 2707 /* 2708 * ehci_compute_classic_bandwidth: 2709 * 2710 * Given a periodic endpoint (interrupt or isochronous) determine the total 2711 * bandwidth for one transaction. The EHCI host controller traverses the 2712 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2713 * services an endpoint, only a single transaction attempt is made. The HC 2714 * moves to the next Endpoint Descriptor after the first transaction attempt 2715 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2716 * Transfer Descriptor is inserted into the lattice, we will only count the 2717 * number of bytes for one transaction. 2718 * 2719 * The following are the formulas used for calculating bandwidth in terms 2720 * bytes and it is for the single USB high speed transaction. The protocol 2721 * overheads will be different for each of type of USB transfer & all these 2722 * formulas & protocol overheads are derived from the 5.11.3 section of the 2723 * USB 2.0 Specification. 2724 * 2725 * Low-Speed: 2726 * Protocol overhead + Hub LS overhead + 2727 * (Low Speed clock * ((MaxPktSz * 7)/6)) + TT_Delay 2728 * 2729 * Full-Speed: 2730 * Protocol overhead + ((MaxPktSz * 7)/6) + TT_Delay 2731 */ 2732 /* ARGSUSED */ 2733 static int 2734 ehci_compute_classic_bandwidth( 2735 usb_ep_descr_t *endpoint, 2736 usb_port_status_t port_status, 2737 uint_t *bandwidth) 2738 { 2739 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2740 2741 /* 2742 * If endpoint maximum packet is zero, then return immediately. 2743 */ 2744 if (maxpacketsize == 0) { 2745 2746 return (USB_NOT_SUPPORTED); 2747 } 2748 2749 /* Add TT delay to required bandwidth */ 2750 *bandwidth = TT_DELAY; 2751 2752 /* Add bit-stuffing overhead */ 2753 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2754 2755 switch (port_status) { 2756 case USBA_LOW_SPEED_DEV: 2757 /* Low speed interrupt transaction */ 2758 *bandwidth += (LOW_SPEED_PROTO_OVERHEAD + 2759 HUB_LOW_SPEED_PROTO_OVERHEAD + 2760 (LOW_SPEED_CLOCK * maxpacketsize)); 2761 break; 2762 case USBA_FULL_SPEED_DEV: 2763 /* Full speed transaction */ 2764 *bandwidth += maxpacketsize; 2765 2766 /* Add xfer specific protocol overheads */ 2767 if ((endpoint->bmAttributes & 2768 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2769 /* Full speed interrupt transaction */ 2770 *bandwidth += FS_NON_ISOC_PROTO_OVERHEAD; 2771 } else { 2772 /* Isochronous and input transaction */ 2773 if ((endpoint->bEndpointAddress & 2774 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2775 *bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD; 2776 } else { 2777 /* Isochronous and output transaction */ 2778 *bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD; 2779 } 2780 } 2781 break; 2782 } 2783 2784 return (USB_SUCCESS); 2785 } 2786 2787 2788 /* 2789 * ehci_adjust_polling_interval: 2790 * 2791 * Adjust bandwidth according usb device speed. 2792 */ 2793 /* ARGSUSED */ 2794 int 2795 ehci_adjust_polling_interval( 2796 ehci_state_t *ehcip, 2797 usb_ep_descr_t *endpoint, 2798 usb_port_status_t port_status) 2799 { 2800 uint_t interval; 2801 int i = 0; 2802 2803 /* Get the polling interval */ 2804 interval = endpoint->bInterval; 2805 2806 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2807 "ehci_adjust_polling_interval: Polling interval 0x%x", interval); 2808 2809 /* 2810 * According USB 2.0 Specifications, a high-speed endpoint's 2811 * polling intervals are specified interms of 125us or micro 2812 * frame, where as full/low endpoint's polling intervals are 2813 * specified in milliseconds. 2814 * 2815 * A high speed interrupt/isochronous endpoints can specify 2816 * desired polling interval between 1 to 16 micro-frames, 2817 * where as full/low endpoints can specify between 1 to 255 2818 * milliseconds. 2819 */ 2820 switch (port_status) { 2821 case USBA_LOW_SPEED_DEV: 2822 /* 2823 * Low speed endpoints are limited to specifying 2824 * only 8ms to 255ms in this driver. If a device 2825 * reports a polling interval that is less than 8ms, 2826 * it will use 8 ms instead. 2827 */ 2828 if (interval < LS_MIN_POLL_INTERVAL) { 2829 2830 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2831 "Low speed endpoint's poll interval of %d ms " 2832 "is below threshold. Rounding up to %d ms", 2833 interval, LS_MIN_POLL_INTERVAL); 2834 2835 interval = LS_MIN_POLL_INTERVAL; 2836 } 2837 2838 /* 2839 * Return an error if the polling interval is greater 2840 * than 255ms. 2841 */ 2842 if (interval > LS_MAX_POLL_INTERVAL) { 2843 2844 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2845 "Low speed endpoint's poll interval is " 2846 "greater than %d ms", LS_MAX_POLL_INTERVAL); 2847 2848 return (USB_FAILURE); 2849 } 2850 break; 2851 2852 case USBA_FULL_SPEED_DEV: 2853 /* 2854 * Return an error if the polling interval is less 2855 * than 1ms and greater than 255ms. 2856 */ 2857 if ((interval < FS_MIN_POLL_INTERVAL) && 2858 (interval > FS_MAX_POLL_INTERVAL)) { 2859 2860 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2861 "Full speed endpoint's poll interval must " 2862 "be between %d and %d ms", FS_MIN_POLL_INTERVAL, 2863 FS_MAX_POLL_INTERVAL); 2864 2865 return (USB_FAILURE); 2866 } 2867 break; 2868 case USBA_HIGH_SPEED_DEV: 2869 /* 2870 * Return an error if the polling interval is less 1 2871 * and greater than 16. Convert this value to 125us 2872 * units using 2^(bInterval -1). refer usb 2.0 spec 2873 * page 51 for details. 2874 */ 2875 if ((interval < HS_MIN_POLL_INTERVAL) && 2876 (interval > HS_MAX_POLL_INTERVAL)) { 2877 2878 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2879 "High speed endpoint's poll interval " 2880 "must be between %d and %d units", 2881 HS_MIN_POLL_INTERVAL, HS_MAX_POLL_INTERVAL); 2882 2883 return (USB_FAILURE); 2884 } 2885 2886 /* Adjust high speed device polling interval */ 2887 interval = 2888 ehci_adjust_high_speed_polling_interval(ehcip, endpoint); 2889 2890 break; 2891 } 2892 2893 /* 2894 * If polling interval is greater than 32ms, 2895 * adjust polling interval equal to 32ms. 2896 */ 2897 if (interval > EHCI_NUM_INTR_QH_LISTS) { 2898 interval = EHCI_NUM_INTR_QH_LISTS; 2899 } 2900 2901 /* 2902 * Find the nearest power of 2 that's less 2903 * than interval. 2904 */ 2905 while ((ehci_pow_2(i)) <= interval) { 2906 i++; 2907 } 2908 2909 return (ehci_pow_2((i - 1))); 2910 } 2911 2912 2913 /* 2914 * ehci_adjust_high_speed_polling_interval: 2915 */ 2916 /* ARGSUSED */ 2917 static int 2918 ehci_adjust_high_speed_polling_interval( 2919 ehci_state_t *ehcip, 2920 usb_ep_descr_t *endpoint) 2921 { 2922 uint_t interval; 2923 2924 /* Get the polling interval */ 2925 interval = ehci_pow_2(endpoint->bInterval - 1); 2926 2927 /* 2928 * Convert polling interval from micro seconds 2929 * to milli seconds. 2930 */ 2931 if (interval <= EHCI_MAX_UFRAMES) { 2932 interval = 1; 2933 } else { 2934 interval = interval/EHCI_MAX_UFRAMES; 2935 } 2936 2937 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2938 "ehci_adjust_high_speed_polling_interval: " 2939 "High speed adjusted interval 0x%x", interval); 2940 2941 return (interval); 2942 } 2943 2944 2945 /* 2946 * ehci_lattice_height: 2947 * 2948 * Given the requested bandwidth, find the height in the tree at which the 2949 * nodes for this bandwidth fall. The height is measured as the number of 2950 * nodes from the leaf to the level specified by bandwidth The root of the 2951 * tree is at height TREE_HEIGHT. 2952 */ 2953 static uint_t 2954 ehci_lattice_height(uint_t interval) 2955 { 2956 return (TREE_HEIGHT - (ehci_log_2(interval))); 2957 } 2958 2959 2960 /* 2961 * ehci_lattice_parent: 2962 * 2963 * Given a node in the lattice, find the index of the parent node 2964 */ 2965 static uint_t 2966 ehci_lattice_parent(uint_t node) 2967 { 2968 if ((node % 2) == 0) { 2969 2970 return ((node/2) - 1); 2971 } else { 2972 2973 return ((node + 1)/2 - 1); 2974 } 2975 } 2976 2977 2978 /* 2979 * ehci_find_periodic_node: 2980 * 2981 * Based on the "real" array leaf node and interval, get the periodic node. 2982 */ 2983 static uint_t 2984 ehci_find_periodic_node(uint_t leaf, int interval) { 2985 uint_t lattice_leaf; 2986 uint_t height = ehci_lattice_height(interval); 2987 uint_t pnode; 2988 int i; 2989 2990 /* Get the leaf number in the lattice */ 2991 lattice_leaf = leaf + EHCI_NUM_INTR_QH_LISTS - 1; 2992 2993 /* Get the node in the lattice based on the height and leaf */ 2994 pnode = lattice_leaf; 2995 for (i = 0; i < height; i++) { 2996 pnode = ehci_lattice_parent(pnode); 2997 } 2998 2999 return (pnode); 3000 } 3001 3002 3003 /* 3004 * ehci_leftmost_leaf: 3005 * 3006 * Find the leftmost leaf in the subtree specified by the node. Height refers 3007 * to number of nodes from the bottom of the tree to the node, including the 3008 * node. 3009 * 3010 * The formula for a zero based tree is: 3011 * 2^H * Node + 2^H - 1 3012 * The leaf of the tree is an array, convert the number for the array. 3013 * Subtract the size of nodes not in the array 3014 * 2^H * Node + 2^H - 1 - (EHCI_NUM_INTR_QH_LISTS - 1) = 3015 * 2^H * Node + 2^H - EHCI_NUM_INTR_QH_LISTS = 3016 * 2^H * (Node + 1) - EHCI_NUM_INTR_QH_LISTS 3017 * 0 3018 * 1 2 3019 * 0 1 2 3 3020 */ 3021 static uint_t 3022 ehci_leftmost_leaf( 3023 uint_t node, 3024 uint_t height) 3025 { 3026 return ((ehci_pow_2(height) * (node + 1)) - EHCI_NUM_INTR_QH_LISTS); 3027 } 3028 3029 3030 /* 3031 * ehci_pow_2: 3032 * 3033 * Compute 2 to the power 3034 */ 3035 static uint_t 3036 ehci_pow_2(uint_t x) 3037 { 3038 if (x == 0) { 3039 3040 return (1); 3041 } else { 3042 3043 return (2 << (x - 1)); 3044 } 3045 } 3046 3047 3048 /* 3049 * ehci_log_2: 3050 * 3051 * Compute log base 2 of x 3052 */ 3053 static uint_t 3054 ehci_log_2(uint_t x) 3055 { 3056 int i = 0; 3057 3058 while (x != 1) { 3059 x = x >> 1; 3060 i++; 3061 } 3062 3063 return (i); 3064 } 3065 3066 3067 /* 3068 * ehci_find_bestfit_hs_mask: 3069 * 3070 * Find the smask and cmask in the bandwidth allocation, and update the 3071 * bandwidth allocation. 3072 */ 3073 static int 3074 ehci_find_bestfit_hs_mask( 3075 ehci_state_t *ehcip, 3076 uchar_t *smask, 3077 uint_t *pnode, 3078 usb_ep_descr_t *endpoint, 3079 uint_t bandwidth, 3080 int interval) 3081 { 3082 int i; 3083 uint_t elements, index; 3084 int array_leaf, best_array_leaf; 3085 uint_t node_bandwidth, best_node_bandwidth; 3086 uint_t leaf_count; 3087 uchar_t bw_mask; 3088 uchar_t best_smask; 3089 3090 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3091 "ehci_find_bestfit_hs_mask: "); 3092 3093 /* Get all the valid smasks */ 3094 switch (ehci_pow_2(endpoint->bInterval - 1)) { 3095 case EHCI_INTR_1US_POLL: 3096 index = EHCI_1US_MASK_INDEX; 3097 elements = EHCI_INTR_1US_POLL; 3098 break; 3099 case EHCI_INTR_2US_POLL: 3100 index = EHCI_2US_MASK_INDEX; 3101 elements = EHCI_INTR_2US_POLL; 3102 break; 3103 case EHCI_INTR_4US_POLL: 3104 index = EHCI_4US_MASK_INDEX; 3105 elements = EHCI_INTR_4US_POLL; 3106 break; 3107 case EHCI_INTR_XUS_POLL: 3108 default: 3109 index = EHCI_XUS_MASK_INDEX; 3110 elements = EHCI_INTR_XUS_POLL; 3111 break; 3112 } 3113 3114 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3115 3116 /* 3117 * Because of the way the leaves are setup, we will automatically 3118 * hit the leftmost leaf of every possible node with this interval. 3119 */ 3120 best_smask = 0x00; 3121 best_node_bandwidth = 0; 3122 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3123 /* Find the bandwidth mask */ 3124 node_bandwidth = ehci_calculate_bw_availability_mask(ehcip, 3125 bandwidth, ehci_index[array_leaf], leaf_count, &bw_mask); 3126 3127 /* 3128 * If this node cannot support our requirements skip to the 3129 * next leaf. 3130 */ 3131 if (bw_mask == 0x00) { 3132 continue; 3133 } 3134 3135 /* 3136 * Now make sure our bandwidth requirements can be 3137 * satisfied with one of smasks in this node. 3138 */ 3139 *smask = 0x00; 3140 for (i = index; i < (index + elements); i++) { 3141 /* Check the start split mask value */ 3142 if (ehci_start_split_mask[index] & bw_mask) { 3143 *smask = ehci_start_split_mask[index]; 3144 break; 3145 } 3146 } 3147 3148 /* 3149 * If an appropriate smask is found save the information if: 3150 * o best_smask has not been found yet. 3151 * - or - 3152 * o This is the node with the least amount of bandwidth 3153 */ 3154 if ((*smask != 0x00) && 3155 ((best_smask == 0x00) || 3156 (best_node_bandwidth > node_bandwidth))) { 3157 3158 best_node_bandwidth = node_bandwidth; 3159 best_array_leaf = array_leaf; 3160 best_smask = *smask; 3161 } 3162 } 3163 3164 /* 3165 * If we find node that can handle the bandwidth populate the 3166 * appropriate variables and return success. 3167 */ 3168 if (best_smask) { 3169 *smask = best_smask; 3170 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3171 interval); 3172 ehci_update_bw_availability(ehcip, bandwidth, 3173 ehci_index[best_array_leaf], leaf_count, best_smask); 3174 3175 return (USB_SUCCESS); 3176 } 3177 3178 return (USB_FAILURE); 3179 } 3180 3181 3182 /* 3183 * ehci_find_bestfit_ls_intr_mask: 3184 * 3185 * Find the smask and cmask in the bandwidth allocation. 3186 */ 3187 static int 3188 ehci_find_bestfit_ls_intr_mask( 3189 ehci_state_t *ehcip, 3190 uchar_t *smask, 3191 uchar_t *cmask, 3192 uint_t *pnode, 3193 uint_t sbandwidth, 3194 uint_t cbandwidth, 3195 int interval) 3196 { 3197 int i; 3198 uint_t elements, index; 3199 int array_leaf, best_array_leaf; 3200 uint_t node_sbandwidth, node_cbandwidth; 3201 uint_t best_node_bandwidth; 3202 uint_t leaf_count; 3203 uchar_t bw_smask, bw_cmask; 3204 uchar_t best_smask, best_cmask; 3205 3206 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3207 "ehci_find_bestfit_ls_intr_mask: "); 3208 3209 /* For low and full speed devices */ 3210 index = EHCI_XUS_MASK_INDEX; 3211 elements = EHCI_INTR_4MS_POLL; 3212 3213 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3214 3215 /* 3216 * Because of the way the leaves are setup, we will automatically 3217 * hit the leftmost leaf of every possible node with this interval. 3218 */ 3219 best_smask = 0x00; 3220 best_node_bandwidth = 0; 3221 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3222 /* Find the bandwidth mask */ 3223 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3224 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3225 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3226 cbandwidth, ehci_index[array_leaf], leaf_count, &bw_cmask); 3227 3228 /* 3229 * If this node cannot support our requirements skip to the 3230 * next leaf. 3231 */ 3232 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3233 continue; 3234 } 3235 3236 /* 3237 * Now make sure our bandwidth requirements can be 3238 * satisfied with one of smasks in this node. 3239 */ 3240 *smask = 0x00; 3241 *cmask = 0x00; 3242 for (i = index; i < (index + elements); i++) { 3243 /* Check the start split mask value */ 3244 if ((ehci_start_split_mask[index] & bw_smask) && 3245 (ehci_intr_complete_split_mask[index] & bw_cmask)) { 3246 *smask = ehci_start_split_mask[index]; 3247 *cmask = ehci_intr_complete_split_mask[index]; 3248 break; 3249 } 3250 } 3251 3252 /* 3253 * If an appropriate smask is found save the information if: 3254 * o best_smask has not been found yet. 3255 * - or - 3256 * o This is the node with the least amount of bandwidth 3257 */ 3258 if ((*smask != 0x00) && 3259 ((best_smask == 0x00) || 3260 (best_node_bandwidth > 3261 (node_sbandwidth + node_cbandwidth)))) { 3262 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3263 best_array_leaf = array_leaf; 3264 best_smask = *smask; 3265 best_cmask = *cmask; 3266 } 3267 } 3268 3269 /* 3270 * If we find node that can handle the bandwidth populate the 3271 * appropriate variables and return success. 3272 */ 3273 if (best_smask) { 3274 *smask = best_smask; 3275 *cmask = best_cmask; 3276 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3277 interval); 3278 ehci_update_bw_availability(ehcip, sbandwidth, 3279 ehci_index[best_array_leaf], leaf_count, best_smask); 3280 ehci_update_bw_availability(ehcip, cbandwidth, 3281 ehci_index[best_array_leaf], leaf_count, best_cmask); 3282 3283 return (USB_SUCCESS); 3284 } 3285 3286 return (USB_FAILURE); 3287 } 3288 3289 3290 /* 3291 * ehci_find_bestfit_sitd_in_mask: 3292 * 3293 * Find the smask and cmask in the bandwidth allocation. 3294 */ 3295 static int 3296 ehci_find_bestfit_sitd_in_mask( 3297 ehci_state_t *ehcip, 3298 uchar_t *smask, 3299 uchar_t *cmask, 3300 uint_t *pnode, 3301 uint_t sbandwidth, 3302 uint_t cbandwidth, 3303 int interval) 3304 { 3305 int i, uFrames, found; 3306 int array_leaf, best_array_leaf; 3307 uint_t node_sbandwidth, node_cbandwidth; 3308 uint_t best_node_bandwidth; 3309 uint_t leaf_count; 3310 uchar_t bw_smask, bw_cmask; 3311 uchar_t best_smask, best_cmask; 3312 3313 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3314 "ehci_find_bestfit_sitd_in_mask: "); 3315 3316 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3317 3318 /* 3319 * Because of the way the leaves are setup, we will automatically 3320 * hit the leftmost leaf of every possible node with this interval. 3321 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3322 */ 3323 /* 3324 * Need to add an additional 2 uFrames, if the "L"ast 3325 * complete split is before uFrame 6. See section 3326 * 11.8.4 in USB 2.0 Spec. Currently we do not support 3327 * the "Back Ptr" which means we support on IN of 3328 * ~4*MAX_UFRAME_SITD_XFER bandwidth/ 3329 */ 3330 uFrames = (cbandwidth / MAX_UFRAME_SITD_XFER) + 2; 3331 if (cbandwidth % MAX_UFRAME_SITD_XFER) { 3332 uFrames++; 3333 } 3334 if (uFrames > 6) { 3335 3336 return (USB_FAILURE); 3337 } 3338 *smask = 0x1; 3339 *cmask = 0x00; 3340 for (i = 0; i < uFrames; i++) { 3341 *cmask = *cmask << 1; 3342 *cmask |= 0x1; 3343 } 3344 /* cmask must start 2 frames after the smask */ 3345 *cmask = *cmask << 2; 3346 3347 found = 0; 3348 best_smask = 0x00; 3349 best_node_bandwidth = 0; 3350 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3351 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3352 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3353 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3354 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3355 &bw_cmask); 3356 3357 /* 3358 * If this node cannot support our requirements skip to the 3359 * next leaf. 3360 */ 3361 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3362 continue; 3363 } 3364 3365 for (i = 0; i < (EHCI_MAX_UFRAMES - uFrames - 2); i++) { 3366 if ((*smask & bw_smask) && (*cmask & bw_cmask)) { 3367 found = 1; 3368 break; 3369 } 3370 *smask = *smask << 1; 3371 *cmask = *cmask << 1; 3372 } 3373 3374 /* 3375 * If an appropriate smask is found save the information if: 3376 * o best_smask has not been found yet. 3377 * - or - 3378 * o This is the node with the least amount of bandwidth 3379 */ 3380 if (found && 3381 ((best_smask == 0x00) || 3382 (best_node_bandwidth > 3383 (node_sbandwidth + node_cbandwidth)))) { 3384 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3385 best_array_leaf = array_leaf; 3386 best_smask = *smask; 3387 best_cmask = *cmask; 3388 } 3389 } 3390 3391 /* 3392 * If we find node that can handle the bandwidth populate the 3393 * appropriate variables and return success. 3394 */ 3395 if (best_smask) { 3396 *smask = best_smask; 3397 *cmask = best_cmask; 3398 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3399 interval); 3400 ehci_update_bw_availability(ehcip, sbandwidth, 3401 ehci_index[best_array_leaf], leaf_count, best_smask); 3402 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3403 ehci_index[best_array_leaf], leaf_count, best_cmask); 3404 3405 return (USB_SUCCESS); 3406 } 3407 3408 return (USB_FAILURE); 3409 } 3410 3411 3412 /* 3413 * ehci_find_bestfit_sitd_out_mask: 3414 * 3415 * Find the smask in the bandwidth allocation. 3416 */ 3417 static int 3418 ehci_find_bestfit_sitd_out_mask( 3419 ehci_state_t *ehcip, 3420 uchar_t *smask, 3421 uint_t *pnode, 3422 uint_t sbandwidth, 3423 int interval) 3424 { 3425 int i, uFrames, found; 3426 int array_leaf, best_array_leaf; 3427 uint_t node_sbandwidth; 3428 uint_t best_node_bandwidth; 3429 uint_t leaf_count; 3430 uchar_t bw_smask; 3431 uchar_t best_smask; 3432 3433 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3434 "ehci_find_bestfit_sitd_out_mask: "); 3435 3436 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3437 3438 /* 3439 * Because of the way the leaves are setup, we will automatically 3440 * hit the leftmost leaf of every possible node with this interval. 3441 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3442 */ 3443 *smask = 0x00; 3444 uFrames = sbandwidth / MAX_UFRAME_SITD_XFER; 3445 if (sbandwidth % MAX_UFRAME_SITD_XFER) { 3446 uFrames++; 3447 } 3448 for (i = 0; i < uFrames; i++) { 3449 *smask = *smask << 1; 3450 *smask |= 0x1; 3451 } 3452 3453 found = 0; 3454 best_smask = 0x00; 3455 best_node_bandwidth = 0; 3456 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3457 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3458 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3459 &bw_smask); 3460 3461 /* 3462 * If this node cannot support our requirements skip to the 3463 * next leaf. 3464 */ 3465 if (bw_smask == 0x00) { 3466 continue; 3467 } 3468 3469 /* You cannot have a start split on the 8th uFrame */ 3470 for (i = 0; (*smask & 0x80) == 0; i++) { 3471 if (*smask & bw_smask) { 3472 found = 1; 3473 break; 3474 } 3475 *smask = *smask << 1; 3476 } 3477 3478 /* 3479 * If an appropriate smask is found save the information if: 3480 * o best_smask has not been found yet. 3481 * - or - 3482 * o This is the node with the least amount of bandwidth 3483 */ 3484 if (found && 3485 ((best_smask == 0x00) || 3486 (best_node_bandwidth > node_sbandwidth))) { 3487 best_node_bandwidth = node_sbandwidth; 3488 best_array_leaf = array_leaf; 3489 best_smask = *smask; 3490 } 3491 } 3492 3493 /* 3494 * If we find node that can handle the bandwidth populate the 3495 * appropriate variables and return success. 3496 */ 3497 if (best_smask) { 3498 *smask = best_smask; 3499 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3500 interval); 3501 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3502 ehci_index[best_array_leaf], leaf_count, best_smask); 3503 3504 return (USB_SUCCESS); 3505 } 3506 3507 return (USB_FAILURE); 3508 } 3509 3510 3511 /* 3512 * ehci_calculate_bw_availability_mask: 3513 * 3514 * Returns the "total bandwidth used" in this node. 3515 * Populates bw_mask with the uFrames that can support the bandwidth. 3516 * 3517 * If all the Frames cannot support this bandwidth, then bw_mask 3518 * will return 0x00 and the "total bandwidth used" will be invalid. 3519 */ 3520 static uint_t 3521 ehci_calculate_bw_availability_mask( 3522 ehci_state_t *ehcip, 3523 uint_t bandwidth, 3524 int leaf, 3525 int leaf_count, 3526 uchar_t *bw_mask) 3527 { 3528 int i, j; 3529 uchar_t bw_uframe; 3530 int uframe_total; 3531 ehci_frame_bandwidth_t *fbp; 3532 uint_t total_bandwidth = 0; 3533 3534 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3535 "ehci_calculate_bw_availability_mask: leaf %d leaf count %d", 3536 leaf, leaf_count); 3537 3538 /* Start by saying all uFrames are available */ 3539 *bw_mask = 0xFF; 3540 3541 for (i = 0; (i < leaf_count) || (*bw_mask == 0x00); i++) { 3542 fbp = &ehcip->ehci_frame_bandwidth[leaf + i]; 3543 3544 total_bandwidth += fbp->ehci_allocated_frame_bandwidth; 3545 3546 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3547 /* 3548 * If the uFrame in bw_mask is available check to see if 3549 * it can support the additional bandwidth. 3550 */ 3551 bw_uframe = (*bw_mask & (0x1 << j)); 3552 uframe_total = 3553 fbp->ehci_micro_frame_bandwidth[j] + 3554 bandwidth; 3555 if ((bw_uframe) && 3556 (uframe_total > HS_PERIODIC_BANDWIDTH)) { 3557 *bw_mask = *bw_mask & ~bw_uframe; 3558 } 3559 } 3560 } 3561 3562 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3563 "ehci_calculate_bw_availability_mask: bandwidth mask 0x%x", 3564 *bw_mask); 3565 3566 return (total_bandwidth); 3567 } 3568 3569 3570 /* 3571 * ehci_update_bw_availability: 3572 * 3573 * The leftmost leaf needs to be in terms of array position and 3574 * not the actual lattice position. 3575 */ 3576 static void 3577 ehci_update_bw_availability( 3578 ehci_state_t *ehcip, 3579 int bandwidth, 3580 int leftmost_leaf, 3581 int leaf_count, 3582 uchar_t mask) 3583 { 3584 int i, j; 3585 ehci_frame_bandwidth_t *fbp; 3586 int uFrame_bandwidth[8]; 3587 3588 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3589 "ehci_update_bw_availability: " 3590 "leaf %d count %d bandwidth 0x%x mask 0x%x", 3591 leftmost_leaf, leaf_count, bandwidth, mask); 3592 3593 ASSERT(leftmost_leaf < 32); 3594 ASSERT(leftmost_leaf >= 0); 3595 3596 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3597 if (mask & 0x1) { 3598 uFrame_bandwidth[j] = bandwidth; 3599 } else { 3600 uFrame_bandwidth[j] = 0; 3601 } 3602 3603 mask = mask >> 1; 3604 } 3605 3606 /* Updated all the effected leafs with the bandwidth */ 3607 for (i = 0; i < leaf_count; i++) { 3608 fbp = &ehcip->ehci_frame_bandwidth[leftmost_leaf + i]; 3609 3610 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3611 fbp->ehci_micro_frame_bandwidth[j] += 3612 uFrame_bandwidth[j]; 3613 fbp->ehci_allocated_frame_bandwidth += 3614 uFrame_bandwidth[j]; 3615 } 3616 } 3617 } 3618 3619 /* 3620 * Miscellaneous functions 3621 */ 3622 3623 /* 3624 * ehci_obtain_state: 3625 * 3626 * NOTE: This function is also called from POLLED MODE. 3627 */ 3628 ehci_state_t * 3629 ehci_obtain_state(dev_info_t *dip) 3630 { 3631 int instance = ddi_get_instance(dip); 3632 3633 ehci_state_t *state = ddi_get_soft_state(ehci_statep, instance); 3634 3635 ASSERT(state != NULL); 3636 3637 return (state); 3638 } 3639 3640 3641 /* 3642 * ehci_state_is_operational: 3643 * 3644 * Check the Host controller state and return proper values. 3645 */ 3646 int 3647 ehci_state_is_operational(ehci_state_t *ehcip) 3648 { 3649 int val; 3650 3651 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3652 3653 switch (ehcip->ehci_hc_soft_state) { 3654 case EHCI_CTLR_INIT_STATE: 3655 case EHCI_CTLR_SUSPEND_STATE: 3656 val = USB_FAILURE; 3657 break; 3658 case EHCI_CTLR_OPERATIONAL_STATE: 3659 val = USB_SUCCESS; 3660 break; 3661 case EHCI_CTLR_ERROR_STATE: 3662 val = USB_HC_HARDWARE_ERROR; 3663 break; 3664 default: 3665 val = USB_FAILURE; 3666 break; 3667 } 3668 3669 return (val); 3670 } 3671 3672 3673 /* 3674 * ehci_do_soft_reset 3675 * 3676 * Do soft reset of ehci host controller. 3677 */ 3678 int 3679 ehci_do_soft_reset(ehci_state_t *ehcip) 3680 { 3681 usb_frame_number_t before_frame_number, after_frame_number; 3682 ehci_regs_t *ehci_save_regs; 3683 3684 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3685 3686 /* Increment host controller error count */ 3687 ehcip->ehci_hc_error++; 3688 3689 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3690 "ehci_do_soft_reset:" 3691 "Reset ehci host controller 0x%x", ehcip->ehci_hc_error); 3692 3693 /* 3694 * Allocate space for saving current Host Controller 3695 * registers. Don't do any recovery if allocation 3696 * fails. 3697 */ 3698 ehci_save_regs = (ehci_regs_t *) 3699 kmem_zalloc(sizeof (ehci_regs_t), KM_NOSLEEP); 3700 3701 if (ehci_save_regs == NULL) { 3702 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3703 "ehci_do_soft_reset: kmem_zalloc failed"); 3704 3705 return (USB_FAILURE); 3706 } 3707 3708 /* Save current ehci registers */ 3709 ehci_save_regs->ehci_command = Get_OpReg(ehci_command); 3710 ehci_save_regs->ehci_interrupt = Get_OpReg(ehci_interrupt); 3711 ehci_save_regs->ehci_ctrl_segment = Get_OpReg(ehci_ctrl_segment); 3712 ehci_save_regs->ehci_async_list_addr = Get_OpReg(ehci_async_list_addr); 3713 ehci_save_regs->ehci_config_flag = Get_OpReg(ehci_config_flag); 3714 ehci_save_regs->ehci_periodic_list_base = 3715 Get_OpReg(ehci_periodic_list_base); 3716 3717 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3718 "ehci_do_soft_reset: Save reg = 0x%p", (void *)ehci_save_regs); 3719 3720 /* Disable all list processing and interrupts */ 3721 Set_OpReg(ehci_command, Get_OpReg(ehci_command) & 3722 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE)); 3723 3724 /* Disable all EHCI interrupts */ 3725 Set_OpReg(ehci_interrupt, 0); 3726 3727 /* Wait for few milliseconds */ 3728 drv_usecwait(EHCI_SOF_TIMEWAIT); 3729 3730 /* Do light soft reset of ehci host controller */ 3731 Set_OpReg(ehci_command, 3732 Get_OpReg(ehci_command) | EHCI_CMD_LIGHT_HC_RESET); 3733 3734 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3735 "ehci_do_soft_reset: Reset in progress"); 3736 3737 /* Wait for reset to complete */ 3738 drv_usecwait(EHCI_RESET_TIMEWAIT); 3739 3740 /* 3741 * Restore previous saved EHCI register value 3742 * into the current EHCI registers. 3743 */ 3744 Set_OpReg(ehci_ctrl_segment, (uint32_t) 3745 ehci_save_regs->ehci_ctrl_segment); 3746 3747 Set_OpReg(ehci_periodic_list_base, (uint32_t) 3748 ehci_save_regs->ehci_periodic_list_base); 3749 3750 Set_OpReg(ehci_async_list_addr, (uint32_t) 3751 ehci_save_regs->ehci_async_list_addr); 3752 3753 /* 3754 * For some reason this register might get nulled out by 3755 * the Uli M1575 South Bridge. To workaround the hardware 3756 * problem, check the value after write and retry if the 3757 * last write fails. 3758 */ 3759 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 3760 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) && 3761 (ehci_save_regs->ehci_async_list_addr != 3762 Get_OpReg(ehci_async_list_addr))) { 3763 int retry = 0; 3764 3765 Set_OpRegRetry(ehci_async_list_addr, (uint32_t) 3766 ehci_save_regs->ehci_async_list_addr, retry); 3767 if (retry >= EHCI_MAX_RETRY) { 3768 USB_DPRINTF_L2(PRINT_MASK_ATTA, 3769 ehcip->ehci_log_hdl, "ehci_do_soft_reset:" 3770 " ASYNCLISTADDR write failed."); 3771 3772 return (USB_FAILURE); 3773 } 3774 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3775 "ehci_do_soft_reset: ASYNCLISTADDR " 3776 "write failed, retry=%d", retry); 3777 } 3778 3779 Set_OpReg(ehci_config_flag, (uint32_t) 3780 ehci_save_regs->ehci_config_flag); 3781 3782 /* Enable both Asynchronous and Periodic Schedule if necessary */ 3783 ehci_toggle_scheduler(ehcip); 3784 3785 /* 3786 * Set ehci_interrupt to enable all interrupts except Root 3787 * Hub Status change and frame list rollover interrupts. 3788 */ 3789 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 3790 EHCI_INTR_FRAME_LIST_ROLLOVER | 3791 EHCI_INTR_USB_ERROR | 3792 EHCI_INTR_USB); 3793 3794 /* 3795 * Deallocate the space that allocated for saving 3796 * HC registers. 3797 */ 3798 kmem_free((void *) ehci_save_regs, sizeof (ehci_regs_t)); 3799 3800 /* 3801 * Set the desired interrupt threshold, frame list size (if 3802 * applicable) and turn EHCI host controller. 3803 */ 3804 Set_OpReg(ehci_command, ((Get_OpReg(ehci_command) & 3805 ~EHCI_CMD_INTR_THRESHOLD) | 3806 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 3807 3808 /* Wait 10ms for EHCI to start sending SOF */ 3809 drv_usecwait(EHCI_RESET_TIMEWAIT); 3810 3811 /* 3812 * Get the current usb frame number before waiting for 3813 * few milliseconds. 3814 */ 3815 before_frame_number = ehci_get_current_frame_number(ehcip); 3816 3817 /* Wait for few milliseconds */ 3818 drv_usecwait(EHCI_SOF_TIMEWAIT); 3819 3820 /* 3821 * Get the current usb frame number after waiting for 3822 * few milliseconds. 3823 */ 3824 after_frame_number = ehci_get_current_frame_number(ehcip); 3825 3826 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3827 "ehci_do_soft_reset: Before Frame Number 0x%llx " 3828 "After Frame Number 0x%llx", 3829 (unsigned long long)before_frame_number, 3830 (unsigned long long)after_frame_number); 3831 3832 if ((after_frame_number <= before_frame_number) && 3833 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 3834 3835 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3836 "ehci_do_soft_reset: Soft reset failed"); 3837 3838 return (USB_FAILURE); 3839 } 3840 3841 return (USB_SUCCESS); 3842 } 3843 3844 3845 /* 3846 * ehci_get_xfer_attrs: 3847 * 3848 * Get the attributes of a particular xfer. 3849 * 3850 * NOTE: This function is also called from POLLED MODE. 3851 */ 3852 usb_req_attrs_t 3853 ehci_get_xfer_attrs( 3854 ehci_state_t *ehcip, 3855 ehci_pipe_private_t *pp, 3856 ehci_trans_wrapper_t *tw) 3857 { 3858 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 3859 usb_req_attrs_t attrs = USB_ATTRS_NONE; 3860 3861 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3862 "ehci_get_xfer_attrs:"); 3863 3864 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 3865 case USB_EP_ATTR_CONTROL: 3866 attrs = ((usb_ctrl_req_t *) 3867 tw->tw_curr_xfer_reqp)->ctrl_attributes; 3868 break; 3869 case USB_EP_ATTR_BULK: 3870 attrs = ((usb_bulk_req_t *) 3871 tw->tw_curr_xfer_reqp)->bulk_attributes; 3872 break; 3873 case USB_EP_ATTR_INTR: 3874 attrs = ((usb_intr_req_t *) 3875 tw->tw_curr_xfer_reqp)->intr_attributes; 3876 break; 3877 } 3878 3879 return (attrs); 3880 } 3881 3882 3883 /* 3884 * ehci_get_current_frame_number: 3885 * 3886 * Get the current software based usb frame number. 3887 */ 3888 usb_frame_number_t 3889 ehci_get_current_frame_number(ehci_state_t *ehcip) 3890 { 3891 usb_frame_number_t usb_frame_number; 3892 usb_frame_number_t ehci_fno, micro_frame_number; 3893 3894 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3895 3896 ehci_fno = ehcip->ehci_fno; 3897 micro_frame_number = Get_OpReg(ehci_frame_index) & 0x3FFF; 3898 3899 /* 3900 * Calculate current software based usb frame number. 3901 * 3902 * This code accounts for the fact that frame number is 3903 * updated by the Host Controller before the ehci driver 3904 * gets an FrameListRollover interrupt that will adjust 3905 * Frame higher part. 3906 * 3907 * Refer ehci specification 1.0, section 2.3.2, page 21. 3908 */ 3909 micro_frame_number = ((micro_frame_number & 0x1FFF) | 3910 ehci_fno) + (((micro_frame_number & 0x3FFF) ^ 3911 ehci_fno) & 0x2000); 3912 3913 /* 3914 * Micro Frame number is equivalent to 125 usec. Eight 3915 * Micro Frame numbers are equivalent to one millsecond 3916 * or one usb frame number. 3917 */ 3918 usb_frame_number = micro_frame_number >> 3919 EHCI_uFRAMES_PER_USB_FRAME_SHIFT; 3920 3921 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3922 "ehci_get_current_frame_number: " 3923 "Current usb uframe number = 0x%llx " 3924 "Current usb frame number = 0x%llx", 3925 (unsigned long long)micro_frame_number, 3926 (unsigned long long)usb_frame_number); 3927 3928 return (usb_frame_number); 3929 } 3930 3931 3932 /* 3933 * ehci_cpr_cleanup: 3934 * 3935 * Cleanup ehci state and other ehci specific informations across 3936 * Check Point Resume (CPR). 3937 */ 3938 static void 3939 ehci_cpr_cleanup(ehci_state_t *ehcip) 3940 { 3941 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3942 3943 /* Reset software part of usb frame number */ 3944 ehcip->ehci_fno = 0; 3945 } 3946 3947 3948 /* 3949 * ehci_wait_for_sof: 3950 * 3951 * Wait for couple of SOF interrupts 3952 */ 3953 int 3954 ehci_wait_for_sof(ehci_state_t *ehcip) 3955 { 3956 usb_frame_number_t before_frame_number, after_frame_number; 3957 int error = USB_SUCCESS; 3958 3959 USB_DPRINTF_L4(PRINT_MASK_LISTS, 3960 ehcip->ehci_log_hdl, "ehci_wait_for_sof"); 3961 3962 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3963 3964 error = ehci_state_is_operational(ehcip); 3965 3966 if (error != USB_SUCCESS) { 3967 3968 return (error); 3969 } 3970 3971 /* Get the current usb frame number before waiting for two SOFs */ 3972 before_frame_number = ehci_get_current_frame_number(ehcip); 3973 3974 mutex_exit(&ehcip->ehci_int_mutex); 3975 3976 /* Wait for few milliseconds */ 3977 delay(drv_usectohz(EHCI_SOF_TIMEWAIT)); 3978 3979 mutex_enter(&ehcip->ehci_int_mutex); 3980 3981 /* Get the current usb frame number after woken up */ 3982 after_frame_number = ehci_get_current_frame_number(ehcip); 3983 3984 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3985 "ehci_wait_for_sof: framenumber: before 0x%llx " 3986 "after 0x%llx", 3987 (unsigned long long)before_frame_number, 3988 (unsigned long long)after_frame_number); 3989 3990 /* Return failure, if usb frame number has not been changed */ 3991 if (after_frame_number <= before_frame_number) { 3992 3993 if ((ehci_do_soft_reset(ehcip)) != USB_SUCCESS) { 3994 3995 USB_DPRINTF_L0(PRINT_MASK_LISTS, 3996 ehcip->ehci_log_hdl, "No SOF interrupts"); 3997 3998 /* Set host controller soft state to error */ 3999 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 4000 4001 return (USB_FAILURE); 4002 } 4003 4004 } 4005 4006 return (USB_SUCCESS); 4007 } 4008 4009 4010 /* 4011 * ehci_toggle_scheduler: 4012 * 4013 * Turn scheduler based on pipe open count. 4014 */ 4015 void 4016 ehci_toggle_scheduler(ehci_state_t *ehcip) { 4017 uint_t temp_reg, cmd_reg; 4018 4019 cmd_reg = Get_OpReg(ehci_command); 4020 temp_reg = cmd_reg; 4021 4022 /* 4023 * Enable/Disable asynchronous scheduler, and 4024 * turn on/off async list door bell 4025 */ 4026 if (ehcip->ehci_open_async_count) { 4027 if (!(cmd_reg & EHCI_CMD_ASYNC_SCHED_ENABLE)) { 4028 /* 4029 * For some reason this address might get nulled out by 4030 * the ehci chip. Set it here just in case it is null. 4031 */ 4032 Set_OpReg(ehci_async_list_addr, 4033 ehci_qh_cpu_to_iommu(ehcip, 4034 ehcip->ehci_head_of_async_sched_list)); 4035 4036 /* 4037 * For some reason this register might get nulled out by 4038 * the Uli M1575 Southbridge. To workaround the HW 4039 * problem, check the value after write and retry if the 4040 * last write fails. 4041 * 4042 * If the ASYNCLISTADDR remains "stuck" after 4043 * EHCI_MAX_RETRY retries, then the M1575 is broken 4044 * and is stuck in an inconsistent state and is about 4045 * to crash the machine with a trn_oor panic when it 4046 * does a DMA read from 0x0. It is better to panic 4047 * now rather than wait for the trn_oor crash; this 4048 * way Customer Service will have a clean signature 4049 * that indicts the M1575 chip rather than a 4050 * mysterious and hard-to-diagnose trn_oor panic. 4051 */ 4052 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 4053 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) && 4054 (ehci_qh_cpu_to_iommu(ehcip, 4055 ehcip->ehci_head_of_async_sched_list) != 4056 Get_OpReg(ehci_async_list_addr))) { 4057 int retry = 0; 4058 4059 Set_OpRegRetry(ehci_async_list_addr, 4060 ehci_qh_cpu_to_iommu(ehcip, 4061 ehcip->ehci_head_of_async_sched_list), 4062 retry); 4063 if (retry >= EHCI_MAX_RETRY) 4064 cmn_err(CE_PANIC, 4065 "ehci_toggle_scheduler: " 4066 "ASYNCLISTADDR write failed."); 4067 4068 USB_DPRINTF_L2(PRINT_MASK_ATTA, 4069 ehcip->ehci_log_hdl, 4070 "ehci_toggle_scheduler: ASYNCLISTADDR " 4071 "write failed, retry=%d", retry); 4072 } 4073 } 4074 cmd_reg |= EHCI_CMD_ASYNC_SCHED_ENABLE; 4075 } else { 4076 cmd_reg &= ~EHCI_CMD_ASYNC_SCHED_ENABLE; 4077 } 4078 4079 if (ehcip->ehci_open_periodic_count) { 4080 if (!(cmd_reg & EHCI_CMD_PERIODIC_SCHED_ENABLE)) { 4081 /* 4082 * For some reason this address get's nulled out by 4083 * the ehci chip. Set it here just in case it is null. 4084 */ 4085 Set_OpReg(ehci_periodic_list_base, 4086 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 4087 0xFFFFF000)); 4088 } 4089 cmd_reg |= EHCI_CMD_PERIODIC_SCHED_ENABLE; 4090 } else { 4091 cmd_reg &= ~EHCI_CMD_PERIODIC_SCHED_ENABLE; 4092 } 4093 4094 /* Just an optimization */ 4095 if (temp_reg != cmd_reg) { 4096 Set_OpReg(ehci_command, cmd_reg); 4097 } 4098 } 4099 4100 /* 4101 * ehci print functions 4102 */ 4103 4104 /* 4105 * ehci_print_caps: 4106 */ 4107 void 4108 ehci_print_caps(ehci_state_t *ehcip) 4109 { 4110 uint_t i; 4111 4112 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4113 "\n\tUSB 2.0 Host Controller Characteristics\n"); 4114 4115 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4116 "Caps Length: 0x%x Version: 0x%x\n", 4117 Get_8Cap(ehci_caps_length), Get_16Cap(ehci_version)); 4118 4119 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4120 "Structural Parameters\n"); 4121 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4122 "Port indicators: %s", (Get_Cap(ehci_hcs_params) & 4123 EHCI_HCS_PORT_INDICATOR) ? "Yes" : "No"); 4124 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4125 "No of Classic host controllers: 0x%x", 4126 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_COMP_CTRLS) 4127 >> EHCI_HCS_NUM_COMP_CTRL_SHIFT); 4128 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4129 "No of ports per Classic host controller: 0x%x", 4130 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS_CC) 4131 >> EHCI_HCS_NUM_PORTS_CC_SHIFT); 4132 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4133 "Port routing rules: %s", (Get_Cap(ehci_hcs_params) & 4134 EHCI_HCS_PORT_ROUTING_RULES) ? "Yes" : "No"); 4135 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4136 "Port power control: %s", (Get_Cap(ehci_hcs_params) & 4137 EHCI_HCS_PORT_POWER_CONTROL) ? "Yes" : "No"); 4138 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4139 "No of root hub ports: 0x%x\n", 4140 Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); 4141 4142 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4143 "Capability Parameters\n"); 4144 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4145 "EHCI extended capability: %s", (Get_Cap(ehci_hcc_params) & 4146 EHCI_HCC_EECP) ? "Yes" : "No"); 4147 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4148 "Isoch schedule threshold: 0x%x", 4149 Get_Cap(ehci_hcc_params) & EHCI_HCC_ISOCH_SCHED_THRESHOLD); 4150 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4151 "Async schedule park capability: %s", (Get_Cap(ehci_hcc_params) & 4152 EHCI_HCC_ASYNC_SCHED_PARK_CAP) ? "Yes" : "No"); 4153 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4154 "Programmable frame list flag: %s", (Get_Cap(ehci_hcc_params) & 4155 EHCI_HCC_PROG_FRAME_LIST_FLAG) ? "256/512/1024" : "1024"); 4156 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4157 "64bit addressing capability: %s\n", (Get_Cap(ehci_hcc_params) & 4158 EHCI_HCC_64BIT_ADDR_CAP) ? "Yes" : "No"); 4159 4160 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4161 "Classic Port Route Description"); 4162 4163 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4164 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4165 "\tPort Route 0x%x: 0x%x", i, Get_8Cap(ehci_port_route[i])); 4166 } 4167 } 4168 4169 4170 /* 4171 * ehci_print_regs: 4172 */ 4173 void 4174 ehci_print_regs(ehci_state_t *ehcip) 4175 { 4176 uint_t i; 4177 4178 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4179 "\n\tEHCI%d Operational Registers\n", 4180 ddi_get_instance(ehcip->ehci_dip)); 4181 4182 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4183 "Command: 0x%x Status: 0x%x", 4184 Get_OpReg(ehci_command), Get_OpReg(ehci_status)); 4185 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4186 "Interrupt: 0x%x Frame Index: 0x%x", 4187 Get_OpReg(ehci_interrupt), Get_OpReg(ehci_frame_index)); 4188 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4189 "Control Segment: 0x%x Periodic List Base: 0x%x", 4190 Get_OpReg(ehci_ctrl_segment), Get_OpReg(ehci_periodic_list_base)); 4191 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4192 "Async List Addr: 0x%x Config Flag: 0x%x", 4193 Get_OpReg(ehci_async_list_addr), Get_OpReg(ehci_config_flag)); 4194 4195 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4196 "Root Hub Port Status"); 4197 4198 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4199 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4200 "\tPort Status 0x%x: 0x%x ", i, 4201 Get_OpReg(ehci_rh_port_status[i])); 4202 } 4203 } 4204 4205 4206 /* 4207 * ehci_print_qh: 4208 */ 4209 void 4210 ehci_print_qh( 4211 ehci_state_t *ehcip, 4212 ehci_qh_t *qh) 4213 { 4214 uint_t i; 4215 4216 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4217 "ehci_print_qh: qh = 0x%p", (void *)qh); 4218 4219 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4220 "\tqh_link_ptr: 0x%x ", Get_QH(qh->qh_link_ptr)); 4221 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4222 "\tqh_ctrl: 0x%x ", Get_QH(qh->qh_ctrl)); 4223 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4224 "\tqh_split_ctrl: 0x%x ", Get_QH(qh->qh_split_ctrl)); 4225 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4226 "\tqh_curr_qtd: 0x%x ", Get_QH(qh->qh_curr_qtd)); 4227 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4228 "\tqh_next_qtd: 0x%x ", Get_QH(qh->qh_next_qtd)); 4229 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4230 "\tqh_alt_next_qtd: 0x%x ", Get_QH(qh->qh_alt_next_qtd)); 4231 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4232 "\tqh_status: 0x%x ", Get_QH(qh->qh_status)); 4233 4234 for (i = 0; i < 5; i++) { 4235 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4236 "\tqh_buf[%d]: 0x%x ", i, Get_QH(qh->qh_buf[i])); 4237 } 4238 4239 for (i = 0; i < 5; i++) { 4240 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4241 "\tqh_buf_high[%d]: 0x%x ", 4242 i, Get_QH(qh->qh_buf_high[i])); 4243 } 4244 4245 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4246 "\tqh_dummy_qtd: 0x%x ", Get_QH(qh->qh_dummy_qtd)); 4247 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4248 "\tqh_prev: 0x%x ", Get_QH(qh->qh_prev)); 4249 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4250 "\tqh_state: 0x%x ", Get_QH(qh->qh_state)); 4251 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4252 "\tqh_reclaim_next: 0x%x ", Get_QH(qh->qh_reclaim_next)); 4253 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4254 "\tqh_reclaim_frame: 0x%x ", Get_QH(qh->qh_reclaim_frame)); 4255 } 4256 4257 4258 /* 4259 * ehci_print_qtd: 4260 */ 4261 void 4262 ehci_print_qtd( 4263 ehci_state_t *ehcip, 4264 ehci_qtd_t *qtd) 4265 { 4266 uint_t i; 4267 4268 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4269 "ehci_print_qtd: qtd = 0x%p", (void *)qtd); 4270 4271 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4272 "\tqtd_next_qtd: 0x%x ", Get_QTD(qtd->qtd_next_qtd)); 4273 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4274 "\tqtd_alt_next_qtd: 0x%x ", Get_QTD(qtd->qtd_alt_next_qtd)); 4275 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4276 "\tqtd_ctrl: 0x%x ", Get_QTD(qtd->qtd_ctrl)); 4277 4278 for (i = 0; i < 5; i++) { 4279 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4280 "\tqtd_buf[%d]: 0x%x ", i, Get_QTD(qtd->qtd_buf[i])); 4281 } 4282 4283 for (i = 0; i < 5; i++) { 4284 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4285 "\tqtd_buf_high[%d]: 0x%x ", 4286 i, Get_QTD(qtd->qtd_buf_high[i])); 4287 } 4288 4289 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4290 "\tqtd_trans_wrapper: 0x%x ", Get_QTD(qtd->qtd_trans_wrapper)); 4291 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4292 "\tqtd_tw_next_qtd: 0x%x ", Get_QTD(qtd->qtd_tw_next_qtd)); 4293 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4294 "\tqtd_active_qtd_next: 0x%x ", Get_QTD(qtd->qtd_active_qtd_next)); 4295 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4296 "\tqtd_active_qtd_prev: 0x%x ", Get_QTD(qtd->qtd_active_qtd_prev)); 4297 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4298 "\tqtd_state: 0x%x ", Get_QTD(qtd->qtd_state)); 4299 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4300 "\tqtd_ctrl_phase: 0x%x ", Get_QTD(qtd->qtd_ctrl_phase)); 4301 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4302 "\tqtd_xfer_offs: 0x%x ", Get_QTD(qtd->qtd_xfer_offs)); 4303 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4304 "\tqtd_xfer_len: 0x%x ", Get_QTD(qtd->qtd_xfer_len)); 4305 } 4306 4307 /* 4308 * ehci kstat functions 4309 */ 4310 4311 /* 4312 * ehci_create_stats: 4313 * 4314 * Allocate and initialize the ehci kstat structures 4315 */ 4316 void 4317 ehci_create_stats(ehci_state_t *ehcip) 4318 { 4319 char kstatname[KSTAT_STRLEN]; 4320 const char *dname = ddi_driver_name(ehcip->ehci_dip); 4321 char *usbtypes[USB_N_COUNT_KSTATS] = 4322 {"ctrl", "isoch", "bulk", "intr"}; 4323 uint_t instance = ehcip->ehci_instance; 4324 ehci_intrs_stats_t *isp; 4325 int i; 4326 4327 if (EHCI_INTRS_STATS(ehcip) == NULL) { 4328 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs", 4329 dname, instance); 4330 EHCI_INTRS_STATS(ehcip) = kstat_create("usba", instance, 4331 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED, 4332 sizeof (ehci_intrs_stats_t) / sizeof (kstat_named_t), 4333 KSTAT_FLAG_PERSISTENT); 4334 4335 if (EHCI_INTRS_STATS(ehcip)) { 4336 isp = EHCI_INTRS_STATS_DATA(ehcip); 4337 kstat_named_init(&isp->ehci_sts_total, 4338 "Interrupts Total", KSTAT_DATA_UINT64); 4339 kstat_named_init(&isp->ehci_sts_not_claimed, 4340 "Not Claimed", KSTAT_DATA_UINT64); 4341 kstat_named_init(&isp->ehci_sts_async_sched_status, 4342 "Async schedule status", KSTAT_DATA_UINT64); 4343 kstat_named_init(&isp->ehci_sts_periodic_sched_status, 4344 "Periodic sched status", KSTAT_DATA_UINT64); 4345 kstat_named_init(&isp->ehci_sts_empty_async_schedule, 4346 "Empty async schedule", KSTAT_DATA_UINT64); 4347 kstat_named_init(&isp->ehci_sts_host_ctrl_halted, 4348 "Host controller Halted", KSTAT_DATA_UINT64); 4349 kstat_named_init(&isp->ehci_sts_async_advance_intr, 4350 "Intr on async advance", KSTAT_DATA_UINT64); 4351 kstat_named_init(&isp->ehci_sts_host_system_error_intr, 4352 "Host system error", KSTAT_DATA_UINT64); 4353 kstat_named_init(&isp->ehci_sts_frm_list_rollover_intr, 4354 "Frame list rollover", KSTAT_DATA_UINT64); 4355 kstat_named_init(&isp->ehci_sts_rh_port_change_intr, 4356 "Port change detect", KSTAT_DATA_UINT64); 4357 kstat_named_init(&isp->ehci_sts_usb_error_intr, 4358 "USB error interrupt", KSTAT_DATA_UINT64); 4359 kstat_named_init(&isp->ehci_sts_usb_intr, 4360 "USB interrupt", KSTAT_DATA_UINT64); 4361 4362 EHCI_INTRS_STATS(ehcip)->ks_private = ehcip; 4363 EHCI_INTRS_STATS(ehcip)->ks_update = nulldev; 4364 kstat_install(EHCI_INTRS_STATS(ehcip)); 4365 } 4366 } 4367 4368 if (EHCI_TOTAL_STATS(ehcip) == NULL) { 4369 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total", 4370 dname, instance); 4371 EHCI_TOTAL_STATS(ehcip) = kstat_create("usba", instance, 4372 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1, 4373 KSTAT_FLAG_PERSISTENT); 4374 4375 if (EHCI_TOTAL_STATS(ehcip)) { 4376 kstat_install(EHCI_TOTAL_STATS(ehcip)); 4377 } 4378 } 4379 4380 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4381 if (ehcip->ehci_count_stats[i] == NULL) { 4382 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s", 4383 dname, instance, usbtypes[i]); 4384 ehcip->ehci_count_stats[i] = kstat_create("usba", 4385 instance, kstatname, "usb_byte_count", 4386 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 4387 4388 if (ehcip->ehci_count_stats[i]) { 4389 kstat_install(ehcip->ehci_count_stats[i]); 4390 } 4391 } 4392 } 4393 } 4394 4395 4396 /* 4397 * ehci_destroy_stats: 4398 * 4399 * Clean up ehci kstat structures 4400 */ 4401 void 4402 ehci_destroy_stats(ehci_state_t *ehcip) 4403 { 4404 int i; 4405 4406 if (EHCI_INTRS_STATS(ehcip)) { 4407 kstat_delete(EHCI_INTRS_STATS(ehcip)); 4408 EHCI_INTRS_STATS(ehcip) = NULL; 4409 } 4410 4411 if (EHCI_TOTAL_STATS(ehcip)) { 4412 kstat_delete(EHCI_TOTAL_STATS(ehcip)); 4413 EHCI_TOTAL_STATS(ehcip) = NULL; 4414 } 4415 4416 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4417 if (ehcip->ehci_count_stats[i]) { 4418 kstat_delete(ehcip->ehci_count_stats[i]); 4419 ehcip->ehci_count_stats[i] = NULL; 4420 } 4421 } 4422 } 4423 4424 4425 /* 4426 * ehci_do_intrs_stats: 4427 * 4428 * ehci status information 4429 */ 4430 void 4431 ehci_do_intrs_stats( 4432 ehci_state_t *ehcip, 4433 int val) 4434 { 4435 if (EHCI_INTRS_STATS(ehcip)) { 4436 EHCI_INTRS_STATS_DATA(ehcip)->ehci_sts_total.value.ui64++; 4437 switch (val) { 4438 case EHCI_STS_ASYNC_SCHED_STATUS: 4439 EHCI_INTRS_STATS_DATA(ehcip)-> 4440 ehci_sts_async_sched_status.value.ui64++; 4441 break; 4442 case EHCI_STS_PERIODIC_SCHED_STATUS: 4443 EHCI_INTRS_STATS_DATA(ehcip)-> 4444 ehci_sts_periodic_sched_status.value.ui64++; 4445 break; 4446 case EHCI_STS_EMPTY_ASYNC_SCHEDULE: 4447 EHCI_INTRS_STATS_DATA(ehcip)-> 4448 ehci_sts_empty_async_schedule.value.ui64++; 4449 break; 4450 case EHCI_STS_HOST_CTRL_HALTED: 4451 EHCI_INTRS_STATS_DATA(ehcip)-> 4452 ehci_sts_host_ctrl_halted.value.ui64++; 4453 break; 4454 case EHCI_STS_ASYNC_ADVANCE_INTR: 4455 EHCI_INTRS_STATS_DATA(ehcip)-> 4456 ehci_sts_async_advance_intr.value.ui64++; 4457 break; 4458 case EHCI_STS_HOST_SYSTEM_ERROR_INTR: 4459 EHCI_INTRS_STATS_DATA(ehcip)-> 4460 ehci_sts_host_system_error_intr.value.ui64++; 4461 break; 4462 case EHCI_STS_FRM_LIST_ROLLOVER_INTR: 4463 EHCI_INTRS_STATS_DATA(ehcip)-> 4464 ehci_sts_frm_list_rollover_intr.value.ui64++; 4465 break; 4466 case EHCI_STS_RH_PORT_CHANGE_INTR: 4467 EHCI_INTRS_STATS_DATA(ehcip)-> 4468 ehci_sts_rh_port_change_intr.value.ui64++; 4469 break; 4470 case EHCI_STS_USB_ERROR_INTR: 4471 EHCI_INTRS_STATS_DATA(ehcip)-> 4472 ehci_sts_usb_error_intr.value.ui64++; 4473 break; 4474 case EHCI_STS_USB_INTR: 4475 EHCI_INTRS_STATS_DATA(ehcip)-> 4476 ehci_sts_usb_intr.value.ui64++; 4477 break; 4478 default: 4479 EHCI_INTRS_STATS_DATA(ehcip)-> 4480 ehci_sts_not_claimed.value.ui64++; 4481 break; 4482 } 4483 } 4484 } 4485 4486 4487 /* 4488 * ehci_do_byte_stats: 4489 * 4490 * ehci data xfer information 4491 */ 4492 void 4493 ehci_do_byte_stats( 4494 ehci_state_t *ehcip, 4495 size_t len, 4496 uint8_t attr, 4497 uint8_t addr) 4498 { 4499 uint8_t type = attr & USB_EP_ATTR_MASK; 4500 uint8_t dir = addr & USB_EP_DIR_MASK; 4501 4502 if (dir == USB_EP_DIR_IN) { 4503 EHCI_TOTAL_STATS_DATA(ehcip)->reads++; 4504 EHCI_TOTAL_STATS_DATA(ehcip)->nread += len; 4505 switch (type) { 4506 case USB_EP_ATTR_CONTROL: 4507 EHCI_CTRL_STATS(ehcip)->reads++; 4508 EHCI_CTRL_STATS(ehcip)->nread += len; 4509 break; 4510 case USB_EP_ATTR_BULK: 4511 EHCI_BULK_STATS(ehcip)->reads++; 4512 EHCI_BULK_STATS(ehcip)->nread += len; 4513 break; 4514 case USB_EP_ATTR_INTR: 4515 EHCI_INTR_STATS(ehcip)->reads++; 4516 EHCI_INTR_STATS(ehcip)->nread += len; 4517 break; 4518 case USB_EP_ATTR_ISOCH: 4519 EHCI_ISOC_STATS(ehcip)->reads++; 4520 EHCI_ISOC_STATS(ehcip)->nread += len; 4521 break; 4522 } 4523 } else if (dir == USB_EP_DIR_OUT) { 4524 EHCI_TOTAL_STATS_DATA(ehcip)->writes++; 4525 EHCI_TOTAL_STATS_DATA(ehcip)->nwritten += len; 4526 switch (type) { 4527 case USB_EP_ATTR_CONTROL: 4528 EHCI_CTRL_STATS(ehcip)->writes++; 4529 EHCI_CTRL_STATS(ehcip)->nwritten += len; 4530 break; 4531 case USB_EP_ATTR_BULK: 4532 EHCI_BULK_STATS(ehcip)->writes++; 4533 EHCI_BULK_STATS(ehcip)->nwritten += len; 4534 break; 4535 case USB_EP_ATTR_INTR: 4536 EHCI_INTR_STATS(ehcip)->writes++; 4537 EHCI_INTR_STATS(ehcip)->nwritten += len; 4538 break; 4539 case USB_EP_ATTR_ISOCH: 4540 EHCI_ISOC_STATS(ehcip)->writes++; 4541 EHCI_ISOC_STATS(ehcip)->nwritten += len; 4542 break; 4543 } 4544 } 4545 } 4546