1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * EHCI Host Controller Driver (EHCI) 30 * 31 * The EHCI driver is a software driver which interfaces to the Universal 32 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 33 * the Host Controller is defined by the EHCI Host Controller Interface. 34 * 35 * This module contains the main EHCI driver code which handles all USB 36 * transfers, bandwidth allocations and other general functionalities. 37 */ 38 39 #include <sys/usb/hcd/ehci/ehcid.h> 40 #include <sys/usb/hcd/ehci/ehci_isoch.h> 41 #include <sys/usb/hcd/ehci/ehci_xfer.h> 42 43 /* 44 * EHCI MSI tunable: 45 * 46 * By default MSI is enabled on all supported platforms except for the 47 * EHCI controller of ULI1575 South bridge. 48 */ 49 boolean_t ehci_enable_msi = B_TRUE; 50 51 /* Pointer to the state structure */ 52 extern void *ehci_statep; 53 54 extern void ehci_handle_endpoint_reclaimation(ehci_state_t *); 55 56 extern uint_t ehci_vt62x2_workaround; 57 58 /* Adjustable variables for the size of the pools */ 59 int ehci_qh_pool_size = EHCI_QH_POOL_SIZE; 60 int ehci_qtd_pool_size = EHCI_QTD_POOL_SIZE; 61 62 /* 63 * Initialize the values which the order of 32ms intr qh are executed 64 * by the host controller in the lattice tree. 65 */ 66 static uchar_t ehci_index[EHCI_NUM_INTR_QH_LISTS] = 67 {0x00, 0x10, 0x08, 0x18, 68 0x04, 0x14, 0x0c, 0x1c, 69 0x02, 0x12, 0x0a, 0x1a, 70 0x06, 0x16, 0x0e, 0x1e, 71 0x01, 0x11, 0x09, 0x19, 72 0x05, 0x15, 0x0d, 0x1d, 73 0x03, 0x13, 0x0b, 0x1b, 74 0x07, 0x17, 0x0f, 0x1f}; 75 76 /* 77 * Initialize the values which are used to calculate start split mask 78 * for the low/full/high speed interrupt and isochronous endpoints. 79 */ 80 static uint_t ehci_start_split_mask[15] = { 81 /* 82 * For high/full/low speed usb devices. For high speed 83 * device with polling interval greater than or equal 84 * to 8us (125us). 85 */ 86 0x01, /* 00000001 */ 87 0x02, /* 00000010 */ 88 0x04, /* 00000100 */ 89 0x08, /* 00001000 */ 90 0x10, /* 00010000 */ 91 0x20, /* 00100000 */ 92 0x40, /* 01000000 */ 93 0x80, /* 10000000 */ 94 95 /* Only for high speed devices with polling interval 4us */ 96 0x11, /* 00010001 */ 97 0x22, /* 00100010 */ 98 0x44, /* 01000100 */ 99 0x88, /* 10001000 */ 100 101 /* Only for high speed devices with polling interval 2us */ 102 0x55, /* 01010101 */ 103 0xaa, /* 10101010 */ 104 105 /* Only for high speed devices with polling interval 1us */ 106 0xff /* 11111111 */ 107 }; 108 109 /* 110 * Initialize the values which are used to calculate complete split mask 111 * for the low/full speed interrupt and isochronous endpoints. 112 */ 113 static uint_t ehci_intr_complete_split_mask[7] = { 114 /* Only full/low speed devices */ 115 0x1c, /* 00011100 */ 116 0x38, /* 00111000 */ 117 0x70, /* 01110000 */ 118 0xe0, /* 11100000 */ 119 0x00, /* Need FSTN feature */ 120 0x00, /* Need FSTN feature */ 121 0x00 /* Need FSTN feature */ 122 }; 123 124 125 /* 126 * EHCI Internal Function Prototypes 127 */ 128 129 /* Host Controller Driver (HCD) initialization functions */ 130 void ehci_set_dma_attributes(ehci_state_t *ehcip); 131 int ehci_allocate_pools(ehci_state_t *ehcip); 132 void ehci_decode_ddi_dma_addr_bind_handle_result( 133 ehci_state_t *ehcip, 134 int result); 135 int ehci_map_regs(ehci_state_t *ehcip); 136 int ehci_register_intrs_and_init_mutex( 137 ehci_state_t *ehcip); 138 static int ehci_add_intrs(ehci_state_t *ehcip, 139 int intr_type); 140 int ehci_init_ctlr(ehci_state_t *ehcip, 141 int init_type); 142 static int ehci_take_control(ehci_state_t *ehcip); 143 static int ehci_init_periodic_frame_lst_table( 144 ehci_state_t *ehcip); 145 static void ehci_build_interrupt_lattice( 146 ehci_state_t *ehcip); 147 usba_hcdi_ops_t *ehci_alloc_hcdi_ops(ehci_state_t *ehcip); 148 149 /* Host Controller Driver (HCD) deinitialization functions */ 150 int ehci_cleanup(ehci_state_t *ehcip); 151 static void ehci_rem_intrs(ehci_state_t *ehcip); 152 int ehci_cpr_suspend(ehci_state_t *ehcip); 153 int ehci_cpr_resume(ehci_state_t *ehcip); 154 155 /* Bandwidth Allocation functions */ 156 int ehci_allocate_bandwidth(ehci_state_t *ehcip, 157 usba_pipe_handle_data_t *ph, 158 uint_t *pnode, 159 uchar_t *smask, 160 uchar_t *cmask); 161 static int ehci_allocate_high_speed_bandwidth( 162 ehci_state_t *ehcip, 163 usba_pipe_handle_data_t *ph, 164 uint_t *hnode, 165 uchar_t *smask, 166 uchar_t *cmask); 167 static int ehci_allocate_classic_tt_bandwidth( 168 ehci_state_t *ehcip, 169 usba_pipe_handle_data_t *ph, 170 uint_t pnode); 171 void ehci_deallocate_bandwidth(ehci_state_t *ehcip, 172 usba_pipe_handle_data_t *ph, 173 uint_t pnode, 174 uchar_t smask, 175 uchar_t cmask); 176 static void ehci_deallocate_high_speed_bandwidth( 177 ehci_state_t *ehcip, 178 usba_pipe_handle_data_t *ph, 179 uint_t hnode, 180 uchar_t smask, 181 uchar_t cmask); 182 static void ehci_deallocate_classic_tt_bandwidth( 183 ehci_state_t *ehcip, 184 usba_pipe_handle_data_t *ph, 185 uint_t pnode); 186 static int ehci_compute_high_speed_bandwidth( 187 ehci_state_t *ehcip, 188 usb_ep_descr_t *endpoint, 189 usb_port_status_t port_status, 190 uint_t *sbandwidth, 191 uint_t *cbandwidth); 192 static int ehci_compute_classic_bandwidth( 193 usb_ep_descr_t *endpoint, 194 usb_port_status_t port_status, 195 uint_t *bandwidth); 196 int ehci_adjust_polling_interval( 197 ehci_state_t *ehcip, 198 usb_ep_descr_t *endpoint, 199 usb_port_status_t port_status); 200 static int ehci_adjust_high_speed_polling_interval( 201 ehci_state_t *ehcip, 202 usb_ep_descr_t *endpoint); 203 static uint_t ehci_lattice_height(uint_t interval); 204 static uint_t ehci_lattice_parent(uint_t node); 205 static uint_t ehci_find_periodic_node( 206 uint_t leaf, 207 int interval); 208 static uint_t ehci_leftmost_leaf(uint_t node, 209 uint_t height); 210 static uint_t ehci_pow_2(uint_t x); 211 static uint_t ehci_log_2(uint_t x); 212 static int ehci_find_bestfit_hs_mask( 213 ehci_state_t *ehcip, 214 uchar_t *smask, 215 uint_t *pnode, 216 usb_ep_descr_t *endpoint, 217 uint_t bandwidth, 218 int interval); 219 static int ehci_find_bestfit_ls_intr_mask( 220 ehci_state_t *ehcip, 221 uchar_t *smask, 222 uchar_t *cmask, 223 uint_t *pnode, 224 uint_t sbandwidth, 225 uint_t cbandwidth, 226 int interval); 227 static int ehci_find_bestfit_sitd_in_mask( 228 ehci_state_t *ehcip, 229 uchar_t *smask, 230 uchar_t *cmask, 231 uint_t *pnode, 232 uint_t sbandwidth, 233 uint_t cbandwidth, 234 int interval); 235 static int ehci_find_bestfit_sitd_out_mask( 236 ehci_state_t *ehcip, 237 uchar_t *smask, 238 uint_t *pnode, 239 uint_t sbandwidth, 240 int interval); 241 static uint_t ehci_calculate_bw_availability_mask( 242 ehci_state_t *ehcip, 243 uint_t bandwidth, 244 int leaf, 245 int leaf_count, 246 uchar_t *bw_mask); 247 static void ehci_update_bw_availability( 248 ehci_state_t *ehcip, 249 int bandwidth, 250 int leftmost_leaf, 251 int leaf_count, 252 uchar_t mask); 253 254 /* Miscellaneous functions */ 255 ehci_state_t *ehci_obtain_state( 256 dev_info_t *dip); 257 int ehci_state_is_operational( 258 ehci_state_t *ehcip); 259 int ehci_do_soft_reset( 260 ehci_state_t *ehcip); 261 usb_req_attrs_t ehci_get_xfer_attrs(ehci_state_t *ehcip, 262 ehci_pipe_private_t *pp, 263 ehci_trans_wrapper_t *tw); 264 usb_frame_number_t ehci_get_current_frame_number( 265 ehci_state_t *ehcip); 266 static void ehci_cpr_cleanup( 267 ehci_state_t *ehcip); 268 int ehci_wait_for_sof( 269 ehci_state_t *ehcip); 270 void ehci_toggle_scheduler( 271 ehci_state_t *ehcip); 272 void ehci_print_caps(ehci_state_t *ehcip); 273 void ehci_print_regs(ehci_state_t *ehcip); 274 void ehci_print_qh(ehci_state_t *ehcip, 275 ehci_qh_t *qh); 276 void ehci_print_qtd(ehci_state_t *ehcip, 277 ehci_qtd_t *qtd); 278 void ehci_create_stats(ehci_state_t *ehcip); 279 void ehci_destroy_stats(ehci_state_t *ehcip); 280 void ehci_do_intrs_stats(ehci_state_t *ehcip, 281 int val); 282 void ehci_do_byte_stats(ehci_state_t *ehcip, 283 size_t len, 284 uint8_t attr, 285 uint8_t addr); 286 287 /* 288 * check if this ehci controller can support PM 289 */ 290 int 291 ehci_hcdi_pm_support(dev_info_t *dip) 292 { 293 ehci_state_t *ehcip = ddi_get_soft_state(ehci_statep, 294 ddi_get_instance(dip)); 295 296 if (((ehcip->ehci_vendor_id == PCI_VENDOR_NEC_COMBO) && 297 (ehcip->ehci_device_id == PCI_DEVICE_NEC_COMBO)) || 298 299 ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 300 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) || 301 302 (ehcip->ehci_vendor_id == PCI_VENDOR_VIA)) { 303 304 return (USB_SUCCESS); 305 } 306 307 return (USB_FAILURE); 308 } 309 310 311 /* 312 * Host Controller Driver (HCD) initialization functions 313 */ 314 315 /* 316 * ehci_set_dma_attributes: 317 * 318 * Set the limits in the DMA attributes structure. Most of the values used 319 * in the DMA limit structures are the default values as specified by the 320 * Writing PCI device drivers document. 321 */ 322 void 323 ehci_set_dma_attributes(ehci_state_t *ehcip) 324 { 325 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 326 "ehci_set_dma_attributes:"); 327 328 /* Initialize the DMA attributes */ 329 ehcip->ehci_dma_attr.dma_attr_version = DMA_ATTR_V0; 330 ehcip->ehci_dma_attr.dma_attr_addr_lo = 0x00000000ull; 331 ehcip->ehci_dma_attr.dma_attr_addr_hi = 0xfffffffeull; 332 333 /* 32 bit addressing */ 334 ehcip->ehci_dma_attr.dma_attr_count_max = EHCI_DMA_ATTR_COUNT_MAX; 335 336 /* Byte alignment */ 337 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 338 339 /* 340 * Since PCI specification is byte alignment, the 341 * burst size field should be set to 1 for PCI devices. 342 */ 343 ehcip->ehci_dma_attr.dma_attr_burstsizes = 0x1; 344 345 ehcip->ehci_dma_attr.dma_attr_minxfer = 0x1; 346 ehcip->ehci_dma_attr.dma_attr_maxxfer = EHCI_DMA_ATTR_MAX_XFER; 347 ehcip->ehci_dma_attr.dma_attr_seg = 0xffffffffull; 348 ehcip->ehci_dma_attr.dma_attr_sgllen = 1; 349 ehcip->ehci_dma_attr.dma_attr_granular = EHCI_DMA_ATTR_GRANULAR; 350 ehcip->ehci_dma_attr.dma_attr_flags = 0; 351 } 352 353 354 /* 355 * ehci_allocate_pools: 356 * 357 * Allocate the system memory for the Endpoint Descriptor (QH) and for the 358 * Transfer Descriptor (QTD) pools. Both QH and QTD structures must be aligned 359 * to a 16 byte boundary. 360 */ 361 int 362 ehci_allocate_pools(ehci_state_t *ehcip) 363 { 364 ddi_device_acc_attr_t dev_attr; 365 size_t real_length; 366 int result; 367 uint_t ccount; 368 int i; 369 370 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 371 "ehci_allocate_pools:"); 372 373 /* The host controller will be little endian */ 374 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 375 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 376 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 377 378 /* Byte alignment */ 379 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_TD_QH_ALIGNMENT; 380 381 /* Allocate the QTD pool DMA handle */ 382 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 383 DDI_DMA_SLEEP, 0, 384 &ehcip->ehci_qtd_pool_dma_handle) != DDI_SUCCESS) { 385 386 goto failure; 387 } 388 389 /* Allocate the memory for the QTD pool */ 390 if (ddi_dma_mem_alloc(ehcip->ehci_qtd_pool_dma_handle, 391 ehci_qtd_pool_size * sizeof (ehci_qtd_t), 392 &dev_attr, 393 DDI_DMA_CONSISTENT, 394 DDI_DMA_SLEEP, 395 0, 396 (caddr_t *)&ehcip->ehci_qtd_pool_addr, 397 &real_length, 398 &ehcip->ehci_qtd_pool_mem_handle)) { 399 400 goto failure; 401 } 402 403 /* Map the QTD pool into the I/O address space */ 404 result = ddi_dma_addr_bind_handle( 405 ehcip->ehci_qtd_pool_dma_handle, 406 NULL, 407 (caddr_t)ehcip->ehci_qtd_pool_addr, 408 real_length, 409 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 410 DDI_DMA_SLEEP, 411 NULL, 412 &ehcip->ehci_qtd_pool_cookie, 413 &ccount); 414 415 bzero((void *)ehcip->ehci_qtd_pool_addr, 416 ehci_qtd_pool_size * sizeof (ehci_qtd_t)); 417 418 /* Process the result */ 419 if (result == DDI_DMA_MAPPED) { 420 /* The cookie count should be 1 */ 421 if (ccount != 1) { 422 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 423 "ehci_allocate_pools: More than 1 cookie"); 424 425 goto failure; 426 } 427 } else { 428 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 429 "ehci_allocate_pools: Result = %d", result); 430 431 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 432 433 goto failure; 434 } 435 436 /* 437 * DMA addresses for QTD pools are bound 438 */ 439 ehcip->ehci_dma_addr_bind_flag |= EHCI_QTD_POOL_BOUND; 440 441 /* Initialize the QTD pool */ 442 for (i = 0; i < ehci_qtd_pool_size; i ++) { 443 Set_QTD(ehcip->ehci_qtd_pool_addr[i]. 444 qtd_state, EHCI_QTD_FREE); 445 } 446 447 /* Allocate the QTD pool DMA handle */ 448 if (ddi_dma_alloc_handle(ehcip->ehci_dip, 449 &ehcip->ehci_dma_attr, 450 DDI_DMA_SLEEP, 451 0, 452 &ehcip->ehci_qh_pool_dma_handle) != DDI_SUCCESS) { 453 454 goto failure; 455 } 456 457 /* Allocate the memory for the QH pool */ 458 if (ddi_dma_mem_alloc(ehcip->ehci_qh_pool_dma_handle, 459 ehci_qh_pool_size * sizeof (ehci_qh_t), 460 &dev_attr, 461 DDI_DMA_CONSISTENT, 462 DDI_DMA_SLEEP, 463 0, 464 (caddr_t *)&ehcip->ehci_qh_pool_addr, 465 &real_length, 466 &ehcip->ehci_qh_pool_mem_handle) != DDI_SUCCESS) { 467 468 goto failure; 469 } 470 471 result = ddi_dma_addr_bind_handle(ehcip->ehci_qh_pool_dma_handle, 472 NULL, 473 (caddr_t)ehcip->ehci_qh_pool_addr, 474 real_length, 475 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 476 DDI_DMA_SLEEP, 477 NULL, 478 &ehcip->ehci_qh_pool_cookie, 479 &ccount); 480 481 bzero((void *)ehcip->ehci_qh_pool_addr, 482 ehci_qh_pool_size * sizeof (ehci_qh_t)); 483 484 /* Process the result */ 485 if (result == DDI_DMA_MAPPED) { 486 /* The cookie count should be 1 */ 487 if (ccount != 1) { 488 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 489 "ehci_allocate_pools: More than 1 cookie"); 490 491 goto failure; 492 } 493 } else { 494 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 495 496 goto failure; 497 } 498 499 /* 500 * DMA addresses for QH pools are bound 501 */ 502 ehcip->ehci_dma_addr_bind_flag |= EHCI_QH_POOL_BOUND; 503 504 /* Initialize the QH pool */ 505 for (i = 0; i < ehci_qh_pool_size; i ++) { 506 Set_QH(ehcip->ehci_qh_pool_addr[i].qh_state, EHCI_QH_FREE); 507 } 508 509 /* Byte alignment */ 510 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 511 512 return (DDI_SUCCESS); 513 514 failure: 515 /* Byte alignment */ 516 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 517 518 return (DDI_FAILURE); 519 } 520 521 522 /* 523 * ehci_decode_ddi_dma_addr_bind_handle_result: 524 * 525 * Process the return values of ddi_dma_addr_bind_handle() 526 */ 527 void 528 ehci_decode_ddi_dma_addr_bind_handle_result( 529 ehci_state_t *ehcip, 530 int result) 531 { 532 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ehcip->ehci_log_hdl, 533 "ehci_decode_ddi_dma_addr_bind_handle_result:"); 534 535 switch (result) { 536 case DDI_DMA_PARTIAL_MAP: 537 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 538 "Partial transfers not allowed"); 539 break; 540 case DDI_DMA_INUSE: 541 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 542 "Handle is in use"); 543 break; 544 case DDI_DMA_NORESOURCES: 545 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 546 "No resources"); 547 break; 548 case DDI_DMA_NOMAPPING: 549 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 550 "No mapping"); 551 break; 552 case DDI_DMA_TOOBIG: 553 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 554 "Object is too big"); 555 break; 556 default: 557 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 558 "Unknown dma error"); 559 } 560 } 561 562 563 /* 564 * ehci_map_regs: 565 * 566 * The Host Controller (HC) contains a set of on-chip operational registers 567 * and which should be mapped into a non-cacheable portion of the system 568 * addressable space. 569 */ 570 int 571 ehci_map_regs(ehci_state_t *ehcip) 572 { 573 ddi_device_acc_attr_t attr; 574 uint16_t cmd_reg; 575 uint_t length; 576 577 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_map_regs:"); 578 579 /* Check to make sure we have memory access */ 580 if (pci_config_setup(ehcip->ehci_dip, 581 &ehcip->ehci_config_handle) != DDI_SUCCESS) { 582 583 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 584 "ehci_map_regs: Config error"); 585 586 return (DDI_FAILURE); 587 } 588 589 /* Make sure Memory Access Enable is set */ 590 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 591 592 if (!(cmd_reg & PCI_COMM_MAE)) { 593 594 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 595 "ehci_map_regs: Memory base address access disabled"); 596 597 return (DDI_FAILURE); 598 } 599 600 /* The host controller will be little endian */ 601 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 602 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 603 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 604 605 /* Map in EHCI Capability registers */ 606 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 607 (caddr_t *)&ehcip->ehci_capsp, 0, 608 sizeof (ehci_caps_t), &attr, 609 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 610 611 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 612 "ehci_map_regs: Map setup error"); 613 614 return (DDI_FAILURE); 615 } 616 617 length = ddi_get8(ehcip->ehci_caps_handle, 618 (uint8_t *)&ehcip->ehci_capsp->ehci_caps_length); 619 620 /* Free the original mapping */ 621 ddi_regs_map_free(&ehcip->ehci_caps_handle); 622 623 /* Re-map in EHCI Capability and Operational registers */ 624 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 625 (caddr_t *)&ehcip->ehci_capsp, 0, 626 length + sizeof (ehci_regs_t), &attr, 627 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 628 629 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 630 "ehci_map_regs: Map setup error"); 631 632 return (DDI_FAILURE); 633 } 634 635 /* Get the pointer to EHCI Operational Register */ 636 ehcip->ehci_regsp = (ehci_regs_t *) 637 ((uintptr_t)ehcip->ehci_capsp + length); 638 639 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 640 "ehci_map_regs: Capsp 0x%p Regsp 0x%p\n", 641 ehcip->ehci_capsp, ehcip->ehci_regsp); 642 643 return (DDI_SUCCESS); 644 } 645 646 /* 647 * The following simulated polling is for debugging purposes only. 648 * It is activated on x86 by setting usb-polling=true in GRUB or ehci.conf. 649 */ 650 static int 651 ehci_is_polled(dev_info_t *dip) 652 { 653 int ret; 654 char *propval; 655 656 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 657 "usb-polling", &propval) != DDI_SUCCESS) 658 659 return (0); 660 661 ret = (strcmp(propval, "true") == 0); 662 ddi_prop_free(propval); 663 664 return (ret); 665 } 666 667 static void 668 ehci_poll_intr(void *arg) 669 { 670 /* poll every msec */ 671 for (;;) { 672 (void) ehci_intr(arg, NULL); 673 delay(drv_usectohz(1000)); 674 } 675 } 676 677 /* 678 * ehci_register_intrs_and_init_mutex: 679 * 680 * Register interrupts and initialize each mutex and condition variables 681 */ 682 int 683 ehci_register_intrs_and_init_mutex(ehci_state_t *ehcip) 684 { 685 int intr_types; 686 687 #if defined(__x86) 688 uint8_t iline; 689 #endif 690 691 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 692 "ehci_register_intrs_and_init_mutex:"); 693 694 /* 695 * There is a known MSI hardware bug with the EHCI controller 696 * of ULI1575 southbridge. Hence MSI is disabled for this chip. 697 */ 698 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 699 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) { 700 ehcip->ehci_msi_enabled = B_FALSE; 701 } else { 702 /* Set the MSI enable flag from the global EHCI MSI tunable */ 703 ehcip->ehci_msi_enabled = ehci_enable_msi; 704 } 705 706 /* launch polling thread instead of enabling pci interrupt */ 707 if (ehci_is_polled(ehcip->ehci_dip)) { 708 extern pri_t maxclsyspri; 709 710 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 711 "ehci_register_intrs_and_init_mutex: " 712 "running in simulated polled mode"); 713 714 (void) thread_create(NULL, 0, ehci_poll_intr, ehcip, 0, &p0, 715 TS_RUN, maxclsyspri); 716 717 goto skip_intr; 718 } 719 720 #if defined(__x86) 721 /* 722 * Make sure that the interrupt pin is connected to the 723 * interrupt controller on x86. Interrupt line 255 means 724 * "unknown" or "not connected" (PCI spec 6.2.4, footnote 43). 725 * If we would return failure when interrupt line equals 255, then 726 * high speed devices will be routed to companion host controllers. 727 * However, it is not necessary to return failure here, and 728 * o/uhci codes don't check the interrupt line either. 729 * But it's good to log a message here for debug purposes. 730 */ 731 iline = pci_config_get8(ehcip->ehci_config_handle, 732 PCI_CONF_ILINE); 733 734 if (iline == 255) { 735 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 736 "ehci_register_intrs_and_init_mutex: " 737 "interrupt line value out of range (%d)", 738 iline); 739 } 740 #endif /* __x86 */ 741 742 /* Get supported interrupt types */ 743 if (ddi_intr_get_supported_types(ehcip->ehci_dip, 744 &intr_types) != DDI_SUCCESS) { 745 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 746 "ehci_register_intrs_and_init_mutex: " 747 "ddi_intr_get_supported_types failed"); 748 749 return (DDI_FAILURE); 750 } 751 752 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 753 "ehci_register_intrs_and_init_mutex: " 754 "supported interrupt types 0x%x", intr_types); 755 756 if ((intr_types & DDI_INTR_TYPE_MSI) && ehcip->ehci_msi_enabled) { 757 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_MSI) 758 != DDI_SUCCESS) { 759 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 760 "ehci_register_intrs_and_init_mutex: MSI " 761 "registration failed, trying FIXED interrupt \n"); 762 } else { 763 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 764 "ehci_register_intrs_and_init_mutex: " 765 "Using MSI interrupt type\n"); 766 767 ehcip->ehci_intr_type = DDI_INTR_TYPE_MSI; 768 ehcip->ehci_flags |= EHCI_INTR; 769 } 770 } 771 772 if ((!(ehcip->ehci_flags & EHCI_INTR)) && 773 (intr_types & DDI_INTR_TYPE_FIXED)) { 774 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_FIXED) 775 != DDI_SUCCESS) { 776 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 777 "ehci_register_intrs_and_init_mutex: " 778 "FIXED interrupt registration failed\n"); 779 780 return (DDI_FAILURE); 781 } 782 783 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 784 "ehci_register_intrs_and_init_mutex: " 785 "Using FIXED interrupt type\n"); 786 787 ehcip->ehci_intr_type = DDI_INTR_TYPE_FIXED; 788 ehcip->ehci_flags |= EHCI_INTR; 789 } 790 791 skip_intr: 792 /* Create prototype for advance on async schedule */ 793 cv_init(&ehcip->ehci_async_schedule_advance_cv, 794 NULL, CV_DRIVER, NULL); 795 796 return (DDI_SUCCESS); 797 } 798 799 800 /* 801 * ehci_add_intrs: 802 * 803 * Register FIXED or MSI interrupts. 804 */ 805 static int 806 ehci_add_intrs(ehci_state_t *ehcip, 807 int intr_type) 808 { 809 int actual, avail, intr_size, count = 0; 810 int i, flag, ret; 811 812 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 813 "ehci_add_intrs: interrupt type 0x%x", intr_type); 814 815 /* Get number of interrupts */ 816 ret = ddi_intr_get_nintrs(ehcip->ehci_dip, intr_type, &count); 817 if ((ret != DDI_SUCCESS) || (count == 0)) { 818 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 819 "ehci_add_intrs: ddi_intr_get_nintrs() failure, " 820 "ret: %d, count: %d", ret, count); 821 822 return (DDI_FAILURE); 823 } 824 825 /* Get number of available interrupts */ 826 ret = ddi_intr_get_navail(ehcip->ehci_dip, intr_type, &avail); 827 if ((ret != DDI_SUCCESS) || (avail == 0)) { 828 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 829 "ehci_add_intrs: ddi_intr_get_navail() failure, " 830 "ret: %d, count: %d", ret, count); 831 832 return (DDI_FAILURE); 833 } 834 835 if (avail < count) { 836 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 837 "ehci_add_intrs: ehci_add_intrs: nintrs () " 838 "returned %d, navail returned %d\n", count, avail); 839 } 840 841 /* Allocate an array of interrupt handles */ 842 intr_size = count * sizeof (ddi_intr_handle_t); 843 ehcip->ehci_htable = kmem_zalloc(intr_size, KM_SLEEP); 844 845 flag = (intr_type == DDI_INTR_TYPE_MSI) ? 846 DDI_INTR_ALLOC_STRICT:DDI_INTR_ALLOC_NORMAL; 847 848 /* call ddi_intr_alloc() */ 849 ret = ddi_intr_alloc(ehcip->ehci_dip, ehcip->ehci_htable, 850 intr_type, 0, count, &actual, flag); 851 852 if ((ret != DDI_SUCCESS) || (actual == 0)) { 853 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 854 "ehci_add_intrs: ddi_intr_alloc() failed %d", ret); 855 856 kmem_free(ehcip->ehci_htable, intr_size); 857 858 return (DDI_FAILURE); 859 } 860 861 if (actual < count) { 862 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 863 "ehci_add_intrs: Requested: %d, Received: %d\n", 864 count, actual); 865 866 for (i = 0; i < actual; i++) 867 (void) ddi_intr_free(ehcip->ehci_htable[i]); 868 869 kmem_free(ehcip->ehci_htable, intr_size); 870 871 return (DDI_FAILURE); 872 } 873 874 ehcip->ehci_intr_cnt = actual; 875 876 if ((ret = ddi_intr_get_pri(ehcip->ehci_htable[0], 877 &ehcip->ehci_intr_pri)) != DDI_SUCCESS) { 878 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 879 "ehci_add_intrs: ddi_intr_get_pri() failed %d", ret); 880 881 for (i = 0; i < actual; i++) 882 (void) ddi_intr_free(ehcip->ehci_htable[i]); 883 884 kmem_free(ehcip->ehci_htable, intr_size); 885 886 return (DDI_FAILURE); 887 } 888 889 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 890 "ehci_add_intrs: Supported Interrupt priority 0x%x", 891 ehcip->ehci_intr_pri); 892 893 /* Test for high level mutex */ 894 if (ehcip->ehci_intr_pri >= ddi_intr_get_hilevel_pri()) { 895 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 896 "ehci_add_intrs: Hi level interrupt not supported"); 897 898 for (i = 0; i < actual; i++) 899 (void) ddi_intr_free(ehcip->ehci_htable[i]); 900 901 kmem_free(ehcip->ehci_htable, intr_size); 902 903 return (DDI_FAILURE); 904 } 905 906 /* Initialize the mutex */ 907 mutex_init(&ehcip->ehci_int_mutex, NULL, MUTEX_DRIVER, 908 DDI_INTR_PRI(ehcip->ehci_intr_pri)); 909 910 /* Call ddi_intr_add_handler() */ 911 for (i = 0; i < actual; i++) { 912 if ((ret = ddi_intr_add_handler(ehcip->ehci_htable[i], 913 ehci_intr, (caddr_t)ehcip, 914 (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 915 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 916 "ehci_add_intrs:ddi_intr_add_handler() " 917 "failed %d", ret); 918 919 for (i = 0; i < actual; i++) 920 (void) ddi_intr_free(ehcip->ehci_htable[i]); 921 922 mutex_destroy(&ehcip->ehci_int_mutex); 923 kmem_free(ehcip->ehci_htable, intr_size); 924 925 return (DDI_FAILURE); 926 } 927 } 928 929 if ((ret = ddi_intr_get_cap(ehcip->ehci_htable[0], 930 &ehcip->ehci_intr_cap)) != DDI_SUCCESS) { 931 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 932 "ehci_add_intrs: ddi_intr_get_cap() failed %d", ret); 933 934 for (i = 0; i < actual; i++) { 935 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 936 (void) ddi_intr_free(ehcip->ehci_htable[i]); 937 } 938 939 mutex_destroy(&ehcip->ehci_int_mutex); 940 kmem_free(ehcip->ehci_htable, intr_size); 941 942 return (DDI_FAILURE); 943 } 944 945 /* Enable all interrupts */ 946 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 947 /* Call ddi_intr_block_enable() for MSI interrupts */ 948 (void) ddi_intr_block_enable(ehcip->ehci_htable, 949 ehcip->ehci_intr_cnt); 950 } else { 951 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 952 for (i = 0; i < ehcip->ehci_intr_cnt; i++) 953 (void) ddi_intr_enable(ehcip->ehci_htable[i]); 954 } 955 956 return (DDI_SUCCESS); 957 } 958 959 960 /* 961 * ehci_init_hardware 962 * 963 * take control from BIOS, reset EHCI host controller, and check version, etc. 964 */ 965 int 966 ehci_init_hardware(ehci_state_t *ehcip) 967 { 968 int revision; 969 uint16_t cmd_reg; 970 int abort_on_BIOS_take_over_failure; 971 972 /* Take control from the BIOS */ 973 if (ehci_take_control(ehcip) != USB_SUCCESS) { 974 975 /* read .conf file properties */ 976 abort_on_BIOS_take_over_failure = 977 ddi_prop_get_int(DDI_DEV_T_ANY, 978 ehcip->ehci_dip, DDI_PROP_DONTPASS, 979 "abort-on-BIOS-take-over-failure", 0); 980 981 if (abort_on_BIOS_take_over_failure) { 982 983 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 984 "Unable to take control from BIOS."); 985 986 return (DDI_FAILURE); 987 } 988 989 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 990 "Unable to take control from BIOS. Failure is ignored."); 991 } 992 993 /* set Memory Master Enable */ 994 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 995 cmd_reg |= (PCI_COMM_MAE | PCI_COMM_ME); 996 pci_config_put16(ehcip->ehci_config_handle, PCI_CONF_COMM, cmd_reg); 997 998 /* Reset the EHCI host controller */ 999 Set_OpReg(ehci_command, 1000 Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET); 1001 1002 /* Wait 10ms for reset to complete */ 1003 drv_usecwait(EHCI_RESET_TIMEWAIT); 1004 1005 ASSERT(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED); 1006 1007 /* Verify the version number */ 1008 revision = Get_16Cap(ehci_version); 1009 1010 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1011 "ehci_init_hardware: Revision 0x%x", revision); 1012 1013 /* 1014 * EHCI driver supports EHCI host controllers compliant to 1015 * 0.95 and higher revisions of EHCI specifications. 1016 */ 1017 if (revision < EHCI_REVISION_0_95) { 1018 1019 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1020 "Revision 0x%x is not supported", revision); 1021 1022 return (DDI_FAILURE); 1023 } 1024 1025 if (ehcip->ehci_hc_soft_state == EHCI_CTLR_INIT_STATE) { 1026 1027 /* Initialize the Frame list base address area */ 1028 if (ehci_init_periodic_frame_lst_table(ehcip) != DDI_SUCCESS) { 1029 1030 return (DDI_FAILURE); 1031 } 1032 1033 /* 1034 * For performance reasons, do not insert anything into the 1035 * asynchronous list or activate the asynch list schedule until 1036 * there is a valid QH. 1037 */ 1038 ehcip->ehci_head_of_async_sched_list = NULL; 1039 1040 if ((ehcip->ehci_vendor_id == PCI_VENDOR_VIA) && 1041 (ehci_vt62x2_workaround & EHCI_VIA_ASYNC_SCHEDULE)) { 1042 /* 1043 * The driver is unable to reliably stop the asynch 1044 * list schedule on VIA VT6202 controllers, so we 1045 * always keep a dummy QH on the list. 1046 */ 1047 ehci_qh_t *dummy_async_qh = 1048 ehci_alloc_qh(ehcip, NULL, NULL); 1049 1050 Set_QH(dummy_async_qh->qh_link_ptr, 1051 ((ehci_qh_cpu_to_iommu(ehcip, dummy_async_qh) & 1052 EHCI_QH_LINK_PTR) | EHCI_QH_LINK_REF_QH)); 1053 1054 /* Set this QH to be the "head" of the circular list */ 1055 Set_QH(dummy_async_qh->qh_ctrl, 1056 Get_QH(dummy_async_qh->qh_ctrl) | 1057 EHCI_QH_CTRL_RECLAIM_HEAD); 1058 1059 Set_QH(dummy_async_qh->qh_next_qtd, 1060 EHCI_QH_NEXT_QTD_PTR_VALID); 1061 Set_QH(dummy_async_qh->qh_alt_next_qtd, 1062 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1063 1064 ehcip->ehci_head_of_async_sched_list = dummy_async_qh; 1065 ehcip->ehci_open_async_count++; 1066 } 1067 } 1068 1069 return (DDI_SUCCESS); 1070 } 1071 1072 1073 /* 1074 * ehci_init_workaround 1075 * 1076 * some workarounds during initializing ehci 1077 */ 1078 int 1079 ehci_init_workaround(ehci_state_t *ehcip) 1080 { 1081 /* 1082 * Acer Labs Inc. M5273 EHCI controller does not send 1083 * interrupts unless the Root hub ports are routed to the EHCI 1084 * host controller; so route the ports now, before we test for 1085 * the presence of SOFs interrupts. 1086 */ 1087 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1088 /* Route all Root hub ports to EHCI host controller */ 1089 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1090 } 1091 1092 /* 1093 * VIA chips have some issues and may not work reliably. 1094 * Revisions >= 0x80 are part of a southbridge and appear 1095 * to be reliable with the workaround. 1096 * For revisions < 0x80, if we were bound using class 1097 * complain, else proceed. This will allow the user to 1098 * bind ehci specifically to this chip and not have the 1099 * warnings 1100 */ 1101 if (ehcip->ehci_vendor_id == PCI_VENDOR_VIA) { 1102 1103 if (ehcip->ehci_rev_id >= PCI_VIA_REVISION_6212) { 1104 1105 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1106 "ehci_init_workaround: Applying VIA workarounds " 1107 "for the 6212 chip."); 1108 1109 } else if (strcmp(DEVI(ehcip->ehci_dip)->devi_binding_name, 1110 "pciclass,0c0320") == 0) { 1111 1112 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1113 "Due to recently discovered incompatibilities"); 1114 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1115 "with this USB controller, USB2.x transfer"); 1116 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1117 "support has been disabled. This device will"); 1118 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1119 "continue to function as a USB1.x controller."); 1120 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1121 "If you are interested in enabling USB2.x"); 1122 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1123 "support please, refer to the ehci(7D) man page."); 1124 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1125 "Please also refer to www.sun.com/io for"); 1126 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1127 "Solaris Ready products and to"); 1128 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1129 "www.sun.com/bigadmin/hcl for additional"); 1130 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1131 "compatible USB products."); 1132 1133 return (DDI_FAILURE); 1134 1135 } else if (ehci_vt62x2_workaround) { 1136 1137 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1138 "Applying VIA workarounds"); 1139 } 1140 } 1141 1142 return (DDI_SUCCESS); 1143 } 1144 1145 1146 /* 1147 * ehci_init_check_status 1148 * 1149 * Check if EHCI host controller is running 1150 */ 1151 int 1152 ehci_init_check_status(ehci_state_t *ehcip) 1153 { 1154 clock_t sof_time_wait; 1155 1156 /* 1157 * Get the number of clock ticks to wait. 1158 * This is based on the maximum time it takes for a frame list rollover 1159 * and maximum time wait for SOFs to begin. 1160 */ 1161 sof_time_wait = drv_usectohz((EHCI_NUM_PERIODIC_FRAME_LISTS * 1000) + 1162 EHCI_SOF_TIMEWAIT); 1163 1164 /* Tell the ISR to broadcast ehci_async_schedule_advance_cv */ 1165 ehcip->ehci_flags |= EHCI_CV_INTR; 1166 1167 /* We need to add a delay to allow the chip time to start running */ 1168 (void) cv_timedwait(&ehcip->ehci_async_schedule_advance_cv, 1169 &ehcip->ehci_int_mutex, ddi_get_lbolt() + sof_time_wait); 1170 1171 /* 1172 * Check EHCI host controller is running, otherwise return failure. 1173 */ 1174 if ((ehcip->ehci_flags & EHCI_CV_INTR) || 1175 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 1176 1177 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1178 "No SOF interrupts have been received, this USB EHCI host" 1179 "controller is unusable"); 1180 1181 /* 1182 * Route all Root hub ports to Classic host 1183 * controller, in case this is an unusable ALI M5273 1184 * EHCI controller. 1185 */ 1186 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1187 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1188 } 1189 1190 return (DDI_FAILURE); 1191 } 1192 1193 return (DDI_SUCCESS); 1194 } 1195 1196 1197 /* 1198 * ehci_init_ctlr: 1199 * 1200 * Initialize the Host Controller (HC). 1201 */ 1202 int 1203 ehci_init_ctlr(ehci_state_t *ehcip, 1204 int init_type) 1205 { 1206 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_init_ctlr:"); 1207 1208 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1209 1210 if (ehci_init_hardware(ehcip) != DDI_SUCCESS) { 1211 1212 return (DDI_FAILURE); 1213 } 1214 } 1215 1216 /* 1217 * Check for Asynchronous schedule park capability feature. If this 1218 * feature is supported, then, program ehci command register with 1219 * appropriate values.. 1220 */ 1221 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_ASYNC_SCHED_PARK_CAP) { 1222 1223 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1224 "ehci_init_ctlr: Async park mode is supported"); 1225 1226 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1227 (EHCI_CMD_ASYNC_PARK_ENABLE | 1228 EHCI_CMD_ASYNC_PARK_COUNT_3))); 1229 } 1230 1231 /* 1232 * Check for programmable periodic frame list feature. If this 1233 * feature is supported, then, program ehci command register with 1234 * 1024 frame list value. 1235 */ 1236 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_PROG_FRAME_LIST_FLAG) { 1237 1238 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1239 "ehci_init_ctlr: Variable programmable periodic " 1240 "frame list is supported"); 1241 1242 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1243 EHCI_CMD_FRAME_1024_SIZE)); 1244 } 1245 1246 /* 1247 * Currently EHCI driver doesn't support 64 bit addressing. 1248 * 1249 * If we are using 64 bit addressing capability, then, program 1250 * ehci_ctrl_segment register with 4 Gigabyte segment where all 1251 * of the interface data structures are allocated. 1252 */ 1253 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_64BIT_ADDR_CAP) { 1254 1255 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1256 "ehci_init_ctlr: EHCI driver doesn't support " 1257 "64 bit addressing"); 1258 } 1259 1260 /* 64 bit addressing is not support */ 1261 Set_OpReg(ehci_ctrl_segment, 0x00000000); 1262 1263 /* Turn on/off the schedulers */ 1264 ehci_toggle_scheduler(ehcip); 1265 1266 /* 1267 * Set the Periodic Frame List Base Address register with the 1268 * starting physical address of the Periodic Frame List. 1269 */ 1270 Set_OpReg(ehci_periodic_list_base, 1271 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 1272 EHCI_PERIODIC_LIST_BASE)); 1273 1274 /* 1275 * Set ehci_interrupt to enable all interrupts except Root 1276 * Hub Status change interrupt. 1277 */ 1278 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 1279 EHCI_INTR_FRAME_LIST_ROLLOVER | EHCI_INTR_USB_ERROR | 1280 EHCI_INTR_USB); 1281 1282 /* 1283 * Set the desired interrupt threshold and turn on EHCI host controller. 1284 */ 1285 Set_OpReg(ehci_command, 1286 ((Get_OpReg(ehci_command) & ~EHCI_CMD_INTR_THRESHOLD) | 1287 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 1288 1289 ASSERT(Get_OpReg(ehci_command) & EHCI_CMD_HOST_CTRL_RUN); 1290 1291 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1292 1293 if (ehci_init_workaround(ehcip) != DDI_SUCCESS) { 1294 1295 return (DDI_FAILURE); 1296 } 1297 1298 if (ehci_init_check_status(ehcip) != DDI_SUCCESS) { 1299 1300 return (DDI_FAILURE); 1301 } 1302 1303 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1304 "ehci_init_ctlr: SOF's have started"); 1305 } 1306 1307 /* Route all Root hub ports to EHCI host controller */ 1308 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1309 1310 /* Set host controller soft state to operational */ 1311 ehcip->ehci_hc_soft_state = EHCI_CTLR_OPERATIONAL_STATE; 1312 1313 return (DDI_SUCCESS); 1314 } 1315 1316 /* 1317 * ehci_take_control: 1318 * 1319 * Handshake to take EHCI control from BIOS if necessary. Its only valid for 1320 * x86 machines, because sparc doesn't have a BIOS. 1321 * On x86 machine, the take control process includes 1322 * o get the base address of the extended capability list 1323 * o find out the capability for handoff synchronization in the list. 1324 * o check if BIOS has owned the host controller. 1325 * o set the OS Owned semaphore bit, ask the BIOS to release the ownership. 1326 * o wait for a constant time and check if BIOS has relinquished control. 1327 */ 1328 /* ARGSUSED */ 1329 static int 1330 ehci_take_control(ehci_state_t *ehcip) 1331 { 1332 #if defined(__x86) 1333 uint32_t extended_cap; 1334 uint32_t extended_cap_offset; 1335 uint32_t extended_cap_id; 1336 uint_t retry; 1337 1338 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1339 "ehci_take_control:"); 1340 1341 /* 1342 * According EHCI Spec 2.2.4, get EECP base address from HCCPARAMS 1343 * register. 1344 */ 1345 extended_cap_offset = (Get_Cap(ehci_hcc_params) & EHCI_HCC_EECP) >> 1346 EHCI_HCC_EECP_SHIFT; 1347 1348 /* 1349 * According EHCI Spec 2.2.4, if the extended capability offset is 1350 * less than 40h then its not valid. This means we don't need to 1351 * worry about BIOS handoff. 1352 */ 1353 if (extended_cap_offset < EHCI_HCC_EECP_MIN_OFFSET) { 1354 1355 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1356 "ehci_take_control: Hardware doesn't support legacy."); 1357 1358 goto success; 1359 } 1360 1361 /* 1362 * According EHCI Spec 2.1.7, A zero offset indicates the 1363 * end of the extended capability list. 1364 */ 1365 while (extended_cap_offset) { 1366 1367 /* Get the extended capability value. */ 1368 extended_cap = pci_config_get32(ehcip->ehci_config_handle, 1369 extended_cap_offset); 1370 1371 /* Get the capability ID */ 1372 extended_cap_id = (extended_cap & EHCI_EX_CAP_ID) >> 1373 EHCI_EX_CAP_ID_SHIFT; 1374 1375 /* Check if the card support legacy */ 1376 if (extended_cap_id == EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1377 break; 1378 } 1379 1380 /* Get the offset of the next capability */ 1381 extended_cap_offset = (extended_cap & EHCI_EX_CAP_NEXT_PTR) >> 1382 EHCI_EX_CAP_NEXT_PTR_SHIFT; 1383 } 1384 1385 /* 1386 * Unable to find legacy support in hardware's extended capability list. 1387 * This means we don't need to worry about BIOS handoff. 1388 */ 1389 if (extended_cap_id != EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1390 1391 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1392 "ehci_take_control: Hardware doesn't support legacy"); 1393 1394 goto success; 1395 } 1396 1397 /* Check if BIOS has owned it. */ 1398 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1399 1400 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1401 "ehci_take_control: BIOS does not own EHCI"); 1402 1403 goto success; 1404 } 1405 1406 /* 1407 * According EHCI Spec 5.1, The OS driver initiates an ownership 1408 * request by setting the OS Owned semaphore to a one. The OS 1409 * waits for the BIOS Owned bit to go to a zero before attempting 1410 * to use the EHCI controller. The time that OS must wait for BIOS 1411 * to respond to the request for ownership is beyond the scope of 1412 * this specification. 1413 * It waits up to EHCI_TAKEOVER_WAIT_COUNT*EHCI_TAKEOVER_DELAY ms 1414 * for BIOS to release the ownership. 1415 */ 1416 extended_cap |= EHCI_LEGSUP_OS_OWNED_SEM; 1417 pci_config_put32(ehcip->ehci_config_handle, extended_cap_offset, 1418 extended_cap); 1419 1420 for (retry = 0; retry < EHCI_TAKEOVER_WAIT_COUNT; retry++) { 1421 1422 /* wait a special interval */ 1423 #ifndef __lock_lint 1424 delay(drv_usectohz(EHCI_TAKEOVER_DELAY)); 1425 #endif 1426 /* Check to see if the BIOS has released the ownership */ 1427 extended_cap = pci_config_get32( 1428 ehcip->ehci_config_handle, extended_cap_offset); 1429 1430 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1431 1432 USB_DPRINTF_L3(PRINT_MASK_ATTA, 1433 ehcip->ehci_log_hdl, 1434 "ehci_take_control: BIOS has released " 1435 "the ownership. retry = %d", retry); 1436 1437 goto success; 1438 } 1439 1440 } 1441 1442 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1443 "ehci_take_control: take control from BIOS failed."); 1444 1445 return (USB_FAILURE); 1446 1447 success: 1448 1449 #endif /* __x86 */ 1450 return (USB_SUCCESS); 1451 } 1452 1453 1454 /* 1455 * ehci_init_periodic_frame_list_table : 1456 * 1457 * Allocate the system memory and initialize Host Controller 1458 * Periodic Frame List table area. The starting of the Periodic 1459 * Frame List Table area must be 4096 byte aligned. 1460 */ 1461 static int 1462 ehci_init_periodic_frame_lst_table(ehci_state_t *ehcip) 1463 { 1464 ddi_device_acc_attr_t dev_attr; 1465 size_t real_length; 1466 uint_t ccount; 1467 int result; 1468 1469 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1470 1471 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1472 "ehci_init_periodic_frame_lst_table:"); 1473 1474 /* The host controller will be little endian */ 1475 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1476 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1477 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1478 1479 /* Force the required 4K restrictive alignment */ 1480 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_PFL_ALIGNMENT; 1481 1482 /* Create space for the Periodic Frame List */ 1483 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 1484 DDI_DMA_SLEEP, 0, &ehcip->ehci_pflt_dma_handle) != DDI_SUCCESS) { 1485 1486 goto failure; 1487 } 1488 1489 if (ddi_dma_mem_alloc(ehcip->ehci_pflt_dma_handle, 1490 sizeof (ehci_periodic_frame_list_t), 1491 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 1492 0, (caddr_t *)&ehcip->ehci_periodic_frame_list_tablep, 1493 &real_length, &ehcip->ehci_pflt_mem_handle)) { 1494 1495 goto failure; 1496 } 1497 1498 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1499 "ehci_init_periodic_frame_lst_table: " 1500 "Real length %lu", real_length); 1501 1502 /* Map the whole Periodic Frame List into the I/O address space */ 1503 result = ddi_dma_addr_bind_handle(ehcip->ehci_pflt_dma_handle, 1504 NULL, (caddr_t)ehcip->ehci_periodic_frame_list_tablep, 1505 real_length, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1506 DDI_DMA_SLEEP, NULL, &ehcip->ehci_pflt_cookie, &ccount); 1507 1508 if (result == DDI_DMA_MAPPED) { 1509 /* The cookie count should be 1 */ 1510 if (ccount != 1) { 1511 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1512 "ehci_init_periodic_frame_lst_table: " 1513 "More than 1 cookie"); 1514 1515 goto failure; 1516 } 1517 } else { 1518 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 1519 1520 goto failure; 1521 } 1522 1523 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1524 "ehci_init_periodic_frame_lst_table: virtual 0x%p physical 0x%x", 1525 (void *)ehcip->ehci_periodic_frame_list_tablep, 1526 ehcip->ehci_pflt_cookie.dmac_address); 1527 1528 /* 1529 * DMA addresses for Periodic Frame List are bound. 1530 */ 1531 ehcip->ehci_dma_addr_bind_flag |= EHCI_PFLT_DMA_BOUND; 1532 1533 bzero((void *)ehcip->ehci_periodic_frame_list_tablep, real_length); 1534 1535 /* Initialize the Periodic Frame List */ 1536 ehci_build_interrupt_lattice(ehcip); 1537 1538 /* Reset Byte Alignment to Default */ 1539 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1540 1541 return (DDI_SUCCESS); 1542 failure: 1543 /* Byte alignment */ 1544 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1545 1546 return (DDI_FAILURE); 1547 } 1548 1549 1550 /* 1551 * ehci_build_interrupt_lattice: 1552 * 1553 * Construct the interrupt lattice tree using static Endpoint Descriptors 1554 * (QH). This interrupt lattice tree will have total of 32 interrupt QH 1555 * lists and the Host Controller (HC) processes one interrupt QH list in 1556 * every frame. The Host Controller traverses the periodic schedule by 1557 * constructing an array offset reference from the Periodic List Base Address 1558 * register and bits 12 to 3 of Frame Index register. It fetches the element 1559 * and begins traversing the graph of linked schedule data structures. 1560 */ 1561 static void 1562 ehci_build_interrupt_lattice(ehci_state_t *ehcip) 1563 { 1564 ehci_qh_t *list_array = ehcip->ehci_qh_pool_addr; 1565 ushort_t ehci_index[EHCI_NUM_PERIODIC_FRAME_LISTS]; 1566 ehci_periodic_frame_list_t *periodic_frame_list = 1567 ehcip->ehci_periodic_frame_list_tablep; 1568 ushort_t *temp, num_of_nodes; 1569 uintptr_t addr; 1570 int i, j, k; 1571 1572 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1573 "ehci_build_interrupt_lattice:"); 1574 1575 /* 1576 * Reserve the first 63 Endpoint Descriptor (QH) structures 1577 * in the pool as static endpoints & these are required for 1578 * constructing interrupt lattice tree. 1579 */ 1580 for (i = 0; i < EHCI_NUM_STATIC_NODES; i++) { 1581 Set_QH(list_array[i].qh_state, EHCI_QH_STATIC); 1582 Set_QH(list_array[i].qh_status, EHCI_QH_STS_HALTED); 1583 Set_QH(list_array[i].qh_next_qtd, EHCI_QH_NEXT_QTD_PTR_VALID); 1584 Set_QH(list_array[i].qh_alt_next_qtd, 1585 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1586 } 1587 1588 /* 1589 * Make sure that last Endpoint on the periodic frame list terminates 1590 * periodic schedule. 1591 */ 1592 Set_QH(list_array[0].qh_link_ptr, EHCI_QH_LINK_PTR_VALID); 1593 1594 /* Build the interrupt lattice tree */ 1595 for (i = 0; i < (EHCI_NUM_STATIC_NODES / 2); i++) { 1596 /* 1597 * The next pointer in the host controller endpoint 1598 * descriptor must contain an iommu address. Calculate 1599 * the offset into the cpu address and add this to the 1600 * starting iommu address. 1601 */ 1602 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *)&list_array[i]); 1603 1604 Set_QH(list_array[2*i + 1].qh_link_ptr, 1605 addr | EHCI_QH_LINK_REF_QH); 1606 Set_QH(list_array[2*i + 2].qh_link_ptr, 1607 addr | EHCI_QH_LINK_REF_QH); 1608 } 1609 1610 /* Build the tree bottom */ 1611 temp = (unsigned short *) 1612 kmem_zalloc(EHCI_NUM_PERIODIC_FRAME_LISTS * 2, KM_SLEEP); 1613 1614 num_of_nodes = 1; 1615 1616 /* 1617 * Initialize the values which are used for setting up head pointers 1618 * for the 32ms scheduling lists which starts from the Periodic Frame 1619 * List. 1620 */ 1621 for (i = 0; i < ehci_log_2(EHCI_NUM_PERIODIC_FRAME_LISTS); i++) { 1622 for (j = 0, k = 0; k < num_of_nodes; k++, j++) { 1623 ehci_index[j++] = temp[k]; 1624 ehci_index[j] = temp[k] + ehci_pow_2(i); 1625 } 1626 1627 num_of_nodes *= 2; 1628 for (k = 0; k < num_of_nodes; k++) 1629 temp[k] = ehci_index[k]; 1630 } 1631 1632 kmem_free((void *)temp, (EHCI_NUM_PERIODIC_FRAME_LISTS * 2)); 1633 1634 /* 1635 * Initialize the interrupt list in the Periodic Frame List Table 1636 * so that it points to the bottom of the tree. 1637 */ 1638 for (i = 0, j = 0; i < ehci_pow_2(TREE_HEIGHT); i++) { 1639 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *) 1640 (&list_array[((EHCI_NUM_STATIC_NODES + 1) / 2) + i - 1])); 1641 1642 ASSERT(addr); 1643 1644 for (k = 0; k < ehci_pow_2(TREE_HEIGHT); k++) { 1645 Set_PFLT(periodic_frame_list-> 1646 ehci_periodic_frame_list_table[ehci_index[j++]], 1647 (uint32_t)(addr | EHCI_QH_LINK_REF_QH)); 1648 } 1649 } 1650 } 1651 1652 1653 /* 1654 * ehci_alloc_hcdi_ops: 1655 * 1656 * The HCDI interfaces or entry points are the software interfaces used by 1657 * the Universal Serial Bus Driver (USBA) to access the services of the 1658 * Host Controller Driver (HCD). During HCD initialization, inform USBA 1659 * about all available HCDI interfaces or entry points. 1660 */ 1661 usba_hcdi_ops_t * 1662 ehci_alloc_hcdi_ops(ehci_state_t *ehcip) 1663 { 1664 usba_hcdi_ops_t *usba_hcdi_ops; 1665 1666 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1667 "ehci_alloc_hcdi_ops:"); 1668 1669 usba_hcdi_ops = usba_alloc_hcdi_ops(); 1670 1671 usba_hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION; 1672 1673 usba_hcdi_ops->usba_hcdi_pm_support = ehci_hcdi_pm_support; 1674 usba_hcdi_ops->usba_hcdi_pipe_open = ehci_hcdi_pipe_open; 1675 usba_hcdi_ops->usba_hcdi_pipe_close = ehci_hcdi_pipe_close; 1676 1677 usba_hcdi_ops->usba_hcdi_pipe_reset = ehci_hcdi_pipe_reset; 1678 1679 usba_hcdi_ops->usba_hcdi_pipe_ctrl_xfer = ehci_hcdi_pipe_ctrl_xfer; 1680 usba_hcdi_ops->usba_hcdi_pipe_bulk_xfer = ehci_hcdi_pipe_bulk_xfer; 1681 usba_hcdi_ops->usba_hcdi_pipe_intr_xfer = ehci_hcdi_pipe_intr_xfer; 1682 usba_hcdi_ops->usba_hcdi_pipe_isoc_xfer = ehci_hcdi_pipe_isoc_xfer; 1683 1684 usba_hcdi_ops->usba_hcdi_bulk_transfer_size = 1685 ehci_hcdi_bulk_transfer_size; 1686 1687 usba_hcdi_ops->usba_hcdi_pipe_stop_intr_polling = 1688 ehci_hcdi_pipe_stop_intr_polling; 1689 usba_hcdi_ops->usba_hcdi_pipe_stop_isoc_polling = 1690 ehci_hcdi_pipe_stop_isoc_polling; 1691 1692 usba_hcdi_ops->usba_hcdi_get_current_frame_number = 1693 ehci_hcdi_get_current_frame_number; 1694 usba_hcdi_ops->usba_hcdi_get_max_isoc_pkts = 1695 ehci_hcdi_get_max_isoc_pkts; 1696 1697 usba_hcdi_ops->usba_hcdi_console_input_init = 1698 ehci_hcdi_polled_input_init; 1699 usba_hcdi_ops->usba_hcdi_console_input_enter = 1700 ehci_hcdi_polled_input_enter; 1701 usba_hcdi_ops->usba_hcdi_console_read = 1702 ehci_hcdi_polled_read; 1703 usba_hcdi_ops->usba_hcdi_console_input_exit = 1704 ehci_hcdi_polled_input_exit; 1705 usba_hcdi_ops->usba_hcdi_console_input_fini = 1706 ehci_hcdi_polled_input_fini; 1707 return (usba_hcdi_ops); 1708 } 1709 1710 1711 /* 1712 * Host Controller Driver (HCD) deinitialization functions 1713 */ 1714 1715 /* 1716 * ehci_cleanup: 1717 * 1718 * Cleanup on attach failure or detach 1719 */ 1720 int 1721 ehci_cleanup(ehci_state_t *ehcip) 1722 { 1723 ehci_trans_wrapper_t *tw; 1724 ehci_pipe_private_t *pp; 1725 ehci_qtd_t *qtd; 1726 int i, ctrl, rval; 1727 int flags = ehcip->ehci_flags; 1728 1729 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_cleanup:"); 1730 1731 if (flags & EHCI_RHREG) { 1732 /* Unload the root hub driver */ 1733 if (ehci_unload_root_hub_driver(ehcip) != USB_SUCCESS) { 1734 1735 return (DDI_FAILURE); 1736 } 1737 } 1738 1739 if (flags & EHCI_USBAREG) { 1740 /* Unregister this HCD instance with USBA */ 1741 usba_hcdi_unregister(ehcip->ehci_dip); 1742 } 1743 1744 if (flags & EHCI_INTR) { 1745 1746 mutex_enter(&ehcip->ehci_int_mutex); 1747 1748 /* Disable all EHCI QH list processing */ 1749 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1750 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | 1751 EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1752 1753 /* Disable all EHCI interrupts */ 1754 Set_OpReg(ehci_interrupt, 0); 1755 1756 /* wait for the next SOF */ 1757 (void) ehci_wait_for_sof(ehcip); 1758 1759 /* Route all Root hub ports to Classic host controller */ 1760 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1761 1762 /* Stop the EHCI host controller */ 1763 Set_OpReg(ehci_command, 1764 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1765 1766 /* Wait for sometime */ 1767 drv_usecwait(EHCI_TIMEWAIT); 1768 1769 mutex_exit(&ehcip->ehci_int_mutex); 1770 1771 ehci_rem_intrs(ehcip); 1772 } 1773 1774 /* Unmap the EHCI registers */ 1775 if (ehcip->ehci_caps_handle) { 1776 ddi_regs_map_free(&ehcip->ehci_caps_handle); 1777 } 1778 1779 if (ehcip->ehci_config_handle) { 1780 pci_config_teardown(&ehcip->ehci_config_handle); 1781 } 1782 1783 /* Free all the buffers */ 1784 if (ehcip->ehci_qtd_pool_addr && ehcip->ehci_qtd_pool_mem_handle) { 1785 for (i = 0; i < ehci_qtd_pool_size; i ++) { 1786 qtd = &ehcip->ehci_qtd_pool_addr[i]; 1787 ctrl = Get_QTD(ehcip-> 1788 ehci_qtd_pool_addr[i].qtd_state); 1789 1790 if ((ctrl != EHCI_QTD_FREE) && 1791 (ctrl != EHCI_QTD_DUMMY) && 1792 (qtd->qtd_trans_wrapper)) { 1793 1794 mutex_enter(&ehcip->ehci_int_mutex); 1795 1796 tw = (ehci_trans_wrapper_t *) 1797 EHCI_LOOKUP_ID((uint32_t) 1798 Get_QTD(qtd->qtd_trans_wrapper)); 1799 1800 /* Obtain the pipe private structure */ 1801 pp = tw->tw_pipe_private; 1802 1803 /* Stop the the transfer timer */ 1804 ehci_stop_xfer_timer(ehcip, tw, 1805 EHCI_REMOVE_XFER_ALWAYS); 1806 1807 ehci_deallocate_tw(ehcip, pp, tw); 1808 1809 mutex_exit(&ehcip->ehci_int_mutex); 1810 } 1811 } 1812 1813 /* 1814 * If EHCI_QTD_POOL_BOUND flag is set, then unbind 1815 * the handle for QTD pools. 1816 */ 1817 if ((ehcip->ehci_dma_addr_bind_flag & 1818 EHCI_QTD_POOL_BOUND) == EHCI_QTD_POOL_BOUND) { 1819 1820 rval = ddi_dma_unbind_handle( 1821 ehcip->ehci_qtd_pool_dma_handle); 1822 1823 ASSERT(rval == DDI_SUCCESS); 1824 } 1825 ddi_dma_mem_free(&ehcip->ehci_qtd_pool_mem_handle); 1826 } 1827 1828 /* Free the QTD pool */ 1829 if (ehcip->ehci_qtd_pool_dma_handle) { 1830 ddi_dma_free_handle(&ehcip->ehci_qtd_pool_dma_handle); 1831 } 1832 1833 if (ehcip->ehci_qh_pool_addr && ehcip->ehci_qh_pool_mem_handle) { 1834 /* 1835 * If EHCI_QH_POOL_BOUND flag is set, then unbind 1836 * the handle for QH pools. 1837 */ 1838 if ((ehcip->ehci_dma_addr_bind_flag & 1839 EHCI_QH_POOL_BOUND) == EHCI_QH_POOL_BOUND) { 1840 1841 rval = ddi_dma_unbind_handle( 1842 ehcip->ehci_qh_pool_dma_handle); 1843 1844 ASSERT(rval == DDI_SUCCESS); 1845 } 1846 1847 ddi_dma_mem_free(&ehcip->ehci_qh_pool_mem_handle); 1848 } 1849 1850 /* Free the QH pool */ 1851 if (ehcip->ehci_qh_pool_dma_handle) { 1852 ddi_dma_free_handle(&ehcip->ehci_qh_pool_dma_handle); 1853 } 1854 1855 /* Free the Periodic frame list table (PFLT) area */ 1856 if (ehcip->ehci_periodic_frame_list_tablep && 1857 ehcip->ehci_pflt_mem_handle) { 1858 /* 1859 * If EHCI_PFLT_DMA_BOUND flag is set, then unbind 1860 * the handle for PFLT. 1861 */ 1862 if ((ehcip->ehci_dma_addr_bind_flag & 1863 EHCI_PFLT_DMA_BOUND) == EHCI_PFLT_DMA_BOUND) { 1864 1865 rval = ddi_dma_unbind_handle( 1866 ehcip->ehci_pflt_dma_handle); 1867 1868 ASSERT(rval == DDI_SUCCESS); 1869 } 1870 1871 ddi_dma_mem_free(&ehcip->ehci_pflt_mem_handle); 1872 } 1873 1874 (void) ehci_isoc_cleanup(ehcip); 1875 1876 if (ehcip->ehci_pflt_dma_handle) { 1877 ddi_dma_free_handle(&ehcip->ehci_pflt_dma_handle); 1878 } 1879 1880 if (flags & EHCI_INTR) { 1881 /* Destroy the mutex */ 1882 mutex_destroy(&ehcip->ehci_int_mutex); 1883 1884 /* Destroy the async schedule advance condition variable */ 1885 cv_destroy(&ehcip->ehci_async_schedule_advance_cv); 1886 } 1887 1888 /* clean up kstat structs */ 1889 ehci_destroy_stats(ehcip); 1890 1891 /* Free ehci hcdi ops */ 1892 if (ehcip->ehci_hcdi_ops) { 1893 usba_free_hcdi_ops(ehcip->ehci_hcdi_ops); 1894 } 1895 1896 if (flags & EHCI_ZALLOC) { 1897 1898 usb_free_log_hdl(ehcip->ehci_log_hdl); 1899 1900 /* Remove all properties that might have been created */ 1901 ddi_prop_remove_all(ehcip->ehci_dip); 1902 1903 /* Free the soft state */ 1904 ddi_soft_state_free(ehci_statep, 1905 ddi_get_instance(ehcip->ehci_dip)); 1906 } 1907 1908 return (DDI_SUCCESS); 1909 } 1910 1911 1912 /* 1913 * ehci_rem_intrs: 1914 * 1915 * Unregister FIXED or MSI interrupts 1916 */ 1917 static void 1918 ehci_rem_intrs(ehci_state_t *ehcip) 1919 { 1920 int i; 1921 1922 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1923 "ehci_rem_intrs: interrupt type 0x%x", ehcip->ehci_intr_type); 1924 1925 /* Disable all interrupts */ 1926 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 1927 (void) ddi_intr_block_disable(ehcip->ehci_htable, 1928 ehcip->ehci_intr_cnt); 1929 } else { 1930 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1931 (void) ddi_intr_disable(ehcip->ehci_htable[i]); 1932 } 1933 } 1934 1935 /* Call ddi_intr_remove_handler() */ 1936 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1937 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 1938 (void) ddi_intr_free(ehcip->ehci_htable[i]); 1939 } 1940 1941 kmem_free(ehcip->ehci_htable, 1942 ehcip->ehci_intr_cnt * sizeof (ddi_intr_handle_t)); 1943 } 1944 1945 1946 /* 1947 * ehci_cpr_suspend 1948 */ 1949 int 1950 ehci_cpr_suspend(ehci_state_t *ehcip) 1951 { 1952 int i; 1953 1954 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1955 "ehci_cpr_suspend:"); 1956 1957 /* Call into the root hub and suspend it */ 1958 if (usba_hubdi_detach(ehcip->ehci_dip, DDI_SUSPEND) != DDI_SUCCESS) { 1959 1960 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1961 "ehci_cpr_suspend: root hub fails to suspend"); 1962 1963 return (DDI_FAILURE); 1964 } 1965 1966 /* Only root hub's intr pipe should be open at this time */ 1967 mutex_enter(&ehcip->ehci_int_mutex); 1968 1969 ASSERT(ehcip->ehci_open_pipe_count == 0); 1970 1971 /* Just wait till all resources are reclaimed */ 1972 i = 0; 1973 while ((ehcip->ehci_reclaim_list != NULL) && (i++ < 3)) { 1974 ehci_handle_endpoint_reclaimation(ehcip); 1975 (void) ehci_wait_for_sof(ehcip); 1976 } 1977 ASSERT(ehcip->ehci_reclaim_list == NULL); 1978 1979 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1980 "ehci_cpr_suspend: Disable HC QH list processing"); 1981 1982 /* Disable all EHCI QH list processing */ 1983 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1984 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1985 1986 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1987 "ehci_cpr_suspend: Disable HC interrupts"); 1988 1989 /* Disable all EHCI interrupts */ 1990 Set_OpReg(ehci_interrupt, 0); 1991 1992 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1993 "ehci_cpr_suspend: Wait for the next SOF"); 1994 1995 /* Wait for the next SOF */ 1996 if (ehci_wait_for_sof(ehcip) != USB_SUCCESS) { 1997 1998 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1999 "ehci_cpr_suspend: ehci host controller suspend failed"); 2000 2001 mutex_exit(&ehcip->ehci_int_mutex); 2002 return (DDI_FAILURE); 2003 } 2004 2005 /* 2006 * Stop the ehci host controller 2007 * if usb keyboard is not connected. 2008 */ 2009 if (ehcip->ehci_polled_kbd_count == 0) { 2010 Set_OpReg(ehci_command, 2011 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 2012 } 2013 2014 /* Set host controller soft state to suspend */ 2015 ehcip->ehci_hc_soft_state = EHCI_CTLR_SUSPEND_STATE; 2016 2017 mutex_exit(&ehcip->ehci_int_mutex); 2018 2019 return (DDI_SUCCESS); 2020 } 2021 2022 2023 /* 2024 * ehci_cpr_resume 2025 */ 2026 int 2027 ehci_cpr_resume(ehci_state_t *ehcip) 2028 { 2029 mutex_enter(&ehcip->ehci_int_mutex); 2030 2031 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2032 "ehci_cpr_resume: Restart the controller"); 2033 2034 /* Cleanup ehci specific information across cpr */ 2035 ehci_cpr_cleanup(ehcip); 2036 2037 /* Restart the controller */ 2038 if (ehci_init_ctlr(ehcip, EHCI_NORMAL_INITIALIZATION) != DDI_SUCCESS) { 2039 2040 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2041 "ehci_cpr_resume: ehci host controller resume failed "); 2042 2043 mutex_exit(&ehcip->ehci_int_mutex); 2044 2045 return (DDI_FAILURE); 2046 } 2047 2048 mutex_exit(&ehcip->ehci_int_mutex); 2049 2050 /* Now resume the root hub */ 2051 if (usba_hubdi_attach(ehcip->ehci_dip, DDI_RESUME) != DDI_SUCCESS) { 2052 2053 return (DDI_FAILURE); 2054 } 2055 2056 return (DDI_SUCCESS); 2057 } 2058 2059 2060 /* 2061 * Bandwidth Allocation functions 2062 */ 2063 2064 /* 2065 * ehci_allocate_bandwidth: 2066 * 2067 * Figure out whether or not this interval may be supported. Return the index 2068 * into the lattice if it can be supported. Return allocation failure if it 2069 * can not be supported. 2070 */ 2071 int 2072 ehci_allocate_bandwidth( 2073 ehci_state_t *ehcip, 2074 usba_pipe_handle_data_t *ph, 2075 uint_t *pnode, 2076 uchar_t *smask, 2077 uchar_t *cmask) 2078 { 2079 int error = USB_SUCCESS; 2080 2081 /* This routine is protected by the ehci_int_mutex */ 2082 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2083 2084 /* Reset the pnode to the last checked pnode */ 2085 *pnode = 0; 2086 2087 /* Allocate high speed bandwidth */ 2088 if ((error = ehci_allocate_high_speed_bandwidth(ehcip, 2089 ph, pnode, smask, cmask)) != USB_SUCCESS) { 2090 2091 return (error); 2092 } 2093 2094 /* 2095 * For low/full speed usb devices, allocate classic TT bandwidth 2096 * in additional to high speed bandwidth. 2097 */ 2098 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2099 2100 /* Allocate classic TT bandwidth */ 2101 if ((error = ehci_allocate_classic_tt_bandwidth( 2102 ehcip, ph, *pnode)) != USB_SUCCESS) { 2103 2104 /* Deallocate high speed bandwidth */ 2105 ehci_deallocate_high_speed_bandwidth( 2106 ehcip, ph, *pnode, *smask, *cmask); 2107 } 2108 } 2109 2110 return (error); 2111 } 2112 2113 2114 /* 2115 * ehci_allocate_high_speed_bandwidth: 2116 * 2117 * Allocate high speed bandwidth for the low/full/high speed interrupt and 2118 * isochronous endpoints. 2119 */ 2120 static int 2121 ehci_allocate_high_speed_bandwidth( 2122 ehci_state_t *ehcip, 2123 usba_pipe_handle_data_t *ph, 2124 uint_t *pnode, 2125 uchar_t *smask, 2126 uchar_t *cmask) 2127 { 2128 uint_t sbandwidth, cbandwidth; 2129 int interval; 2130 usb_ep_descr_t *endpoint = &ph->p_ep; 2131 usba_device_t *child_ud; 2132 usb_port_status_t port_status; 2133 int error; 2134 2135 /* This routine is protected by the ehci_int_mutex */ 2136 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2137 2138 /* Get child's usba device structure */ 2139 child_ud = ph->p_usba_device; 2140 2141 mutex_enter(&child_ud->usb_mutex); 2142 2143 /* Get the current usb device's port status */ 2144 port_status = ph->p_usba_device->usb_port_status; 2145 2146 mutex_exit(&child_ud->usb_mutex); 2147 2148 /* 2149 * Calculate the length in bytes of a transaction on this 2150 * periodic endpoint. Return failure if maximum packet is 2151 * zero. 2152 */ 2153 error = ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2154 port_status, &sbandwidth, &cbandwidth); 2155 if (error != USB_SUCCESS) { 2156 2157 return (error); 2158 } 2159 2160 /* 2161 * Adjust polling interval to be a power of 2. 2162 * If this interval can't be supported, return 2163 * allocation failure. 2164 */ 2165 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2166 if (interval == USB_FAILURE) { 2167 2168 return (USB_FAILURE); 2169 } 2170 2171 if (port_status == USBA_HIGH_SPEED_DEV) { 2172 /* Allocate bandwidth for high speed devices, except ITD */ 2173 error = ehci_find_bestfit_hs_mask(ehcip, smask, pnode, 2174 endpoint, sbandwidth, interval); 2175 *cmask = 0x00; 2176 2177 } else { 2178 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2179 USB_EP_ATTR_INTR) { 2180 2181 /* Allocate bandwidth for low speed interrupt */ 2182 error = ehci_find_bestfit_ls_intr_mask(ehcip, 2183 smask, cmask, pnode, sbandwidth, cbandwidth, 2184 interval); 2185 } else { 2186 if ((endpoint->bEndpointAddress & 2187 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2188 2189 /* Allocate bandwidth for sitd in */ 2190 error = ehci_find_bestfit_sitd_in_mask(ehcip, 2191 smask, cmask, pnode, sbandwidth, cbandwidth, 2192 interval); 2193 } else { 2194 2195 /* Allocate bandwidth for sitd out */ 2196 error = ehci_find_bestfit_sitd_out_mask(ehcip, 2197 smask, pnode, sbandwidth, interval); 2198 *cmask = 0x00; 2199 } 2200 } 2201 } 2202 2203 if (error != USB_SUCCESS) { 2204 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2205 "ehci_allocate_high_speed_bandwidth: Reached maximum " 2206 "bandwidth value and cannot allocate bandwidth for a " 2207 "given high-speed periodic endpoint"); 2208 2209 return (USB_NO_BANDWIDTH); 2210 } 2211 2212 return (error); 2213 } 2214 2215 2216 /* 2217 * ehci_allocate_classic_tt_speed_bandwidth: 2218 * 2219 * Allocate classic TT bandwidth for the low/full speed interrupt and 2220 * isochronous endpoints. 2221 */ 2222 static int 2223 ehci_allocate_classic_tt_bandwidth( 2224 ehci_state_t *ehcip, 2225 usba_pipe_handle_data_t *ph, 2226 uint_t pnode) 2227 { 2228 uint_t bandwidth, min; 2229 uint_t height, leftmost, list; 2230 usb_ep_descr_t *endpoint = &ph->p_ep; 2231 usba_device_t *child_ud, *parent_ud; 2232 usb_port_status_t port_status; 2233 int i, interval; 2234 2235 /* This routine is protected by the ehci_int_mutex */ 2236 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2237 2238 /* Get child's usba device structure */ 2239 child_ud = ph->p_usba_device; 2240 2241 mutex_enter(&child_ud->usb_mutex); 2242 2243 /* Get the current usb device's port status */ 2244 port_status = child_ud->usb_port_status; 2245 2246 /* Get the parent high speed hub's usba device structure */ 2247 parent_ud = child_ud->usb_hs_hub_usba_dev; 2248 2249 mutex_exit(&child_ud->usb_mutex); 2250 2251 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2252 "ehci_allocate_classic_tt_bandwidth: " 2253 "child_ud 0x%p parent_ud 0x%p", child_ud, parent_ud); 2254 2255 /* 2256 * Calculate the length in bytes of a transaction on this 2257 * periodic endpoint. Return failure if maximum packet is 2258 * zero. 2259 */ 2260 if (ehci_compute_classic_bandwidth(endpoint, 2261 port_status, &bandwidth) != USB_SUCCESS) { 2262 2263 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2264 "ehci_allocate_classic_tt_bandwidth: Periodic endpoint " 2265 "with zero endpoint maximum packet size is not supported"); 2266 2267 return (USB_NOT_SUPPORTED); 2268 } 2269 2270 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2271 "ehci_allocate_classic_tt_bandwidth: bandwidth %d", bandwidth); 2272 2273 mutex_enter(&parent_ud->usb_mutex); 2274 2275 /* 2276 * If the length in bytes plus the allocated bandwidth exceeds 2277 * the maximum, return bandwidth allocation failure. 2278 */ 2279 if ((parent_ud->usb_hs_hub_min_bandwidth + bandwidth) > 2280 FS_PERIODIC_BANDWIDTH) { 2281 2282 mutex_exit(&parent_ud->usb_mutex); 2283 2284 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2285 "ehci_allocate_classic_tt_bandwidth: Reached maximum " 2286 "bandwidth value and cannot allocate bandwidth for a " 2287 "given low/full speed periodic endpoint"); 2288 2289 return (USB_NO_BANDWIDTH); 2290 } 2291 2292 mutex_exit(&parent_ud->usb_mutex); 2293 2294 /* Adjust polling interval to be a power of 2 */ 2295 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2296 2297 /* Find the height in the tree */ 2298 height = ehci_lattice_height(interval); 2299 2300 /* Find the leftmost leaf in the subtree specified by the node. */ 2301 leftmost = ehci_leftmost_leaf(pnode, height); 2302 2303 mutex_enter(&parent_ud->usb_mutex); 2304 2305 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2306 list = ehci_index[leftmost + i]; 2307 2308 if ((parent_ud->usb_hs_hub_bandwidth[list] + 2309 bandwidth) > FS_PERIODIC_BANDWIDTH) { 2310 2311 mutex_exit(&parent_ud->usb_mutex); 2312 2313 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2314 "ehci_allocate_classic_tt_bandwidth: Reached " 2315 "maximum bandwidth value and cannot allocate " 2316 "bandwidth for low/full periodic endpoint"); 2317 2318 return (USB_NO_BANDWIDTH); 2319 } 2320 } 2321 2322 /* 2323 * All the leaves for this node must be updated with the bandwidth. 2324 */ 2325 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2326 list = ehci_index[leftmost + i]; 2327 parent_ud->usb_hs_hub_bandwidth[list] += bandwidth; 2328 } 2329 2330 /* Find the leaf with the smallest allocated bandwidth */ 2331 min = parent_ud->usb_hs_hub_bandwidth[0]; 2332 2333 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2334 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2335 min = parent_ud->usb_hs_hub_bandwidth[i]; 2336 } 2337 } 2338 2339 /* Save the minimum for later use */ 2340 parent_ud->usb_hs_hub_min_bandwidth = min; 2341 2342 mutex_exit(&parent_ud->usb_mutex); 2343 2344 return (USB_SUCCESS); 2345 } 2346 2347 2348 /* 2349 * ehci_deallocate_bandwidth: 2350 * 2351 * Deallocate bandwidth for the given node in the lattice and the length 2352 * of transfer. 2353 */ 2354 void 2355 ehci_deallocate_bandwidth( 2356 ehci_state_t *ehcip, 2357 usba_pipe_handle_data_t *ph, 2358 uint_t pnode, 2359 uchar_t smask, 2360 uchar_t cmask) 2361 { 2362 /* This routine is protected by the ehci_int_mutex */ 2363 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2364 2365 ehci_deallocate_high_speed_bandwidth(ehcip, ph, pnode, smask, cmask); 2366 2367 /* 2368 * For low/full speed usb devices, deallocate classic TT bandwidth 2369 * in additional to high speed bandwidth. 2370 */ 2371 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2372 2373 /* Deallocate classic TT bandwidth */ 2374 ehci_deallocate_classic_tt_bandwidth(ehcip, ph, pnode); 2375 } 2376 } 2377 2378 2379 /* 2380 * ehci_deallocate_high_speed_bandwidth: 2381 * 2382 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2383 */ 2384 static void 2385 ehci_deallocate_high_speed_bandwidth( 2386 ehci_state_t *ehcip, 2387 usba_pipe_handle_data_t *ph, 2388 uint_t pnode, 2389 uchar_t smask, 2390 uchar_t cmask) 2391 { 2392 uint_t height, leftmost; 2393 uint_t list_count; 2394 uint_t sbandwidth, cbandwidth; 2395 int interval; 2396 usb_ep_descr_t *endpoint = &ph->p_ep; 2397 usba_device_t *child_ud; 2398 usb_port_status_t port_status; 2399 2400 /* This routine is protected by the ehci_int_mutex */ 2401 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2402 2403 /* Get child's usba device structure */ 2404 child_ud = ph->p_usba_device; 2405 2406 mutex_enter(&child_ud->usb_mutex); 2407 2408 /* Get the current usb device's port status */ 2409 port_status = ph->p_usba_device->usb_port_status; 2410 2411 mutex_exit(&child_ud->usb_mutex); 2412 2413 (void) ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2414 port_status, &sbandwidth, &cbandwidth); 2415 2416 /* Adjust polling interval to be a power of 2 */ 2417 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2418 2419 /* Find the height in the tree */ 2420 height = ehci_lattice_height(interval); 2421 2422 /* 2423 * Find the leftmost leaf in the subtree specified by the node 2424 */ 2425 leftmost = ehci_leftmost_leaf(pnode, height); 2426 2427 list_count = EHCI_NUM_INTR_QH_LISTS/interval; 2428 2429 /* Delete the bandwidth from the appropriate lists */ 2430 if (port_status == USBA_HIGH_SPEED_DEV) { 2431 2432 ehci_update_bw_availability(ehcip, -sbandwidth, 2433 leftmost, list_count, smask); 2434 } else { 2435 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2436 USB_EP_ATTR_INTR) { 2437 2438 ehci_update_bw_availability(ehcip, -sbandwidth, 2439 leftmost, list_count, smask); 2440 ehci_update_bw_availability(ehcip, -cbandwidth, 2441 leftmost, list_count, cmask); 2442 } else { 2443 if ((endpoint->bEndpointAddress & 2444 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2445 2446 ehci_update_bw_availability(ehcip, -sbandwidth, 2447 leftmost, list_count, smask); 2448 ehci_update_bw_availability(ehcip, 2449 -MAX_UFRAME_SITD_XFER, leftmost, 2450 list_count, cmask); 2451 } else { 2452 2453 ehci_update_bw_availability(ehcip, 2454 -MAX_UFRAME_SITD_XFER, leftmost, 2455 list_count, smask); 2456 } 2457 } 2458 } 2459 } 2460 2461 /* 2462 * ehci_deallocate_classic_tt_bandwidth: 2463 * 2464 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2465 */ 2466 static void 2467 ehci_deallocate_classic_tt_bandwidth( 2468 ehci_state_t *ehcip, 2469 usba_pipe_handle_data_t *ph, 2470 uint_t pnode) 2471 { 2472 uint_t bandwidth, height, leftmost, list, min; 2473 int i, interval; 2474 usb_ep_descr_t *endpoint = &ph->p_ep; 2475 usba_device_t *child_ud, *parent_ud; 2476 usb_port_status_t port_status; 2477 2478 /* This routine is protected by the ehci_int_mutex */ 2479 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2480 2481 /* Get child's usba device structure */ 2482 child_ud = ph->p_usba_device; 2483 2484 mutex_enter(&child_ud->usb_mutex); 2485 2486 /* Get the current usb device's port status */ 2487 port_status = child_ud->usb_port_status; 2488 2489 /* Get the parent high speed hub's usba device structure */ 2490 parent_ud = child_ud->usb_hs_hub_usba_dev; 2491 2492 mutex_exit(&child_ud->usb_mutex); 2493 2494 /* Obtain the bandwidth */ 2495 (void) ehci_compute_classic_bandwidth(endpoint, 2496 port_status, &bandwidth); 2497 2498 /* Adjust polling interval to be a power of 2 */ 2499 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2500 2501 /* Find the height in the tree */ 2502 height = ehci_lattice_height(interval); 2503 2504 /* Find the leftmost leaf in the subtree specified by the node */ 2505 leftmost = ehci_leftmost_leaf(pnode, height); 2506 2507 mutex_enter(&parent_ud->usb_mutex); 2508 2509 /* Delete the bandwidth from the appropriate lists */ 2510 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2511 list = ehci_index[leftmost + i]; 2512 parent_ud->usb_hs_hub_bandwidth[list] -= bandwidth; 2513 } 2514 2515 /* Find the leaf with the smallest allocated bandwidth */ 2516 min = parent_ud->usb_hs_hub_bandwidth[0]; 2517 2518 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2519 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2520 min = parent_ud->usb_hs_hub_bandwidth[i]; 2521 } 2522 } 2523 2524 /* Save the minimum for later use */ 2525 parent_ud->usb_hs_hub_min_bandwidth = min; 2526 2527 mutex_exit(&parent_ud->usb_mutex); 2528 } 2529 2530 2531 /* 2532 * ehci_compute_high_speed_bandwidth: 2533 * 2534 * Given a periodic endpoint (interrupt or isochronous) determine the total 2535 * bandwidth for one transaction. The EHCI host controller traverses the 2536 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2537 * services an endpoint, only a single transaction attempt is made. The HC 2538 * moves to the next Endpoint Descriptor after the first transaction attempt 2539 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2540 * Transfer Descriptor is inserted into the lattice, we will only count the 2541 * number of bytes for one transaction. 2542 * 2543 * The following are the formulas used for calculating bandwidth in terms 2544 * bytes and it is for the single USB high speed transaction. The protocol 2545 * overheads will be different for each of type of USB transfer & all these 2546 * formulas & protocol overheads are derived from the 5.11.3 section of the 2547 * USB 2.0 Specification. 2548 * 2549 * High-Speed: 2550 * Protocol overhead + ((MaxPktSz * 7)/6) + Host_Delay 2551 * 2552 * Split Transaction: (Low/Full speed devices connected behind usb2.0 hub) 2553 * 2554 * Protocol overhead + Split transaction overhead + 2555 * ((MaxPktSz * 7)/6) + Host_Delay; 2556 */ 2557 /* ARGSUSED */ 2558 static int 2559 ehci_compute_high_speed_bandwidth( 2560 ehci_state_t *ehcip, 2561 usb_ep_descr_t *endpoint, 2562 usb_port_status_t port_status, 2563 uint_t *sbandwidth, 2564 uint_t *cbandwidth) 2565 { 2566 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2567 2568 /* Return failure if endpoint maximum packet is zero */ 2569 if (maxpacketsize == 0) { 2570 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2571 "ehci_allocate_high_speed_bandwidth: Periodic endpoint " 2572 "with zero endpoint maximum packet size is not supported"); 2573 2574 return (USB_NOT_SUPPORTED); 2575 } 2576 2577 /* Add bit-stuffing overhead */ 2578 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2579 2580 /* Add Host Controller specific delay to required bandwidth */ 2581 *sbandwidth = EHCI_HOST_CONTROLLER_DELAY; 2582 2583 /* Add xfer specific protocol overheads */ 2584 if ((endpoint->bmAttributes & 2585 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2586 /* High speed interrupt transaction */ 2587 *sbandwidth += HS_NON_ISOC_PROTO_OVERHEAD; 2588 } else { 2589 /* Isochronous transaction */ 2590 *sbandwidth += HS_ISOC_PROTO_OVERHEAD; 2591 } 2592 2593 /* 2594 * For low/full speed devices, add split transaction specific 2595 * overheads. 2596 */ 2597 if (port_status != USBA_HIGH_SPEED_DEV) { 2598 /* 2599 * Add start and complete split transaction 2600 * tokens overheads. 2601 */ 2602 *cbandwidth = *sbandwidth + COMPLETE_SPLIT_OVERHEAD; 2603 *sbandwidth += START_SPLIT_OVERHEAD; 2604 2605 /* Add data overhead depending on data direction */ 2606 if ((endpoint->bEndpointAddress & 2607 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2608 *cbandwidth += maxpacketsize; 2609 } else { 2610 if ((endpoint->bmAttributes & 2611 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 2612 /* There is no compete splits for out */ 2613 *cbandwidth = 0; 2614 } 2615 *sbandwidth += maxpacketsize; 2616 } 2617 } else { 2618 uint_t xactions; 2619 2620 /* Get the max transactions per microframe */ 2621 xactions = ((maxpacketsize & USB_EP_MAX_XACTS_MASK) >> 2622 USB_EP_MAX_XACTS_SHIFT) + 1; 2623 2624 /* High speed transaction */ 2625 *sbandwidth += maxpacketsize; 2626 2627 /* Calculate bandwidth per micro-frame */ 2628 *sbandwidth *= xactions; 2629 2630 *cbandwidth = 0; 2631 } 2632 2633 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2634 "ehci_allocate_high_speed_bandwidth: " 2635 "Start split bandwidth %d Complete split bandwidth %d", 2636 *sbandwidth, *cbandwidth); 2637 2638 return (USB_SUCCESS); 2639 } 2640 2641 2642 /* 2643 * ehci_compute_classic_bandwidth: 2644 * 2645 * Given a periodic endpoint (interrupt or isochronous) determine the total 2646 * bandwidth for one transaction. The EHCI host controller traverses the 2647 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2648 * services an endpoint, only a single transaction attempt is made. The HC 2649 * moves to the next Endpoint Descriptor after the first transaction attempt 2650 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2651 * Transfer Descriptor is inserted into the lattice, we will only count the 2652 * number of bytes for one transaction. 2653 * 2654 * The following are the formulas used for calculating bandwidth in terms 2655 * bytes and it is for the single USB high speed transaction. The protocol 2656 * overheads will be different for each of type of USB transfer & all these 2657 * formulas & protocol overheads are derived from the 5.11.3 section of the 2658 * USB 2.0 Specification. 2659 * 2660 * Low-Speed: 2661 * Protocol overhead + Hub LS overhead + 2662 * (Low Speed clock * ((MaxPktSz * 7)/6)) + TT_Delay 2663 * 2664 * Full-Speed: 2665 * Protocol overhead + ((MaxPktSz * 7)/6) + TT_Delay 2666 */ 2667 /* ARGSUSED */ 2668 static int 2669 ehci_compute_classic_bandwidth( 2670 usb_ep_descr_t *endpoint, 2671 usb_port_status_t port_status, 2672 uint_t *bandwidth) 2673 { 2674 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2675 2676 /* 2677 * If endpoint maximum packet is zero, then return immediately. 2678 */ 2679 if (maxpacketsize == 0) { 2680 2681 return (USB_NOT_SUPPORTED); 2682 } 2683 2684 /* Add TT delay to required bandwidth */ 2685 *bandwidth = TT_DELAY; 2686 2687 /* Add bit-stuffing overhead */ 2688 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2689 2690 switch (port_status) { 2691 case USBA_LOW_SPEED_DEV: 2692 /* Low speed interrupt transaction */ 2693 *bandwidth += (LOW_SPEED_PROTO_OVERHEAD + 2694 HUB_LOW_SPEED_PROTO_OVERHEAD + 2695 (LOW_SPEED_CLOCK * maxpacketsize)); 2696 break; 2697 case USBA_FULL_SPEED_DEV: 2698 /* Full speed transaction */ 2699 *bandwidth += maxpacketsize; 2700 2701 /* Add xfer specific protocol overheads */ 2702 if ((endpoint->bmAttributes & 2703 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2704 /* Full speed interrupt transaction */ 2705 *bandwidth += FS_NON_ISOC_PROTO_OVERHEAD; 2706 } else { 2707 /* Isochronous and input transaction */ 2708 if ((endpoint->bEndpointAddress & 2709 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2710 *bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD; 2711 } else { 2712 /* Isochronous and output transaction */ 2713 *bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD; 2714 } 2715 } 2716 break; 2717 } 2718 2719 return (USB_SUCCESS); 2720 } 2721 2722 2723 /* 2724 * ehci_adjust_polling_interval: 2725 * 2726 * Adjust bandwidth according usb device speed. 2727 */ 2728 /* ARGSUSED */ 2729 int 2730 ehci_adjust_polling_interval( 2731 ehci_state_t *ehcip, 2732 usb_ep_descr_t *endpoint, 2733 usb_port_status_t port_status) 2734 { 2735 uint_t interval; 2736 int i = 0; 2737 2738 /* Get the polling interval */ 2739 interval = endpoint->bInterval; 2740 2741 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2742 "ehci_adjust_polling_interval: Polling interval 0x%x", interval); 2743 2744 /* 2745 * According USB 2.0 Specifications, a high-speed endpoint's 2746 * polling intervals are specified interms of 125us or micro 2747 * frame, where as full/low endpoint's polling intervals are 2748 * specified in milliseconds. 2749 * 2750 * A high speed interrupt/isochronous endpoints can specify 2751 * desired polling interval between 1 to 16 micro-frames, 2752 * where as full/low endpoints can specify between 1 to 255 2753 * milliseconds. 2754 */ 2755 switch (port_status) { 2756 case USBA_LOW_SPEED_DEV: 2757 /* 2758 * Low speed endpoints are limited to specifying 2759 * only 8ms to 255ms in this driver. If a device 2760 * reports a polling interval that is less than 8ms, 2761 * it will use 8 ms instead. 2762 */ 2763 if (interval < LS_MIN_POLL_INTERVAL) { 2764 2765 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2766 "Low speed endpoint's poll interval of %d ms " 2767 "is below threshold. Rounding up to %d ms", 2768 interval, LS_MIN_POLL_INTERVAL); 2769 2770 interval = LS_MIN_POLL_INTERVAL; 2771 } 2772 2773 /* 2774 * Return an error if the polling interval is greater 2775 * than 255ms. 2776 */ 2777 if (interval > LS_MAX_POLL_INTERVAL) { 2778 2779 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2780 "Low speed endpoint's poll interval is " 2781 "greater than %d ms", LS_MAX_POLL_INTERVAL); 2782 2783 return (USB_FAILURE); 2784 } 2785 break; 2786 2787 case USBA_FULL_SPEED_DEV: 2788 /* 2789 * Return an error if the polling interval is less 2790 * than 1ms and greater than 255ms. 2791 */ 2792 if ((interval < FS_MIN_POLL_INTERVAL) && 2793 (interval > FS_MAX_POLL_INTERVAL)) { 2794 2795 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2796 "Full speed endpoint's poll interval must " 2797 "be between %d and %d ms", FS_MIN_POLL_INTERVAL, 2798 FS_MAX_POLL_INTERVAL); 2799 2800 return (USB_FAILURE); 2801 } 2802 break; 2803 case USBA_HIGH_SPEED_DEV: 2804 /* 2805 * Return an error if the polling interval is less 1 2806 * and greater than 16. Convert this value to 125us 2807 * units using 2^(bInterval -1). refer usb 2.0 spec 2808 * page 51 for details. 2809 */ 2810 if ((interval < HS_MIN_POLL_INTERVAL) && 2811 (interval > HS_MAX_POLL_INTERVAL)) { 2812 2813 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2814 "High speed endpoint's poll interval " 2815 "must be between %d and %d units", 2816 HS_MIN_POLL_INTERVAL, HS_MAX_POLL_INTERVAL); 2817 2818 return (USB_FAILURE); 2819 } 2820 2821 /* Adjust high speed device polling interval */ 2822 interval = 2823 ehci_adjust_high_speed_polling_interval(ehcip, endpoint); 2824 2825 break; 2826 } 2827 2828 /* 2829 * If polling interval is greater than 32ms, 2830 * adjust polling interval equal to 32ms. 2831 */ 2832 if (interval > EHCI_NUM_INTR_QH_LISTS) { 2833 interval = EHCI_NUM_INTR_QH_LISTS; 2834 } 2835 2836 /* 2837 * Find the nearest power of 2 that's less 2838 * than interval. 2839 */ 2840 while ((ehci_pow_2(i)) <= interval) { 2841 i++; 2842 } 2843 2844 return (ehci_pow_2((i - 1))); 2845 } 2846 2847 2848 /* 2849 * ehci_adjust_high_speed_polling_interval: 2850 */ 2851 /* ARGSUSED */ 2852 static int 2853 ehci_adjust_high_speed_polling_interval( 2854 ehci_state_t *ehcip, 2855 usb_ep_descr_t *endpoint) 2856 { 2857 uint_t interval; 2858 2859 /* Get the polling interval */ 2860 interval = ehci_pow_2(endpoint->bInterval - 1); 2861 2862 /* 2863 * Convert polling interval from micro seconds 2864 * to milli seconds. 2865 */ 2866 if (interval <= EHCI_MAX_UFRAMES) { 2867 interval = 1; 2868 } else { 2869 interval = interval/EHCI_MAX_UFRAMES; 2870 } 2871 2872 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2873 "ehci_adjust_high_speed_polling_interval: " 2874 "High speed adjusted interval 0x%x", interval); 2875 2876 return (interval); 2877 } 2878 2879 2880 /* 2881 * ehci_lattice_height: 2882 * 2883 * Given the requested bandwidth, find the height in the tree at which the 2884 * nodes for this bandwidth fall. The height is measured as the number of 2885 * nodes from the leaf to the level specified by bandwidth The root of the 2886 * tree is at height TREE_HEIGHT. 2887 */ 2888 static uint_t 2889 ehci_lattice_height(uint_t interval) 2890 { 2891 return (TREE_HEIGHT - (ehci_log_2(interval))); 2892 } 2893 2894 2895 /* 2896 * ehci_lattice_parent: 2897 * 2898 * Given a node in the lattice, find the index of the parent node 2899 */ 2900 static uint_t 2901 ehci_lattice_parent(uint_t node) 2902 { 2903 if ((node % 2) == 0) { 2904 2905 return ((node/2) - 1); 2906 } else { 2907 2908 return ((node + 1)/2 - 1); 2909 } 2910 } 2911 2912 2913 /* 2914 * ehci_find_periodic_node: 2915 * 2916 * Based on the "real" array leaf node and interval, get the periodic node. 2917 */ 2918 static uint_t 2919 ehci_find_periodic_node(uint_t leaf, int interval) { 2920 uint_t lattice_leaf; 2921 uint_t height = ehci_lattice_height(interval); 2922 uint_t pnode; 2923 int i; 2924 2925 /* Get the leaf number in the lattice */ 2926 lattice_leaf = leaf + EHCI_NUM_INTR_QH_LISTS - 1; 2927 2928 /* Get the node in the lattice based on the height and leaf */ 2929 pnode = lattice_leaf; 2930 for (i = 0; i < height; i++) { 2931 pnode = ehci_lattice_parent(pnode); 2932 } 2933 2934 return (pnode); 2935 } 2936 2937 2938 /* 2939 * ehci_leftmost_leaf: 2940 * 2941 * Find the leftmost leaf in the subtree specified by the node. Height refers 2942 * to number of nodes from the bottom of the tree to the node, including the 2943 * node. 2944 * 2945 * The formula for a zero based tree is: 2946 * 2^H * Node + 2^H - 1 2947 * The leaf of the tree is an array, convert the number for the array. 2948 * Subtract the size of nodes not in the array 2949 * 2^H * Node + 2^H - 1 - (EHCI_NUM_INTR_QH_LISTS - 1) = 2950 * 2^H * Node + 2^H - EHCI_NUM_INTR_QH_LISTS = 2951 * 2^H * (Node + 1) - EHCI_NUM_INTR_QH_LISTS 2952 * 0 2953 * 1 2 2954 * 0 1 2 3 2955 */ 2956 static uint_t 2957 ehci_leftmost_leaf( 2958 uint_t node, 2959 uint_t height) 2960 { 2961 return ((ehci_pow_2(height) * (node + 1)) - EHCI_NUM_INTR_QH_LISTS); 2962 } 2963 2964 2965 /* 2966 * ehci_pow_2: 2967 * 2968 * Compute 2 to the power 2969 */ 2970 static uint_t 2971 ehci_pow_2(uint_t x) 2972 { 2973 if (x == 0) { 2974 2975 return (1); 2976 } else { 2977 2978 return (2 << (x - 1)); 2979 } 2980 } 2981 2982 2983 /* 2984 * ehci_log_2: 2985 * 2986 * Compute log base 2 of x 2987 */ 2988 static uint_t 2989 ehci_log_2(uint_t x) 2990 { 2991 int i = 0; 2992 2993 while (x != 1) { 2994 x = x >> 1; 2995 i++; 2996 } 2997 2998 return (i); 2999 } 3000 3001 3002 /* 3003 * ehci_find_bestfit_hs_mask: 3004 * 3005 * Find the smask and cmask in the bandwidth allocation, and update the 3006 * bandwidth allocation. 3007 */ 3008 static int 3009 ehci_find_bestfit_hs_mask( 3010 ehci_state_t *ehcip, 3011 uchar_t *smask, 3012 uint_t *pnode, 3013 usb_ep_descr_t *endpoint, 3014 uint_t bandwidth, 3015 int interval) 3016 { 3017 int i; 3018 uint_t elements, index; 3019 int array_leaf, best_array_leaf; 3020 uint_t node_bandwidth, best_node_bandwidth; 3021 uint_t leaf_count; 3022 uchar_t bw_mask; 3023 uchar_t best_smask; 3024 3025 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3026 "ehci_find_bestfit_hs_mask: "); 3027 3028 /* Get all the valid smasks */ 3029 switch (ehci_pow_2(endpoint->bInterval - 1)) { 3030 case EHCI_INTR_1US_POLL: 3031 index = EHCI_1US_MASK_INDEX; 3032 elements = EHCI_INTR_1US_POLL; 3033 break; 3034 case EHCI_INTR_2US_POLL: 3035 index = EHCI_2US_MASK_INDEX; 3036 elements = EHCI_INTR_2US_POLL; 3037 break; 3038 case EHCI_INTR_4US_POLL: 3039 index = EHCI_4US_MASK_INDEX; 3040 elements = EHCI_INTR_4US_POLL; 3041 break; 3042 case EHCI_INTR_XUS_POLL: 3043 default: 3044 index = EHCI_XUS_MASK_INDEX; 3045 elements = EHCI_INTR_XUS_POLL; 3046 break; 3047 } 3048 3049 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3050 3051 /* 3052 * Because of the way the leaves are setup, we will automatically 3053 * hit the leftmost leaf of every possible node with this interval. 3054 */ 3055 best_smask = 0x00; 3056 best_node_bandwidth = 0; 3057 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3058 /* Find the bandwidth mask */ 3059 node_bandwidth = ehci_calculate_bw_availability_mask(ehcip, 3060 bandwidth, ehci_index[array_leaf], leaf_count, &bw_mask); 3061 3062 /* 3063 * If this node cannot support our requirements skip to the 3064 * next leaf. 3065 */ 3066 if (bw_mask == 0x00) { 3067 continue; 3068 } 3069 3070 /* 3071 * Now make sure our bandwidth requirements can be 3072 * satisfied with one of smasks in this node. 3073 */ 3074 *smask = 0x00; 3075 for (i = index; i < (index + elements); i++) { 3076 /* Check the start split mask value */ 3077 if (ehci_start_split_mask[index] & bw_mask) { 3078 *smask = ehci_start_split_mask[index]; 3079 break; 3080 } 3081 } 3082 3083 /* 3084 * If an appropriate smask is found save the information if: 3085 * o best_smask has not been found yet. 3086 * - or - 3087 * o This is the node with the least amount of bandwidth 3088 */ 3089 if ((*smask != 0x00) && 3090 ((best_smask == 0x00) || 3091 (best_node_bandwidth > node_bandwidth))) { 3092 3093 best_node_bandwidth = node_bandwidth; 3094 best_array_leaf = array_leaf; 3095 best_smask = *smask; 3096 } 3097 } 3098 3099 /* 3100 * If we find node that can handle the bandwidth populate the 3101 * appropriate variables and return success. 3102 */ 3103 if (best_smask) { 3104 *smask = best_smask; 3105 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3106 interval); 3107 ehci_update_bw_availability(ehcip, bandwidth, 3108 ehci_index[best_array_leaf], leaf_count, best_smask); 3109 3110 return (USB_SUCCESS); 3111 } 3112 3113 return (USB_FAILURE); 3114 } 3115 3116 3117 /* 3118 * ehci_find_bestfit_ls_intr_mask: 3119 * 3120 * Find the smask and cmask in the bandwidth allocation. 3121 */ 3122 static int 3123 ehci_find_bestfit_ls_intr_mask( 3124 ehci_state_t *ehcip, 3125 uchar_t *smask, 3126 uchar_t *cmask, 3127 uint_t *pnode, 3128 uint_t sbandwidth, 3129 uint_t cbandwidth, 3130 int interval) 3131 { 3132 int i; 3133 uint_t elements, index; 3134 int array_leaf, best_array_leaf; 3135 uint_t node_sbandwidth, node_cbandwidth; 3136 uint_t best_node_bandwidth; 3137 uint_t leaf_count; 3138 uchar_t bw_smask, bw_cmask; 3139 uchar_t best_smask, best_cmask; 3140 3141 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3142 "ehci_find_bestfit_ls_intr_mask: "); 3143 3144 /* For low and full speed devices */ 3145 index = EHCI_XUS_MASK_INDEX; 3146 elements = EHCI_INTR_4MS_POLL; 3147 3148 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3149 3150 /* 3151 * Because of the way the leaves are setup, we will automatically 3152 * hit the leftmost leaf of every possible node with this interval. 3153 */ 3154 best_smask = 0x00; 3155 best_node_bandwidth = 0; 3156 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3157 /* Find the bandwidth mask */ 3158 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3159 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3160 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3161 cbandwidth, ehci_index[array_leaf], leaf_count, &bw_cmask); 3162 3163 /* 3164 * If this node cannot support our requirements skip to the 3165 * next leaf. 3166 */ 3167 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3168 continue; 3169 } 3170 3171 /* 3172 * Now make sure our bandwidth requirements can be 3173 * satisfied with one of smasks in this node. 3174 */ 3175 *smask = 0x00; 3176 *cmask = 0x00; 3177 for (i = index; i < (index + elements); i++) { 3178 /* Check the start split mask value */ 3179 if ((ehci_start_split_mask[index] & bw_smask) && 3180 (ehci_intr_complete_split_mask[index] & bw_cmask)) { 3181 *smask = ehci_start_split_mask[index]; 3182 *cmask = ehci_intr_complete_split_mask[index]; 3183 break; 3184 } 3185 } 3186 3187 /* 3188 * If an appropriate smask is found save the information if: 3189 * o best_smask has not been found yet. 3190 * - or - 3191 * o This is the node with the least amount of bandwidth 3192 */ 3193 if ((*smask != 0x00) && 3194 ((best_smask == 0x00) || 3195 (best_node_bandwidth > 3196 (node_sbandwidth + node_cbandwidth)))) { 3197 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3198 best_array_leaf = array_leaf; 3199 best_smask = *smask; 3200 best_cmask = *cmask; 3201 } 3202 } 3203 3204 /* 3205 * If we find node that can handle the bandwidth populate the 3206 * appropriate variables and return success. 3207 */ 3208 if (best_smask) { 3209 *smask = best_smask; 3210 *cmask = best_cmask; 3211 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3212 interval); 3213 ehci_update_bw_availability(ehcip, sbandwidth, 3214 ehci_index[best_array_leaf], leaf_count, best_smask); 3215 ehci_update_bw_availability(ehcip, cbandwidth, 3216 ehci_index[best_array_leaf], leaf_count, best_cmask); 3217 3218 return (USB_SUCCESS); 3219 } 3220 3221 return (USB_FAILURE); 3222 } 3223 3224 3225 /* 3226 * ehci_find_bestfit_sitd_in_mask: 3227 * 3228 * Find the smask and cmask in the bandwidth allocation. 3229 */ 3230 static int 3231 ehci_find_bestfit_sitd_in_mask( 3232 ehci_state_t *ehcip, 3233 uchar_t *smask, 3234 uchar_t *cmask, 3235 uint_t *pnode, 3236 uint_t sbandwidth, 3237 uint_t cbandwidth, 3238 int interval) 3239 { 3240 int i, uFrames, found; 3241 int array_leaf, best_array_leaf; 3242 uint_t node_sbandwidth, node_cbandwidth; 3243 uint_t best_node_bandwidth; 3244 uint_t leaf_count; 3245 uchar_t bw_smask, bw_cmask; 3246 uchar_t best_smask, best_cmask; 3247 3248 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3249 "ehci_find_bestfit_sitd_in_mask: "); 3250 3251 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3252 3253 /* 3254 * Because of the way the leaves are setup, we will automatically 3255 * hit the leftmost leaf of every possible node with this interval. 3256 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3257 */ 3258 /* 3259 * Need to add an additional 2 uFrames, if the "L"ast 3260 * complete split is before uFrame 6. See section 3261 * 11.8.4 in USB 2.0 Spec. Currently we do not support 3262 * the "Back Ptr" which means we support on IN of 3263 * ~4*MAX_UFRAME_SITD_XFER bandwidth/ 3264 */ 3265 uFrames = (cbandwidth / MAX_UFRAME_SITD_XFER) + 2; 3266 if (cbandwidth % MAX_UFRAME_SITD_XFER) { 3267 uFrames++; 3268 } 3269 if (uFrames > 6) { 3270 3271 return (USB_FAILURE); 3272 } 3273 *smask = 0x1; 3274 *cmask = 0x00; 3275 for (i = 0; i < uFrames; i++) { 3276 *cmask = *cmask << 1; 3277 *cmask |= 0x1; 3278 } 3279 /* cmask must start 2 frames after the smask */ 3280 *cmask = *cmask << 2; 3281 3282 found = 0; 3283 best_smask = 0x00; 3284 best_node_bandwidth = 0; 3285 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3286 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3287 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3288 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3289 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3290 &bw_cmask); 3291 3292 /* 3293 * If this node cannot support our requirements skip to the 3294 * next leaf. 3295 */ 3296 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3297 continue; 3298 } 3299 3300 for (i = 0; i < (EHCI_MAX_UFRAMES - uFrames - 2); i++) { 3301 if ((*smask & bw_smask) && (*cmask & bw_cmask)) { 3302 found = 1; 3303 break; 3304 } 3305 *smask = *smask << 1; 3306 *cmask = *cmask << 1; 3307 } 3308 3309 /* 3310 * If an appropriate smask is found save the information if: 3311 * o best_smask has not been found yet. 3312 * - or - 3313 * o This is the node with the least amount of bandwidth 3314 */ 3315 if (found && 3316 ((best_smask == 0x00) || 3317 (best_node_bandwidth > 3318 (node_sbandwidth + node_cbandwidth)))) { 3319 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3320 best_array_leaf = array_leaf; 3321 best_smask = *smask; 3322 best_cmask = *cmask; 3323 } 3324 } 3325 3326 /* 3327 * If we find node that can handle the bandwidth populate the 3328 * appropriate variables and return success. 3329 */ 3330 if (best_smask) { 3331 *smask = best_smask; 3332 *cmask = best_cmask; 3333 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3334 interval); 3335 ehci_update_bw_availability(ehcip, sbandwidth, 3336 ehci_index[best_array_leaf], leaf_count, best_smask); 3337 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3338 ehci_index[best_array_leaf], leaf_count, best_cmask); 3339 3340 return (USB_SUCCESS); 3341 } 3342 3343 return (USB_FAILURE); 3344 } 3345 3346 3347 /* 3348 * ehci_find_bestfit_sitd_out_mask: 3349 * 3350 * Find the smask in the bandwidth allocation. 3351 */ 3352 static int 3353 ehci_find_bestfit_sitd_out_mask( 3354 ehci_state_t *ehcip, 3355 uchar_t *smask, 3356 uint_t *pnode, 3357 uint_t sbandwidth, 3358 int interval) 3359 { 3360 int i, uFrames, found; 3361 int array_leaf, best_array_leaf; 3362 uint_t node_sbandwidth; 3363 uint_t best_node_bandwidth; 3364 uint_t leaf_count; 3365 uchar_t bw_smask; 3366 uchar_t best_smask; 3367 3368 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3369 "ehci_find_bestfit_sitd_out_mask: "); 3370 3371 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3372 3373 /* 3374 * Because of the way the leaves are setup, we will automatically 3375 * hit the leftmost leaf of every possible node with this interval. 3376 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3377 */ 3378 *smask = 0x00; 3379 uFrames = sbandwidth / MAX_UFRAME_SITD_XFER; 3380 if (sbandwidth % MAX_UFRAME_SITD_XFER) { 3381 uFrames++; 3382 } 3383 for (i = 0; i < uFrames; i++) { 3384 *smask = *smask << 1; 3385 *smask |= 0x1; 3386 } 3387 3388 found = 0; 3389 best_smask = 0x00; 3390 best_node_bandwidth = 0; 3391 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3392 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3393 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3394 &bw_smask); 3395 3396 /* 3397 * If this node cannot support our requirements skip to the 3398 * next leaf. 3399 */ 3400 if (bw_smask == 0x00) { 3401 continue; 3402 } 3403 3404 /* You cannot have a start split on the 8th uFrame */ 3405 for (i = 0; (*smask & 0x80) == 0; i++) { 3406 if (*smask & bw_smask) { 3407 found = 1; 3408 break; 3409 } 3410 *smask = *smask << 1; 3411 } 3412 3413 /* 3414 * If an appropriate smask is found save the information if: 3415 * o best_smask has not been found yet. 3416 * - or - 3417 * o This is the node with the least amount of bandwidth 3418 */ 3419 if (found && 3420 ((best_smask == 0x00) || 3421 (best_node_bandwidth > node_sbandwidth))) { 3422 best_node_bandwidth = node_sbandwidth; 3423 best_array_leaf = array_leaf; 3424 best_smask = *smask; 3425 } 3426 } 3427 3428 /* 3429 * If we find node that can handle the bandwidth populate the 3430 * appropriate variables and return success. 3431 */ 3432 if (best_smask) { 3433 *smask = best_smask; 3434 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3435 interval); 3436 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3437 ehci_index[best_array_leaf], leaf_count, best_smask); 3438 3439 return (USB_SUCCESS); 3440 } 3441 3442 return (USB_FAILURE); 3443 } 3444 3445 3446 /* 3447 * ehci_calculate_bw_availability_mask: 3448 * 3449 * Returns the "total bandwidth used" in this node. 3450 * Populates bw_mask with the uFrames that can support the bandwidth. 3451 * 3452 * If all the Frames cannot support this bandwidth, then bw_mask 3453 * will return 0x00 and the "total bandwidth used" will be invalid. 3454 */ 3455 static uint_t 3456 ehci_calculate_bw_availability_mask( 3457 ehci_state_t *ehcip, 3458 uint_t bandwidth, 3459 int leaf, 3460 int leaf_count, 3461 uchar_t *bw_mask) 3462 { 3463 int i, j; 3464 uchar_t bw_uframe; 3465 int uframe_total; 3466 ehci_frame_bandwidth_t *fbp; 3467 uint_t total_bandwidth = 0; 3468 3469 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3470 "ehci_calculate_bw_availability_mask: leaf %d leaf count %d", 3471 leaf, leaf_count); 3472 3473 /* Start by saying all uFrames are available */ 3474 *bw_mask = 0xFF; 3475 3476 for (i = 0; (i < leaf_count) || (*bw_mask == 0x00); i++) { 3477 fbp = &ehcip->ehci_frame_bandwidth[leaf + i]; 3478 3479 total_bandwidth += fbp->ehci_allocated_frame_bandwidth; 3480 3481 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3482 /* 3483 * If the uFrame in bw_mask is available check to see if 3484 * it can support the additional bandwidth. 3485 */ 3486 bw_uframe = (*bw_mask & (0x1 << j)); 3487 uframe_total = 3488 fbp->ehci_micro_frame_bandwidth[j] + 3489 bandwidth; 3490 if ((bw_uframe) && 3491 (uframe_total > HS_PERIODIC_BANDWIDTH)) { 3492 *bw_mask = *bw_mask & ~bw_uframe; 3493 } 3494 } 3495 } 3496 3497 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3498 "ehci_calculate_bw_availability_mask: bandwidth mask 0x%x", 3499 *bw_mask); 3500 3501 return (total_bandwidth); 3502 } 3503 3504 3505 /* 3506 * ehci_update_bw_availability: 3507 * 3508 * The leftmost leaf needs to be in terms of array position and 3509 * not the actual lattice position. 3510 */ 3511 static void 3512 ehci_update_bw_availability( 3513 ehci_state_t *ehcip, 3514 int bandwidth, 3515 int leftmost_leaf, 3516 int leaf_count, 3517 uchar_t mask) 3518 { 3519 int i, j; 3520 ehci_frame_bandwidth_t *fbp; 3521 int uFrame_bandwidth[8]; 3522 3523 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3524 "ehci_update_bw_availability: " 3525 "leaf %d count %d bandwidth 0x%x mask 0x%x", 3526 leftmost_leaf, leaf_count, bandwidth, mask); 3527 3528 ASSERT(leftmost_leaf < 32); 3529 ASSERT(leftmost_leaf >= 0); 3530 3531 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3532 if (mask & 0x1) { 3533 uFrame_bandwidth[j] = bandwidth; 3534 } else { 3535 uFrame_bandwidth[j] = 0; 3536 } 3537 3538 mask = mask >> 1; 3539 } 3540 3541 /* Updated all the effected leafs with the bandwidth */ 3542 for (i = 0; i < leaf_count; i++) { 3543 fbp = &ehcip->ehci_frame_bandwidth[leftmost_leaf + i]; 3544 3545 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3546 fbp->ehci_micro_frame_bandwidth[j] += 3547 uFrame_bandwidth[j]; 3548 fbp->ehci_allocated_frame_bandwidth += 3549 uFrame_bandwidth[j]; 3550 } 3551 } 3552 } 3553 3554 /* 3555 * Miscellaneous functions 3556 */ 3557 3558 /* 3559 * ehci_obtain_state: 3560 * 3561 * NOTE: This function is also called from POLLED MODE. 3562 */ 3563 ehci_state_t * 3564 ehci_obtain_state(dev_info_t *dip) 3565 { 3566 int instance = ddi_get_instance(dip); 3567 3568 ehci_state_t *state = ddi_get_soft_state(ehci_statep, instance); 3569 3570 ASSERT(state != NULL); 3571 3572 return (state); 3573 } 3574 3575 3576 /* 3577 * ehci_state_is_operational: 3578 * 3579 * Check the Host controller state and return proper values. 3580 */ 3581 int 3582 ehci_state_is_operational(ehci_state_t *ehcip) 3583 { 3584 int val; 3585 3586 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3587 3588 switch (ehcip->ehci_hc_soft_state) { 3589 case EHCI_CTLR_INIT_STATE: 3590 case EHCI_CTLR_SUSPEND_STATE: 3591 val = USB_FAILURE; 3592 break; 3593 case EHCI_CTLR_OPERATIONAL_STATE: 3594 val = USB_SUCCESS; 3595 break; 3596 case EHCI_CTLR_ERROR_STATE: 3597 val = USB_HC_HARDWARE_ERROR; 3598 break; 3599 default: 3600 val = USB_FAILURE; 3601 break; 3602 } 3603 3604 return (val); 3605 } 3606 3607 3608 /* 3609 * ehci_do_soft_reset 3610 * 3611 * Do soft reset of ehci host controller. 3612 */ 3613 int 3614 ehci_do_soft_reset(ehci_state_t *ehcip) 3615 { 3616 usb_frame_number_t before_frame_number, after_frame_number; 3617 ehci_regs_t *ehci_save_regs; 3618 3619 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3620 3621 /* Increment host controller error count */ 3622 ehcip->ehci_hc_error++; 3623 3624 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3625 "ehci_do_soft_reset:" 3626 "Reset ehci host controller 0x%x", ehcip->ehci_hc_error); 3627 3628 /* 3629 * Allocate space for saving current Host Controller 3630 * registers. Don't do any recovery if allocation 3631 * fails. 3632 */ 3633 ehci_save_regs = (ehci_regs_t *) 3634 kmem_zalloc(sizeof (ehci_regs_t), KM_NOSLEEP); 3635 3636 if (ehci_save_regs == NULL) { 3637 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3638 "ehci_do_soft_reset: kmem_zalloc failed"); 3639 3640 return (USB_FAILURE); 3641 } 3642 3643 /* Save current ehci registers */ 3644 ehci_save_regs->ehci_command = Get_OpReg(ehci_command); 3645 ehci_save_regs->ehci_interrupt = Get_OpReg(ehci_interrupt); 3646 ehci_save_regs->ehci_ctrl_segment = Get_OpReg(ehci_ctrl_segment); 3647 ehci_save_regs->ehci_async_list_addr = Get_OpReg(ehci_async_list_addr); 3648 ehci_save_regs->ehci_config_flag = Get_OpReg(ehci_config_flag); 3649 ehci_save_regs->ehci_periodic_list_base = 3650 Get_OpReg(ehci_periodic_list_base); 3651 3652 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3653 "ehci_do_soft_reset: Save reg = 0x%p", ehci_save_regs); 3654 3655 /* Disable all list processing and interrupts */ 3656 Set_OpReg(ehci_command, Get_OpReg(ehci_command) & 3657 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE)); 3658 3659 /* Disable all EHCI interrupts */ 3660 Set_OpReg(ehci_interrupt, 0); 3661 3662 /* Wait for few milliseconds */ 3663 drv_usecwait(EHCI_SOF_TIMEWAIT); 3664 3665 /* Do light soft reset of ehci host controller */ 3666 Set_OpReg(ehci_command, 3667 Get_OpReg(ehci_command) | EHCI_CMD_LIGHT_HC_RESET); 3668 3669 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3670 "ehci_do_soft_reset: Reset in progress"); 3671 3672 /* Wait for reset to complete */ 3673 drv_usecwait(EHCI_RESET_TIMEWAIT); 3674 3675 /* 3676 * Restore previous saved EHCI register value 3677 * into the current EHCI registers. 3678 */ 3679 Set_OpReg(ehci_ctrl_segment, (uint32_t) 3680 ehci_save_regs->ehci_ctrl_segment); 3681 3682 Set_OpReg(ehci_periodic_list_base, (uint32_t) 3683 ehci_save_regs->ehci_periodic_list_base); 3684 3685 Set_OpReg(ehci_async_list_addr, (uint32_t) 3686 ehci_save_regs->ehci_async_list_addr); 3687 3688 /* 3689 * For some reason this register might get nulled out by 3690 * the Uli M1575 South Bridge. To workaround the hardware 3691 * problem, check the value after write and retry if the 3692 * last write fails. 3693 */ 3694 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 3695 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) && 3696 (ehci_save_regs->ehci_async_list_addr != 3697 Get_OpReg(ehci_async_list_addr))) { 3698 int retry = 0; 3699 3700 Set_OpRegRetry(ehci_async_list_addr, (uint32_t) 3701 ehci_save_regs->ehci_async_list_addr, retry); 3702 if (retry >= EHCI_MAX_RETRY) { 3703 USB_DPRINTF_L0(PRINT_MASK_ATTA, 3704 ehcip->ehci_log_hdl, "ehci_do_soft_reset:" 3705 " ASYNCLISTADDR write failed."); 3706 3707 return (USB_FAILURE); 3708 } 3709 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3710 "ehci_do_soft_reset: ASYNCLISTADDR " 3711 "write failed, retry=%d", retry); 3712 } 3713 3714 Set_OpReg(ehci_config_flag, (uint32_t) 3715 ehci_save_regs->ehci_config_flag); 3716 3717 /* Enable both Asynchronous and Periodic Schedule if necessary */ 3718 ehci_toggle_scheduler(ehcip); 3719 3720 /* 3721 * Set ehci_interrupt to enable all interrupts except Root 3722 * Hub Status change and frame list rollover interrupts. 3723 */ 3724 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 3725 EHCI_INTR_FRAME_LIST_ROLLOVER | 3726 EHCI_INTR_USB_ERROR | 3727 EHCI_INTR_USB); 3728 3729 /* 3730 * Deallocate the space that allocated for saving 3731 * HC registers. 3732 */ 3733 kmem_free((void *) ehci_save_regs, sizeof (ehci_regs_t)); 3734 3735 /* 3736 * Set the desired interrupt threshold, frame list size (if 3737 * applicable) and turn EHCI host controller. 3738 */ 3739 Set_OpReg(ehci_command, ((Get_OpReg(ehci_command) & 3740 ~EHCI_CMD_INTR_THRESHOLD) | 3741 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 3742 3743 /* Wait 10ms for EHCI to start sending SOF */ 3744 drv_usecwait(EHCI_RESET_TIMEWAIT); 3745 3746 /* 3747 * Get the current usb frame number before waiting for 3748 * few milliseconds. 3749 */ 3750 before_frame_number = ehci_get_current_frame_number(ehcip); 3751 3752 /* Wait for few milliseconds */ 3753 drv_usecwait(EHCI_SOF_TIMEWAIT); 3754 3755 /* 3756 * Get the current usb frame number after waiting for 3757 * few milliseconds. 3758 */ 3759 after_frame_number = ehci_get_current_frame_number(ehcip); 3760 3761 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3762 "ehci_do_soft_reset: Before Frame Number 0x%llx " 3763 "After Frame Number 0x%llx", 3764 before_frame_number, after_frame_number); 3765 3766 if ((after_frame_number <= before_frame_number) && 3767 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 3768 3769 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3770 "ehci_do_soft_reset: Soft reset failed"); 3771 3772 return (USB_FAILURE); 3773 } 3774 3775 return (USB_SUCCESS); 3776 } 3777 3778 3779 /* 3780 * ehci_get_xfer_attrs: 3781 * 3782 * Get the attributes of a particular xfer. 3783 * 3784 * NOTE: This function is also called from POLLED MODE. 3785 */ 3786 usb_req_attrs_t 3787 ehci_get_xfer_attrs( 3788 ehci_state_t *ehcip, 3789 ehci_pipe_private_t *pp, 3790 ehci_trans_wrapper_t *tw) 3791 { 3792 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 3793 usb_req_attrs_t attrs = USB_ATTRS_NONE; 3794 3795 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3796 "ehci_get_xfer_attrs:"); 3797 3798 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 3799 case USB_EP_ATTR_CONTROL: 3800 attrs = ((usb_ctrl_req_t *) 3801 tw->tw_curr_xfer_reqp)->ctrl_attributes; 3802 break; 3803 case USB_EP_ATTR_BULK: 3804 attrs = ((usb_bulk_req_t *) 3805 tw->tw_curr_xfer_reqp)->bulk_attributes; 3806 break; 3807 case USB_EP_ATTR_INTR: 3808 attrs = ((usb_intr_req_t *) 3809 tw->tw_curr_xfer_reqp)->intr_attributes; 3810 break; 3811 } 3812 3813 return (attrs); 3814 } 3815 3816 3817 /* 3818 * ehci_get_current_frame_number: 3819 * 3820 * Get the current software based usb frame number. 3821 */ 3822 usb_frame_number_t 3823 ehci_get_current_frame_number(ehci_state_t *ehcip) 3824 { 3825 usb_frame_number_t usb_frame_number; 3826 usb_frame_number_t ehci_fno, micro_frame_number; 3827 3828 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3829 3830 ehci_fno = ehcip->ehci_fno; 3831 micro_frame_number = Get_OpReg(ehci_frame_index) & 0x3FFF; 3832 3833 /* 3834 * Calculate current software based usb frame number. 3835 * 3836 * This code accounts for the fact that frame number is 3837 * updated by the Host Controller before the ehci driver 3838 * gets an FrameListRollover interrupt that will adjust 3839 * Frame higher part. 3840 * 3841 * Refer ehci specification 1.0, section 2.3.2, page 21. 3842 */ 3843 micro_frame_number = ((micro_frame_number & 0x1FFF) | 3844 ehci_fno) + (((micro_frame_number & 0x3FFF) ^ 3845 ehci_fno) & 0x2000); 3846 3847 /* 3848 * Micro Frame number is equivalent to 125 usec. Eight 3849 * Micro Frame numbers are equivalent to one millsecond 3850 * or one usb frame number. 3851 */ 3852 usb_frame_number = micro_frame_number >> 3853 EHCI_uFRAMES_PER_USB_FRAME_SHIFT; 3854 3855 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3856 "ehci_get_current_frame_number: " 3857 "Current usb uframe number = 0x%llx " 3858 "Current usb frame number = 0x%llx", 3859 micro_frame_number, usb_frame_number); 3860 3861 return (usb_frame_number); 3862 } 3863 3864 3865 /* 3866 * ehci_cpr_cleanup: 3867 * 3868 * Cleanup ehci state and other ehci specific informations across 3869 * Check Point Resume (CPR). 3870 */ 3871 static void 3872 ehci_cpr_cleanup(ehci_state_t *ehcip) 3873 { 3874 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3875 3876 /* Reset software part of usb frame number */ 3877 ehcip->ehci_fno = 0; 3878 } 3879 3880 3881 /* 3882 * ehci_wait_for_sof: 3883 * 3884 * Wait for couple of SOF interrupts 3885 */ 3886 int 3887 ehci_wait_for_sof(ehci_state_t *ehcip) 3888 { 3889 usb_frame_number_t before_frame_number, after_frame_number; 3890 int error = USB_SUCCESS; 3891 3892 USB_DPRINTF_L4(PRINT_MASK_LISTS, 3893 ehcip->ehci_log_hdl, "ehci_wait_for_sof"); 3894 3895 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3896 3897 error = ehci_state_is_operational(ehcip); 3898 3899 if (error != USB_SUCCESS) { 3900 3901 return (error); 3902 } 3903 3904 /* Get the current usb frame number before waiting for two SOFs */ 3905 before_frame_number = ehci_get_current_frame_number(ehcip); 3906 3907 mutex_exit(&ehcip->ehci_int_mutex); 3908 3909 /* Wait for few milliseconds */ 3910 delay(drv_usectohz(EHCI_SOF_TIMEWAIT)); 3911 3912 mutex_enter(&ehcip->ehci_int_mutex); 3913 3914 /* Get the current usb frame number after woken up */ 3915 after_frame_number = ehci_get_current_frame_number(ehcip); 3916 3917 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3918 "ehci_wait_for_sof: framenumber: before 0x%llx " 3919 "after 0x%llx", before_frame_number, after_frame_number); 3920 3921 /* Return failure, if usb frame number has not been changed */ 3922 if (after_frame_number <= before_frame_number) { 3923 3924 if ((ehci_do_soft_reset(ehcip)) != USB_SUCCESS) { 3925 3926 USB_DPRINTF_L0(PRINT_MASK_LISTS, 3927 ehcip->ehci_log_hdl, "No SOF interrupts"); 3928 3929 /* Set host controller soft state to error */ 3930 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 3931 3932 return (USB_FAILURE); 3933 } 3934 3935 /* Get new usb frame number */ 3936 after_frame_number = before_frame_number = 3937 ehci_get_current_frame_number(ehcip); 3938 } 3939 3940 ASSERT(after_frame_number > before_frame_number); 3941 3942 return (USB_SUCCESS); 3943 } 3944 3945 3946 /* 3947 * ehci_toggle_scheduler: 3948 * 3949 * Turn scheduler based on pipe open count. 3950 */ 3951 void 3952 ehci_toggle_scheduler(ehci_state_t *ehcip) { 3953 uint_t temp_reg, cmd_reg; 3954 3955 cmd_reg = Get_OpReg(ehci_command); 3956 temp_reg = cmd_reg; 3957 3958 /* 3959 * Enable/Disable asynchronous scheduler, and 3960 * turn on/off async list door bell 3961 */ 3962 if (ehcip->ehci_open_async_count) { 3963 if (!(cmd_reg & EHCI_CMD_ASYNC_SCHED_ENABLE)) { 3964 /* 3965 * For some reason this address might get nulled out by 3966 * the ehci chip. Set it here just in case it is null. 3967 */ 3968 Set_OpReg(ehci_async_list_addr, 3969 ehci_qh_cpu_to_iommu(ehcip, 3970 ehcip->ehci_head_of_async_sched_list)); 3971 3972 /* 3973 * For some reason this register might get nulled out by 3974 * the Uli M1575 Southbridge. To workaround the HW 3975 * problem, check the value after write and retry if the 3976 * last write fails. 3977 * 3978 * If the ASYNCLISTADDR remains "stuck" after 3979 * EHCI_MAX_RETRY retries, then the M1575 is broken 3980 * and is stuck in an inconsistent state and is about 3981 * to crash the machine with a trn_oor panic when it 3982 * does a DMA read from 0x0. It is better to panic 3983 * now rather than wait for the trn_oor crash; this 3984 * way Customer Service will have a clean signature 3985 * that indicts the M1575 chip rather than a 3986 * mysterious and hard-to-diagnose trn_oor panic. 3987 */ 3988 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 3989 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) && 3990 (ehci_qh_cpu_to_iommu(ehcip, 3991 ehcip->ehci_head_of_async_sched_list) != 3992 Get_OpReg(ehci_async_list_addr))) { 3993 int retry = 0; 3994 3995 Set_OpRegRetry(ehci_async_list_addr, 3996 ehci_qh_cpu_to_iommu(ehcip, 3997 ehcip->ehci_head_of_async_sched_list), 3998 retry); 3999 if (retry >= EHCI_MAX_RETRY) 4000 cmn_err(CE_PANIC, 4001 "ehci_toggle_scheduler: " 4002 "ASYNCLISTADDR write failed."); 4003 4004 USB_DPRINTF_L2(PRINT_MASK_ATTA, 4005 ehcip->ehci_log_hdl, 4006 "ehci_toggle_scheduler: ASYNCLISTADDR " 4007 "write failed, retry=%d", retry); 4008 } 4009 } 4010 cmd_reg |= EHCI_CMD_ASYNC_SCHED_ENABLE; 4011 } else { 4012 cmd_reg &= ~EHCI_CMD_ASYNC_SCHED_ENABLE; 4013 } 4014 4015 if (ehcip->ehci_open_periodic_count) { 4016 if (!(cmd_reg & EHCI_CMD_PERIODIC_SCHED_ENABLE)) { 4017 /* 4018 * For some reason this address get's nulled out by 4019 * the ehci chip. Set it here just in case it is null. 4020 */ 4021 Set_OpReg(ehci_periodic_list_base, 4022 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 4023 0xFFFFF000)); 4024 } 4025 cmd_reg |= EHCI_CMD_PERIODIC_SCHED_ENABLE; 4026 } else { 4027 cmd_reg &= ~EHCI_CMD_PERIODIC_SCHED_ENABLE; 4028 } 4029 4030 /* Just an optimization */ 4031 if (temp_reg != cmd_reg) { 4032 Set_OpReg(ehci_command, cmd_reg); 4033 } 4034 } 4035 4036 /* 4037 * ehci print functions 4038 */ 4039 4040 /* 4041 * ehci_print_caps: 4042 */ 4043 void 4044 ehci_print_caps(ehci_state_t *ehcip) 4045 { 4046 uint_t i; 4047 4048 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4049 "\n\tUSB 2.0 Host Controller Characteristics\n"); 4050 4051 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4052 "Caps Length: 0x%x Version: 0x%x\n", 4053 Get_8Cap(ehci_caps_length), Get_16Cap(ehci_version)); 4054 4055 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4056 "Structural Parameters\n"); 4057 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4058 "Port indicators: %s", (Get_Cap(ehci_hcs_params) & 4059 EHCI_HCS_PORT_INDICATOR) ? "Yes" : "No"); 4060 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4061 "No of Classic host controllers: 0x%x", 4062 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_COMP_CTRLS) 4063 >> EHCI_HCS_NUM_COMP_CTRL_SHIFT); 4064 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4065 "No of ports per Classic host controller: 0x%x", 4066 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS_CC) 4067 >> EHCI_HCS_NUM_PORTS_CC_SHIFT); 4068 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4069 "Port routing rules: %s", (Get_Cap(ehci_hcs_params) & 4070 EHCI_HCS_PORT_ROUTING_RULES) ? "Yes" : "No"); 4071 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4072 "Port power control: %s", (Get_Cap(ehci_hcs_params) & 4073 EHCI_HCS_PORT_POWER_CONTROL) ? "Yes" : "No"); 4074 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4075 "No of root hub ports: 0x%x\n", 4076 Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); 4077 4078 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4079 "Capability Parameters\n"); 4080 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4081 "EHCI extended capability: %s", (Get_Cap(ehci_hcc_params) & 4082 EHCI_HCC_EECP) ? "Yes" : "No"); 4083 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4084 "Isoch schedule threshold: 0x%x", 4085 Get_Cap(ehci_hcc_params) & EHCI_HCC_ISOCH_SCHED_THRESHOLD); 4086 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4087 "Async schedule park capability: %s", (Get_Cap(ehci_hcc_params) & 4088 EHCI_HCC_ASYNC_SCHED_PARK_CAP) ? "Yes" : "No"); 4089 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4090 "Programmable frame list flag: %s", (Get_Cap(ehci_hcc_params) & 4091 EHCI_HCC_PROG_FRAME_LIST_FLAG) ? "256/512/1024" : "1024"); 4092 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4093 "64bit addressing capability: %s\n", (Get_Cap(ehci_hcc_params) & 4094 EHCI_HCC_64BIT_ADDR_CAP) ? "Yes" : "No"); 4095 4096 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4097 "Classic Port Route Description"); 4098 4099 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4100 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4101 "\tPort Route 0x%x: 0x%x", i, Get_8Cap(ehci_port_route[i])); 4102 } 4103 } 4104 4105 4106 /* 4107 * ehci_print_regs: 4108 */ 4109 void 4110 ehci_print_regs(ehci_state_t *ehcip) 4111 { 4112 uint_t i; 4113 4114 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4115 "\n\tEHCI%d Operational Registers\n", 4116 ddi_get_instance(ehcip->ehci_dip)); 4117 4118 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4119 "Command: 0x%x Status: 0x%x", 4120 Get_OpReg(ehci_command), Get_OpReg(ehci_status)); 4121 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4122 "Interrupt: 0x%x Frame Index: 0x%x", 4123 Get_OpReg(ehci_interrupt), Get_OpReg(ehci_frame_index)); 4124 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4125 "Control Segment: 0x%x Periodic List Base: 0x%x", 4126 Get_OpReg(ehci_ctrl_segment), Get_OpReg(ehci_periodic_list_base)); 4127 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4128 "Async List Addr: 0x%x Config Flag: 0x%x", 4129 Get_OpReg(ehci_async_list_addr), Get_OpReg(ehci_config_flag)); 4130 4131 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4132 "Root Hub Port Status"); 4133 4134 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4135 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4136 "\tPort Status 0x%x: 0x%x ", i, 4137 Get_OpReg(ehci_rh_port_status[i])); 4138 } 4139 } 4140 4141 4142 /* 4143 * ehci_print_qh: 4144 */ 4145 void 4146 ehci_print_qh( 4147 ehci_state_t *ehcip, 4148 ehci_qh_t *qh) 4149 { 4150 uint_t i; 4151 4152 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4153 "ehci_print_qh: qh = 0x%p", (void *)qh); 4154 4155 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4156 "\tqh_link_ptr: 0x%x ", Get_QH(qh->qh_link_ptr)); 4157 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4158 "\tqh_ctrl: 0x%x ", Get_QH(qh->qh_ctrl)); 4159 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4160 "\tqh_split_ctrl: 0x%x ", Get_QH(qh->qh_split_ctrl)); 4161 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4162 "\tqh_curr_qtd: 0x%x ", Get_QH(qh->qh_curr_qtd)); 4163 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4164 "\tqh_next_qtd: 0x%x ", Get_QH(qh->qh_next_qtd)); 4165 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4166 "\tqh_alt_next_qtd: 0x%x ", Get_QH(qh->qh_alt_next_qtd)); 4167 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4168 "\tqh_status: 0x%x ", Get_QH(qh->qh_status)); 4169 4170 for (i = 0; i < 5; i++) { 4171 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4172 "\tqh_buf[%d]: 0x%x ", i, Get_QH(qh->qh_buf[i])); 4173 } 4174 4175 for (i = 0; i < 5; i++) { 4176 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4177 "\tqh_buf_high[%d]: 0x%x ", 4178 i, Get_QH(qh->qh_buf_high[i])); 4179 } 4180 4181 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4182 "\tqh_dummy_qtd: 0x%x ", Get_QH(qh->qh_dummy_qtd)); 4183 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4184 "\tqh_prev: 0x%x ", Get_QH(qh->qh_prev)); 4185 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4186 "\tqh_state: 0x%x ", Get_QH(qh->qh_state)); 4187 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4188 "\tqh_reclaim_next: 0x%x ", Get_QH(qh->qh_reclaim_next)); 4189 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4190 "\tqh_reclaim_frame: 0x%x ", Get_QH(qh->qh_reclaim_frame)); 4191 } 4192 4193 4194 /* 4195 * ehci_print_qtd: 4196 */ 4197 void 4198 ehci_print_qtd( 4199 ehci_state_t *ehcip, 4200 ehci_qtd_t *qtd) 4201 { 4202 uint_t i; 4203 4204 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4205 "ehci_print_qtd: qtd = 0x%p", (void *)qtd); 4206 4207 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4208 "\tqtd_next_qtd: 0x%x ", Get_QTD(qtd->qtd_next_qtd)); 4209 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4210 "\tqtd_alt_next_qtd: 0x%x ", Get_QTD(qtd->qtd_alt_next_qtd)); 4211 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4212 "\tqtd_ctrl: 0x%x ", Get_QTD(qtd->qtd_ctrl)); 4213 4214 for (i = 0; i < 5; i++) { 4215 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4216 "\tqtd_buf[%d]: 0x%x ", i, Get_QTD(qtd->qtd_buf[i])); 4217 } 4218 4219 for (i = 0; i < 5; i++) { 4220 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4221 "\tqtd_buf_high[%d]: 0x%x ", 4222 i, Get_QTD(qtd->qtd_buf_high[i])); 4223 } 4224 4225 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4226 "\tqtd_trans_wrapper: 0x%x ", Get_QTD(qtd->qtd_trans_wrapper)); 4227 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4228 "\tqtd_tw_next_qtd: 0x%x ", Get_QTD(qtd->qtd_tw_next_qtd)); 4229 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4230 "\tqtd_active_qtd_next: 0x%x ", Get_QTD(qtd->qtd_active_qtd_next)); 4231 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4232 "\tqtd_active_qtd_prev: 0x%x ", Get_QTD(qtd->qtd_active_qtd_prev)); 4233 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4234 "\tqtd_state: 0x%x ", Get_QTD(qtd->qtd_state)); 4235 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4236 "\tqtd_ctrl_phase: 0x%x ", Get_QTD(qtd->qtd_ctrl_phase)); 4237 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4238 "\tqtd_xfer_offs: 0x%x ", Get_QTD(qtd->qtd_xfer_offs)); 4239 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4240 "\tqtd_xfer_len: 0x%x ", Get_QTD(qtd->qtd_xfer_len)); 4241 } 4242 4243 /* 4244 * ehci kstat functions 4245 */ 4246 4247 /* 4248 * ehci_create_stats: 4249 * 4250 * Allocate and initialize the ehci kstat structures 4251 */ 4252 void 4253 ehci_create_stats(ehci_state_t *ehcip) 4254 { 4255 char kstatname[KSTAT_STRLEN]; 4256 const char *dname = ddi_driver_name(ehcip->ehci_dip); 4257 char *usbtypes[USB_N_COUNT_KSTATS] = 4258 {"ctrl", "isoch", "bulk", "intr"}; 4259 uint_t instance = ehcip->ehci_instance; 4260 ehci_intrs_stats_t *isp; 4261 int i; 4262 4263 if (EHCI_INTRS_STATS(ehcip) == NULL) { 4264 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs", 4265 dname, instance); 4266 EHCI_INTRS_STATS(ehcip) = kstat_create("usba", instance, 4267 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED, 4268 sizeof (ehci_intrs_stats_t) / sizeof (kstat_named_t), 4269 KSTAT_FLAG_PERSISTENT); 4270 4271 if (EHCI_INTRS_STATS(ehcip)) { 4272 isp = EHCI_INTRS_STATS_DATA(ehcip); 4273 kstat_named_init(&isp->ehci_sts_total, 4274 "Interrupts Total", KSTAT_DATA_UINT64); 4275 kstat_named_init(&isp->ehci_sts_not_claimed, 4276 "Not Claimed", KSTAT_DATA_UINT64); 4277 kstat_named_init(&isp->ehci_sts_async_sched_status, 4278 "Async schedule status", KSTAT_DATA_UINT64); 4279 kstat_named_init(&isp->ehci_sts_periodic_sched_status, 4280 "Periodic sched status", KSTAT_DATA_UINT64); 4281 kstat_named_init(&isp->ehci_sts_empty_async_schedule, 4282 "Empty async schedule", KSTAT_DATA_UINT64); 4283 kstat_named_init(&isp->ehci_sts_host_ctrl_halted, 4284 "Host controller Halted", KSTAT_DATA_UINT64); 4285 kstat_named_init(&isp->ehci_sts_async_advance_intr, 4286 "Intr on async advance", KSTAT_DATA_UINT64); 4287 kstat_named_init(&isp->ehci_sts_host_system_error_intr, 4288 "Host system error", KSTAT_DATA_UINT64); 4289 kstat_named_init(&isp->ehci_sts_frm_list_rollover_intr, 4290 "Frame list rollover", KSTAT_DATA_UINT64); 4291 kstat_named_init(&isp->ehci_sts_rh_port_change_intr, 4292 "Port change detect", KSTAT_DATA_UINT64); 4293 kstat_named_init(&isp->ehci_sts_usb_error_intr, 4294 "USB error interrupt", KSTAT_DATA_UINT64); 4295 kstat_named_init(&isp->ehci_sts_usb_intr, 4296 "USB interrupt", KSTAT_DATA_UINT64); 4297 4298 EHCI_INTRS_STATS(ehcip)->ks_private = ehcip; 4299 EHCI_INTRS_STATS(ehcip)->ks_update = nulldev; 4300 kstat_install(EHCI_INTRS_STATS(ehcip)); 4301 } 4302 } 4303 4304 if (EHCI_TOTAL_STATS(ehcip) == NULL) { 4305 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total", 4306 dname, instance); 4307 EHCI_TOTAL_STATS(ehcip) = kstat_create("usba", instance, 4308 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1, 4309 KSTAT_FLAG_PERSISTENT); 4310 4311 if (EHCI_TOTAL_STATS(ehcip)) { 4312 kstat_install(EHCI_TOTAL_STATS(ehcip)); 4313 } 4314 } 4315 4316 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4317 if (ehcip->ehci_count_stats[i] == NULL) { 4318 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s", 4319 dname, instance, usbtypes[i]); 4320 ehcip->ehci_count_stats[i] = kstat_create("usba", 4321 instance, kstatname, "usb_byte_count", 4322 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 4323 4324 if (ehcip->ehci_count_stats[i]) { 4325 kstat_install(ehcip->ehci_count_stats[i]); 4326 } 4327 } 4328 } 4329 } 4330 4331 4332 /* 4333 * ehci_destroy_stats: 4334 * 4335 * Clean up ehci kstat structures 4336 */ 4337 void 4338 ehci_destroy_stats(ehci_state_t *ehcip) 4339 { 4340 int i; 4341 4342 if (EHCI_INTRS_STATS(ehcip)) { 4343 kstat_delete(EHCI_INTRS_STATS(ehcip)); 4344 EHCI_INTRS_STATS(ehcip) = NULL; 4345 } 4346 4347 if (EHCI_TOTAL_STATS(ehcip)) { 4348 kstat_delete(EHCI_TOTAL_STATS(ehcip)); 4349 EHCI_TOTAL_STATS(ehcip) = NULL; 4350 } 4351 4352 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4353 if (ehcip->ehci_count_stats[i]) { 4354 kstat_delete(ehcip->ehci_count_stats[i]); 4355 ehcip->ehci_count_stats[i] = NULL; 4356 } 4357 } 4358 } 4359 4360 4361 /* 4362 * ehci_do_intrs_stats: 4363 * 4364 * ehci status information 4365 */ 4366 void 4367 ehci_do_intrs_stats( 4368 ehci_state_t *ehcip, 4369 int val) 4370 { 4371 if (EHCI_INTRS_STATS(ehcip)) { 4372 EHCI_INTRS_STATS_DATA(ehcip)->ehci_sts_total.value.ui64++; 4373 switch (val) { 4374 case EHCI_STS_ASYNC_SCHED_STATUS: 4375 EHCI_INTRS_STATS_DATA(ehcip)-> 4376 ehci_sts_async_sched_status.value.ui64++; 4377 break; 4378 case EHCI_STS_PERIODIC_SCHED_STATUS: 4379 EHCI_INTRS_STATS_DATA(ehcip)-> 4380 ehci_sts_periodic_sched_status.value.ui64++; 4381 break; 4382 case EHCI_STS_EMPTY_ASYNC_SCHEDULE: 4383 EHCI_INTRS_STATS_DATA(ehcip)-> 4384 ehci_sts_empty_async_schedule.value.ui64++; 4385 break; 4386 case EHCI_STS_HOST_CTRL_HALTED: 4387 EHCI_INTRS_STATS_DATA(ehcip)-> 4388 ehci_sts_host_ctrl_halted.value.ui64++; 4389 break; 4390 case EHCI_STS_ASYNC_ADVANCE_INTR: 4391 EHCI_INTRS_STATS_DATA(ehcip)-> 4392 ehci_sts_async_advance_intr.value.ui64++; 4393 break; 4394 case EHCI_STS_HOST_SYSTEM_ERROR_INTR: 4395 EHCI_INTRS_STATS_DATA(ehcip)-> 4396 ehci_sts_host_system_error_intr.value.ui64++; 4397 break; 4398 case EHCI_STS_FRM_LIST_ROLLOVER_INTR: 4399 EHCI_INTRS_STATS_DATA(ehcip)-> 4400 ehci_sts_frm_list_rollover_intr.value.ui64++; 4401 break; 4402 case EHCI_STS_RH_PORT_CHANGE_INTR: 4403 EHCI_INTRS_STATS_DATA(ehcip)-> 4404 ehci_sts_rh_port_change_intr.value.ui64++; 4405 break; 4406 case EHCI_STS_USB_ERROR_INTR: 4407 EHCI_INTRS_STATS_DATA(ehcip)-> 4408 ehci_sts_usb_error_intr.value.ui64++; 4409 break; 4410 case EHCI_STS_USB_INTR: 4411 EHCI_INTRS_STATS_DATA(ehcip)-> 4412 ehci_sts_usb_intr.value.ui64++; 4413 break; 4414 default: 4415 EHCI_INTRS_STATS_DATA(ehcip)-> 4416 ehci_sts_not_claimed.value.ui64++; 4417 break; 4418 } 4419 } 4420 } 4421 4422 4423 /* 4424 * ehci_do_byte_stats: 4425 * 4426 * ehci data xfer information 4427 */ 4428 void 4429 ehci_do_byte_stats( 4430 ehci_state_t *ehcip, 4431 size_t len, 4432 uint8_t attr, 4433 uint8_t addr) 4434 { 4435 uint8_t type = attr & USB_EP_ATTR_MASK; 4436 uint8_t dir = addr & USB_EP_DIR_MASK; 4437 4438 if (dir == USB_EP_DIR_IN) { 4439 EHCI_TOTAL_STATS_DATA(ehcip)->reads++; 4440 EHCI_TOTAL_STATS_DATA(ehcip)->nread += len; 4441 switch (type) { 4442 case USB_EP_ATTR_CONTROL: 4443 EHCI_CTRL_STATS(ehcip)->reads++; 4444 EHCI_CTRL_STATS(ehcip)->nread += len; 4445 break; 4446 case USB_EP_ATTR_BULK: 4447 EHCI_BULK_STATS(ehcip)->reads++; 4448 EHCI_BULK_STATS(ehcip)->nread += len; 4449 break; 4450 case USB_EP_ATTR_INTR: 4451 EHCI_INTR_STATS(ehcip)->reads++; 4452 EHCI_INTR_STATS(ehcip)->nread += len; 4453 break; 4454 case USB_EP_ATTR_ISOCH: 4455 EHCI_ISOC_STATS(ehcip)->reads++; 4456 EHCI_ISOC_STATS(ehcip)->nread += len; 4457 break; 4458 } 4459 } else if (dir == USB_EP_DIR_OUT) { 4460 EHCI_TOTAL_STATS_DATA(ehcip)->writes++; 4461 EHCI_TOTAL_STATS_DATA(ehcip)->nwritten += len; 4462 switch (type) { 4463 case USB_EP_ATTR_CONTROL: 4464 EHCI_CTRL_STATS(ehcip)->writes++; 4465 EHCI_CTRL_STATS(ehcip)->nwritten += len; 4466 break; 4467 case USB_EP_ATTR_BULK: 4468 EHCI_BULK_STATS(ehcip)->writes++; 4469 EHCI_BULK_STATS(ehcip)->nwritten += len; 4470 break; 4471 case USB_EP_ATTR_INTR: 4472 EHCI_INTR_STATS(ehcip)->writes++; 4473 EHCI_INTR_STATS(ehcip)->nwritten += len; 4474 break; 4475 case USB_EP_ATTR_ISOCH: 4476 EHCI_ISOC_STATS(ehcip)->writes++; 4477 EHCI_ISOC_STATS(ehcip)->nwritten += len; 4478 break; 4479 } 4480 } 4481 } 4482