1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * EHCI Host Controller Driver (EHCI) 30 * 31 * The EHCI driver is a software driver which interfaces to the Universal 32 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 33 * the Host Controller is defined by the EHCI Host Controller Interface. 34 * 35 * This module contains the main EHCI driver code which handles all USB 36 * transfers, bandwidth allocations and other general functionalities. 37 */ 38 39 #include <sys/usb/hcd/ehci/ehcid.h> 40 #include <sys/usb/hcd/ehci/ehci_isoch.h> 41 #include <sys/usb/hcd/ehci/ehci_xfer.h> 42 43 /* 44 * EHCI MSI tunable: 45 * 46 * By default MSI is enabled on all supported platforms except for the 47 * EHCI controller of ULI1575 South bridge. 48 */ 49 boolean_t ehci_enable_msi = B_TRUE; 50 51 /* Pointer to the state structure */ 52 extern void *ehci_statep; 53 54 extern void ehci_handle_endpoint_reclaimation(ehci_state_t *); 55 56 extern uint_t ehci_vt62x2_workaround; 57 extern int force_ehci_off; 58 59 /* Adjustable variables for the size of the pools */ 60 int ehci_qh_pool_size = EHCI_QH_POOL_SIZE; 61 int ehci_qtd_pool_size = EHCI_QTD_POOL_SIZE; 62 63 /* 64 * Initialize the values which the order of 32ms intr qh are executed 65 * by the host controller in the lattice tree. 66 */ 67 static uchar_t ehci_index[EHCI_NUM_INTR_QH_LISTS] = 68 {0x00, 0x10, 0x08, 0x18, 69 0x04, 0x14, 0x0c, 0x1c, 70 0x02, 0x12, 0x0a, 0x1a, 71 0x06, 0x16, 0x0e, 0x1e, 72 0x01, 0x11, 0x09, 0x19, 73 0x05, 0x15, 0x0d, 0x1d, 74 0x03, 0x13, 0x0b, 0x1b, 75 0x07, 0x17, 0x0f, 0x1f}; 76 77 /* 78 * Initialize the values which are used to calculate start split mask 79 * for the low/full/high speed interrupt and isochronous endpoints. 80 */ 81 static uint_t ehci_start_split_mask[15] = { 82 /* 83 * For high/full/low speed usb devices. For high speed 84 * device with polling interval greater than or equal 85 * to 8us (125us). 86 */ 87 0x01, /* 00000001 */ 88 0x02, /* 00000010 */ 89 0x04, /* 00000100 */ 90 0x08, /* 00001000 */ 91 0x10, /* 00010000 */ 92 0x20, /* 00100000 */ 93 0x40, /* 01000000 */ 94 0x80, /* 10000000 */ 95 96 /* Only for high speed devices with polling interval 4us */ 97 0x11, /* 00010001 */ 98 0x22, /* 00100010 */ 99 0x44, /* 01000100 */ 100 0x88, /* 10001000 */ 101 102 /* Only for high speed devices with polling interval 2us */ 103 0x55, /* 01010101 */ 104 0xaa, /* 10101010 */ 105 106 /* Only for high speed devices with polling interval 1us */ 107 0xff /* 11111111 */ 108 }; 109 110 /* 111 * Initialize the values which are used to calculate complete split mask 112 * for the low/full speed interrupt and isochronous endpoints. 113 */ 114 static uint_t ehci_intr_complete_split_mask[7] = { 115 /* Only full/low speed devices */ 116 0x1c, /* 00011100 */ 117 0x38, /* 00111000 */ 118 0x70, /* 01110000 */ 119 0xe0, /* 11100000 */ 120 0x00, /* Need FSTN feature */ 121 0x00, /* Need FSTN feature */ 122 0x00 /* Need FSTN feature */ 123 }; 124 125 126 /* 127 * EHCI Internal Function Prototypes 128 */ 129 130 /* Host Controller Driver (HCD) initialization functions */ 131 void ehci_set_dma_attributes(ehci_state_t *ehcip); 132 int ehci_allocate_pools(ehci_state_t *ehcip); 133 void ehci_decode_ddi_dma_addr_bind_handle_result( 134 ehci_state_t *ehcip, 135 int result); 136 int ehci_map_regs(ehci_state_t *ehcip); 137 int ehci_register_intrs_and_init_mutex( 138 ehci_state_t *ehcip); 139 static int ehci_add_intrs(ehci_state_t *ehcip, 140 int intr_type); 141 int ehci_init_ctlr(ehci_state_t *ehcip, 142 int init_type); 143 static int ehci_take_control(ehci_state_t *ehcip); 144 static int ehci_init_periodic_frame_lst_table( 145 ehci_state_t *ehcip); 146 static void ehci_build_interrupt_lattice( 147 ehci_state_t *ehcip); 148 usba_hcdi_ops_t *ehci_alloc_hcdi_ops(ehci_state_t *ehcip); 149 150 /* Host Controller Driver (HCD) deinitialization functions */ 151 int ehci_cleanup(ehci_state_t *ehcip); 152 static void ehci_rem_intrs(ehci_state_t *ehcip); 153 int ehci_cpr_suspend(ehci_state_t *ehcip); 154 int ehci_cpr_resume(ehci_state_t *ehcip); 155 156 /* Bandwidth Allocation functions */ 157 int ehci_allocate_bandwidth(ehci_state_t *ehcip, 158 usba_pipe_handle_data_t *ph, 159 uint_t *pnode, 160 uchar_t *smask, 161 uchar_t *cmask); 162 static int ehci_allocate_high_speed_bandwidth( 163 ehci_state_t *ehcip, 164 usba_pipe_handle_data_t *ph, 165 uint_t *hnode, 166 uchar_t *smask, 167 uchar_t *cmask); 168 static int ehci_allocate_classic_tt_bandwidth( 169 ehci_state_t *ehcip, 170 usba_pipe_handle_data_t *ph, 171 uint_t pnode); 172 void ehci_deallocate_bandwidth(ehci_state_t *ehcip, 173 usba_pipe_handle_data_t *ph, 174 uint_t pnode, 175 uchar_t smask, 176 uchar_t cmask); 177 static void ehci_deallocate_high_speed_bandwidth( 178 ehci_state_t *ehcip, 179 usba_pipe_handle_data_t *ph, 180 uint_t hnode, 181 uchar_t smask, 182 uchar_t cmask); 183 static void ehci_deallocate_classic_tt_bandwidth( 184 ehci_state_t *ehcip, 185 usba_pipe_handle_data_t *ph, 186 uint_t pnode); 187 static int ehci_compute_high_speed_bandwidth( 188 ehci_state_t *ehcip, 189 usb_ep_descr_t *endpoint, 190 usb_port_status_t port_status, 191 uint_t *sbandwidth, 192 uint_t *cbandwidth); 193 static int ehci_compute_classic_bandwidth( 194 usb_ep_descr_t *endpoint, 195 usb_port_status_t port_status, 196 uint_t *bandwidth); 197 int ehci_adjust_polling_interval( 198 ehci_state_t *ehcip, 199 usb_ep_descr_t *endpoint, 200 usb_port_status_t port_status); 201 static int ehci_adjust_high_speed_polling_interval( 202 ehci_state_t *ehcip, 203 usb_ep_descr_t *endpoint); 204 static uint_t ehci_lattice_height(uint_t interval); 205 static uint_t ehci_lattice_parent(uint_t node); 206 static uint_t ehci_find_periodic_node( 207 uint_t leaf, 208 int interval); 209 static uint_t ehci_leftmost_leaf(uint_t node, 210 uint_t height); 211 static uint_t ehci_pow_2(uint_t x); 212 static uint_t ehci_log_2(uint_t x); 213 static int ehci_find_bestfit_hs_mask( 214 ehci_state_t *ehcip, 215 uchar_t *smask, 216 uint_t *pnode, 217 usb_ep_descr_t *endpoint, 218 uint_t bandwidth, 219 int interval); 220 static int ehci_find_bestfit_ls_intr_mask( 221 ehci_state_t *ehcip, 222 uchar_t *smask, 223 uchar_t *cmask, 224 uint_t *pnode, 225 uint_t sbandwidth, 226 uint_t cbandwidth, 227 int interval); 228 static int ehci_find_bestfit_sitd_in_mask( 229 ehci_state_t *ehcip, 230 uchar_t *smask, 231 uchar_t *cmask, 232 uint_t *pnode, 233 uint_t sbandwidth, 234 uint_t cbandwidth, 235 int interval); 236 static int ehci_find_bestfit_sitd_out_mask( 237 ehci_state_t *ehcip, 238 uchar_t *smask, 239 uint_t *pnode, 240 uint_t sbandwidth, 241 int interval); 242 static uint_t ehci_calculate_bw_availability_mask( 243 ehci_state_t *ehcip, 244 uint_t bandwidth, 245 int leaf, 246 int leaf_count, 247 uchar_t *bw_mask); 248 static void ehci_update_bw_availability( 249 ehci_state_t *ehcip, 250 int bandwidth, 251 int leftmost_leaf, 252 int leaf_count, 253 uchar_t mask); 254 255 /* Miscellaneous functions */ 256 ehci_state_t *ehci_obtain_state( 257 dev_info_t *dip); 258 int ehci_state_is_operational( 259 ehci_state_t *ehcip); 260 int ehci_do_soft_reset( 261 ehci_state_t *ehcip); 262 usb_req_attrs_t ehci_get_xfer_attrs(ehci_state_t *ehcip, 263 ehci_pipe_private_t *pp, 264 ehci_trans_wrapper_t *tw); 265 usb_frame_number_t ehci_get_current_frame_number( 266 ehci_state_t *ehcip); 267 static void ehci_cpr_cleanup( 268 ehci_state_t *ehcip); 269 int ehci_wait_for_sof( 270 ehci_state_t *ehcip); 271 void ehci_toggle_scheduler( 272 ehci_state_t *ehcip); 273 void ehci_print_caps(ehci_state_t *ehcip); 274 void ehci_print_regs(ehci_state_t *ehcip); 275 void ehci_print_qh(ehci_state_t *ehcip, 276 ehci_qh_t *qh); 277 void ehci_print_qtd(ehci_state_t *ehcip, 278 ehci_qtd_t *qtd); 279 void ehci_create_stats(ehci_state_t *ehcip); 280 void ehci_destroy_stats(ehci_state_t *ehcip); 281 void ehci_do_intrs_stats(ehci_state_t *ehcip, 282 int val); 283 void ehci_do_byte_stats(ehci_state_t *ehcip, 284 size_t len, 285 uint8_t attr, 286 uint8_t addr); 287 288 /* 289 * check if this ehci controller can support PM 290 */ 291 int 292 ehci_hcdi_pm_support(dev_info_t *dip) 293 { 294 ehci_state_t *ehcip = ddi_get_soft_state(ehci_statep, 295 ddi_get_instance(dip)); 296 297 if (((ehcip->ehci_vendor_id == PCI_VENDOR_NEC_COMBO) && 298 (ehcip->ehci_device_id == PCI_DEVICE_NEC_COMBO)) || 299 300 ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 301 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) || 302 303 (ehcip->ehci_vendor_id == PCI_VENDOR_VIA)) { 304 305 return (USB_SUCCESS); 306 } 307 308 return (USB_FAILURE); 309 } 310 311 312 /* 313 * Host Controller Driver (HCD) initialization functions 314 */ 315 316 /* 317 * ehci_set_dma_attributes: 318 * 319 * Set the limits in the DMA attributes structure. Most of the values used 320 * in the DMA limit structures are the default values as specified by the 321 * Writing PCI device drivers document. 322 */ 323 void 324 ehci_set_dma_attributes(ehci_state_t *ehcip) 325 { 326 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 327 "ehci_set_dma_attributes:"); 328 329 /* Initialize the DMA attributes */ 330 ehcip->ehci_dma_attr.dma_attr_version = DMA_ATTR_V0; 331 ehcip->ehci_dma_attr.dma_attr_addr_lo = 0x00000000ull; 332 ehcip->ehci_dma_attr.dma_attr_addr_hi = 0xfffffffeull; 333 334 /* 32 bit addressing */ 335 ehcip->ehci_dma_attr.dma_attr_count_max = EHCI_DMA_ATTR_COUNT_MAX; 336 337 /* Byte alignment */ 338 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 339 340 /* 341 * Since PCI specification is byte alignment, the 342 * burst size field should be set to 1 for PCI devices. 343 */ 344 ehcip->ehci_dma_attr.dma_attr_burstsizes = 0x1; 345 346 ehcip->ehci_dma_attr.dma_attr_minxfer = 0x1; 347 ehcip->ehci_dma_attr.dma_attr_maxxfer = EHCI_DMA_ATTR_MAX_XFER; 348 ehcip->ehci_dma_attr.dma_attr_seg = 0xffffffffull; 349 ehcip->ehci_dma_attr.dma_attr_sgllen = 1; 350 ehcip->ehci_dma_attr.dma_attr_granular = EHCI_DMA_ATTR_GRANULAR; 351 ehcip->ehci_dma_attr.dma_attr_flags = 0; 352 } 353 354 355 /* 356 * ehci_allocate_pools: 357 * 358 * Allocate the system memory for the Endpoint Descriptor (QH) and for the 359 * Transfer Descriptor (QTD) pools. Both QH and QTD structures must be aligned 360 * to a 16 byte boundary. 361 */ 362 int 363 ehci_allocate_pools(ehci_state_t *ehcip) 364 { 365 ddi_device_acc_attr_t dev_attr; 366 size_t real_length; 367 int result; 368 uint_t ccount; 369 int i; 370 371 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 372 "ehci_allocate_pools:"); 373 374 /* The host controller will be little endian */ 375 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 376 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 377 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 378 379 /* Byte alignment */ 380 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_TD_QH_ALIGNMENT; 381 382 /* Allocate the QTD pool DMA handle */ 383 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 384 DDI_DMA_SLEEP, 0, 385 &ehcip->ehci_qtd_pool_dma_handle) != DDI_SUCCESS) { 386 387 goto failure; 388 } 389 390 /* Allocate the memory for the QTD pool */ 391 if (ddi_dma_mem_alloc(ehcip->ehci_qtd_pool_dma_handle, 392 ehci_qtd_pool_size * sizeof (ehci_qtd_t), 393 &dev_attr, 394 DDI_DMA_CONSISTENT, 395 DDI_DMA_SLEEP, 396 0, 397 (caddr_t *)&ehcip->ehci_qtd_pool_addr, 398 &real_length, 399 &ehcip->ehci_qtd_pool_mem_handle)) { 400 401 goto failure; 402 } 403 404 /* Map the QTD pool into the I/O address space */ 405 result = ddi_dma_addr_bind_handle( 406 ehcip->ehci_qtd_pool_dma_handle, 407 NULL, 408 (caddr_t)ehcip->ehci_qtd_pool_addr, 409 real_length, 410 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 411 DDI_DMA_SLEEP, 412 NULL, 413 &ehcip->ehci_qtd_pool_cookie, 414 &ccount); 415 416 bzero((void *)ehcip->ehci_qtd_pool_addr, 417 ehci_qtd_pool_size * sizeof (ehci_qtd_t)); 418 419 /* Process the result */ 420 if (result == DDI_DMA_MAPPED) { 421 /* The cookie count should be 1 */ 422 if (ccount != 1) { 423 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 424 "ehci_allocate_pools: More than 1 cookie"); 425 426 goto failure; 427 } 428 } else { 429 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 430 "ehci_allocate_pools: Result = %d", result); 431 432 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 433 434 goto failure; 435 } 436 437 /* 438 * DMA addresses for QTD pools are bound 439 */ 440 ehcip->ehci_dma_addr_bind_flag |= EHCI_QTD_POOL_BOUND; 441 442 /* Initialize the QTD pool */ 443 for (i = 0; i < ehci_qtd_pool_size; i ++) { 444 Set_QTD(ehcip->ehci_qtd_pool_addr[i]. 445 qtd_state, EHCI_QTD_FREE); 446 } 447 448 /* Allocate the QTD pool DMA handle */ 449 if (ddi_dma_alloc_handle(ehcip->ehci_dip, 450 &ehcip->ehci_dma_attr, 451 DDI_DMA_SLEEP, 452 0, 453 &ehcip->ehci_qh_pool_dma_handle) != DDI_SUCCESS) { 454 455 goto failure; 456 } 457 458 /* Allocate the memory for the QH pool */ 459 if (ddi_dma_mem_alloc(ehcip->ehci_qh_pool_dma_handle, 460 ehci_qh_pool_size * sizeof (ehci_qh_t), 461 &dev_attr, 462 DDI_DMA_CONSISTENT, 463 DDI_DMA_SLEEP, 464 0, 465 (caddr_t *)&ehcip->ehci_qh_pool_addr, 466 &real_length, 467 &ehcip->ehci_qh_pool_mem_handle) != DDI_SUCCESS) { 468 469 goto failure; 470 } 471 472 result = ddi_dma_addr_bind_handle(ehcip->ehci_qh_pool_dma_handle, 473 NULL, 474 (caddr_t)ehcip->ehci_qh_pool_addr, 475 real_length, 476 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 477 DDI_DMA_SLEEP, 478 NULL, 479 &ehcip->ehci_qh_pool_cookie, 480 &ccount); 481 482 bzero((void *)ehcip->ehci_qh_pool_addr, 483 ehci_qh_pool_size * sizeof (ehci_qh_t)); 484 485 /* Process the result */ 486 if (result == DDI_DMA_MAPPED) { 487 /* The cookie count should be 1 */ 488 if (ccount != 1) { 489 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 490 "ehci_allocate_pools: More than 1 cookie"); 491 492 goto failure; 493 } 494 } else { 495 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 496 497 goto failure; 498 } 499 500 /* 501 * DMA addresses for QH pools are bound 502 */ 503 ehcip->ehci_dma_addr_bind_flag |= EHCI_QH_POOL_BOUND; 504 505 /* Initialize the QH pool */ 506 for (i = 0; i < ehci_qh_pool_size; i ++) { 507 Set_QH(ehcip->ehci_qh_pool_addr[i].qh_state, EHCI_QH_FREE); 508 } 509 510 /* Byte alignment */ 511 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 512 513 return (DDI_SUCCESS); 514 515 failure: 516 /* Byte alignment */ 517 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 518 519 return (DDI_FAILURE); 520 } 521 522 523 /* 524 * ehci_decode_ddi_dma_addr_bind_handle_result: 525 * 526 * Process the return values of ddi_dma_addr_bind_handle() 527 */ 528 void 529 ehci_decode_ddi_dma_addr_bind_handle_result( 530 ehci_state_t *ehcip, 531 int result) 532 { 533 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ehcip->ehci_log_hdl, 534 "ehci_decode_ddi_dma_addr_bind_handle_result:"); 535 536 switch (result) { 537 case DDI_DMA_PARTIAL_MAP: 538 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 539 "Partial transfers not allowed"); 540 break; 541 case DDI_DMA_INUSE: 542 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 543 "Handle is in use"); 544 break; 545 case DDI_DMA_NORESOURCES: 546 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 547 "No resources"); 548 break; 549 case DDI_DMA_NOMAPPING: 550 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 551 "No mapping"); 552 break; 553 case DDI_DMA_TOOBIG: 554 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 555 "Object is too big"); 556 break; 557 default: 558 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 559 "Unknown dma error"); 560 } 561 } 562 563 564 /* 565 * ehci_map_regs: 566 * 567 * The Host Controller (HC) contains a set of on-chip operational registers 568 * and which should be mapped into a non-cacheable portion of the system 569 * addressable space. 570 */ 571 int 572 ehci_map_regs(ehci_state_t *ehcip) 573 { 574 ddi_device_acc_attr_t attr; 575 uint16_t cmd_reg; 576 uint_t length; 577 578 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_map_regs:"); 579 580 /* Check to make sure we have memory access */ 581 if (pci_config_setup(ehcip->ehci_dip, 582 &ehcip->ehci_config_handle) != DDI_SUCCESS) { 583 584 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 585 "ehci_map_regs: Config error"); 586 587 return (DDI_FAILURE); 588 } 589 590 /* Make sure Memory Access Enable is set */ 591 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 592 593 if (!(cmd_reg & PCI_COMM_MAE)) { 594 595 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 596 "ehci_map_regs: Memory base address access disabled"); 597 598 return (DDI_FAILURE); 599 } 600 601 /* The host controller will be little endian */ 602 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 603 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 604 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 605 606 /* Map in EHCI Capability registers */ 607 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 608 (caddr_t *)&ehcip->ehci_capsp, 0, 609 sizeof (ehci_caps_t), &attr, 610 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 611 612 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 613 "ehci_map_regs: Map setup error"); 614 615 return (DDI_FAILURE); 616 } 617 618 length = ddi_get8(ehcip->ehci_caps_handle, 619 (uint8_t *)&ehcip->ehci_capsp->ehci_caps_length); 620 621 /* Free the original mapping */ 622 ddi_regs_map_free(&ehcip->ehci_caps_handle); 623 624 /* Re-map in EHCI Capability and Operational registers */ 625 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 626 (caddr_t *)&ehcip->ehci_capsp, 0, 627 length + sizeof (ehci_regs_t), &attr, 628 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 629 630 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 631 "ehci_map_regs: Map setup error"); 632 633 return (DDI_FAILURE); 634 } 635 636 /* Get the pointer to EHCI Operational Register */ 637 ehcip->ehci_regsp = (ehci_regs_t *) 638 ((uintptr_t)ehcip->ehci_capsp + length); 639 640 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 641 "ehci_map_regs: Capsp 0x%p Regsp 0x%p\n", 642 ehcip->ehci_capsp, ehcip->ehci_regsp); 643 644 return (DDI_SUCCESS); 645 } 646 647 /* 648 * The following simulated polling is for debugging purposes only. 649 * It is activated on x86 by setting usb-polling=true in GRUB or ehci.conf. 650 */ 651 static int 652 ehci_is_polled(dev_info_t *dip) 653 { 654 int ret; 655 char *propval; 656 657 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 658 "usb-polling", &propval) != DDI_SUCCESS) 659 660 return (0); 661 662 ret = (strcmp(propval, "true") == 0); 663 ddi_prop_free(propval); 664 665 return (ret); 666 } 667 668 static void 669 ehci_poll_intr(void *arg) 670 { 671 /* poll every msec */ 672 for (;;) { 673 (void) ehci_intr(arg, NULL); 674 delay(drv_usectohz(1000)); 675 } 676 } 677 678 /* 679 * ehci_register_intrs_and_init_mutex: 680 * 681 * Register interrupts and initialize each mutex and condition variables 682 */ 683 int 684 ehci_register_intrs_and_init_mutex(ehci_state_t *ehcip) 685 { 686 int intr_types; 687 688 #if defined(__x86) 689 uint8_t iline; 690 #endif 691 692 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 693 "ehci_register_intrs_and_init_mutex:"); 694 695 /* 696 * There is a known MSI hardware bug with the EHCI controller 697 * of ULI1575 southbridge. Hence MSI is disabled for this chip. 698 */ 699 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 700 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) { 701 ehcip->ehci_msi_enabled = B_FALSE; 702 } else { 703 /* Set the MSI enable flag from the global EHCI MSI tunable */ 704 ehcip->ehci_msi_enabled = ehci_enable_msi; 705 } 706 707 /* launch polling thread instead of enabling pci interrupt */ 708 if (ehci_is_polled(ehcip->ehci_dip)) { 709 extern pri_t maxclsyspri; 710 711 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 712 "ehci_register_intrs_and_init_mutex: " 713 "running in simulated polled mode"); 714 715 (void) thread_create(NULL, 0, ehci_poll_intr, ehcip, 0, &p0, 716 TS_RUN, maxclsyspri); 717 718 goto skip_intr; 719 } 720 721 #if defined(__x86) 722 /* 723 * Make sure that the interrupt pin is connected to the 724 * interrupt controller on x86. Interrupt line 255 means 725 * "unknown" or "not connected" (PCI spec 6.2.4, footnote 43). 726 * If we would return failure when interrupt line equals 255, then 727 * high speed devices will be routed to companion host controllers. 728 * However, it is not necessary to return failure here, and 729 * o/uhci codes don't check the interrupt line either. 730 * But it's good to log a message here for debug purposes. 731 */ 732 iline = pci_config_get8(ehcip->ehci_config_handle, 733 PCI_CONF_ILINE); 734 735 if (iline == 255) { 736 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 737 "ehci_register_intrs_and_init_mutex: " 738 "interrupt line value out of range (%d)", 739 iline); 740 } 741 #endif /* __x86 */ 742 743 /* Get supported interrupt types */ 744 if (ddi_intr_get_supported_types(ehcip->ehci_dip, 745 &intr_types) != DDI_SUCCESS) { 746 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 747 "ehci_register_intrs_and_init_mutex: " 748 "ddi_intr_get_supported_types failed"); 749 750 return (DDI_FAILURE); 751 } 752 753 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 754 "ehci_register_intrs_and_init_mutex: " 755 "supported interrupt types 0x%x", intr_types); 756 757 if ((intr_types & DDI_INTR_TYPE_MSI) && ehcip->ehci_msi_enabled) { 758 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_MSI) 759 != DDI_SUCCESS) { 760 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 761 "ehci_register_intrs_and_init_mutex: MSI " 762 "registration failed, trying FIXED interrupt \n"); 763 } else { 764 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 765 "ehci_register_intrs_and_init_mutex: " 766 "Using MSI interrupt type\n"); 767 768 ehcip->ehci_intr_type = DDI_INTR_TYPE_MSI; 769 ehcip->ehci_flags |= EHCI_INTR; 770 } 771 } 772 773 if ((!(ehcip->ehci_flags & EHCI_INTR)) && 774 (intr_types & DDI_INTR_TYPE_FIXED)) { 775 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_FIXED) 776 != DDI_SUCCESS) { 777 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 778 "ehci_register_intrs_and_init_mutex: " 779 "FIXED interrupt registration failed\n"); 780 781 return (DDI_FAILURE); 782 } 783 784 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 785 "ehci_register_intrs_and_init_mutex: " 786 "Using FIXED interrupt type\n"); 787 788 ehcip->ehci_intr_type = DDI_INTR_TYPE_FIXED; 789 ehcip->ehci_flags |= EHCI_INTR; 790 } 791 792 skip_intr: 793 /* Create prototype for advance on async schedule */ 794 cv_init(&ehcip->ehci_async_schedule_advance_cv, 795 NULL, CV_DRIVER, NULL); 796 797 return (DDI_SUCCESS); 798 } 799 800 801 /* 802 * ehci_add_intrs: 803 * 804 * Register FIXED or MSI interrupts. 805 */ 806 static int 807 ehci_add_intrs(ehci_state_t *ehcip, 808 int intr_type) 809 { 810 int actual, avail, intr_size, count = 0; 811 int i, flag, ret; 812 813 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 814 "ehci_add_intrs: interrupt type 0x%x", intr_type); 815 816 /* Get number of interrupts */ 817 ret = ddi_intr_get_nintrs(ehcip->ehci_dip, intr_type, &count); 818 if ((ret != DDI_SUCCESS) || (count == 0)) { 819 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 820 "ehci_add_intrs: ddi_intr_get_nintrs() failure, " 821 "ret: %d, count: %d", ret, count); 822 823 return (DDI_FAILURE); 824 } 825 826 /* Get number of available interrupts */ 827 ret = ddi_intr_get_navail(ehcip->ehci_dip, intr_type, &avail); 828 if ((ret != DDI_SUCCESS) || (avail == 0)) { 829 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 830 "ehci_add_intrs: ddi_intr_get_navail() failure, " 831 "ret: %d, count: %d", ret, count); 832 833 return (DDI_FAILURE); 834 } 835 836 if (avail < count) { 837 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 838 "ehci_add_intrs: ehci_add_intrs: nintrs () " 839 "returned %d, navail returned %d\n", count, avail); 840 } 841 842 /* Allocate an array of interrupt handles */ 843 intr_size = count * sizeof (ddi_intr_handle_t); 844 ehcip->ehci_htable = kmem_zalloc(intr_size, KM_SLEEP); 845 846 flag = (intr_type == DDI_INTR_TYPE_MSI) ? 847 DDI_INTR_ALLOC_STRICT:DDI_INTR_ALLOC_NORMAL; 848 849 /* call ddi_intr_alloc() */ 850 ret = ddi_intr_alloc(ehcip->ehci_dip, ehcip->ehci_htable, 851 intr_type, 0, count, &actual, flag); 852 853 if ((ret != DDI_SUCCESS) || (actual == 0)) { 854 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 855 "ehci_add_intrs: ddi_intr_alloc() failed %d", ret); 856 857 kmem_free(ehcip->ehci_htable, intr_size); 858 859 return (DDI_FAILURE); 860 } 861 862 if (actual < count) { 863 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 864 "ehci_add_intrs: Requested: %d, Received: %d\n", 865 count, actual); 866 867 for (i = 0; i < actual; i++) 868 (void) ddi_intr_free(ehcip->ehci_htable[i]); 869 870 kmem_free(ehcip->ehci_htable, intr_size); 871 872 return (DDI_FAILURE); 873 } 874 875 ehcip->ehci_intr_cnt = actual; 876 877 if ((ret = ddi_intr_get_pri(ehcip->ehci_htable[0], 878 &ehcip->ehci_intr_pri)) != DDI_SUCCESS) { 879 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 880 "ehci_add_intrs: ddi_intr_get_pri() failed %d", ret); 881 882 for (i = 0; i < actual; i++) 883 (void) ddi_intr_free(ehcip->ehci_htable[i]); 884 885 kmem_free(ehcip->ehci_htable, intr_size); 886 887 return (DDI_FAILURE); 888 } 889 890 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 891 "ehci_add_intrs: Supported Interrupt priority 0x%x", 892 ehcip->ehci_intr_pri); 893 894 /* Test for high level mutex */ 895 if (ehcip->ehci_intr_pri >= ddi_intr_get_hilevel_pri()) { 896 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 897 "ehci_add_intrs: Hi level interrupt not supported"); 898 899 for (i = 0; i < actual; i++) 900 (void) ddi_intr_free(ehcip->ehci_htable[i]); 901 902 kmem_free(ehcip->ehci_htable, intr_size); 903 904 return (DDI_FAILURE); 905 } 906 907 /* Initialize the mutex */ 908 mutex_init(&ehcip->ehci_int_mutex, NULL, MUTEX_DRIVER, 909 DDI_INTR_PRI(ehcip->ehci_intr_pri)); 910 911 /* Call ddi_intr_add_handler() */ 912 for (i = 0; i < actual; i++) { 913 if ((ret = ddi_intr_add_handler(ehcip->ehci_htable[i], 914 ehci_intr, (caddr_t)ehcip, 915 (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 916 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 917 "ehci_add_intrs:ddi_intr_add_handler() " 918 "failed %d", ret); 919 920 for (i = 0; i < actual; i++) 921 (void) ddi_intr_free(ehcip->ehci_htable[i]); 922 923 mutex_destroy(&ehcip->ehci_int_mutex); 924 kmem_free(ehcip->ehci_htable, intr_size); 925 926 return (DDI_FAILURE); 927 } 928 } 929 930 if ((ret = ddi_intr_get_cap(ehcip->ehci_htable[0], 931 &ehcip->ehci_intr_cap)) != DDI_SUCCESS) { 932 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 933 "ehci_add_intrs: ddi_intr_get_cap() failed %d", ret); 934 935 for (i = 0; i < actual; i++) { 936 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 937 (void) ddi_intr_free(ehcip->ehci_htable[i]); 938 } 939 940 mutex_destroy(&ehcip->ehci_int_mutex); 941 kmem_free(ehcip->ehci_htable, intr_size); 942 943 return (DDI_FAILURE); 944 } 945 946 /* Enable all interrupts */ 947 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 948 /* Call ddi_intr_block_enable() for MSI interrupts */ 949 (void) ddi_intr_block_enable(ehcip->ehci_htable, 950 ehcip->ehci_intr_cnt); 951 } else { 952 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 953 for (i = 0; i < ehcip->ehci_intr_cnt; i++) 954 (void) ddi_intr_enable(ehcip->ehci_htable[i]); 955 } 956 957 return (DDI_SUCCESS); 958 } 959 960 961 /* 962 * ehci_init_hardware 963 * 964 * take control from BIOS, reset EHCI host controller, and check version, etc. 965 */ 966 int 967 ehci_init_hardware(ehci_state_t *ehcip) 968 { 969 int revision; 970 uint16_t cmd_reg; 971 int abort_on_BIOS_take_over_failure; 972 973 /* Take control from the BIOS */ 974 if (ehci_take_control(ehcip) != USB_SUCCESS) { 975 976 /* read .conf file properties */ 977 abort_on_BIOS_take_over_failure = 978 ddi_prop_get_int(DDI_DEV_T_ANY, 979 ehcip->ehci_dip, DDI_PROP_DONTPASS, 980 "abort-on-BIOS-take-over-failure", 0); 981 982 if (abort_on_BIOS_take_over_failure) { 983 984 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 985 "Unable to take control from BIOS."); 986 987 return (DDI_FAILURE); 988 } 989 990 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 991 "Unable to take control from BIOS. Failure is ignored."); 992 } 993 994 /* set Memory Master Enable */ 995 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 996 cmd_reg |= (PCI_COMM_MAE | PCI_COMM_ME); 997 pci_config_put16(ehcip->ehci_config_handle, PCI_CONF_COMM, cmd_reg); 998 999 /* Reset the EHCI host controller */ 1000 Set_OpReg(ehci_command, 1001 Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET); 1002 1003 /* Wait 10ms for reset to complete */ 1004 drv_usecwait(EHCI_RESET_TIMEWAIT); 1005 1006 ASSERT(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED); 1007 1008 /* Verify the version number */ 1009 revision = Get_16Cap(ehci_version); 1010 1011 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1012 "ehci_init_hardware: Revision 0x%x", revision); 1013 1014 /* 1015 * EHCI driver supports EHCI host controllers compliant to 1016 * 0.95 and higher revisions of EHCI specifications. 1017 */ 1018 if (revision < EHCI_REVISION_0_95) { 1019 1020 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1021 "Revision 0x%x is not supported", revision); 1022 1023 return (DDI_FAILURE); 1024 } 1025 1026 if (ehcip->ehci_hc_soft_state == EHCI_CTLR_INIT_STATE) { 1027 1028 /* Initialize the Frame list base address area */ 1029 if (ehci_init_periodic_frame_lst_table(ehcip) != DDI_SUCCESS) { 1030 1031 return (DDI_FAILURE); 1032 } 1033 1034 /* 1035 * For performance reasons, do not insert anything into the 1036 * asynchronous list or activate the asynch list schedule until 1037 * there is a valid QH. 1038 */ 1039 ehcip->ehci_head_of_async_sched_list = NULL; 1040 1041 if ((ehcip->ehci_vendor_id == PCI_VENDOR_VIA) && 1042 (ehci_vt62x2_workaround & EHCI_VIA_ASYNC_SCHEDULE)) { 1043 /* 1044 * The driver is unable to reliably stop the asynch 1045 * list schedule on VIA VT6202 controllers, so we 1046 * always keep a dummy QH on the list. 1047 */ 1048 ehci_qh_t *dummy_async_qh = 1049 ehci_alloc_qh(ehcip, NULL, NULL); 1050 1051 Set_QH(dummy_async_qh->qh_link_ptr, 1052 ((ehci_qh_cpu_to_iommu(ehcip, dummy_async_qh) & 1053 EHCI_QH_LINK_PTR) | EHCI_QH_LINK_REF_QH)); 1054 1055 /* Set this QH to be the "head" of the circular list */ 1056 Set_QH(dummy_async_qh->qh_ctrl, 1057 Get_QH(dummy_async_qh->qh_ctrl) | 1058 EHCI_QH_CTRL_RECLAIM_HEAD); 1059 1060 Set_QH(dummy_async_qh->qh_next_qtd, 1061 EHCI_QH_NEXT_QTD_PTR_VALID); 1062 Set_QH(dummy_async_qh->qh_alt_next_qtd, 1063 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1064 1065 ehcip->ehci_head_of_async_sched_list = dummy_async_qh; 1066 ehcip->ehci_open_async_count++; 1067 } 1068 } 1069 1070 return (DDI_SUCCESS); 1071 } 1072 1073 1074 /* 1075 * ehci_init_workaround 1076 * 1077 * some workarounds during initializing ehci 1078 */ 1079 int 1080 ehci_init_workaround(ehci_state_t *ehcip) 1081 { 1082 /* 1083 * Acer Labs Inc. M5273 EHCI controller does not send 1084 * interrupts unless the Root hub ports are routed to the EHCI 1085 * host controller; so route the ports now, before we test for 1086 * the presence of SOFs interrupts. 1087 */ 1088 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1089 /* Route all Root hub ports to EHCI host controller */ 1090 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1091 } 1092 1093 /* 1094 * VIA chips have some issues and may not work reliably. 1095 * Revisions >= 0x80 are part of a southbridge and appear 1096 * to be reliable with the workaround. 1097 * For revisions < 0x80, if we were bound using class 1098 * complain, else proceed. This will allow the user to 1099 * bind ehci specifically to this chip and not have the 1100 * warnings 1101 */ 1102 if (ehcip->ehci_vendor_id == PCI_VENDOR_VIA) { 1103 1104 if (ehcip->ehci_rev_id >= PCI_VIA_REVISION_6212) { 1105 1106 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1107 "ehci_init_workaround: Applying VIA workarounds " 1108 "for the 6212 chip."); 1109 1110 } else if (strcmp(DEVI(ehcip->ehci_dip)->devi_binding_name, 1111 "pciclass,0c0320") == 0) { 1112 1113 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1114 "Due to recently discovered incompatibilities"); 1115 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1116 "with this USB controller, USB2.x transfer"); 1117 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1118 "support has been disabled. This device will"); 1119 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1120 "continue to function as a USB1.x controller."); 1121 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1122 "If you are interested in enabling USB2.x"); 1123 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1124 "support please, refer to the ehci(7D) man page."); 1125 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1126 "Please also refer to www.sun.com/io for"); 1127 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1128 "Solaris Ready products and to"); 1129 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1130 "www.sun.com/bigadmin/hcl for additional"); 1131 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1132 "compatible USB products."); 1133 1134 return (DDI_FAILURE); 1135 1136 } else if (ehci_vt62x2_workaround) { 1137 1138 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1139 "Applying VIA workarounds"); 1140 } 1141 } 1142 1143 return (DDI_SUCCESS); 1144 } 1145 1146 1147 /* 1148 * ehci_init_check_status 1149 * 1150 * Check if EHCI host controller is running 1151 */ 1152 int 1153 ehci_init_check_status(ehci_state_t *ehcip) 1154 { 1155 clock_t sof_time_wait; 1156 1157 /* 1158 * Get the number of clock ticks to wait. 1159 * This is based on the maximum time it takes for a frame list rollover 1160 * and maximum time wait for SOFs to begin. 1161 */ 1162 sof_time_wait = drv_usectohz((EHCI_NUM_PERIODIC_FRAME_LISTS * 1000) + 1163 EHCI_SOF_TIMEWAIT); 1164 1165 /* Tell the ISR to broadcast ehci_async_schedule_advance_cv */ 1166 ehcip->ehci_flags |= EHCI_CV_INTR; 1167 1168 /* We need to add a delay to allow the chip time to start running */ 1169 (void) cv_timedwait(&ehcip->ehci_async_schedule_advance_cv, 1170 &ehcip->ehci_int_mutex, ddi_get_lbolt() + sof_time_wait); 1171 1172 /* 1173 * Check EHCI host controller is running, otherwise return failure. 1174 */ 1175 if ((ehcip->ehci_flags & EHCI_CV_INTR) || 1176 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 1177 1178 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1179 "No SOF interrupts have been received, this USB EHCI host" 1180 "controller is unusable"); 1181 1182 /* 1183 * Route all Root hub ports to Classic host 1184 * controller, in case this is an unusable ALI M5273 1185 * EHCI controller. 1186 */ 1187 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1188 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1189 } 1190 1191 return (DDI_FAILURE); 1192 } 1193 1194 return (DDI_SUCCESS); 1195 } 1196 1197 1198 /* 1199 * ehci_init_ctlr: 1200 * 1201 * Initialize the Host Controller (HC). 1202 */ 1203 int 1204 ehci_init_ctlr(ehci_state_t *ehcip, 1205 int init_type) 1206 { 1207 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_init_ctlr:"); 1208 1209 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1210 1211 if (ehci_init_hardware(ehcip) != DDI_SUCCESS) { 1212 1213 return (DDI_FAILURE); 1214 } 1215 } 1216 1217 /* 1218 * Check for Asynchronous schedule park capability feature. If this 1219 * feature is supported, then, program ehci command register with 1220 * appropriate values.. 1221 */ 1222 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_ASYNC_SCHED_PARK_CAP) { 1223 1224 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1225 "ehci_init_ctlr: Async park mode is supported"); 1226 1227 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1228 (EHCI_CMD_ASYNC_PARK_ENABLE | 1229 EHCI_CMD_ASYNC_PARK_COUNT_3))); 1230 } 1231 1232 /* 1233 * Check for programmable periodic frame list feature. If this 1234 * feature is supported, then, program ehci command register with 1235 * 1024 frame list value. 1236 */ 1237 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_PROG_FRAME_LIST_FLAG) { 1238 1239 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1240 "ehci_init_ctlr: Variable programmable periodic " 1241 "frame list is supported"); 1242 1243 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1244 EHCI_CMD_FRAME_1024_SIZE)); 1245 } 1246 1247 /* 1248 * Currently EHCI driver doesn't support 64 bit addressing. 1249 * 1250 * If we are using 64 bit addressing capability, then, program 1251 * ehci_ctrl_segment register with 4 Gigabyte segment where all 1252 * of the interface data structures are allocated. 1253 */ 1254 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_64BIT_ADDR_CAP) { 1255 1256 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1257 "ehci_init_ctlr: EHCI driver doesn't support " 1258 "64 bit addressing"); 1259 } 1260 1261 /* 64 bit addressing is not support */ 1262 Set_OpReg(ehci_ctrl_segment, 0x00000000); 1263 1264 /* Turn on/off the schedulers */ 1265 ehci_toggle_scheduler(ehcip); 1266 1267 /* 1268 * Set the Periodic Frame List Base Address register with the 1269 * starting physical address of the Periodic Frame List. 1270 */ 1271 Set_OpReg(ehci_periodic_list_base, 1272 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 1273 EHCI_PERIODIC_LIST_BASE)); 1274 1275 /* 1276 * Set ehci_interrupt to enable all interrupts except Root 1277 * Hub Status change interrupt. 1278 */ 1279 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 1280 EHCI_INTR_FRAME_LIST_ROLLOVER | EHCI_INTR_USB_ERROR | 1281 EHCI_INTR_USB); 1282 1283 /* 1284 * Set the desired interrupt threshold and turn on EHCI host controller. 1285 */ 1286 Set_OpReg(ehci_command, 1287 ((Get_OpReg(ehci_command) & ~EHCI_CMD_INTR_THRESHOLD) | 1288 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 1289 1290 ASSERT(Get_OpReg(ehci_command) & EHCI_CMD_HOST_CTRL_RUN); 1291 1292 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1293 1294 if (ehci_init_workaround(ehcip) != DDI_SUCCESS) { 1295 1296 return (DDI_FAILURE); 1297 } 1298 1299 if (ehci_init_check_status(ehcip) != DDI_SUCCESS) { 1300 1301 return (DDI_FAILURE); 1302 } 1303 1304 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1305 "ehci_init_ctlr: SOF's have started"); 1306 } 1307 1308 /* Route all Root hub ports to EHCI host controller */ 1309 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1310 1311 /* Set host controller soft state to operational */ 1312 ehcip->ehci_hc_soft_state = EHCI_CTLR_OPERATIONAL_STATE; 1313 1314 return (DDI_SUCCESS); 1315 } 1316 1317 /* 1318 * ehci_take_control: 1319 * 1320 * Handshake to take EHCI control from BIOS if necessary. Its only valid for 1321 * x86 machines, because sparc doesn't have a BIOS. 1322 * On x86 machine, the take control process includes 1323 * o get the base address of the extended capability list 1324 * o find out the capability for handoff synchronization in the list. 1325 * o check if BIOS has owned the host controller. 1326 * o set the OS Owned semaphore bit, ask the BIOS to release the ownership. 1327 * o wait for a constant time and check if BIOS has relinquished control. 1328 */ 1329 /* ARGSUSED */ 1330 static int 1331 ehci_take_control(ehci_state_t *ehcip) 1332 { 1333 #if defined(__x86) 1334 uint32_t extended_cap; 1335 uint32_t extended_cap_offset; 1336 uint32_t extended_cap_id; 1337 uint_t retry; 1338 1339 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1340 "ehci_take_control:"); 1341 1342 /* 1343 * According EHCI Spec 2.2.4, get EECP base address from HCCPARAMS 1344 * register. 1345 */ 1346 extended_cap_offset = (Get_Cap(ehci_hcc_params) & EHCI_HCC_EECP) >> 1347 EHCI_HCC_EECP_SHIFT; 1348 1349 /* 1350 * According EHCI Spec 2.2.4, if the extended capability offset is 1351 * less than 40h then its not valid. This means we don't need to 1352 * worry about BIOS handoff. 1353 */ 1354 if (extended_cap_offset < EHCI_HCC_EECP_MIN_OFFSET) { 1355 1356 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1357 "ehci_take_control: Hardware doesn't support legacy."); 1358 1359 goto success; 1360 } 1361 1362 /* 1363 * According EHCI Spec 2.1.7, A zero offset indicates the 1364 * end of the extended capability list. 1365 */ 1366 while (extended_cap_offset) { 1367 1368 /* Get the extended capability value. */ 1369 extended_cap = pci_config_get32(ehcip->ehci_config_handle, 1370 extended_cap_offset); 1371 1372 /* Get the capability ID */ 1373 extended_cap_id = (extended_cap & EHCI_EX_CAP_ID) >> 1374 EHCI_EX_CAP_ID_SHIFT; 1375 1376 /* Check if the card support legacy */ 1377 if (extended_cap_id == EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1378 break; 1379 } 1380 1381 /* Get the offset of the next capability */ 1382 extended_cap_offset = (extended_cap & EHCI_EX_CAP_NEXT_PTR) >> 1383 EHCI_EX_CAP_NEXT_PTR_SHIFT; 1384 } 1385 1386 /* 1387 * Unable to find legacy support in hardware's extended capability list. 1388 * This means we don't need to worry about BIOS handoff. 1389 */ 1390 if (extended_cap_id != EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1391 1392 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1393 "ehci_take_control: Hardware doesn't support legacy"); 1394 1395 goto success; 1396 } 1397 1398 /* Check if BIOS has owned it. */ 1399 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1400 1401 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1402 "ehci_take_control: BIOS does not own EHCI"); 1403 1404 goto success; 1405 } 1406 1407 /* 1408 * According EHCI Spec 5.1, The OS driver initiates an ownership 1409 * request by setting the OS Owned semaphore to a one. The OS 1410 * waits for the BIOS Owned bit to go to a zero before attempting 1411 * to use the EHCI controller. The time that OS must wait for BIOS 1412 * to respond to the request for ownership is beyond the scope of 1413 * this specification. 1414 * It waits up to EHCI_TAKEOVER_WAIT_COUNT*EHCI_TAKEOVER_DELAY ms 1415 * for BIOS to release the ownership. 1416 */ 1417 extended_cap |= EHCI_LEGSUP_OS_OWNED_SEM; 1418 pci_config_put32(ehcip->ehci_config_handle, extended_cap_offset, 1419 extended_cap); 1420 1421 for (retry = 0; retry < EHCI_TAKEOVER_WAIT_COUNT; retry++) { 1422 1423 /* wait a special interval */ 1424 #ifndef __lock_lint 1425 delay(drv_usectohz(EHCI_TAKEOVER_DELAY)); 1426 #endif 1427 /* Check to see if the BIOS has released the ownership */ 1428 extended_cap = pci_config_get32( 1429 ehcip->ehci_config_handle, extended_cap_offset); 1430 1431 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1432 1433 USB_DPRINTF_L3(PRINT_MASK_ATTA, 1434 ehcip->ehci_log_hdl, 1435 "ehci_take_control: BIOS has released " 1436 "the ownership. retry = %d", retry); 1437 1438 goto success; 1439 } 1440 1441 } 1442 1443 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1444 "ehci_take_control: take control from BIOS failed."); 1445 1446 return (USB_FAILURE); 1447 1448 success: 1449 1450 #endif /* __x86 */ 1451 return (USB_SUCCESS); 1452 } 1453 1454 1455 /* 1456 * ehci_init_periodic_frame_list_table : 1457 * 1458 * Allocate the system memory and initialize Host Controller 1459 * Periodic Frame List table area. The starting of the Periodic 1460 * Frame List Table area must be 4096 byte aligned. 1461 */ 1462 static int 1463 ehci_init_periodic_frame_lst_table(ehci_state_t *ehcip) 1464 { 1465 ddi_device_acc_attr_t dev_attr; 1466 size_t real_length; 1467 uint_t ccount; 1468 int result; 1469 1470 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1471 1472 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1473 "ehci_init_periodic_frame_lst_table:"); 1474 1475 /* The host controller will be little endian */ 1476 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1477 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1478 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1479 1480 /* Force the required 4K restrictive alignment */ 1481 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_PFL_ALIGNMENT; 1482 1483 /* Create space for the Periodic Frame List */ 1484 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 1485 DDI_DMA_SLEEP, 0, &ehcip->ehci_pflt_dma_handle) != DDI_SUCCESS) { 1486 1487 goto failure; 1488 } 1489 1490 if (ddi_dma_mem_alloc(ehcip->ehci_pflt_dma_handle, 1491 sizeof (ehci_periodic_frame_list_t), 1492 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 1493 0, (caddr_t *)&ehcip->ehci_periodic_frame_list_tablep, 1494 &real_length, &ehcip->ehci_pflt_mem_handle)) { 1495 1496 goto failure; 1497 } 1498 1499 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1500 "ehci_init_periodic_frame_lst_table: " 1501 "Real length %lu", real_length); 1502 1503 /* Map the whole Periodic Frame List into the I/O address space */ 1504 result = ddi_dma_addr_bind_handle(ehcip->ehci_pflt_dma_handle, 1505 NULL, (caddr_t)ehcip->ehci_periodic_frame_list_tablep, 1506 real_length, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1507 DDI_DMA_SLEEP, NULL, &ehcip->ehci_pflt_cookie, &ccount); 1508 1509 if (result == DDI_DMA_MAPPED) { 1510 /* The cookie count should be 1 */ 1511 if (ccount != 1) { 1512 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1513 "ehci_init_periodic_frame_lst_table: " 1514 "More than 1 cookie"); 1515 1516 goto failure; 1517 } 1518 } else { 1519 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 1520 1521 goto failure; 1522 } 1523 1524 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1525 "ehci_init_periodic_frame_lst_table: virtual 0x%p physical 0x%x", 1526 (void *)ehcip->ehci_periodic_frame_list_tablep, 1527 ehcip->ehci_pflt_cookie.dmac_address); 1528 1529 /* 1530 * DMA addresses for Periodic Frame List are bound. 1531 */ 1532 ehcip->ehci_dma_addr_bind_flag |= EHCI_PFLT_DMA_BOUND; 1533 1534 bzero((void *)ehcip->ehci_periodic_frame_list_tablep, real_length); 1535 1536 /* Initialize the Periodic Frame List */ 1537 ehci_build_interrupt_lattice(ehcip); 1538 1539 /* Reset Byte Alignment to Default */ 1540 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1541 1542 return (DDI_SUCCESS); 1543 failure: 1544 /* Byte alignment */ 1545 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1546 1547 return (DDI_FAILURE); 1548 } 1549 1550 1551 /* 1552 * ehci_build_interrupt_lattice: 1553 * 1554 * Construct the interrupt lattice tree using static Endpoint Descriptors 1555 * (QH). This interrupt lattice tree will have total of 32 interrupt QH 1556 * lists and the Host Controller (HC) processes one interrupt QH list in 1557 * every frame. The Host Controller traverses the periodic schedule by 1558 * constructing an array offset reference from the Periodic List Base Address 1559 * register and bits 12 to 3 of Frame Index register. It fetches the element 1560 * and begins traversing the graph of linked schedule data structures. 1561 */ 1562 static void 1563 ehci_build_interrupt_lattice(ehci_state_t *ehcip) 1564 { 1565 ehci_qh_t *list_array = ehcip->ehci_qh_pool_addr; 1566 ushort_t ehci_index[EHCI_NUM_PERIODIC_FRAME_LISTS]; 1567 ehci_periodic_frame_list_t *periodic_frame_list = 1568 ehcip->ehci_periodic_frame_list_tablep; 1569 ushort_t *temp, num_of_nodes; 1570 uintptr_t addr; 1571 int i, j, k; 1572 1573 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1574 "ehci_build_interrupt_lattice:"); 1575 1576 /* 1577 * Reserve the first 63 Endpoint Descriptor (QH) structures 1578 * in the pool as static endpoints & these are required for 1579 * constructing interrupt lattice tree. 1580 */ 1581 for (i = 0; i < EHCI_NUM_STATIC_NODES; i++) { 1582 Set_QH(list_array[i].qh_state, EHCI_QH_STATIC); 1583 Set_QH(list_array[i].qh_status, EHCI_QH_STS_HALTED); 1584 Set_QH(list_array[i].qh_next_qtd, EHCI_QH_NEXT_QTD_PTR_VALID); 1585 Set_QH(list_array[i].qh_alt_next_qtd, 1586 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1587 } 1588 1589 /* 1590 * Make sure that last Endpoint on the periodic frame list terminates 1591 * periodic schedule. 1592 */ 1593 Set_QH(list_array[0].qh_link_ptr, EHCI_QH_LINK_PTR_VALID); 1594 1595 /* Build the interrupt lattice tree */ 1596 for (i = 0; i < (EHCI_NUM_STATIC_NODES / 2); i++) { 1597 /* 1598 * The next pointer in the host controller endpoint 1599 * descriptor must contain an iommu address. Calculate 1600 * the offset into the cpu address and add this to the 1601 * starting iommu address. 1602 */ 1603 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *)&list_array[i]); 1604 1605 Set_QH(list_array[2*i + 1].qh_link_ptr, 1606 addr | EHCI_QH_LINK_REF_QH); 1607 Set_QH(list_array[2*i + 2].qh_link_ptr, 1608 addr | EHCI_QH_LINK_REF_QH); 1609 } 1610 1611 /* Build the tree bottom */ 1612 temp = (unsigned short *) 1613 kmem_zalloc(EHCI_NUM_PERIODIC_FRAME_LISTS * 2, KM_SLEEP); 1614 1615 num_of_nodes = 1; 1616 1617 /* 1618 * Initialize the values which are used for setting up head pointers 1619 * for the 32ms scheduling lists which starts from the Periodic Frame 1620 * List. 1621 */ 1622 for (i = 0; i < ehci_log_2(EHCI_NUM_PERIODIC_FRAME_LISTS); i++) { 1623 for (j = 0, k = 0; k < num_of_nodes; k++, j++) { 1624 ehci_index[j++] = temp[k]; 1625 ehci_index[j] = temp[k] + ehci_pow_2(i); 1626 } 1627 1628 num_of_nodes *= 2; 1629 for (k = 0; k < num_of_nodes; k++) 1630 temp[k] = ehci_index[k]; 1631 } 1632 1633 kmem_free((void *)temp, (EHCI_NUM_PERIODIC_FRAME_LISTS * 2)); 1634 1635 /* 1636 * Initialize the interrupt list in the Periodic Frame List Table 1637 * so that it points to the bottom of the tree. 1638 */ 1639 for (i = 0, j = 0; i < ehci_pow_2(TREE_HEIGHT); i++) { 1640 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *) 1641 (&list_array[((EHCI_NUM_STATIC_NODES + 1) / 2) + i - 1])); 1642 1643 ASSERT(addr); 1644 1645 for (k = 0; k < ehci_pow_2(TREE_HEIGHT); k++) { 1646 Set_PFLT(periodic_frame_list-> 1647 ehci_periodic_frame_list_table[ehci_index[j++]], 1648 (uint32_t)(addr | EHCI_QH_LINK_REF_QH)); 1649 } 1650 } 1651 } 1652 1653 1654 /* 1655 * ehci_alloc_hcdi_ops: 1656 * 1657 * The HCDI interfaces or entry points are the software interfaces used by 1658 * the Universal Serial Bus Driver (USBA) to access the services of the 1659 * Host Controller Driver (HCD). During HCD initialization, inform USBA 1660 * about all available HCDI interfaces or entry points. 1661 */ 1662 usba_hcdi_ops_t * 1663 ehci_alloc_hcdi_ops(ehci_state_t *ehcip) 1664 { 1665 usba_hcdi_ops_t *usba_hcdi_ops; 1666 1667 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1668 "ehci_alloc_hcdi_ops:"); 1669 1670 usba_hcdi_ops = usba_alloc_hcdi_ops(); 1671 1672 usba_hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION; 1673 1674 usba_hcdi_ops->usba_hcdi_pm_support = ehci_hcdi_pm_support; 1675 usba_hcdi_ops->usba_hcdi_pipe_open = ehci_hcdi_pipe_open; 1676 usba_hcdi_ops->usba_hcdi_pipe_close = ehci_hcdi_pipe_close; 1677 1678 usba_hcdi_ops->usba_hcdi_pipe_reset = ehci_hcdi_pipe_reset; 1679 1680 usba_hcdi_ops->usba_hcdi_pipe_ctrl_xfer = ehci_hcdi_pipe_ctrl_xfer; 1681 usba_hcdi_ops->usba_hcdi_pipe_bulk_xfer = ehci_hcdi_pipe_bulk_xfer; 1682 usba_hcdi_ops->usba_hcdi_pipe_intr_xfer = ehci_hcdi_pipe_intr_xfer; 1683 usba_hcdi_ops->usba_hcdi_pipe_isoc_xfer = ehci_hcdi_pipe_isoc_xfer; 1684 1685 usba_hcdi_ops->usba_hcdi_bulk_transfer_size = 1686 ehci_hcdi_bulk_transfer_size; 1687 1688 usba_hcdi_ops->usba_hcdi_pipe_stop_intr_polling = 1689 ehci_hcdi_pipe_stop_intr_polling; 1690 usba_hcdi_ops->usba_hcdi_pipe_stop_isoc_polling = 1691 ehci_hcdi_pipe_stop_isoc_polling; 1692 1693 usba_hcdi_ops->usba_hcdi_get_current_frame_number = 1694 ehci_hcdi_get_current_frame_number; 1695 usba_hcdi_ops->usba_hcdi_get_max_isoc_pkts = 1696 ehci_hcdi_get_max_isoc_pkts; 1697 1698 usba_hcdi_ops->usba_hcdi_console_input_init = 1699 ehci_hcdi_polled_input_init; 1700 usba_hcdi_ops->usba_hcdi_console_input_enter = 1701 ehci_hcdi_polled_input_enter; 1702 usba_hcdi_ops->usba_hcdi_console_read = 1703 ehci_hcdi_polled_read; 1704 usba_hcdi_ops->usba_hcdi_console_input_exit = 1705 ehci_hcdi_polled_input_exit; 1706 usba_hcdi_ops->usba_hcdi_console_input_fini = 1707 ehci_hcdi_polled_input_fini; 1708 return (usba_hcdi_ops); 1709 } 1710 1711 1712 /* 1713 * Host Controller Driver (HCD) deinitialization functions 1714 */ 1715 1716 /* 1717 * ehci_cleanup: 1718 * 1719 * Cleanup on attach failure or detach 1720 */ 1721 int 1722 ehci_cleanup(ehci_state_t *ehcip) 1723 { 1724 ehci_trans_wrapper_t *tw; 1725 ehci_pipe_private_t *pp; 1726 ehci_qtd_t *qtd; 1727 int i, ctrl, rval; 1728 int flags = ehcip->ehci_flags; 1729 1730 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_cleanup:"); 1731 1732 if (flags & EHCI_RHREG) { 1733 /* Unload the root hub driver */ 1734 if (ehci_unload_root_hub_driver(ehcip) != USB_SUCCESS) { 1735 1736 return (DDI_FAILURE); 1737 } 1738 } 1739 1740 if (flags & EHCI_USBAREG) { 1741 /* Unregister this HCD instance with USBA */ 1742 usba_hcdi_unregister(ehcip->ehci_dip); 1743 } 1744 1745 if (flags & EHCI_INTR) { 1746 1747 mutex_enter(&ehcip->ehci_int_mutex); 1748 1749 /* Disable all EHCI QH list processing */ 1750 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1751 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | 1752 EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1753 1754 /* Disable all EHCI interrupts */ 1755 Set_OpReg(ehci_interrupt, 0); 1756 1757 /* wait for the next SOF */ 1758 (void) ehci_wait_for_sof(ehcip); 1759 1760 /* Route all Root hub ports to Classic host controller */ 1761 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1762 1763 /* Stop the EHCI host controller */ 1764 Set_OpReg(ehci_command, 1765 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1766 1767 mutex_exit(&ehcip->ehci_int_mutex); 1768 1769 /* Wait for sometime */ 1770 delay(drv_usectohz(EHCI_TIMEWAIT)); 1771 1772 ehci_rem_intrs(ehcip); 1773 } 1774 1775 /* Unmap the EHCI registers */ 1776 if (ehcip->ehci_caps_handle) { 1777 ddi_regs_map_free(&ehcip->ehci_caps_handle); 1778 } 1779 1780 if (ehcip->ehci_config_handle) { 1781 pci_config_teardown(&ehcip->ehci_config_handle); 1782 } 1783 1784 /* Free all the buffers */ 1785 if (ehcip->ehci_qtd_pool_addr && ehcip->ehci_qtd_pool_mem_handle) { 1786 for (i = 0; i < ehci_qtd_pool_size; i ++) { 1787 qtd = &ehcip->ehci_qtd_pool_addr[i]; 1788 ctrl = Get_QTD(ehcip-> 1789 ehci_qtd_pool_addr[i].qtd_state); 1790 1791 if ((ctrl != EHCI_QTD_FREE) && 1792 (ctrl != EHCI_QTD_DUMMY) && 1793 (qtd->qtd_trans_wrapper)) { 1794 1795 mutex_enter(&ehcip->ehci_int_mutex); 1796 1797 tw = (ehci_trans_wrapper_t *) 1798 EHCI_LOOKUP_ID((uint32_t) 1799 Get_QTD(qtd->qtd_trans_wrapper)); 1800 1801 /* Obtain the pipe private structure */ 1802 pp = tw->tw_pipe_private; 1803 1804 /* Stop the the transfer timer */ 1805 ehci_stop_xfer_timer(ehcip, tw, 1806 EHCI_REMOVE_XFER_ALWAYS); 1807 1808 ehci_deallocate_tw(ehcip, pp, tw); 1809 1810 mutex_exit(&ehcip->ehci_int_mutex); 1811 } 1812 } 1813 1814 /* 1815 * If EHCI_QTD_POOL_BOUND flag is set, then unbind 1816 * the handle for QTD pools. 1817 */ 1818 if ((ehcip->ehci_dma_addr_bind_flag & 1819 EHCI_QTD_POOL_BOUND) == EHCI_QTD_POOL_BOUND) { 1820 1821 rval = ddi_dma_unbind_handle( 1822 ehcip->ehci_qtd_pool_dma_handle); 1823 1824 ASSERT(rval == DDI_SUCCESS); 1825 } 1826 ddi_dma_mem_free(&ehcip->ehci_qtd_pool_mem_handle); 1827 } 1828 1829 /* Free the QTD pool */ 1830 if (ehcip->ehci_qtd_pool_dma_handle) { 1831 ddi_dma_free_handle(&ehcip->ehci_qtd_pool_dma_handle); 1832 } 1833 1834 if (ehcip->ehci_qh_pool_addr && ehcip->ehci_qh_pool_mem_handle) { 1835 /* 1836 * If EHCI_QH_POOL_BOUND flag is set, then unbind 1837 * the handle for QH pools. 1838 */ 1839 if ((ehcip->ehci_dma_addr_bind_flag & 1840 EHCI_QH_POOL_BOUND) == EHCI_QH_POOL_BOUND) { 1841 1842 rval = ddi_dma_unbind_handle( 1843 ehcip->ehci_qh_pool_dma_handle); 1844 1845 ASSERT(rval == DDI_SUCCESS); 1846 } 1847 1848 ddi_dma_mem_free(&ehcip->ehci_qh_pool_mem_handle); 1849 } 1850 1851 /* Free the QH pool */ 1852 if (ehcip->ehci_qh_pool_dma_handle) { 1853 ddi_dma_free_handle(&ehcip->ehci_qh_pool_dma_handle); 1854 } 1855 1856 /* Free the Periodic frame list table (PFLT) area */ 1857 if (ehcip->ehci_periodic_frame_list_tablep && 1858 ehcip->ehci_pflt_mem_handle) { 1859 /* 1860 * If EHCI_PFLT_DMA_BOUND flag is set, then unbind 1861 * the handle for PFLT. 1862 */ 1863 if ((ehcip->ehci_dma_addr_bind_flag & 1864 EHCI_PFLT_DMA_BOUND) == EHCI_PFLT_DMA_BOUND) { 1865 1866 rval = ddi_dma_unbind_handle( 1867 ehcip->ehci_pflt_dma_handle); 1868 1869 ASSERT(rval == DDI_SUCCESS); 1870 } 1871 1872 ddi_dma_mem_free(&ehcip->ehci_pflt_mem_handle); 1873 } 1874 1875 (void) ehci_isoc_cleanup(ehcip); 1876 1877 if (ehcip->ehci_pflt_dma_handle) { 1878 ddi_dma_free_handle(&ehcip->ehci_pflt_dma_handle); 1879 } 1880 1881 if (flags & EHCI_INTR) { 1882 /* Destroy the mutex */ 1883 mutex_destroy(&ehcip->ehci_int_mutex); 1884 1885 /* Destroy the async schedule advance condition variable */ 1886 cv_destroy(&ehcip->ehci_async_schedule_advance_cv); 1887 } 1888 1889 /* clean up kstat structs */ 1890 ehci_destroy_stats(ehcip); 1891 1892 /* Free ehci hcdi ops */ 1893 if (ehcip->ehci_hcdi_ops) { 1894 usba_free_hcdi_ops(ehcip->ehci_hcdi_ops); 1895 } 1896 1897 if (flags & EHCI_ZALLOC) { 1898 1899 usb_free_log_hdl(ehcip->ehci_log_hdl); 1900 1901 /* Remove all properties that might have been created */ 1902 ddi_prop_remove_all(ehcip->ehci_dip); 1903 1904 /* Free the soft state */ 1905 ddi_soft_state_free(ehci_statep, 1906 ddi_get_instance(ehcip->ehci_dip)); 1907 } 1908 1909 return (DDI_SUCCESS); 1910 } 1911 1912 1913 /* 1914 * ehci_rem_intrs: 1915 * 1916 * Unregister FIXED or MSI interrupts 1917 */ 1918 static void 1919 ehci_rem_intrs(ehci_state_t *ehcip) 1920 { 1921 int i; 1922 1923 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1924 "ehci_rem_intrs: interrupt type 0x%x", ehcip->ehci_intr_type); 1925 1926 /* Disable all interrupts */ 1927 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 1928 (void) ddi_intr_block_disable(ehcip->ehci_htable, 1929 ehcip->ehci_intr_cnt); 1930 } else { 1931 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1932 (void) ddi_intr_disable(ehcip->ehci_htable[i]); 1933 } 1934 } 1935 1936 /* Call ddi_intr_remove_handler() */ 1937 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1938 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 1939 (void) ddi_intr_free(ehcip->ehci_htable[i]); 1940 } 1941 1942 kmem_free(ehcip->ehci_htable, 1943 ehcip->ehci_intr_cnt * sizeof (ddi_intr_handle_t)); 1944 } 1945 1946 1947 /* 1948 * ehci_cpr_suspend 1949 */ 1950 int 1951 ehci_cpr_suspend(ehci_state_t *ehcip) 1952 { 1953 int i; 1954 1955 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1956 "ehci_cpr_suspend:"); 1957 1958 /* Call into the root hub and suspend it */ 1959 if (usba_hubdi_detach(ehcip->ehci_dip, DDI_SUSPEND) != DDI_SUCCESS) { 1960 1961 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1962 "ehci_cpr_suspend: root hub fails to suspend"); 1963 1964 return (DDI_FAILURE); 1965 } 1966 1967 /* Only root hub's intr pipe should be open at this time */ 1968 mutex_enter(&ehcip->ehci_int_mutex); 1969 1970 ASSERT(ehcip->ehci_open_pipe_count == 0); 1971 1972 /* Just wait till all resources are reclaimed */ 1973 i = 0; 1974 while ((ehcip->ehci_reclaim_list != NULL) && (i++ < 3)) { 1975 ehci_handle_endpoint_reclaimation(ehcip); 1976 (void) ehci_wait_for_sof(ehcip); 1977 } 1978 ASSERT(ehcip->ehci_reclaim_list == NULL); 1979 1980 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1981 "ehci_cpr_suspend: Disable HC QH list processing"); 1982 1983 /* Disable all EHCI QH list processing */ 1984 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1985 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1986 1987 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1988 "ehci_cpr_suspend: Disable HC interrupts"); 1989 1990 /* Disable all EHCI interrupts */ 1991 Set_OpReg(ehci_interrupt, 0); 1992 1993 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1994 "ehci_cpr_suspend: Wait for the next SOF"); 1995 1996 /* Wait for the next SOF */ 1997 if (ehci_wait_for_sof(ehcip) != USB_SUCCESS) { 1998 1999 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2000 "ehci_cpr_suspend: ehci host controller suspend failed"); 2001 2002 mutex_exit(&ehcip->ehci_int_mutex); 2003 return (DDI_FAILURE); 2004 } 2005 2006 /* 2007 * Stop the ehci host controller 2008 * if usb keyboard is not connected. 2009 */ 2010 if (ehcip->ehci_polled_kbd_count == 0 || force_ehci_off != 0) { 2011 Set_OpReg(ehci_command, 2012 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 2013 } 2014 2015 /* Set host controller soft state to suspend */ 2016 ehcip->ehci_hc_soft_state = EHCI_CTLR_SUSPEND_STATE; 2017 2018 mutex_exit(&ehcip->ehci_int_mutex); 2019 2020 return (DDI_SUCCESS); 2021 } 2022 2023 2024 /* 2025 * ehci_cpr_resume 2026 */ 2027 int 2028 ehci_cpr_resume(ehci_state_t *ehcip) 2029 { 2030 mutex_enter(&ehcip->ehci_int_mutex); 2031 2032 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2033 "ehci_cpr_resume: Restart the controller"); 2034 2035 /* Cleanup ehci specific information across cpr */ 2036 ehci_cpr_cleanup(ehcip); 2037 2038 /* Restart the controller */ 2039 if (ehci_init_ctlr(ehcip, EHCI_NORMAL_INITIALIZATION) != DDI_SUCCESS) { 2040 2041 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2042 "ehci_cpr_resume: ehci host controller resume failed "); 2043 2044 mutex_exit(&ehcip->ehci_int_mutex); 2045 2046 return (DDI_FAILURE); 2047 } 2048 2049 mutex_exit(&ehcip->ehci_int_mutex); 2050 2051 /* Now resume the root hub */ 2052 if (usba_hubdi_attach(ehcip->ehci_dip, DDI_RESUME) != DDI_SUCCESS) { 2053 2054 return (DDI_FAILURE); 2055 } 2056 2057 return (DDI_SUCCESS); 2058 } 2059 2060 2061 /* 2062 * Bandwidth Allocation functions 2063 */ 2064 2065 /* 2066 * ehci_allocate_bandwidth: 2067 * 2068 * Figure out whether or not this interval may be supported. Return the index 2069 * into the lattice if it can be supported. Return allocation failure if it 2070 * can not be supported. 2071 */ 2072 int 2073 ehci_allocate_bandwidth( 2074 ehci_state_t *ehcip, 2075 usba_pipe_handle_data_t *ph, 2076 uint_t *pnode, 2077 uchar_t *smask, 2078 uchar_t *cmask) 2079 { 2080 int error = USB_SUCCESS; 2081 2082 /* This routine is protected by the ehci_int_mutex */ 2083 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2084 2085 /* Reset the pnode to the last checked pnode */ 2086 *pnode = 0; 2087 2088 /* Allocate high speed bandwidth */ 2089 if ((error = ehci_allocate_high_speed_bandwidth(ehcip, 2090 ph, pnode, smask, cmask)) != USB_SUCCESS) { 2091 2092 return (error); 2093 } 2094 2095 /* 2096 * For low/full speed usb devices, allocate classic TT bandwidth 2097 * in additional to high speed bandwidth. 2098 */ 2099 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2100 2101 /* Allocate classic TT bandwidth */ 2102 if ((error = ehci_allocate_classic_tt_bandwidth( 2103 ehcip, ph, *pnode)) != USB_SUCCESS) { 2104 2105 /* Deallocate high speed bandwidth */ 2106 ehci_deallocate_high_speed_bandwidth( 2107 ehcip, ph, *pnode, *smask, *cmask); 2108 } 2109 } 2110 2111 return (error); 2112 } 2113 2114 2115 /* 2116 * ehci_allocate_high_speed_bandwidth: 2117 * 2118 * Allocate high speed bandwidth for the low/full/high speed interrupt and 2119 * isochronous endpoints. 2120 */ 2121 static int 2122 ehci_allocate_high_speed_bandwidth( 2123 ehci_state_t *ehcip, 2124 usba_pipe_handle_data_t *ph, 2125 uint_t *pnode, 2126 uchar_t *smask, 2127 uchar_t *cmask) 2128 { 2129 uint_t sbandwidth, cbandwidth; 2130 int interval; 2131 usb_ep_descr_t *endpoint = &ph->p_ep; 2132 usba_device_t *child_ud; 2133 usb_port_status_t port_status; 2134 int error; 2135 2136 /* This routine is protected by the ehci_int_mutex */ 2137 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2138 2139 /* Get child's usba device structure */ 2140 child_ud = ph->p_usba_device; 2141 2142 mutex_enter(&child_ud->usb_mutex); 2143 2144 /* Get the current usb device's port status */ 2145 port_status = ph->p_usba_device->usb_port_status; 2146 2147 mutex_exit(&child_ud->usb_mutex); 2148 2149 /* 2150 * Calculate the length in bytes of a transaction on this 2151 * periodic endpoint. Return failure if maximum packet is 2152 * zero. 2153 */ 2154 error = ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2155 port_status, &sbandwidth, &cbandwidth); 2156 if (error != USB_SUCCESS) { 2157 2158 return (error); 2159 } 2160 2161 /* 2162 * Adjust polling interval to be a power of 2. 2163 * If this interval can't be supported, return 2164 * allocation failure. 2165 */ 2166 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2167 if (interval == USB_FAILURE) { 2168 2169 return (USB_FAILURE); 2170 } 2171 2172 if (port_status == USBA_HIGH_SPEED_DEV) { 2173 /* Allocate bandwidth for high speed devices */ 2174 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2175 USB_EP_ATTR_ISOCH) { 2176 error = USB_SUCCESS; 2177 } else { 2178 2179 error = ehci_find_bestfit_hs_mask(ehcip, smask, pnode, 2180 endpoint, sbandwidth, interval); 2181 } 2182 2183 *cmask = 0x00; 2184 2185 } else { 2186 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2187 USB_EP_ATTR_INTR) { 2188 2189 /* Allocate bandwidth for low speed interrupt */ 2190 error = ehci_find_bestfit_ls_intr_mask(ehcip, 2191 smask, cmask, pnode, sbandwidth, cbandwidth, 2192 interval); 2193 } else { 2194 if ((endpoint->bEndpointAddress & 2195 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2196 2197 /* Allocate bandwidth for sitd in */ 2198 error = ehci_find_bestfit_sitd_in_mask(ehcip, 2199 smask, cmask, pnode, sbandwidth, cbandwidth, 2200 interval); 2201 } else { 2202 2203 /* Allocate bandwidth for sitd out */ 2204 error = ehci_find_bestfit_sitd_out_mask(ehcip, 2205 smask, pnode, sbandwidth, interval); 2206 *cmask = 0x00; 2207 } 2208 } 2209 } 2210 2211 if (error != USB_SUCCESS) { 2212 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2213 "ehci_allocate_high_speed_bandwidth: Reached maximum " 2214 "bandwidth value and cannot allocate bandwidth for a " 2215 "given high-speed periodic endpoint"); 2216 2217 return (USB_NO_BANDWIDTH); 2218 } 2219 2220 return (error); 2221 } 2222 2223 2224 /* 2225 * ehci_allocate_classic_tt_speed_bandwidth: 2226 * 2227 * Allocate classic TT bandwidth for the low/full speed interrupt and 2228 * isochronous endpoints. 2229 */ 2230 static int 2231 ehci_allocate_classic_tt_bandwidth( 2232 ehci_state_t *ehcip, 2233 usba_pipe_handle_data_t *ph, 2234 uint_t pnode) 2235 { 2236 uint_t bandwidth, min; 2237 uint_t height, leftmost, list; 2238 usb_ep_descr_t *endpoint = &ph->p_ep; 2239 usba_device_t *child_ud, *parent_ud; 2240 usb_port_status_t port_status; 2241 int i, interval; 2242 2243 /* This routine is protected by the ehci_int_mutex */ 2244 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2245 2246 /* Get child's usba device structure */ 2247 child_ud = ph->p_usba_device; 2248 2249 mutex_enter(&child_ud->usb_mutex); 2250 2251 /* Get the current usb device's port status */ 2252 port_status = child_ud->usb_port_status; 2253 2254 /* Get the parent high speed hub's usba device structure */ 2255 parent_ud = child_ud->usb_hs_hub_usba_dev; 2256 2257 mutex_exit(&child_ud->usb_mutex); 2258 2259 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2260 "ehci_allocate_classic_tt_bandwidth: " 2261 "child_ud 0x%p parent_ud 0x%p", child_ud, parent_ud); 2262 2263 /* 2264 * Calculate the length in bytes of a transaction on this 2265 * periodic endpoint. Return failure if maximum packet is 2266 * zero. 2267 */ 2268 if (ehci_compute_classic_bandwidth(endpoint, 2269 port_status, &bandwidth) != USB_SUCCESS) { 2270 2271 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2272 "ehci_allocate_classic_tt_bandwidth: Periodic endpoint " 2273 "with zero endpoint maximum packet size is not supported"); 2274 2275 return (USB_NOT_SUPPORTED); 2276 } 2277 2278 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2279 "ehci_allocate_classic_tt_bandwidth: bandwidth %d", bandwidth); 2280 2281 mutex_enter(&parent_ud->usb_mutex); 2282 2283 /* 2284 * If the length in bytes plus the allocated bandwidth exceeds 2285 * the maximum, return bandwidth allocation failure. 2286 */ 2287 if ((parent_ud->usb_hs_hub_min_bandwidth + bandwidth) > 2288 FS_PERIODIC_BANDWIDTH) { 2289 2290 mutex_exit(&parent_ud->usb_mutex); 2291 2292 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2293 "ehci_allocate_classic_tt_bandwidth: Reached maximum " 2294 "bandwidth value and cannot allocate bandwidth for a " 2295 "given low/full speed periodic endpoint"); 2296 2297 return (USB_NO_BANDWIDTH); 2298 } 2299 2300 mutex_exit(&parent_ud->usb_mutex); 2301 2302 /* Adjust polling interval to be a power of 2 */ 2303 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2304 2305 /* Find the height in the tree */ 2306 height = ehci_lattice_height(interval); 2307 2308 /* Find the leftmost leaf in the subtree specified by the node. */ 2309 leftmost = ehci_leftmost_leaf(pnode, height); 2310 2311 mutex_enter(&parent_ud->usb_mutex); 2312 2313 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2314 list = ehci_index[leftmost + i]; 2315 2316 if ((parent_ud->usb_hs_hub_bandwidth[list] + 2317 bandwidth) > FS_PERIODIC_BANDWIDTH) { 2318 2319 mutex_exit(&parent_ud->usb_mutex); 2320 2321 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2322 "ehci_allocate_classic_tt_bandwidth: Reached " 2323 "maximum bandwidth value and cannot allocate " 2324 "bandwidth for low/full periodic endpoint"); 2325 2326 return (USB_NO_BANDWIDTH); 2327 } 2328 } 2329 2330 /* 2331 * All the leaves for this node must be updated with the bandwidth. 2332 */ 2333 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2334 list = ehci_index[leftmost + i]; 2335 parent_ud->usb_hs_hub_bandwidth[list] += bandwidth; 2336 } 2337 2338 /* Find the leaf with the smallest allocated bandwidth */ 2339 min = parent_ud->usb_hs_hub_bandwidth[0]; 2340 2341 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2342 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2343 min = parent_ud->usb_hs_hub_bandwidth[i]; 2344 } 2345 } 2346 2347 /* Save the minimum for later use */ 2348 parent_ud->usb_hs_hub_min_bandwidth = min; 2349 2350 mutex_exit(&parent_ud->usb_mutex); 2351 2352 return (USB_SUCCESS); 2353 } 2354 2355 2356 /* 2357 * ehci_deallocate_bandwidth: 2358 * 2359 * Deallocate bandwidth for the given node in the lattice and the length 2360 * of transfer. 2361 */ 2362 void 2363 ehci_deallocate_bandwidth( 2364 ehci_state_t *ehcip, 2365 usba_pipe_handle_data_t *ph, 2366 uint_t pnode, 2367 uchar_t smask, 2368 uchar_t cmask) 2369 { 2370 /* This routine is protected by the ehci_int_mutex */ 2371 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2372 2373 ehci_deallocate_high_speed_bandwidth(ehcip, ph, pnode, smask, cmask); 2374 2375 /* 2376 * For low/full speed usb devices, deallocate classic TT bandwidth 2377 * in additional to high speed bandwidth. 2378 */ 2379 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2380 2381 /* Deallocate classic TT bandwidth */ 2382 ehci_deallocate_classic_tt_bandwidth(ehcip, ph, pnode); 2383 } 2384 } 2385 2386 2387 /* 2388 * ehci_deallocate_high_speed_bandwidth: 2389 * 2390 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2391 */ 2392 static void 2393 ehci_deallocate_high_speed_bandwidth( 2394 ehci_state_t *ehcip, 2395 usba_pipe_handle_data_t *ph, 2396 uint_t pnode, 2397 uchar_t smask, 2398 uchar_t cmask) 2399 { 2400 uint_t height, leftmost; 2401 uint_t list_count; 2402 uint_t sbandwidth, cbandwidth; 2403 int interval; 2404 usb_ep_descr_t *endpoint = &ph->p_ep; 2405 usba_device_t *child_ud; 2406 usb_port_status_t port_status; 2407 2408 /* This routine is protected by the ehci_int_mutex */ 2409 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2410 2411 /* Get child's usba device structure */ 2412 child_ud = ph->p_usba_device; 2413 2414 mutex_enter(&child_ud->usb_mutex); 2415 2416 /* Get the current usb device's port status */ 2417 port_status = ph->p_usba_device->usb_port_status; 2418 2419 mutex_exit(&child_ud->usb_mutex); 2420 2421 (void) ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2422 port_status, &sbandwidth, &cbandwidth); 2423 2424 /* Adjust polling interval to be a power of 2 */ 2425 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2426 2427 /* Find the height in the tree */ 2428 height = ehci_lattice_height(interval); 2429 2430 /* 2431 * Find the leftmost leaf in the subtree specified by the node 2432 */ 2433 leftmost = ehci_leftmost_leaf(pnode, height); 2434 2435 list_count = EHCI_NUM_INTR_QH_LISTS/interval; 2436 2437 /* Delete the bandwidth from the appropriate lists */ 2438 if (port_status == USBA_HIGH_SPEED_DEV) { 2439 2440 ehci_update_bw_availability(ehcip, -sbandwidth, 2441 leftmost, list_count, smask); 2442 } else { 2443 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2444 USB_EP_ATTR_INTR) { 2445 2446 ehci_update_bw_availability(ehcip, -sbandwidth, 2447 leftmost, list_count, smask); 2448 ehci_update_bw_availability(ehcip, -cbandwidth, 2449 leftmost, list_count, cmask); 2450 } else { 2451 if ((endpoint->bEndpointAddress & 2452 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2453 2454 ehci_update_bw_availability(ehcip, -sbandwidth, 2455 leftmost, list_count, smask); 2456 ehci_update_bw_availability(ehcip, 2457 -MAX_UFRAME_SITD_XFER, leftmost, 2458 list_count, cmask); 2459 } else { 2460 2461 ehci_update_bw_availability(ehcip, 2462 -MAX_UFRAME_SITD_XFER, leftmost, 2463 list_count, smask); 2464 } 2465 } 2466 } 2467 } 2468 2469 /* 2470 * ehci_deallocate_classic_tt_bandwidth: 2471 * 2472 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2473 */ 2474 static void 2475 ehci_deallocate_classic_tt_bandwidth( 2476 ehci_state_t *ehcip, 2477 usba_pipe_handle_data_t *ph, 2478 uint_t pnode) 2479 { 2480 uint_t bandwidth, height, leftmost, list, min; 2481 int i, interval; 2482 usb_ep_descr_t *endpoint = &ph->p_ep; 2483 usba_device_t *child_ud, *parent_ud; 2484 usb_port_status_t port_status; 2485 2486 /* This routine is protected by the ehci_int_mutex */ 2487 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2488 2489 /* Get child's usba device structure */ 2490 child_ud = ph->p_usba_device; 2491 2492 mutex_enter(&child_ud->usb_mutex); 2493 2494 /* Get the current usb device's port status */ 2495 port_status = child_ud->usb_port_status; 2496 2497 /* Get the parent high speed hub's usba device structure */ 2498 parent_ud = child_ud->usb_hs_hub_usba_dev; 2499 2500 mutex_exit(&child_ud->usb_mutex); 2501 2502 /* Obtain the bandwidth */ 2503 (void) ehci_compute_classic_bandwidth(endpoint, 2504 port_status, &bandwidth); 2505 2506 /* Adjust polling interval to be a power of 2 */ 2507 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2508 2509 /* Find the height in the tree */ 2510 height = ehci_lattice_height(interval); 2511 2512 /* Find the leftmost leaf in the subtree specified by the node */ 2513 leftmost = ehci_leftmost_leaf(pnode, height); 2514 2515 mutex_enter(&parent_ud->usb_mutex); 2516 2517 /* Delete the bandwidth from the appropriate lists */ 2518 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2519 list = ehci_index[leftmost + i]; 2520 parent_ud->usb_hs_hub_bandwidth[list] -= bandwidth; 2521 } 2522 2523 /* Find the leaf with the smallest allocated bandwidth */ 2524 min = parent_ud->usb_hs_hub_bandwidth[0]; 2525 2526 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2527 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2528 min = parent_ud->usb_hs_hub_bandwidth[i]; 2529 } 2530 } 2531 2532 /* Save the minimum for later use */ 2533 parent_ud->usb_hs_hub_min_bandwidth = min; 2534 2535 mutex_exit(&parent_ud->usb_mutex); 2536 } 2537 2538 2539 /* 2540 * ehci_compute_high_speed_bandwidth: 2541 * 2542 * Given a periodic endpoint (interrupt or isochronous) determine the total 2543 * bandwidth for one transaction. The EHCI host controller traverses the 2544 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2545 * services an endpoint, only a single transaction attempt is made. The HC 2546 * moves to the next Endpoint Descriptor after the first transaction attempt 2547 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2548 * Transfer Descriptor is inserted into the lattice, we will only count the 2549 * number of bytes for one transaction. 2550 * 2551 * The following are the formulas used for calculating bandwidth in terms 2552 * bytes and it is for the single USB high speed transaction. The protocol 2553 * overheads will be different for each of type of USB transfer & all these 2554 * formulas & protocol overheads are derived from the 5.11.3 section of the 2555 * USB 2.0 Specification. 2556 * 2557 * High-Speed: 2558 * Protocol overhead + ((MaxPktSz * 7)/6) + Host_Delay 2559 * 2560 * Split Transaction: (Low/Full speed devices connected behind usb2.0 hub) 2561 * 2562 * Protocol overhead + Split transaction overhead + 2563 * ((MaxPktSz * 7)/6) + Host_Delay; 2564 */ 2565 /* ARGSUSED */ 2566 static int 2567 ehci_compute_high_speed_bandwidth( 2568 ehci_state_t *ehcip, 2569 usb_ep_descr_t *endpoint, 2570 usb_port_status_t port_status, 2571 uint_t *sbandwidth, 2572 uint_t *cbandwidth) 2573 { 2574 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2575 2576 /* Return failure if endpoint maximum packet is zero */ 2577 if (maxpacketsize == 0) { 2578 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2579 "ehci_allocate_high_speed_bandwidth: Periodic endpoint " 2580 "with zero endpoint maximum packet size is not supported"); 2581 2582 return (USB_NOT_SUPPORTED); 2583 } 2584 2585 /* Add bit-stuffing overhead */ 2586 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2587 2588 /* Add Host Controller specific delay to required bandwidth */ 2589 *sbandwidth = EHCI_HOST_CONTROLLER_DELAY; 2590 2591 /* Add xfer specific protocol overheads */ 2592 if ((endpoint->bmAttributes & 2593 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2594 /* High speed interrupt transaction */ 2595 *sbandwidth += HS_NON_ISOC_PROTO_OVERHEAD; 2596 } else { 2597 /* Isochronous transaction */ 2598 *sbandwidth += HS_ISOC_PROTO_OVERHEAD; 2599 } 2600 2601 /* 2602 * For low/full speed devices, add split transaction specific 2603 * overheads. 2604 */ 2605 if (port_status != USBA_HIGH_SPEED_DEV) { 2606 /* 2607 * Add start and complete split transaction 2608 * tokens overheads. 2609 */ 2610 *cbandwidth = *sbandwidth + COMPLETE_SPLIT_OVERHEAD; 2611 *sbandwidth += START_SPLIT_OVERHEAD; 2612 2613 /* Add data overhead depending on data direction */ 2614 if ((endpoint->bEndpointAddress & 2615 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2616 *cbandwidth += maxpacketsize; 2617 } else { 2618 if ((endpoint->bmAttributes & 2619 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 2620 /* There is no compete splits for out */ 2621 *cbandwidth = 0; 2622 } 2623 *sbandwidth += maxpacketsize; 2624 } 2625 } else { 2626 uint_t xactions; 2627 2628 /* Get the max transactions per microframe */ 2629 xactions = ((maxpacketsize & USB_EP_MAX_XACTS_MASK) >> 2630 USB_EP_MAX_XACTS_SHIFT) + 1; 2631 2632 /* High speed transaction */ 2633 *sbandwidth += maxpacketsize; 2634 2635 /* Calculate bandwidth per micro-frame */ 2636 *sbandwidth *= xactions; 2637 2638 *cbandwidth = 0; 2639 } 2640 2641 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2642 "ehci_allocate_high_speed_bandwidth: " 2643 "Start split bandwidth %d Complete split bandwidth %d", 2644 *sbandwidth, *cbandwidth); 2645 2646 return (USB_SUCCESS); 2647 } 2648 2649 2650 /* 2651 * ehci_compute_classic_bandwidth: 2652 * 2653 * Given a periodic endpoint (interrupt or isochronous) determine the total 2654 * bandwidth for one transaction. The EHCI host controller traverses the 2655 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2656 * services an endpoint, only a single transaction attempt is made. The HC 2657 * moves to the next Endpoint Descriptor after the first transaction attempt 2658 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2659 * Transfer Descriptor is inserted into the lattice, we will only count the 2660 * number of bytes for one transaction. 2661 * 2662 * The following are the formulas used for calculating bandwidth in terms 2663 * bytes and it is for the single USB high speed transaction. The protocol 2664 * overheads will be different for each of type of USB transfer & all these 2665 * formulas & protocol overheads are derived from the 5.11.3 section of the 2666 * USB 2.0 Specification. 2667 * 2668 * Low-Speed: 2669 * Protocol overhead + Hub LS overhead + 2670 * (Low Speed clock * ((MaxPktSz * 7)/6)) + TT_Delay 2671 * 2672 * Full-Speed: 2673 * Protocol overhead + ((MaxPktSz * 7)/6) + TT_Delay 2674 */ 2675 /* ARGSUSED */ 2676 static int 2677 ehci_compute_classic_bandwidth( 2678 usb_ep_descr_t *endpoint, 2679 usb_port_status_t port_status, 2680 uint_t *bandwidth) 2681 { 2682 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2683 2684 /* 2685 * If endpoint maximum packet is zero, then return immediately. 2686 */ 2687 if (maxpacketsize == 0) { 2688 2689 return (USB_NOT_SUPPORTED); 2690 } 2691 2692 /* Add TT delay to required bandwidth */ 2693 *bandwidth = TT_DELAY; 2694 2695 /* Add bit-stuffing overhead */ 2696 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2697 2698 switch (port_status) { 2699 case USBA_LOW_SPEED_DEV: 2700 /* Low speed interrupt transaction */ 2701 *bandwidth += (LOW_SPEED_PROTO_OVERHEAD + 2702 HUB_LOW_SPEED_PROTO_OVERHEAD + 2703 (LOW_SPEED_CLOCK * maxpacketsize)); 2704 break; 2705 case USBA_FULL_SPEED_DEV: 2706 /* Full speed transaction */ 2707 *bandwidth += maxpacketsize; 2708 2709 /* Add xfer specific protocol overheads */ 2710 if ((endpoint->bmAttributes & 2711 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2712 /* Full speed interrupt transaction */ 2713 *bandwidth += FS_NON_ISOC_PROTO_OVERHEAD; 2714 } else { 2715 /* Isochronous and input transaction */ 2716 if ((endpoint->bEndpointAddress & 2717 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2718 *bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD; 2719 } else { 2720 /* Isochronous and output transaction */ 2721 *bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD; 2722 } 2723 } 2724 break; 2725 } 2726 2727 return (USB_SUCCESS); 2728 } 2729 2730 2731 /* 2732 * ehci_adjust_polling_interval: 2733 * 2734 * Adjust bandwidth according usb device speed. 2735 */ 2736 /* ARGSUSED */ 2737 int 2738 ehci_adjust_polling_interval( 2739 ehci_state_t *ehcip, 2740 usb_ep_descr_t *endpoint, 2741 usb_port_status_t port_status) 2742 { 2743 uint_t interval; 2744 int i = 0; 2745 2746 /* Get the polling interval */ 2747 interval = endpoint->bInterval; 2748 2749 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2750 "ehci_adjust_polling_interval: Polling interval 0x%x", interval); 2751 2752 /* 2753 * According USB 2.0 Specifications, a high-speed endpoint's 2754 * polling intervals are specified interms of 125us or micro 2755 * frame, where as full/low endpoint's polling intervals are 2756 * specified in milliseconds. 2757 * 2758 * A high speed interrupt/isochronous endpoints can specify 2759 * desired polling interval between 1 to 16 micro-frames, 2760 * where as full/low endpoints can specify between 1 to 255 2761 * milliseconds. 2762 */ 2763 switch (port_status) { 2764 case USBA_LOW_SPEED_DEV: 2765 /* 2766 * Low speed endpoints are limited to specifying 2767 * only 8ms to 255ms in this driver. If a device 2768 * reports a polling interval that is less than 8ms, 2769 * it will use 8 ms instead. 2770 */ 2771 if (interval < LS_MIN_POLL_INTERVAL) { 2772 2773 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2774 "Low speed endpoint's poll interval of %d ms " 2775 "is below threshold. Rounding up to %d ms", 2776 interval, LS_MIN_POLL_INTERVAL); 2777 2778 interval = LS_MIN_POLL_INTERVAL; 2779 } 2780 2781 /* 2782 * Return an error if the polling interval is greater 2783 * than 255ms. 2784 */ 2785 if (interval > LS_MAX_POLL_INTERVAL) { 2786 2787 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2788 "Low speed endpoint's poll interval is " 2789 "greater than %d ms", LS_MAX_POLL_INTERVAL); 2790 2791 return (USB_FAILURE); 2792 } 2793 break; 2794 2795 case USBA_FULL_SPEED_DEV: 2796 /* 2797 * Return an error if the polling interval is less 2798 * than 1ms and greater than 255ms. 2799 */ 2800 if ((interval < FS_MIN_POLL_INTERVAL) && 2801 (interval > FS_MAX_POLL_INTERVAL)) { 2802 2803 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2804 "Full speed endpoint's poll interval must " 2805 "be between %d and %d ms", FS_MIN_POLL_INTERVAL, 2806 FS_MAX_POLL_INTERVAL); 2807 2808 return (USB_FAILURE); 2809 } 2810 break; 2811 case USBA_HIGH_SPEED_DEV: 2812 /* 2813 * Return an error if the polling interval is less 1 2814 * and greater than 16. Convert this value to 125us 2815 * units using 2^(bInterval -1). refer usb 2.0 spec 2816 * page 51 for details. 2817 */ 2818 if ((interval < HS_MIN_POLL_INTERVAL) && 2819 (interval > HS_MAX_POLL_INTERVAL)) { 2820 2821 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2822 "High speed endpoint's poll interval " 2823 "must be between %d and %d units", 2824 HS_MIN_POLL_INTERVAL, HS_MAX_POLL_INTERVAL); 2825 2826 return (USB_FAILURE); 2827 } 2828 2829 /* Adjust high speed device polling interval */ 2830 interval = 2831 ehci_adjust_high_speed_polling_interval(ehcip, endpoint); 2832 2833 break; 2834 } 2835 2836 /* 2837 * If polling interval is greater than 32ms, 2838 * adjust polling interval equal to 32ms. 2839 */ 2840 if (interval > EHCI_NUM_INTR_QH_LISTS) { 2841 interval = EHCI_NUM_INTR_QH_LISTS; 2842 } 2843 2844 /* 2845 * Find the nearest power of 2 that's less 2846 * than interval. 2847 */ 2848 while ((ehci_pow_2(i)) <= interval) { 2849 i++; 2850 } 2851 2852 return (ehci_pow_2((i - 1))); 2853 } 2854 2855 2856 /* 2857 * ehci_adjust_high_speed_polling_interval: 2858 */ 2859 /* ARGSUSED */ 2860 static int 2861 ehci_adjust_high_speed_polling_interval( 2862 ehci_state_t *ehcip, 2863 usb_ep_descr_t *endpoint) 2864 { 2865 uint_t interval; 2866 2867 /* Get the polling interval */ 2868 interval = ehci_pow_2(endpoint->bInterval - 1); 2869 2870 /* 2871 * Convert polling interval from micro seconds 2872 * to milli seconds. 2873 */ 2874 if (interval <= EHCI_MAX_UFRAMES) { 2875 interval = 1; 2876 } else { 2877 interval = interval/EHCI_MAX_UFRAMES; 2878 } 2879 2880 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2881 "ehci_adjust_high_speed_polling_interval: " 2882 "High speed adjusted interval 0x%x", interval); 2883 2884 return (interval); 2885 } 2886 2887 2888 /* 2889 * ehci_lattice_height: 2890 * 2891 * Given the requested bandwidth, find the height in the tree at which the 2892 * nodes for this bandwidth fall. The height is measured as the number of 2893 * nodes from the leaf to the level specified by bandwidth The root of the 2894 * tree is at height TREE_HEIGHT. 2895 */ 2896 static uint_t 2897 ehci_lattice_height(uint_t interval) 2898 { 2899 return (TREE_HEIGHT - (ehci_log_2(interval))); 2900 } 2901 2902 2903 /* 2904 * ehci_lattice_parent: 2905 * 2906 * Given a node in the lattice, find the index of the parent node 2907 */ 2908 static uint_t 2909 ehci_lattice_parent(uint_t node) 2910 { 2911 if ((node % 2) == 0) { 2912 2913 return ((node/2) - 1); 2914 } else { 2915 2916 return ((node + 1)/2 - 1); 2917 } 2918 } 2919 2920 2921 /* 2922 * ehci_find_periodic_node: 2923 * 2924 * Based on the "real" array leaf node and interval, get the periodic node. 2925 */ 2926 static uint_t 2927 ehci_find_periodic_node(uint_t leaf, int interval) { 2928 uint_t lattice_leaf; 2929 uint_t height = ehci_lattice_height(interval); 2930 uint_t pnode; 2931 int i; 2932 2933 /* Get the leaf number in the lattice */ 2934 lattice_leaf = leaf + EHCI_NUM_INTR_QH_LISTS - 1; 2935 2936 /* Get the node in the lattice based on the height and leaf */ 2937 pnode = lattice_leaf; 2938 for (i = 0; i < height; i++) { 2939 pnode = ehci_lattice_parent(pnode); 2940 } 2941 2942 return (pnode); 2943 } 2944 2945 2946 /* 2947 * ehci_leftmost_leaf: 2948 * 2949 * Find the leftmost leaf in the subtree specified by the node. Height refers 2950 * to number of nodes from the bottom of the tree to the node, including the 2951 * node. 2952 * 2953 * The formula for a zero based tree is: 2954 * 2^H * Node + 2^H - 1 2955 * The leaf of the tree is an array, convert the number for the array. 2956 * Subtract the size of nodes not in the array 2957 * 2^H * Node + 2^H - 1 - (EHCI_NUM_INTR_QH_LISTS - 1) = 2958 * 2^H * Node + 2^H - EHCI_NUM_INTR_QH_LISTS = 2959 * 2^H * (Node + 1) - EHCI_NUM_INTR_QH_LISTS 2960 * 0 2961 * 1 2 2962 * 0 1 2 3 2963 */ 2964 static uint_t 2965 ehci_leftmost_leaf( 2966 uint_t node, 2967 uint_t height) 2968 { 2969 return ((ehci_pow_2(height) * (node + 1)) - EHCI_NUM_INTR_QH_LISTS); 2970 } 2971 2972 2973 /* 2974 * ehci_pow_2: 2975 * 2976 * Compute 2 to the power 2977 */ 2978 static uint_t 2979 ehci_pow_2(uint_t x) 2980 { 2981 if (x == 0) { 2982 2983 return (1); 2984 } else { 2985 2986 return (2 << (x - 1)); 2987 } 2988 } 2989 2990 2991 /* 2992 * ehci_log_2: 2993 * 2994 * Compute log base 2 of x 2995 */ 2996 static uint_t 2997 ehci_log_2(uint_t x) 2998 { 2999 int i = 0; 3000 3001 while (x != 1) { 3002 x = x >> 1; 3003 i++; 3004 } 3005 3006 return (i); 3007 } 3008 3009 3010 /* 3011 * ehci_find_bestfit_hs_mask: 3012 * 3013 * Find the smask and cmask in the bandwidth allocation, and update the 3014 * bandwidth allocation. 3015 */ 3016 static int 3017 ehci_find_bestfit_hs_mask( 3018 ehci_state_t *ehcip, 3019 uchar_t *smask, 3020 uint_t *pnode, 3021 usb_ep_descr_t *endpoint, 3022 uint_t bandwidth, 3023 int interval) 3024 { 3025 int i; 3026 uint_t elements, index; 3027 int array_leaf, best_array_leaf; 3028 uint_t node_bandwidth, best_node_bandwidth; 3029 uint_t leaf_count; 3030 uchar_t bw_mask; 3031 uchar_t best_smask; 3032 3033 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3034 "ehci_find_bestfit_hs_mask: "); 3035 3036 /* Get all the valid smasks */ 3037 switch (ehci_pow_2(endpoint->bInterval - 1)) { 3038 case EHCI_INTR_1US_POLL: 3039 index = EHCI_1US_MASK_INDEX; 3040 elements = EHCI_INTR_1US_POLL; 3041 break; 3042 case EHCI_INTR_2US_POLL: 3043 index = EHCI_2US_MASK_INDEX; 3044 elements = EHCI_INTR_2US_POLL; 3045 break; 3046 case EHCI_INTR_4US_POLL: 3047 index = EHCI_4US_MASK_INDEX; 3048 elements = EHCI_INTR_4US_POLL; 3049 break; 3050 case EHCI_INTR_XUS_POLL: 3051 default: 3052 index = EHCI_XUS_MASK_INDEX; 3053 elements = EHCI_INTR_XUS_POLL; 3054 break; 3055 } 3056 3057 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3058 3059 /* 3060 * Because of the way the leaves are setup, we will automatically 3061 * hit the leftmost leaf of every possible node with this interval. 3062 */ 3063 best_smask = 0x00; 3064 best_node_bandwidth = 0; 3065 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3066 /* Find the bandwidth mask */ 3067 node_bandwidth = ehci_calculate_bw_availability_mask(ehcip, 3068 bandwidth, ehci_index[array_leaf], leaf_count, &bw_mask); 3069 3070 /* 3071 * If this node cannot support our requirements skip to the 3072 * next leaf. 3073 */ 3074 if (bw_mask == 0x00) { 3075 continue; 3076 } 3077 3078 /* 3079 * Now make sure our bandwidth requirements can be 3080 * satisfied with one of smasks in this node. 3081 */ 3082 *smask = 0x00; 3083 for (i = index; i < (index + elements); i++) { 3084 /* Check the start split mask value */ 3085 if (ehci_start_split_mask[index] & bw_mask) { 3086 *smask = ehci_start_split_mask[index]; 3087 break; 3088 } 3089 } 3090 3091 /* 3092 * If an appropriate smask is found save the information if: 3093 * o best_smask has not been found yet. 3094 * - or - 3095 * o This is the node with the least amount of bandwidth 3096 */ 3097 if ((*smask != 0x00) && 3098 ((best_smask == 0x00) || 3099 (best_node_bandwidth > node_bandwidth))) { 3100 3101 best_node_bandwidth = node_bandwidth; 3102 best_array_leaf = array_leaf; 3103 best_smask = *smask; 3104 } 3105 } 3106 3107 /* 3108 * If we find node that can handle the bandwidth populate the 3109 * appropriate variables and return success. 3110 */ 3111 if (best_smask) { 3112 *smask = best_smask; 3113 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3114 interval); 3115 ehci_update_bw_availability(ehcip, bandwidth, 3116 ehci_index[best_array_leaf], leaf_count, best_smask); 3117 3118 return (USB_SUCCESS); 3119 } 3120 3121 return (USB_FAILURE); 3122 } 3123 3124 3125 /* 3126 * ehci_find_bestfit_ls_intr_mask: 3127 * 3128 * Find the smask and cmask in the bandwidth allocation. 3129 */ 3130 static int 3131 ehci_find_bestfit_ls_intr_mask( 3132 ehci_state_t *ehcip, 3133 uchar_t *smask, 3134 uchar_t *cmask, 3135 uint_t *pnode, 3136 uint_t sbandwidth, 3137 uint_t cbandwidth, 3138 int interval) 3139 { 3140 int i; 3141 uint_t elements, index; 3142 int array_leaf, best_array_leaf; 3143 uint_t node_sbandwidth, node_cbandwidth; 3144 uint_t best_node_bandwidth; 3145 uint_t leaf_count; 3146 uchar_t bw_smask, bw_cmask; 3147 uchar_t best_smask, best_cmask; 3148 3149 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3150 "ehci_find_bestfit_ls_intr_mask: "); 3151 3152 /* For low and full speed devices */ 3153 index = EHCI_XUS_MASK_INDEX; 3154 elements = EHCI_INTR_4MS_POLL; 3155 3156 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3157 3158 /* 3159 * Because of the way the leaves are setup, we will automatically 3160 * hit the leftmost leaf of every possible node with this interval. 3161 */ 3162 best_smask = 0x00; 3163 best_node_bandwidth = 0; 3164 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3165 /* Find the bandwidth mask */ 3166 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3167 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3168 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3169 cbandwidth, ehci_index[array_leaf], leaf_count, &bw_cmask); 3170 3171 /* 3172 * If this node cannot support our requirements skip to the 3173 * next leaf. 3174 */ 3175 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3176 continue; 3177 } 3178 3179 /* 3180 * Now make sure our bandwidth requirements can be 3181 * satisfied with one of smasks in this node. 3182 */ 3183 *smask = 0x00; 3184 *cmask = 0x00; 3185 for (i = index; i < (index + elements); i++) { 3186 /* Check the start split mask value */ 3187 if ((ehci_start_split_mask[index] & bw_smask) && 3188 (ehci_intr_complete_split_mask[index] & bw_cmask)) { 3189 *smask = ehci_start_split_mask[index]; 3190 *cmask = ehci_intr_complete_split_mask[index]; 3191 break; 3192 } 3193 } 3194 3195 /* 3196 * If an appropriate smask is found save the information if: 3197 * o best_smask has not been found yet. 3198 * - or - 3199 * o This is the node with the least amount of bandwidth 3200 */ 3201 if ((*smask != 0x00) && 3202 ((best_smask == 0x00) || 3203 (best_node_bandwidth > 3204 (node_sbandwidth + node_cbandwidth)))) { 3205 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3206 best_array_leaf = array_leaf; 3207 best_smask = *smask; 3208 best_cmask = *cmask; 3209 } 3210 } 3211 3212 /* 3213 * If we find node that can handle the bandwidth populate the 3214 * appropriate variables and return success. 3215 */ 3216 if (best_smask) { 3217 *smask = best_smask; 3218 *cmask = best_cmask; 3219 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3220 interval); 3221 ehci_update_bw_availability(ehcip, sbandwidth, 3222 ehci_index[best_array_leaf], leaf_count, best_smask); 3223 ehci_update_bw_availability(ehcip, cbandwidth, 3224 ehci_index[best_array_leaf], leaf_count, best_cmask); 3225 3226 return (USB_SUCCESS); 3227 } 3228 3229 return (USB_FAILURE); 3230 } 3231 3232 3233 /* 3234 * ehci_find_bestfit_sitd_in_mask: 3235 * 3236 * Find the smask and cmask in the bandwidth allocation. 3237 */ 3238 static int 3239 ehci_find_bestfit_sitd_in_mask( 3240 ehci_state_t *ehcip, 3241 uchar_t *smask, 3242 uchar_t *cmask, 3243 uint_t *pnode, 3244 uint_t sbandwidth, 3245 uint_t cbandwidth, 3246 int interval) 3247 { 3248 int i, uFrames, found; 3249 int array_leaf, best_array_leaf; 3250 uint_t node_sbandwidth, node_cbandwidth; 3251 uint_t best_node_bandwidth; 3252 uint_t leaf_count; 3253 uchar_t bw_smask, bw_cmask; 3254 uchar_t best_smask, best_cmask; 3255 3256 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3257 "ehci_find_bestfit_sitd_in_mask: "); 3258 3259 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3260 3261 /* 3262 * Because of the way the leaves are setup, we will automatically 3263 * hit the leftmost leaf of every possible node with this interval. 3264 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3265 */ 3266 /* 3267 * Need to add an additional 2 uFrames, if the "L"ast 3268 * complete split is before uFrame 6. See section 3269 * 11.8.4 in USB 2.0 Spec. Currently we do not support 3270 * the "Back Ptr" which means we support on IN of 3271 * ~4*MAX_UFRAME_SITD_XFER bandwidth/ 3272 */ 3273 uFrames = (cbandwidth / MAX_UFRAME_SITD_XFER) + 2; 3274 if (cbandwidth % MAX_UFRAME_SITD_XFER) { 3275 uFrames++; 3276 } 3277 if (uFrames > 6) { 3278 3279 return (USB_FAILURE); 3280 } 3281 *smask = 0x1; 3282 *cmask = 0x00; 3283 for (i = 0; i < uFrames; i++) { 3284 *cmask = *cmask << 1; 3285 *cmask |= 0x1; 3286 } 3287 /* cmask must start 2 frames after the smask */ 3288 *cmask = *cmask << 2; 3289 3290 found = 0; 3291 best_smask = 0x00; 3292 best_node_bandwidth = 0; 3293 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3294 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3295 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3296 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3297 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3298 &bw_cmask); 3299 3300 /* 3301 * If this node cannot support our requirements skip to the 3302 * next leaf. 3303 */ 3304 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3305 continue; 3306 } 3307 3308 for (i = 0; i < (EHCI_MAX_UFRAMES - uFrames - 2); i++) { 3309 if ((*smask & bw_smask) && (*cmask & bw_cmask)) { 3310 found = 1; 3311 break; 3312 } 3313 *smask = *smask << 1; 3314 *cmask = *cmask << 1; 3315 } 3316 3317 /* 3318 * If an appropriate smask is found save the information if: 3319 * o best_smask has not been found yet. 3320 * - or - 3321 * o This is the node with the least amount of bandwidth 3322 */ 3323 if (found && 3324 ((best_smask == 0x00) || 3325 (best_node_bandwidth > 3326 (node_sbandwidth + node_cbandwidth)))) { 3327 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3328 best_array_leaf = array_leaf; 3329 best_smask = *smask; 3330 best_cmask = *cmask; 3331 } 3332 } 3333 3334 /* 3335 * If we find node that can handle the bandwidth populate the 3336 * appropriate variables and return success. 3337 */ 3338 if (best_smask) { 3339 *smask = best_smask; 3340 *cmask = best_cmask; 3341 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3342 interval); 3343 ehci_update_bw_availability(ehcip, sbandwidth, 3344 ehci_index[best_array_leaf], leaf_count, best_smask); 3345 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3346 ehci_index[best_array_leaf], leaf_count, best_cmask); 3347 3348 return (USB_SUCCESS); 3349 } 3350 3351 return (USB_FAILURE); 3352 } 3353 3354 3355 /* 3356 * ehci_find_bestfit_sitd_out_mask: 3357 * 3358 * Find the smask in the bandwidth allocation. 3359 */ 3360 static int 3361 ehci_find_bestfit_sitd_out_mask( 3362 ehci_state_t *ehcip, 3363 uchar_t *smask, 3364 uint_t *pnode, 3365 uint_t sbandwidth, 3366 int interval) 3367 { 3368 int i, uFrames, found; 3369 int array_leaf, best_array_leaf; 3370 uint_t node_sbandwidth; 3371 uint_t best_node_bandwidth; 3372 uint_t leaf_count; 3373 uchar_t bw_smask; 3374 uchar_t best_smask; 3375 3376 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3377 "ehci_find_bestfit_sitd_out_mask: "); 3378 3379 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3380 3381 /* 3382 * Because of the way the leaves are setup, we will automatically 3383 * hit the leftmost leaf of every possible node with this interval. 3384 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3385 */ 3386 *smask = 0x00; 3387 uFrames = sbandwidth / MAX_UFRAME_SITD_XFER; 3388 if (sbandwidth % MAX_UFRAME_SITD_XFER) { 3389 uFrames++; 3390 } 3391 for (i = 0; i < uFrames; i++) { 3392 *smask = *smask << 1; 3393 *smask |= 0x1; 3394 } 3395 3396 found = 0; 3397 best_smask = 0x00; 3398 best_node_bandwidth = 0; 3399 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3400 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3401 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3402 &bw_smask); 3403 3404 /* 3405 * If this node cannot support our requirements skip to the 3406 * next leaf. 3407 */ 3408 if (bw_smask == 0x00) { 3409 continue; 3410 } 3411 3412 /* You cannot have a start split on the 8th uFrame */ 3413 for (i = 0; (*smask & 0x80) == 0; i++) { 3414 if (*smask & bw_smask) { 3415 found = 1; 3416 break; 3417 } 3418 *smask = *smask << 1; 3419 } 3420 3421 /* 3422 * If an appropriate smask is found save the information if: 3423 * o best_smask has not been found yet. 3424 * - or - 3425 * o This is the node with the least amount of bandwidth 3426 */ 3427 if (found && 3428 ((best_smask == 0x00) || 3429 (best_node_bandwidth > node_sbandwidth))) { 3430 best_node_bandwidth = node_sbandwidth; 3431 best_array_leaf = array_leaf; 3432 best_smask = *smask; 3433 } 3434 } 3435 3436 /* 3437 * If we find node that can handle the bandwidth populate the 3438 * appropriate variables and return success. 3439 */ 3440 if (best_smask) { 3441 *smask = best_smask; 3442 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3443 interval); 3444 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3445 ehci_index[best_array_leaf], leaf_count, best_smask); 3446 3447 return (USB_SUCCESS); 3448 } 3449 3450 return (USB_FAILURE); 3451 } 3452 3453 3454 /* 3455 * ehci_calculate_bw_availability_mask: 3456 * 3457 * Returns the "total bandwidth used" in this node. 3458 * Populates bw_mask with the uFrames that can support the bandwidth. 3459 * 3460 * If all the Frames cannot support this bandwidth, then bw_mask 3461 * will return 0x00 and the "total bandwidth used" will be invalid. 3462 */ 3463 static uint_t 3464 ehci_calculate_bw_availability_mask( 3465 ehci_state_t *ehcip, 3466 uint_t bandwidth, 3467 int leaf, 3468 int leaf_count, 3469 uchar_t *bw_mask) 3470 { 3471 int i, j; 3472 uchar_t bw_uframe; 3473 int uframe_total; 3474 ehci_frame_bandwidth_t *fbp; 3475 uint_t total_bandwidth = 0; 3476 3477 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3478 "ehci_calculate_bw_availability_mask: leaf %d leaf count %d", 3479 leaf, leaf_count); 3480 3481 /* Start by saying all uFrames are available */ 3482 *bw_mask = 0xFF; 3483 3484 for (i = 0; (i < leaf_count) || (*bw_mask == 0x00); i++) { 3485 fbp = &ehcip->ehci_frame_bandwidth[leaf + i]; 3486 3487 total_bandwidth += fbp->ehci_allocated_frame_bandwidth; 3488 3489 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3490 /* 3491 * If the uFrame in bw_mask is available check to see if 3492 * it can support the additional bandwidth. 3493 */ 3494 bw_uframe = (*bw_mask & (0x1 << j)); 3495 uframe_total = 3496 fbp->ehci_micro_frame_bandwidth[j] + 3497 bandwidth; 3498 if ((bw_uframe) && 3499 (uframe_total > HS_PERIODIC_BANDWIDTH)) { 3500 *bw_mask = *bw_mask & ~bw_uframe; 3501 } 3502 } 3503 } 3504 3505 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3506 "ehci_calculate_bw_availability_mask: bandwidth mask 0x%x", 3507 *bw_mask); 3508 3509 return (total_bandwidth); 3510 } 3511 3512 3513 /* 3514 * ehci_update_bw_availability: 3515 * 3516 * The leftmost leaf needs to be in terms of array position and 3517 * not the actual lattice position. 3518 */ 3519 static void 3520 ehci_update_bw_availability( 3521 ehci_state_t *ehcip, 3522 int bandwidth, 3523 int leftmost_leaf, 3524 int leaf_count, 3525 uchar_t mask) 3526 { 3527 int i, j; 3528 ehci_frame_bandwidth_t *fbp; 3529 int uFrame_bandwidth[8]; 3530 3531 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3532 "ehci_update_bw_availability: " 3533 "leaf %d count %d bandwidth 0x%x mask 0x%x", 3534 leftmost_leaf, leaf_count, bandwidth, mask); 3535 3536 ASSERT(leftmost_leaf < 32); 3537 ASSERT(leftmost_leaf >= 0); 3538 3539 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3540 if (mask & 0x1) { 3541 uFrame_bandwidth[j] = bandwidth; 3542 } else { 3543 uFrame_bandwidth[j] = 0; 3544 } 3545 3546 mask = mask >> 1; 3547 } 3548 3549 /* Updated all the effected leafs with the bandwidth */ 3550 for (i = 0; i < leaf_count; i++) { 3551 fbp = &ehcip->ehci_frame_bandwidth[leftmost_leaf + i]; 3552 3553 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3554 fbp->ehci_micro_frame_bandwidth[j] += 3555 uFrame_bandwidth[j]; 3556 fbp->ehci_allocated_frame_bandwidth += 3557 uFrame_bandwidth[j]; 3558 } 3559 } 3560 } 3561 3562 /* 3563 * Miscellaneous functions 3564 */ 3565 3566 /* 3567 * ehci_obtain_state: 3568 * 3569 * NOTE: This function is also called from POLLED MODE. 3570 */ 3571 ehci_state_t * 3572 ehci_obtain_state(dev_info_t *dip) 3573 { 3574 int instance = ddi_get_instance(dip); 3575 3576 ehci_state_t *state = ddi_get_soft_state(ehci_statep, instance); 3577 3578 ASSERT(state != NULL); 3579 3580 return (state); 3581 } 3582 3583 3584 /* 3585 * ehci_state_is_operational: 3586 * 3587 * Check the Host controller state and return proper values. 3588 */ 3589 int 3590 ehci_state_is_operational(ehci_state_t *ehcip) 3591 { 3592 int val; 3593 3594 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3595 3596 switch (ehcip->ehci_hc_soft_state) { 3597 case EHCI_CTLR_INIT_STATE: 3598 case EHCI_CTLR_SUSPEND_STATE: 3599 val = USB_FAILURE; 3600 break; 3601 case EHCI_CTLR_OPERATIONAL_STATE: 3602 val = USB_SUCCESS; 3603 break; 3604 case EHCI_CTLR_ERROR_STATE: 3605 val = USB_HC_HARDWARE_ERROR; 3606 break; 3607 default: 3608 val = USB_FAILURE; 3609 break; 3610 } 3611 3612 return (val); 3613 } 3614 3615 3616 /* 3617 * ehci_do_soft_reset 3618 * 3619 * Do soft reset of ehci host controller. 3620 */ 3621 int 3622 ehci_do_soft_reset(ehci_state_t *ehcip) 3623 { 3624 usb_frame_number_t before_frame_number, after_frame_number; 3625 ehci_regs_t *ehci_save_regs; 3626 3627 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3628 3629 /* Increment host controller error count */ 3630 ehcip->ehci_hc_error++; 3631 3632 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3633 "ehci_do_soft_reset:" 3634 "Reset ehci host controller 0x%x", ehcip->ehci_hc_error); 3635 3636 /* 3637 * Allocate space for saving current Host Controller 3638 * registers. Don't do any recovery if allocation 3639 * fails. 3640 */ 3641 ehci_save_regs = (ehci_regs_t *) 3642 kmem_zalloc(sizeof (ehci_regs_t), KM_NOSLEEP); 3643 3644 if (ehci_save_regs == NULL) { 3645 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3646 "ehci_do_soft_reset: kmem_zalloc failed"); 3647 3648 return (USB_FAILURE); 3649 } 3650 3651 /* Save current ehci registers */ 3652 ehci_save_regs->ehci_command = Get_OpReg(ehci_command); 3653 ehci_save_regs->ehci_interrupt = Get_OpReg(ehci_interrupt); 3654 ehci_save_regs->ehci_ctrl_segment = Get_OpReg(ehci_ctrl_segment); 3655 ehci_save_regs->ehci_async_list_addr = Get_OpReg(ehci_async_list_addr); 3656 ehci_save_regs->ehci_config_flag = Get_OpReg(ehci_config_flag); 3657 ehci_save_regs->ehci_periodic_list_base = 3658 Get_OpReg(ehci_periodic_list_base); 3659 3660 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3661 "ehci_do_soft_reset: Save reg = 0x%p", ehci_save_regs); 3662 3663 /* Disable all list processing and interrupts */ 3664 Set_OpReg(ehci_command, Get_OpReg(ehci_command) & 3665 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE)); 3666 3667 /* Disable all EHCI interrupts */ 3668 Set_OpReg(ehci_interrupt, 0); 3669 3670 /* Wait for few milliseconds */ 3671 drv_usecwait(EHCI_SOF_TIMEWAIT); 3672 3673 /* Do light soft reset of ehci host controller */ 3674 Set_OpReg(ehci_command, 3675 Get_OpReg(ehci_command) | EHCI_CMD_LIGHT_HC_RESET); 3676 3677 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3678 "ehci_do_soft_reset: Reset in progress"); 3679 3680 /* Wait for reset to complete */ 3681 drv_usecwait(EHCI_RESET_TIMEWAIT); 3682 3683 /* 3684 * Restore previous saved EHCI register value 3685 * into the current EHCI registers. 3686 */ 3687 Set_OpReg(ehci_ctrl_segment, (uint32_t) 3688 ehci_save_regs->ehci_ctrl_segment); 3689 3690 Set_OpReg(ehci_periodic_list_base, (uint32_t) 3691 ehci_save_regs->ehci_periodic_list_base); 3692 3693 Set_OpReg(ehci_async_list_addr, (uint32_t) 3694 ehci_save_regs->ehci_async_list_addr); 3695 3696 /* 3697 * For some reason this register might get nulled out by 3698 * the Uli M1575 South Bridge. To workaround the hardware 3699 * problem, check the value after write and retry if the 3700 * last write fails. 3701 */ 3702 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 3703 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) && 3704 (ehci_save_regs->ehci_async_list_addr != 3705 Get_OpReg(ehci_async_list_addr))) { 3706 int retry = 0; 3707 3708 Set_OpRegRetry(ehci_async_list_addr, (uint32_t) 3709 ehci_save_regs->ehci_async_list_addr, retry); 3710 if (retry >= EHCI_MAX_RETRY) { 3711 USB_DPRINTF_L2(PRINT_MASK_ATTA, 3712 ehcip->ehci_log_hdl, "ehci_do_soft_reset:" 3713 " ASYNCLISTADDR write failed."); 3714 3715 return (USB_FAILURE); 3716 } 3717 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3718 "ehci_do_soft_reset: ASYNCLISTADDR " 3719 "write failed, retry=%d", retry); 3720 } 3721 3722 Set_OpReg(ehci_config_flag, (uint32_t) 3723 ehci_save_regs->ehci_config_flag); 3724 3725 /* Enable both Asynchronous and Periodic Schedule if necessary */ 3726 ehci_toggle_scheduler(ehcip); 3727 3728 /* 3729 * Set ehci_interrupt to enable all interrupts except Root 3730 * Hub Status change and frame list rollover interrupts. 3731 */ 3732 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 3733 EHCI_INTR_FRAME_LIST_ROLLOVER | 3734 EHCI_INTR_USB_ERROR | 3735 EHCI_INTR_USB); 3736 3737 /* 3738 * Deallocate the space that allocated for saving 3739 * HC registers. 3740 */ 3741 kmem_free((void *) ehci_save_regs, sizeof (ehci_regs_t)); 3742 3743 /* 3744 * Set the desired interrupt threshold, frame list size (if 3745 * applicable) and turn EHCI host controller. 3746 */ 3747 Set_OpReg(ehci_command, ((Get_OpReg(ehci_command) & 3748 ~EHCI_CMD_INTR_THRESHOLD) | 3749 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 3750 3751 /* Wait 10ms for EHCI to start sending SOF */ 3752 drv_usecwait(EHCI_RESET_TIMEWAIT); 3753 3754 /* 3755 * Get the current usb frame number before waiting for 3756 * few milliseconds. 3757 */ 3758 before_frame_number = ehci_get_current_frame_number(ehcip); 3759 3760 /* Wait for few milliseconds */ 3761 drv_usecwait(EHCI_SOF_TIMEWAIT); 3762 3763 /* 3764 * Get the current usb frame number after waiting for 3765 * few milliseconds. 3766 */ 3767 after_frame_number = ehci_get_current_frame_number(ehcip); 3768 3769 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3770 "ehci_do_soft_reset: Before Frame Number 0x%llx " 3771 "After Frame Number 0x%llx", 3772 before_frame_number, after_frame_number); 3773 3774 if ((after_frame_number <= before_frame_number) && 3775 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 3776 3777 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3778 "ehci_do_soft_reset: Soft reset failed"); 3779 3780 return (USB_FAILURE); 3781 } 3782 3783 return (USB_SUCCESS); 3784 } 3785 3786 3787 /* 3788 * ehci_get_xfer_attrs: 3789 * 3790 * Get the attributes of a particular xfer. 3791 * 3792 * NOTE: This function is also called from POLLED MODE. 3793 */ 3794 usb_req_attrs_t 3795 ehci_get_xfer_attrs( 3796 ehci_state_t *ehcip, 3797 ehci_pipe_private_t *pp, 3798 ehci_trans_wrapper_t *tw) 3799 { 3800 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 3801 usb_req_attrs_t attrs = USB_ATTRS_NONE; 3802 3803 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3804 "ehci_get_xfer_attrs:"); 3805 3806 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 3807 case USB_EP_ATTR_CONTROL: 3808 attrs = ((usb_ctrl_req_t *) 3809 tw->tw_curr_xfer_reqp)->ctrl_attributes; 3810 break; 3811 case USB_EP_ATTR_BULK: 3812 attrs = ((usb_bulk_req_t *) 3813 tw->tw_curr_xfer_reqp)->bulk_attributes; 3814 break; 3815 case USB_EP_ATTR_INTR: 3816 attrs = ((usb_intr_req_t *) 3817 tw->tw_curr_xfer_reqp)->intr_attributes; 3818 break; 3819 } 3820 3821 return (attrs); 3822 } 3823 3824 3825 /* 3826 * ehci_get_current_frame_number: 3827 * 3828 * Get the current software based usb frame number. 3829 */ 3830 usb_frame_number_t 3831 ehci_get_current_frame_number(ehci_state_t *ehcip) 3832 { 3833 usb_frame_number_t usb_frame_number; 3834 usb_frame_number_t ehci_fno, micro_frame_number; 3835 3836 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3837 3838 ehci_fno = ehcip->ehci_fno; 3839 micro_frame_number = Get_OpReg(ehci_frame_index) & 0x3FFF; 3840 3841 /* 3842 * Calculate current software based usb frame number. 3843 * 3844 * This code accounts for the fact that frame number is 3845 * updated by the Host Controller before the ehci driver 3846 * gets an FrameListRollover interrupt that will adjust 3847 * Frame higher part. 3848 * 3849 * Refer ehci specification 1.0, section 2.3.2, page 21. 3850 */ 3851 micro_frame_number = ((micro_frame_number & 0x1FFF) | 3852 ehci_fno) + (((micro_frame_number & 0x3FFF) ^ 3853 ehci_fno) & 0x2000); 3854 3855 /* 3856 * Micro Frame number is equivalent to 125 usec. Eight 3857 * Micro Frame numbers are equivalent to one millsecond 3858 * or one usb frame number. 3859 */ 3860 usb_frame_number = micro_frame_number >> 3861 EHCI_uFRAMES_PER_USB_FRAME_SHIFT; 3862 3863 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3864 "ehci_get_current_frame_number: " 3865 "Current usb uframe number = 0x%llx " 3866 "Current usb frame number = 0x%llx", 3867 micro_frame_number, usb_frame_number); 3868 3869 return (usb_frame_number); 3870 } 3871 3872 3873 /* 3874 * ehci_cpr_cleanup: 3875 * 3876 * Cleanup ehci state and other ehci specific informations across 3877 * Check Point Resume (CPR). 3878 */ 3879 static void 3880 ehci_cpr_cleanup(ehci_state_t *ehcip) 3881 { 3882 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3883 3884 /* Reset software part of usb frame number */ 3885 ehcip->ehci_fno = 0; 3886 } 3887 3888 3889 /* 3890 * ehci_wait_for_sof: 3891 * 3892 * Wait for couple of SOF interrupts 3893 */ 3894 int 3895 ehci_wait_for_sof(ehci_state_t *ehcip) 3896 { 3897 usb_frame_number_t before_frame_number, after_frame_number; 3898 int error = USB_SUCCESS; 3899 3900 USB_DPRINTF_L4(PRINT_MASK_LISTS, 3901 ehcip->ehci_log_hdl, "ehci_wait_for_sof"); 3902 3903 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3904 3905 error = ehci_state_is_operational(ehcip); 3906 3907 if (error != USB_SUCCESS) { 3908 3909 return (error); 3910 } 3911 3912 /* Get the current usb frame number before waiting for two SOFs */ 3913 before_frame_number = ehci_get_current_frame_number(ehcip); 3914 3915 mutex_exit(&ehcip->ehci_int_mutex); 3916 3917 /* Wait for few milliseconds */ 3918 delay(drv_usectohz(EHCI_SOF_TIMEWAIT)); 3919 3920 mutex_enter(&ehcip->ehci_int_mutex); 3921 3922 /* Get the current usb frame number after woken up */ 3923 after_frame_number = ehci_get_current_frame_number(ehcip); 3924 3925 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3926 "ehci_wait_for_sof: framenumber: before 0x%llx " 3927 "after 0x%llx", before_frame_number, after_frame_number); 3928 3929 /* Return failure, if usb frame number has not been changed */ 3930 if (after_frame_number <= before_frame_number) { 3931 3932 if ((ehci_do_soft_reset(ehcip)) != USB_SUCCESS) { 3933 3934 USB_DPRINTF_L0(PRINT_MASK_LISTS, 3935 ehcip->ehci_log_hdl, "No SOF interrupts"); 3936 3937 /* Set host controller soft state to error */ 3938 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 3939 3940 return (USB_FAILURE); 3941 } 3942 3943 /* Get new usb frame number */ 3944 after_frame_number = before_frame_number = 3945 ehci_get_current_frame_number(ehcip); 3946 } 3947 3948 ASSERT(after_frame_number > before_frame_number); 3949 3950 return (USB_SUCCESS); 3951 } 3952 3953 3954 /* 3955 * ehci_toggle_scheduler: 3956 * 3957 * Turn scheduler based on pipe open count. 3958 */ 3959 void 3960 ehci_toggle_scheduler(ehci_state_t *ehcip) { 3961 uint_t temp_reg, cmd_reg; 3962 3963 cmd_reg = Get_OpReg(ehci_command); 3964 temp_reg = cmd_reg; 3965 3966 /* 3967 * Enable/Disable asynchronous scheduler, and 3968 * turn on/off async list door bell 3969 */ 3970 if (ehcip->ehci_open_async_count) { 3971 if (!(cmd_reg & EHCI_CMD_ASYNC_SCHED_ENABLE)) { 3972 /* 3973 * For some reason this address might get nulled out by 3974 * the ehci chip. Set it here just in case it is null. 3975 */ 3976 Set_OpReg(ehci_async_list_addr, 3977 ehci_qh_cpu_to_iommu(ehcip, 3978 ehcip->ehci_head_of_async_sched_list)); 3979 3980 /* 3981 * For some reason this register might get nulled out by 3982 * the Uli M1575 Southbridge. To workaround the HW 3983 * problem, check the value after write and retry if the 3984 * last write fails. 3985 * 3986 * If the ASYNCLISTADDR remains "stuck" after 3987 * EHCI_MAX_RETRY retries, then the M1575 is broken 3988 * and is stuck in an inconsistent state and is about 3989 * to crash the machine with a trn_oor panic when it 3990 * does a DMA read from 0x0. It is better to panic 3991 * now rather than wait for the trn_oor crash; this 3992 * way Customer Service will have a clean signature 3993 * that indicts the M1575 chip rather than a 3994 * mysterious and hard-to-diagnose trn_oor panic. 3995 */ 3996 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 3997 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) && 3998 (ehci_qh_cpu_to_iommu(ehcip, 3999 ehcip->ehci_head_of_async_sched_list) != 4000 Get_OpReg(ehci_async_list_addr))) { 4001 int retry = 0; 4002 4003 Set_OpRegRetry(ehci_async_list_addr, 4004 ehci_qh_cpu_to_iommu(ehcip, 4005 ehcip->ehci_head_of_async_sched_list), 4006 retry); 4007 if (retry >= EHCI_MAX_RETRY) 4008 cmn_err(CE_PANIC, 4009 "ehci_toggle_scheduler: " 4010 "ASYNCLISTADDR write failed."); 4011 4012 USB_DPRINTF_L2(PRINT_MASK_ATTA, 4013 ehcip->ehci_log_hdl, 4014 "ehci_toggle_scheduler: ASYNCLISTADDR " 4015 "write failed, retry=%d", retry); 4016 } 4017 } 4018 cmd_reg |= EHCI_CMD_ASYNC_SCHED_ENABLE; 4019 } else { 4020 cmd_reg &= ~EHCI_CMD_ASYNC_SCHED_ENABLE; 4021 } 4022 4023 if (ehcip->ehci_open_periodic_count) { 4024 if (!(cmd_reg & EHCI_CMD_PERIODIC_SCHED_ENABLE)) { 4025 /* 4026 * For some reason this address get's nulled out by 4027 * the ehci chip. Set it here just in case it is null. 4028 */ 4029 Set_OpReg(ehci_periodic_list_base, 4030 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 4031 0xFFFFF000)); 4032 } 4033 cmd_reg |= EHCI_CMD_PERIODIC_SCHED_ENABLE; 4034 } else { 4035 cmd_reg &= ~EHCI_CMD_PERIODIC_SCHED_ENABLE; 4036 } 4037 4038 /* Just an optimization */ 4039 if (temp_reg != cmd_reg) { 4040 Set_OpReg(ehci_command, cmd_reg); 4041 } 4042 } 4043 4044 /* 4045 * ehci print functions 4046 */ 4047 4048 /* 4049 * ehci_print_caps: 4050 */ 4051 void 4052 ehci_print_caps(ehci_state_t *ehcip) 4053 { 4054 uint_t i; 4055 4056 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4057 "\n\tUSB 2.0 Host Controller Characteristics\n"); 4058 4059 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4060 "Caps Length: 0x%x Version: 0x%x\n", 4061 Get_8Cap(ehci_caps_length), Get_16Cap(ehci_version)); 4062 4063 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4064 "Structural Parameters\n"); 4065 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4066 "Port indicators: %s", (Get_Cap(ehci_hcs_params) & 4067 EHCI_HCS_PORT_INDICATOR) ? "Yes" : "No"); 4068 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4069 "No of Classic host controllers: 0x%x", 4070 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_COMP_CTRLS) 4071 >> EHCI_HCS_NUM_COMP_CTRL_SHIFT); 4072 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4073 "No of ports per Classic host controller: 0x%x", 4074 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS_CC) 4075 >> EHCI_HCS_NUM_PORTS_CC_SHIFT); 4076 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4077 "Port routing rules: %s", (Get_Cap(ehci_hcs_params) & 4078 EHCI_HCS_PORT_ROUTING_RULES) ? "Yes" : "No"); 4079 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4080 "Port power control: %s", (Get_Cap(ehci_hcs_params) & 4081 EHCI_HCS_PORT_POWER_CONTROL) ? "Yes" : "No"); 4082 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4083 "No of root hub ports: 0x%x\n", 4084 Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); 4085 4086 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4087 "Capability Parameters\n"); 4088 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4089 "EHCI extended capability: %s", (Get_Cap(ehci_hcc_params) & 4090 EHCI_HCC_EECP) ? "Yes" : "No"); 4091 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4092 "Isoch schedule threshold: 0x%x", 4093 Get_Cap(ehci_hcc_params) & EHCI_HCC_ISOCH_SCHED_THRESHOLD); 4094 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4095 "Async schedule park capability: %s", (Get_Cap(ehci_hcc_params) & 4096 EHCI_HCC_ASYNC_SCHED_PARK_CAP) ? "Yes" : "No"); 4097 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4098 "Programmable frame list flag: %s", (Get_Cap(ehci_hcc_params) & 4099 EHCI_HCC_PROG_FRAME_LIST_FLAG) ? "256/512/1024" : "1024"); 4100 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4101 "64bit addressing capability: %s\n", (Get_Cap(ehci_hcc_params) & 4102 EHCI_HCC_64BIT_ADDR_CAP) ? "Yes" : "No"); 4103 4104 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4105 "Classic Port Route Description"); 4106 4107 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4108 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4109 "\tPort Route 0x%x: 0x%x", i, Get_8Cap(ehci_port_route[i])); 4110 } 4111 } 4112 4113 4114 /* 4115 * ehci_print_regs: 4116 */ 4117 void 4118 ehci_print_regs(ehci_state_t *ehcip) 4119 { 4120 uint_t i; 4121 4122 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4123 "\n\tEHCI%d Operational Registers\n", 4124 ddi_get_instance(ehcip->ehci_dip)); 4125 4126 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4127 "Command: 0x%x Status: 0x%x", 4128 Get_OpReg(ehci_command), Get_OpReg(ehci_status)); 4129 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4130 "Interrupt: 0x%x Frame Index: 0x%x", 4131 Get_OpReg(ehci_interrupt), Get_OpReg(ehci_frame_index)); 4132 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4133 "Control Segment: 0x%x Periodic List Base: 0x%x", 4134 Get_OpReg(ehci_ctrl_segment), Get_OpReg(ehci_periodic_list_base)); 4135 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4136 "Async List Addr: 0x%x Config Flag: 0x%x", 4137 Get_OpReg(ehci_async_list_addr), Get_OpReg(ehci_config_flag)); 4138 4139 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4140 "Root Hub Port Status"); 4141 4142 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4143 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4144 "\tPort Status 0x%x: 0x%x ", i, 4145 Get_OpReg(ehci_rh_port_status[i])); 4146 } 4147 } 4148 4149 4150 /* 4151 * ehci_print_qh: 4152 */ 4153 void 4154 ehci_print_qh( 4155 ehci_state_t *ehcip, 4156 ehci_qh_t *qh) 4157 { 4158 uint_t i; 4159 4160 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4161 "ehci_print_qh: qh = 0x%p", (void *)qh); 4162 4163 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4164 "\tqh_link_ptr: 0x%x ", Get_QH(qh->qh_link_ptr)); 4165 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4166 "\tqh_ctrl: 0x%x ", Get_QH(qh->qh_ctrl)); 4167 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4168 "\tqh_split_ctrl: 0x%x ", Get_QH(qh->qh_split_ctrl)); 4169 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4170 "\tqh_curr_qtd: 0x%x ", Get_QH(qh->qh_curr_qtd)); 4171 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4172 "\tqh_next_qtd: 0x%x ", Get_QH(qh->qh_next_qtd)); 4173 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4174 "\tqh_alt_next_qtd: 0x%x ", Get_QH(qh->qh_alt_next_qtd)); 4175 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4176 "\tqh_status: 0x%x ", Get_QH(qh->qh_status)); 4177 4178 for (i = 0; i < 5; i++) { 4179 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4180 "\tqh_buf[%d]: 0x%x ", i, Get_QH(qh->qh_buf[i])); 4181 } 4182 4183 for (i = 0; i < 5; i++) { 4184 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4185 "\tqh_buf_high[%d]: 0x%x ", 4186 i, Get_QH(qh->qh_buf_high[i])); 4187 } 4188 4189 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4190 "\tqh_dummy_qtd: 0x%x ", Get_QH(qh->qh_dummy_qtd)); 4191 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4192 "\tqh_prev: 0x%x ", Get_QH(qh->qh_prev)); 4193 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4194 "\tqh_state: 0x%x ", Get_QH(qh->qh_state)); 4195 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4196 "\tqh_reclaim_next: 0x%x ", Get_QH(qh->qh_reclaim_next)); 4197 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4198 "\tqh_reclaim_frame: 0x%x ", Get_QH(qh->qh_reclaim_frame)); 4199 } 4200 4201 4202 /* 4203 * ehci_print_qtd: 4204 */ 4205 void 4206 ehci_print_qtd( 4207 ehci_state_t *ehcip, 4208 ehci_qtd_t *qtd) 4209 { 4210 uint_t i; 4211 4212 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4213 "ehci_print_qtd: qtd = 0x%p", (void *)qtd); 4214 4215 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4216 "\tqtd_next_qtd: 0x%x ", Get_QTD(qtd->qtd_next_qtd)); 4217 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4218 "\tqtd_alt_next_qtd: 0x%x ", Get_QTD(qtd->qtd_alt_next_qtd)); 4219 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4220 "\tqtd_ctrl: 0x%x ", Get_QTD(qtd->qtd_ctrl)); 4221 4222 for (i = 0; i < 5; i++) { 4223 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4224 "\tqtd_buf[%d]: 0x%x ", i, Get_QTD(qtd->qtd_buf[i])); 4225 } 4226 4227 for (i = 0; i < 5; i++) { 4228 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4229 "\tqtd_buf_high[%d]: 0x%x ", 4230 i, Get_QTD(qtd->qtd_buf_high[i])); 4231 } 4232 4233 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4234 "\tqtd_trans_wrapper: 0x%x ", Get_QTD(qtd->qtd_trans_wrapper)); 4235 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4236 "\tqtd_tw_next_qtd: 0x%x ", Get_QTD(qtd->qtd_tw_next_qtd)); 4237 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4238 "\tqtd_active_qtd_next: 0x%x ", Get_QTD(qtd->qtd_active_qtd_next)); 4239 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4240 "\tqtd_active_qtd_prev: 0x%x ", Get_QTD(qtd->qtd_active_qtd_prev)); 4241 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4242 "\tqtd_state: 0x%x ", Get_QTD(qtd->qtd_state)); 4243 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4244 "\tqtd_ctrl_phase: 0x%x ", Get_QTD(qtd->qtd_ctrl_phase)); 4245 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4246 "\tqtd_xfer_offs: 0x%x ", Get_QTD(qtd->qtd_xfer_offs)); 4247 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4248 "\tqtd_xfer_len: 0x%x ", Get_QTD(qtd->qtd_xfer_len)); 4249 } 4250 4251 /* 4252 * ehci kstat functions 4253 */ 4254 4255 /* 4256 * ehci_create_stats: 4257 * 4258 * Allocate and initialize the ehci kstat structures 4259 */ 4260 void 4261 ehci_create_stats(ehci_state_t *ehcip) 4262 { 4263 char kstatname[KSTAT_STRLEN]; 4264 const char *dname = ddi_driver_name(ehcip->ehci_dip); 4265 char *usbtypes[USB_N_COUNT_KSTATS] = 4266 {"ctrl", "isoch", "bulk", "intr"}; 4267 uint_t instance = ehcip->ehci_instance; 4268 ehci_intrs_stats_t *isp; 4269 int i; 4270 4271 if (EHCI_INTRS_STATS(ehcip) == NULL) { 4272 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs", 4273 dname, instance); 4274 EHCI_INTRS_STATS(ehcip) = kstat_create("usba", instance, 4275 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED, 4276 sizeof (ehci_intrs_stats_t) / sizeof (kstat_named_t), 4277 KSTAT_FLAG_PERSISTENT); 4278 4279 if (EHCI_INTRS_STATS(ehcip)) { 4280 isp = EHCI_INTRS_STATS_DATA(ehcip); 4281 kstat_named_init(&isp->ehci_sts_total, 4282 "Interrupts Total", KSTAT_DATA_UINT64); 4283 kstat_named_init(&isp->ehci_sts_not_claimed, 4284 "Not Claimed", KSTAT_DATA_UINT64); 4285 kstat_named_init(&isp->ehci_sts_async_sched_status, 4286 "Async schedule status", KSTAT_DATA_UINT64); 4287 kstat_named_init(&isp->ehci_sts_periodic_sched_status, 4288 "Periodic sched status", KSTAT_DATA_UINT64); 4289 kstat_named_init(&isp->ehci_sts_empty_async_schedule, 4290 "Empty async schedule", KSTAT_DATA_UINT64); 4291 kstat_named_init(&isp->ehci_sts_host_ctrl_halted, 4292 "Host controller Halted", KSTAT_DATA_UINT64); 4293 kstat_named_init(&isp->ehci_sts_async_advance_intr, 4294 "Intr on async advance", KSTAT_DATA_UINT64); 4295 kstat_named_init(&isp->ehci_sts_host_system_error_intr, 4296 "Host system error", KSTAT_DATA_UINT64); 4297 kstat_named_init(&isp->ehci_sts_frm_list_rollover_intr, 4298 "Frame list rollover", KSTAT_DATA_UINT64); 4299 kstat_named_init(&isp->ehci_sts_rh_port_change_intr, 4300 "Port change detect", KSTAT_DATA_UINT64); 4301 kstat_named_init(&isp->ehci_sts_usb_error_intr, 4302 "USB error interrupt", KSTAT_DATA_UINT64); 4303 kstat_named_init(&isp->ehci_sts_usb_intr, 4304 "USB interrupt", KSTAT_DATA_UINT64); 4305 4306 EHCI_INTRS_STATS(ehcip)->ks_private = ehcip; 4307 EHCI_INTRS_STATS(ehcip)->ks_update = nulldev; 4308 kstat_install(EHCI_INTRS_STATS(ehcip)); 4309 } 4310 } 4311 4312 if (EHCI_TOTAL_STATS(ehcip) == NULL) { 4313 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total", 4314 dname, instance); 4315 EHCI_TOTAL_STATS(ehcip) = kstat_create("usba", instance, 4316 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1, 4317 KSTAT_FLAG_PERSISTENT); 4318 4319 if (EHCI_TOTAL_STATS(ehcip)) { 4320 kstat_install(EHCI_TOTAL_STATS(ehcip)); 4321 } 4322 } 4323 4324 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4325 if (ehcip->ehci_count_stats[i] == NULL) { 4326 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s", 4327 dname, instance, usbtypes[i]); 4328 ehcip->ehci_count_stats[i] = kstat_create("usba", 4329 instance, kstatname, "usb_byte_count", 4330 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 4331 4332 if (ehcip->ehci_count_stats[i]) { 4333 kstat_install(ehcip->ehci_count_stats[i]); 4334 } 4335 } 4336 } 4337 } 4338 4339 4340 /* 4341 * ehci_destroy_stats: 4342 * 4343 * Clean up ehci kstat structures 4344 */ 4345 void 4346 ehci_destroy_stats(ehci_state_t *ehcip) 4347 { 4348 int i; 4349 4350 if (EHCI_INTRS_STATS(ehcip)) { 4351 kstat_delete(EHCI_INTRS_STATS(ehcip)); 4352 EHCI_INTRS_STATS(ehcip) = NULL; 4353 } 4354 4355 if (EHCI_TOTAL_STATS(ehcip)) { 4356 kstat_delete(EHCI_TOTAL_STATS(ehcip)); 4357 EHCI_TOTAL_STATS(ehcip) = NULL; 4358 } 4359 4360 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4361 if (ehcip->ehci_count_stats[i]) { 4362 kstat_delete(ehcip->ehci_count_stats[i]); 4363 ehcip->ehci_count_stats[i] = NULL; 4364 } 4365 } 4366 } 4367 4368 4369 /* 4370 * ehci_do_intrs_stats: 4371 * 4372 * ehci status information 4373 */ 4374 void 4375 ehci_do_intrs_stats( 4376 ehci_state_t *ehcip, 4377 int val) 4378 { 4379 if (EHCI_INTRS_STATS(ehcip)) { 4380 EHCI_INTRS_STATS_DATA(ehcip)->ehci_sts_total.value.ui64++; 4381 switch (val) { 4382 case EHCI_STS_ASYNC_SCHED_STATUS: 4383 EHCI_INTRS_STATS_DATA(ehcip)-> 4384 ehci_sts_async_sched_status.value.ui64++; 4385 break; 4386 case EHCI_STS_PERIODIC_SCHED_STATUS: 4387 EHCI_INTRS_STATS_DATA(ehcip)-> 4388 ehci_sts_periodic_sched_status.value.ui64++; 4389 break; 4390 case EHCI_STS_EMPTY_ASYNC_SCHEDULE: 4391 EHCI_INTRS_STATS_DATA(ehcip)-> 4392 ehci_sts_empty_async_schedule.value.ui64++; 4393 break; 4394 case EHCI_STS_HOST_CTRL_HALTED: 4395 EHCI_INTRS_STATS_DATA(ehcip)-> 4396 ehci_sts_host_ctrl_halted.value.ui64++; 4397 break; 4398 case EHCI_STS_ASYNC_ADVANCE_INTR: 4399 EHCI_INTRS_STATS_DATA(ehcip)-> 4400 ehci_sts_async_advance_intr.value.ui64++; 4401 break; 4402 case EHCI_STS_HOST_SYSTEM_ERROR_INTR: 4403 EHCI_INTRS_STATS_DATA(ehcip)-> 4404 ehci_sts_host_system_error_intr.value.ui64++; 4405 break; 4406 case EHCI_STS_FRM_LIST_ROLLOVER_INTR: 4407 EHCI_INTRS_STATS_DATA(ehcip)-> 4408 ehci_sts_frm_list_rollover_intr.value.ui64++; 4409 break; 4410 case EHCI_STS_RH_PORT_CHANGE_INTR: 4411 EHCI_INTRS_STATS_DATA(ehcip)-> 4412 ehci_sts_rh_port_change_intr.value.ui64++; 4413 break; 4414 case EHCI_STS_USB_ERROR_INTR: 4415 EHCI_INTRS_STATS_DATA(ehcip)-> 4416 ehci_sts_usb_error_intr.value.ui64++; 4417 break; 4418 case EHCI_STS_USB_INTR: 4419 EHCI_INTRS_STATS_DATA(ehcip)-> 4420 ehci_sts_usb_intr.value.ui64++; 4421 break; 4422 default: 4423 EHCI_INTRS_STATS_DATA(ehcip)-> 4424 ehci_sts_not_claimed.value.ui64++; 4425 break; 4426 } 4427 } 4428 } 4429 4430 4431 /* 4432 * ehci_do_byte_stats: 4433 * 4434 * ehci data xfer information 4435 */ 4436 void 4437 ehci_do_byte_stats( 4438 ehci_state_t *ehcip, 4439 size_t len, 4440 uint8_t attr, 4441 uint8_t addr) 4442 { 4443 uint8_t type = attr & USB_EP_ATTR_MASK; 4444 uint8_t dir = addr & USB_EP_DIR_MASK; 4445 4446 if (dir == USB_EP_DIR_IN) { 4447 EHCI_TOTAL_STATS_DATA(ehcip)->reads++; 4448 EHCI_TOTAL_STATS_DATA(ehcip)->nread += len; 4449 switch (type) { 4450 case USB_EP_ATTR_CONTROL: 4451 EHCI_CTRL_STATS(ehcip)->reads++; 4452 EHCI_CTRL_STATS(ehcip)->nread += len; 4453 break; 4454 case USB_EP_ATTR_BULK: 4455 EHCI_BULK_STATS(ehcip)->reads++; 4456 EHCI_BULK_STATS(ehcip)->nread += len; 4457 break; 4458 case USB_EP_ATTR_INTR: 4459 EHCI_INTR_STATS(ehcip)->reads++; 4460 EHCI_INTR_STATS(ehcip)->nread += len; 4461 break; 4462 case USB_EP_ATTR_ISOCH: 4463 EHCI_ISOC_STATS(ehcip)->reads++; 4464 EHCI_ISOC_STATS(ehcip)->nread += len; 4465 break; 4466 } 4467 } else if (dir == USB_EP_DIR_OUT) { 4468 EHCI_TOTAL_STATS_DATA(ehcip)->writes++; 4469 EHCI_TOTAL_STATS_DATA(ehcip)->nwritten += len; 4470 switch (type) { 4471 case USB_EP_ATTR_CONTROL: 4472 EHCI_CTRL_STATS(ehcip)->writes++; 4473 EHCI_CTRL_STATS(ehcip)->nwritten += len; 4474 break; 4475 case USB_EP_ATTR_BULK: 4476 EHCI_BULK_STATS(ehcip)->writes++; 4477 EHCI_BULK_STATS(ehcip)->nwritten += len; 4478 break; 4479 case USB_EP_ATTR_INTR: 4480 EHCI_INTR_STATS(ehcip)->writes++; 4481 EHCI_INTR_STATS(ehcip)->nwritten += len; 4482 break; 4483 case USB_EP_ATTR_ISOCH: 4484 EHCI_ISOC_STATS(ehcip)->writes++; 4485 EHCI_ISOC_STATS(ehcip)->nwritten += len; 4486 break; 4487 } 4488 } 4489 } 4490