1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * EHCI Host Controller Driver (EHCI) 30 * 31 * The EHCI driver is a software driver which interfaces to the Universal 32 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 33 * the Host Controller is defined by the EHCI Host Controller Interface. 34 * 35 * This module contains the main EHCI driver code which handles all USB 36 * transfers, bandwidth allocations and other general functionalities. 37 */ 38 39 #include <sys/usb/hcd/ehci/ehcid.h> 40 #include <sys/usb/hcd/ehci/ehci_isoch.h> 41 #include <sys/usb/hcd/ehci/ehci_xfer.h> 42 43 /* 44 * EHCI MSI tunable: 45 * 46 * By default MSI is enabled on all supported platforms except for the 47 * EHCI controller of ULI1575 South bridge. 48 */ 49 boolean_t ehci_enable_msi = B_TRUE; 50 51 /* Pointer to the state structure */ 52 extern void *ehci_statep; 53 54 extern void ehci_handle_endpoint_reclaimation(ehci_state_t *); 55 56 extern uint_t ehci_vt62x2_workaround; 57 58 /* Adjustable variables for the size of the pools */ 59 int ehci_qh_pool_size = EHCI_QH_POOL_SIZE; 60 int ehci_qtd_pool_size = EHCI_QTD_POOL_SIZE; 61 62 /* 63 * Initialize the values which the order of 32ms intr qh are executed 64 * by the host controller in the lattice tree. 65 */ 66 static uchar_t ehci_index[EHCI_NUM_INTR_QH_LISTS] = 67 {0x00, 0x10, 0x08, 0x18, 68 0x04, 0x14, 0x0c, 0x1c, 69 0x02, 0x12, 0x0a, 0x1a, 70 0x06, 0x16, 0x0e, 0x1e, 71 0x01, 0x11, 0x09, 0x19, 72 0x05, 0x15, 0x0d, 0x1d, 73 0x03, 0x13, 0x0b, 0x1b, 74 0x07, 0x17, 0x0f, 0x1f}; 75 76 /* 77 * Initialize the values which are used to calculate start split mask 78 * for the low/full/high speed interrupt and isochronous endpoints. 79 */ 80 static uint_t ehci_start_split_mask[15] = { 81 /* 82 * For high/full/low speed usb devices. For high speed 83 * device with polling interval greater than or equal 84 * to 8us (125us). 85 */ 86 0x01, /* 00000001 */ 87 0x02, /* 00000010 */ 88 0x04, /* 00000100 */ 89 0x08, /* 00001000 */ 90 0x10, /* 00010000 */ 91 0x20, /* 00100000 */ 92 0x40, /* 01000000 */ 93 0x80, /* 10000000 */ 94 95 /* Only for high speed devices with polling interval 4us */ 96 0x11, /* 00010001 */ 97 0x22, /* 00100010 */ 98 0x44, /* 01000100 */ 99 0x88, /* 10001000 */ 100 101 /* Only for high speed devices with polling interval 2us */ 102 0x55, /* 01010101 */ 103 0xaa, /* 10101010 */ 104 105 /* Only for high speed devices with polling interval 1us */ 106 0xff /* 11111111 */ 107 }; 108 109 /* 110 * Initialize the values which are used to calculate complete split mask 111 * for the low/full speed interrupt and isochronous endpoints. 112 */ 113 static uint_t ehci_intr_complete_split_mask[7] = { 114 /* Only full/low speed devices */ 115 0x1c, /* 00011100 */ 116 0x38, /* 00111000 */ 117 0x70, /* 01110000 */ 118 0xe0, /* 11100000 */ 119 0x00, /* Need FSTN feature */ 120 0x00, /* Need FSTN feature */ 121 0x00 /* Need FSTN feature */ 122 }; 123 124 125 /* 126 * EHCI Internal Function Prototypes 127 */ 128 129 /* Host Controller Driver (HCD) initialization functions */ 130 void ehci_set_dma_attributes(ehci_state_t *ehcip); 131 int ehci_allocate_pools(ehci_state_t *ehcip); 132 void ehci_decode_ddi_dma_addr_bind_handle_result( 133 ehci_state_t *ehcip, 134 int result); 135 int ehci_map_regs(ehci_state_t *ehcip); 136 int ehci_register_intrs_and_init_mutex( 137 ehci_state_t *ehcip); 138 static int ehci_add_intrs(ehci_state_t *ehcip, 139 int intr_type); 140 int ehci_init_ctlr(ehci_state_t *ehcip, 141 int init_type); 142 static int ehci_take_control(ehci_state_t *ehcip); 143 static int ehci_init_periodic_frame_lst_table( 144 ehci_state_t *ehcip); 145 static void ehci_build_interrupt_lattice( 146 ehci_state_t *ehcip); 147 usba_hcdi_ops_t *ehci_alloc_hcdi_ops(ehci_state_t *ehcip); 148 149 /* Host Controller Driver (HCD) deinitialization functions */ 150 int ehci_cleanup(ehci_state_t *ehcip); 151 static void ehci_rem_intrs(ehci_state_t *ehcip); 152 int ehci_cpr_suspend(ehci_state_t *ehcip); 153 int ehci_cpr_resume(ehci_state_t *ehcip); 154 155 /* Bandwidth Allocation functions */ 156 int ehci_allocate_bandwidth(ehci_state_t *ehcip, 157 usba_pipe_handle_data_t *ph, 158 uint_t *pnode, 159 uchar_t *smask, 160 uchar_t *cmask); 161 static int ehci_allocate_high_speed_bandwidth( 162 ehci_state_t *ehcip, 163 usba_pipe_handle_data_t *ph, 164 uint_t *hnode, 165 uchar_t *smask, 166 uchar_t *cmask); 167 static int ehci_allocate_classic_tt_bandwidth( 168 ehci_state_t *ehcip, 169 usba_pipe_handle_data_t *ph, 170 uint_t pnode); 171 void ehci_deallocate_bandwidth(ehci_state_t *ehcip, 172 usba_pipe_handle_data_t *ph, 173 uint_t pnode, 174 uchar_t smask, 175 uchar_t cmask); 176 static void ehci_deallocate_high_speed_bandwidth( 177 ehci_state_t *ehcip, 178 usba_pipe_handle_data_t *ph, 179 uint_t hnode, 180 uchar_t smask, 181 uchar_t cmask); 182 static void ehci_deallocate_classic_tt_bandwidth( 183 ehci_state_t *ehcip, 184 usba_pipe_handle_data_t *ph, 185 uint_t pnode); 186 static int ehci_compute_high_speed_bandwidth( 187 ehci_state_t *ehcip, 188 usb_ep_descr_t *endpoint, 189 usb_port_status_t port_status, 190 uint_t *sbandwidth, 191 uint_t *cbandwidth); 192 static int ehci_compute_classic_bandwidth( 193 usb_ep_descr_t *endpoint, 194 usb_port_status_t port_status, 195 uint_t *bandwidth); 196 int ehci_adjust_polling_interval( 197 ehci_state_t *ehcip, 198 usb_ep_descr_t *endpoint, 199 usb_port_status_t port_status); 200 static int ehci_adjust_high_speed_polling_interval( 201 ehci_state_t *ehcip, 202 usb_ep_descr_t *endpoint); 203 static uint_t ehci_lattice_height(uint_t interval); 204 static uint_t ehci_lattice_parent(uint_t node); 205 static uint_t ehci_find_periodic_node( 206 uint_t leaf, 207 int interval); 208 static uint_t ehci_leftmost_leaf(uint_t node, 209 uint_t height); 210 static uint_t ehci_pow_2(uint_t x); 211 static uint_t ehci_log_2(uint_t x); 212 static int ehci_find_bestfit_hs_mask( 213 ehci_state_t *ehcip, 214 uchar_t *smask, 215 uint_t *pnode, 216 usb_ep_descr_t *endpoint, 217 uint_t bandwidth, 218 int interval); 219 static int ehci_find_bestfit_ls_intr_mask( 220 ehci_state_t *ehcip, 221 uchar_t *smask, 222 uchar_t *cmask, 223 uint_t *pnode, 224 uint_t sbandwidth, 225 uint_t cbandwidth, 226 int interval); 227 static int ehci_find_bestfit_sitd_in_mask( 228 ehci_state_t *ehcip, 229 uchar_t *smask, 230 uchar_t *cmask, 231 uint_t *pnode, 232 uint_t sbandwidth, 233 uint_t cbandwidth, 234 int interval); 235 static int ehci_find_bestfit_sitd_out_mask( 236 ehci_state_t *ehcip, 237 uchar_t *smask, 238 uint_t *pnode, 239 uint_t sbandwidth, 240 int interval); 241 static uint_t ehci_calculate_bw_availability_mask( 242 ehci_state_t *ehcip, 243 uint_t bandwidth, 244 int leaf, 245 int leaf_count, 246 uchar_t *bw_mask); 247 static void ehci_update_bw_availability( 248 ehci_state_t *ehcip, 249 int bandwidth, 250 int leftmost_leaf, 251 int leaf_count, 252 uchar_t mask); 253 254 /* Miscellaneous functions */ 255 ehci_state_t *ehci_obtain_state( 256 dev_info_t *dip); 257 int ehci_state_is_operational( 258 ehci_state_t *ehcip); 259 int ehci_do_soft_reset( 260 ehci_state_t *ehcip); 261 usb_req_attrs_t ehci_get_xfer_attrs(ehci_state_t *ehcip, 262 ehci_pipe_private_t *pp, 263 ehci_trans_wrapper_t *tw); 264 usb_frame_number_t ehci_get_current_frame_number( 265 ehci_state_t *ehcip); 266 static void ehci_cpr_cleanup( 267 ehci_state_t *ehcip); 268 int ehci_wait_for_sof( 269 ehci_state_t *ehcip); 270 void ehci_toggle_scheduler( 271 ehci_state_t *ehcip); 272 void ehci_print_caps(ehci_state_t *ehcip); 273 void ehci_print_regs(ehci_state_t *ehcip); 274 void ehci_print_qh(ehci_state_t *ehcip, 275 ehci_qh_t *qh); 276 void ehci_print_qtd(ehci_state_t *ehcip, 277 ehci_qtd_t *qtd); 278 void ehci_create_stats(ehci_state_t *ehcip); 279 void ehci_destroy_stats(ehci_state_t *ehcip); 280 void ehci_do_intrs_stats(ehci_state_t *ehcip, 281 int val); 282 void ehci_do_byte_stats(ehci_state_t *ehcip, 283 size_t len, 284 uint8_t attr, 285 uint8_t addr); 286 287 /* 288 * check if this ehci controller can support PM 289 */ 290 int 291 ehci_hcdi_pm_support(dev_info_t *dip) 292 { 293 ehci_state_t *ehcip = ddi_get_soft_state(ehci_statep, 294 ddi_get_instance(dip)); 295 296 if (((ehcip->ehci_vendor_id == PCI_VENDOR_NEC_COMBO) && 297 (ehcip->ehci_device_id == PCI_DEVICE_NEC_COMBO)) || 298 299 ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 300 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) || 301 302 (ehcip->ehci_vendor_id == PCI_VENDOR_VIA)) { 303 304 return (USB_SUCCESS); 305 } 306 307 return (USB_FAILURE); 308 } 309 310 311 /* 312 * Host Controller Driver (HCD) initialization functions 313 */ 314 315 /* 316 * ehci_set_dma_attributes: 317 * 318 * Set the limits in the DMA attributes structure. Most of the values used 319 * in the DMA limit structures are the default values as specified by the 320 * Writing PCI device drivers document. 321 */ 322 void 323 ehci_set_dma_attributes(ehci_state_t *ehcip) 324 { 325 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 326 "ehci_set_dma_attributes:"); 327 328 /* Initialize the DMA attributes */ 329 ehcip->ehci_dma_attr.dma_attr_version = DMA_ATTR_V0; 330 ehcip->ehci_dma_attr.dma_attr_addr_lo = 0x00000000ull; 331 ehcip->ehci_dma_attr.dma_attr_addr_hi = 0xfffffffeull; 332 333 /* 32 bit addressing */ 334 ehcip->ehci_dma_attr.dma_attr_count_max = EHCI_DMA_ATTR_COUNT_MAX; 335 336 /* Byte alignment */ 337 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 338 339 /* 340 * Since PCI specification is byte alignment, the 341 * burst size field should be set to 1 for PCI devices. 342 */ 343 ehcip->ehci_dma_attr.dma_attr_burstsizes = 0x1; 344 345 ehcip->ehci_dma_attr.dma_attr_minxfer = 0x1; 346 ehcip->ehci_dma_attr.dma_attr_maxxfer = EHCI_DMA_ATTR_MAX_XFER; 347 ehcip->ehci_dma_attr.dma_attr_seg = 0xffffffffull; 348 ehcip->ehci_dma_attr.dma_attr_sgllen = 1; 349 ehcip->ehci_dma_attr.dma_attr_granular = EHCI_DMA_ATTR_GRANULAR; 350 ehcip->ehci_dma_attr.dma_attr_flags = 0; 351 } 352 353 354 /* 355 * ehci_allocate_pools: 356 * 357 * Allocate the system memory for the Endpoint Descriptor (QH) and for the 358 * Transfer Descriptor (QTD) pools. Both QH and QTD structures must be aligned 359 * to a 16 byte boundary. 360 */ 361 int 362 ehci_allocate_pools(ehci_state_t *ehcip) 363 { 364 ddi_device_acc_attr_t dev_attr; 365 size_t real_length; 366 int result; 367 uint_t ccount; 368 int i; 369 370 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 371 "ehci_allocate_pools:"); 372 373 /* The host controller will be little endian */ 374 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 375 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 376 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 377 378 /* Byte alignment */ 379 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_TD_QH_ALIGNMENT; 380 381 /* Allocate the QTD pool DMA handle */ 382 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 383 DDI_DMA_SLEEP, 0, 384 &ehcip->ehci_qtd_pool_dma_handle) != DDI_SUCCESS) { 385 386 goto failure; 387 } 388 389 /* Allocate the memory for the QTD pool */ 390 if (ddi_dma_mem_alloc(ehcip->ehci_qtd_pool_dma_handle, 391 ehci_qtd_pool_size * sizeof (ehci_qtd_t), 392 &dev_attr, 393 DDI_DMA_CONSISTENT, 394 DDI_DMA_SLEEP, 395 0, 396 (caddr_t *)&ehcip->ehci_qtd_pool_addr, 397 &real_length, 398 &ehcip->ehci_qtd_pool_mem_handle)) { 399 400 goto failure; 401 } 402 403 /* Map the QTD pool into the I/O address space */ 404 result = ddi_dma_addr_bind_handle( 405 ehcip->ehci_qtd_pool_dma_handle, 406 NULL, 407 (caddr_t)ehcip->ehci_qtd_pool_addr, 408 real_length, 409 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 410 DDI_DMA_SLEEP, 411 NULL, 412 &ehcip->ehci_qtd_pool_cookie, 413 &ccount); 414 415 bzero((void *)ehcip->ehci_qtd_pool_addr, 416 ehci_qtd_pool_size * sizeof (ehci_qtd_t)); 417 418 /* Process the result */ 419 if (result == DDI_DMA_MAPPED) { 420 /* The cookie count should be 1 */ 421 if (ccount != 1) { 422 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 423 "ehci_allocate_pools: More than 1 cookie"); 424 425 goto failure; 426 } 427 } else { 428 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 429 "ehci_allocate_pools: Result = %d", result); 430 431 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 432 433 goto failure; 434 } 435 436 /* 437 * DMA addresses for QTD pools are bound 438 */ 439 ehcip->ehci_dma_addr_bind_flag |= EHCI_QTD_POOL_BOUND; 440 441 /* Initialize the QTD pool */ 442 for (i = 0; i < ehci_qtd_pool_size; i ++) { 443 Set_QTD(ehcip->ehci_qtd_pool_addr[i]. 444 qtd_state, EHCI_QTD_FREE); 445 } 446 447 /* Allocate the QTD pool DMA handle */ 448 if (ddi_dma_alloc_handle(ehcip->ehci_dip, 449 &ehcip->ehci_dma_attr, 450 DDI_DMA_SLEEP, 451 0, 452 &ehcip->ehci_qh_pool_dma_handle) != DDI_SUCCESS) { 453 454 goto failure; 455 } 456 457 /* Allocate the memory for the QH pool */ 458 if (ddi_dma_mem_alloc(ehcip->ehci_qh_pool_dma_handle, 459 ehci_qh_pool_size * sizeof (ehci_qh_t), 460 &dev_attr, 461 DDI_DMA_CONSISTENT, 462 DDI_DMA_SLEEP, 463 0, 464 (caddr_t *)&ehcip->ehci_qh_pool_addr, 465 &real_length, 466 &ehcip->ehci_qh_pool_mem_handle) != DDI_SUCCESS) { 467 468 goto failure; 469 } 470 471 result = ddi_dma_addr_bind_handle(ehcip->ehci_qh_pool_dma_handle, 472 NULL, 473 (caddr_t)ehcip->ehci_qh_pool_addr, 474 real_length, 475 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 476 DDI_DMA_SLEEP, 477 NULL, 478 &ehcip->ehci_qh_pool_cookie, 479 &ccount); 480 481 bzero((void *)ehcip->ehci_qh_pool_addr, 482 ehci_qh_pool_size * sizeof (ehci_qh_t)); 483 484 /* Process the result */ 485 if (result == DDI_DMA_MAPPED) { 486 /* The cookie count should be 1 */ 487 if (ccount != 1) { 488 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 489 "ehci_allocate_pools: More than 1 cookie"); 490 491 goto failure; 492 } 493 } else { 494 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 495 496 goto failure; 497 } 498 499 /* 500 * DMA addresses for QH pools are bound 501 */ 502 ehcip->ehci_dma_addr_bind_flag |= EHCI_QH_POOL_BOUND; 503 504 /* Initialize the QH pool */ 505 for (i = 0; i < ehci_qh_pool_size; i ++) { 506 Set_QH(ehcip->ehci_qh_pool_addr[i].qh_state, EHCI_QH_FREE); 507 } 508 509 /* Byte alignment */ 510 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 511 512 return (DDI_SUCCESS); 513 514 failure: 515 /* Byte alignment */ 516 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 517 518 return (DDI_FAILURE); 519 } 520 521 522 /* 523 * ehci_decode_ddi_dma_addr_bind_handle_result: 524 * 525 * Process the return values of ddi_dma_addr_bind_handle() 526 */ 527 void 528 ehci_decode_ddi_dma_addr_bind_handle_result( 529 ehci_state_t *ehcip, 530 int result) 531 { 532 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ehcip->ehci_log_hdl, 533 "ehci_decode_ddi_dma_addr_bind_handle_result:"); 534 535 switch (result) { 536 case DDI_DMA_PARTIAL_MAP: 537 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 538 "Partial transfers not allowed"); 539 break; 540 case DDI_DMA_INUSE: 541 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 542 "Handle is in use"); 543 break; 544 case DDI_DMA_NORESOURCES: 545 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 546 "No resources"); 547 break; 548 case DDI_DMA_NOMAPPING: 549 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 550 "No mapping"); 551 break; 552 case DDI_DMA_TOOBIG: 553 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 554 "Object is too big"); 555 break; 556 default: 557 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 558 "Unknown dma error"); 559 } 560 } 561 562 563 /* 564 * ehci_map_regs: 565 * 566 * The Host Controller (HC) contains a set of on-chip operational registers 567 * and which should be mapped into a non-cacheable portion of the system 568 * addressable space. 569 */ 570 int 571 ehci_map_regs(ehci_state_t *ehcip) 572 { 573 ddi_device_acc_attr_t attr; 574 uint16_t cmd_reg; 575 uint_t length; 576 577 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_map_regs:"); 578 579 /* Check to make sure we have memory access */ 580 if (pci_config_setup(ehcip->ehci_dip, 581 &ehcip->ehci_config_handle) != DDI_SUCCESS) { 582 583 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 584 "ehci_map_regs: Config error"); 585 586 return (DDI_FAILURE); 587 } 588 589 /* Make sure Memory Access Enable is set */ 590 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 591 592 if (!(cmd_reg & PCI_COMM_MAE)) { 593 594 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 595 "ehci_map_regs: Memory base address access disabled"); 596 597 return (DDI_FAILURE); 598 } 599 600 /* The host controller will be little endian */ 601 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 602 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 603 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 604 605 /* Map in EHCI Capability registers */ 606 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 607 (caddr_t *)&ehcip->ehci_capsp, 0, 608 sizeof (ehci_caps_t), &attr, 609 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 610 611 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 612 "ehci_map_regs: Map setup error"); 613 614 return (DDI_FAILURE); 615 } 616 617 length = ddi_get8(ehcip->ehci_caps_handle, 618 (uint8_t *)&ehcip->ehci_capsp->ehci_caps_length); 619 620 /* Free the original mapping */ 621 ddi_regs_map_free(&ehcip->ehci_caps_handle); 622 623 /* Re-map in EHCI Capability and Operational registers */ 624 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 625 (caddr_t *)&ehcip->ehci_capsp, 0, 626 length + sizeof (ehci_regs_t), &attr, 627 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 628 629 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 630 "ehci_map_regs: Map setup error"); 631 632 return (DDI_FAILURE); 633 } 634 635 /* Get the pointer to EHCI Operational Register */ 636 ehcip->ehci_regsp = (ehci_regs_t *) 637 ((uintptr_t)ehcip->ehci_capsp + length); 638 639 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 640 "ehci_map_regs: Capsp 0x%p Regsp 0x%p\n", 641 ehcip->ehci_capsp, ehcip->ehci_regsp); 642 643 return (DDI_SUCCESS); 644 } 645 646 /* 647 * The following simulated polling is for debugging purposes only. 648 * It is activated on x86 by setting usb-polling=true in GRUB or ehci.conf. 649 */ 650 static int 651 ehci_is_polled(dev_info_t *dip) 652 { 653 int ret; 654 char *propval; 655 656 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 657 "usb-polling", &propval) != DDI_SUCCESS) 658 659 return (0); 660 661 ret = (strcmp(propval, "true") == 0); 662 ddi_prop_free(propval); 663 664 return (ret); 665 } 666 667 static void 668 ehci_poll_intr(void *arg) 669 { 670 /* poll every msec */ 671 for (;;) { 672 (void) ehci_intr(arg, NULL); 673 delay(drv_usectohz(1000)); 674 } 675 } 676 677 /* 678 * ehci_register_intrs_and_init_mutex: 679 * 680 * Register interrupts and initialize each mutex and condition variables 681 */ 682 int 683 ehci_register_intrs_and_init_mutex(ehci_state_t *ehcip) 684 { 685 int intr_types; 686 687 #if defined(__x86) 688 uint8_t iline; 689 #endif 690 691 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 692 "ehci_register_intrs_and_init_mutex:"); 693 694 /* 695 * There is a known MSI hardware bug with the EHCI controller 696 * of ULI1575 southbridge. Hence MSI is disabled for this chip. 697 */ 698 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 699 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) { 700 ehcip->ehci_msi_enabled = B_FALSE; 701 } else { 702 /* Set the MSI enable flag from the global EHCI MSI tunable */ 703 ehcip->ehci_msi_enabled = ehci_enable_msi; 704 } 705 706 /* launch polling thread instead of enabling pci interrupt */ 707 if (ehci_is_polled(ehcip->ehci_dip)) { 708 extern pri_t maxclsyspri; 709 710 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 711 "ehci_register_intrs_and_init_mutex: " 712 "running in simulated polled mode"); 713 714 (void) thread_create(NULL, 0, ehci_poll_intr, ehcip, 0, &p0, 715 TS_RUN, maxclsyspri); 716 717 goto skip_intr; 718 } 719 720 #if defined(__x86) 721 /* 722 * Make sure that the interrupt pin is connected to the 723 * interrupt controller on x86. Interrupt line 255 means 724 * "unknown" or "not connected" (PCI spec 6.2.4, footnote 43). 725 * If we would return failure when interrupt line equals 255, then 726 * high speed devices will be routed to companion host controllers. 727 * However, it is not necessary to return failure here, and 728 * o/uhci codes don't check the interrupt line either. 729 * But it's good to log a message here for debug purposes. 730 */ 731 iline = pci_config_get8(ehcip->ehci_config_handle, 732 PCI_CONF_ILINE); 733 734 if (iline == 255) { 735 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 736 "ehci_register_intrs_and_init_mutex: " 737 "interrupt line value out of range (%d)", 738 iline); 739 } 740 #endif /* __x86 */ 741 742 /* Get supported interrupt types */ 743 if (ddi_intr_get_supported_types(ehcip->ehci_dip, 744 &intr_types) != DDI_SUCCESS) { 745 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 746 "ehci_register_intrs_and_init_mutex: " 747 "ddi_intr_get_supported_types failed"); 748 749 return (DDI_FAILURE); 750 } 751 752 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 753 "ehci_register_intrs_and_init_mutex: " 754 "supported interrupt types 0x%x", intr_types); 755 756 if ((intr_types & DDI_INTR_TYPE_MSI) && ehcip->ehci_msi_enabled) { 757 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_MSI) 758 != DDI_SUCCESS) { 759 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 760 "ehci_register_intrs_and_init_mutex: MSI " 761 "registration failed, trying FIXED interrupt \n"); 762 } else { 763 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 764 "ehci_register_intrs_and_init_mutex: " 765 "Using MSI interrupt type\n"); 766 767 ehcip->ehci_intr_type = DDI_INTR_TYPE_MSI; 768 ehcip->ehci_flags |= EHCI_INTR; 769 } 770 } 771 772 if ((!(ehcip->ehci_flags & EHCI_INTR)) && 773 (intr_types & DDI_INTR_TYPE_FIXED)) { 774 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_FIXED) 775 != DDI_SUCCESS) { 776 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 777 "ehci_register_intrs_and_init_mutex: " 778 "FIXED interrupt registration failed\n"); 779 780 return (DDI_FAILURE); 781 } 782 783 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 784 "ehci_register_intrs_and_init_mutex: " 785 "Using FIXED interrupt type\n"); 786 787 ehcip->ehci_intr_type = DDI_INTR_TYPE_FIXED; 788 ehcip->ehci_flags |= EHCI_INTR; 789 } 790 791 skip_intr: 792 /* Create prototype for advance on async schedule */ 793 cv_init(&ehcip->ehci_async_schedule_advance_cv, 794 NULL, CV_DRIVER, NULL); 795 796 return (DDI_SUCCESS); 797 } 798 799 800 /* 801 * ehci_add_intrs: 802 * 803 * Register FIXED or MSI interrupts. 804 */ 805 static int 806 ehci_add_intrs(ehci_state_t *ehcip, 807 int intr_type) 808 { 809 int actual, avail, intr_size, count = 0; 810 int i, flag, ret; 811 812 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 813 "ehci_add_intrs: interrupt type 0x%x", intr_type); 814 815 /* Get number of interrupts */ 816 ret = ddi_intr_get_nintrs(ehcip->ehci_dip, intr_type, &count); 817 if ((ret != DDI_SUCCESS) || (count == 0)) { 818 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 819 "ehci_add_intrs: ddi_intr_get_nintrs() failure, " 820 "ret: %d, count: %d", ret, count); 821 822 return (DDI_FAILURE); 823 } 824 825 /* Get number of available interrupts */ 826 ret = ddi_intr_get_navail(ehcip->ehci_dip, intr_type, &avail); 827 if ((ret != DDI_SUCCESS) || (avail == 0)) { 828 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 829 "ehci_add_intrs: ddi_intr_get_navail() failure, " 830 "ret: %d, count: %d", ret, count); 831 832 return (DDI_FAILURE); 833 } 834 835 if (avail < count) { 836 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 837 "ehci_add_intrs: ehci_add_intrs: nintrs () " 838 "returned %d, navail returned %d\n", count, avail); 839 } 840 841 /* Allocate an array of interrupt handles */ 842 intr_size = count * sizeof (ddi_intr_handle_t); 843 ehcip->ehci_htable = kmem_zalloc(intr_size, KM_SLEEP); 844 845 flag = (intr_type == DDI_INTR_TYPE_MSI) ? 846 DDI_INTR_ALLOC_STRICT:DDI_INTR_ALLOC_NORMAL; 847 848 /* call ddi_intr_alloc() */ 849 ret = ddi_intr_alloc(ehcip->ehci_dip, ehcip->ehci_htable, 850 intr_type, 0, count, &actual, flag); 851 852 if ((ret != DDI_SUCCESS) || (actual == 0)) { 853 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 854 "ehci_add_intrs: ddi_intr_alloc() failed %d", ret); 855 856 kmem_free(ehcip->ehci_htable, intr_size); 857 858 return (DDI_FAILURE); 859 } 860 861 if (actual < count) { 862 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 863 "ehci_add_intrs: Requested: %d, Received: %d\n", 864 count, actual); 865 866 for (i = 0; i < actual; i++) 867 (void) ddi_intr_free(ehcip->ehci_htable[i]); 868 869 kmem_free(ehcip->ehci_htable, intr_size); 870 871 return (DDI_FAILURE); 872 } 873 874 ehcip->ehci_intr_cnt = actual; 875 876 if ((ret = ddi_intr_get_pri(ehcip->ehci_htable[0], 877 &ehcip->ehci_intr_pri)) != DDI_SUCCESS) { 878 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 879 "ehci_add_intrs: ddi_intr_get_pri() failed %d", ret); 880 881 for (i = 0; i < actual; i++) 882 (void) ddi_intr_free(ehcip->ehci_htable[i]); 883 884 kmem_free(ehcip->ehci_htable, intr_size); 885 886 return (DDI_FAILURE); 887 } 888 889 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 890 "ehci_add_intrs: Supported Interrupt priority 0x%x", 891 ehcip->ehci_intr_pri); 892 893 /* Test for high level mutex */ 894 if (ehcip->ehci_intr_pri >= ddi_intr_get_hilevel_pri()) { 895 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 896 "ehci_add_intrs: Hi level interrupt not supported"); 897 898 for (i = 0; i < actual; i++) 899 (void) ddi_intr_free(ehcip->ehci_htable[i]); 900 901 kmem_free(ehcip->ehci_htable, intr_size); 902 903 return (DDI_FAILURE); 904 } 905 906 /* Initialize the mutex */ 907 mutex_init(&ehcip->ehci_int_mutex, NULL, MUTEX_DRIVER, 908 DDI_INTR_PRI(ehcip->ehci_intr_pri)); 909 910 /* Call ddi_intr_add_handler() */ 911 for (i = 0; i < actual; i++) { 912 if ((ret = ddi_intr_add_handler(ehcip->ehci_htable[i], 913 ehci_intr, (caddr_t)ehcip, 914 (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 915 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 916 "ehci_add_intrs:ddi_intr_add_handler() " 917 "failed %d", ret); 918 919 for (i = 0; i < actual; i++) 920 (void) ddi_intr_free(ehcip->ehci_htable[i]); 921 922 mutex_destroy(&ehcip->ehci_int_mutex); 923 kmem_free(ehcip->ehci_htable, intr_size); 924 925 return (DDI_FAILURE); 926 } 927 } 928 929 if ((ret = ddi_intr_get_cap(ehcip->ehci_htable[0], 930 &ehcip->ehci_intr_cap)) != DDI_SUCCESS) { 931 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 932 "ehci_add_intrs: ddi_intr_get_cap() failed %d", ret); 933 934 for (i = 0; i < actual; i++) { 935 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 936 (void) ddi_intr_free(ehcip->ehci_htable[i]); 937 } 938 939 mutex_destroy(&ehcip->ehci_int_mutex); 940 kmem_free(ehcip->ehci_htable, intr_size); 941 942 return (DDI_FAILURE); 943 } 944 945 /* Enable all interrupts */ 946 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 947 /* Call ddi_intr_block_enable() for MSI interrupts */ 948 (void) ddi_intr_block_enable(ehcip->ehci_htable, 949 ehcip->ehci_intr_cnt); 950 } else { 951 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 952 for (i = 0; i < ehcip->ehci_intr_cnt; i++) 953 (void) ddi_intr_enable(ehcip->ehci_htable[i]); 954 } 955 956 return (DDI_SUCCESS); 957 } 958 959 960 /* 961 * ehci_init_hardware 962 * 963 * take control from BIOS, reset EHCI host controller, and check version, etc. 964 */ 965 int 966 ehci_init_hardware(ehci_state_t *ehcip) 967 { 968 int revision; 969 uint16_t cmd_reg; 970 int abort_on_BIOS_take_over_failure; 971 972 /* Take control from the BIOS */ 973 if (ehci_take_control(ehcip) != USB_SUCCESS) { 974 975 /* read .conf file properties */ 976 abort_on_BIOS_take_over_failure = 977 ddi_prop_get_int(DDI_DEV_T_ANY, 978 ehcip->ehci_dip, DDI_PROP_DONTPASS, 979 "abort-on-BIOS-take-over-failure", 0); 980 981 if (abort_on_BIOS_take_over_failure) { 982 983 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 984 "Unable to take control from BIOS."); 985 986 return (DDI_FAILURE); 987 } 988 989 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 990 "Unable to take control from BIOS. Failure is ignored."); 991 } 992 993 /* set Memory Master Enable */ 994 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 995 cmd_reg |= (PCI_COMM_MAE | PCI_COMM_ME); 996 pci_config_put16(ehcip->ehci_config_handle, PCI_CONF_COMM, cmd_reg); 997 998 /* Reset the EHCI host controller */ 999 Set_OpReg(ehci_command, 1000 Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET); 1001 1002 /* Wait 10ms for reset to complete */ 1003 drv_usecwait(EHCI_RESET_TIMEWAIT); 1004 1005 ASSERT(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED); 1006 1007 /* Verify the version number */ 1008 revision = Get_16Cap(ehci_version); 1009 1010 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1011 "ehci_init_hardware: Revision 0x%x", revision); 1012 1013 /* 1014 * EHCI driver supports EHCI host controllers compliant to 1015 * 0.95 and higher revisions of EHCI specifications. 1016 */ 1017 if (revision < EHCI_REVISION_0_95) { 1018 1019 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1020 "Revision 0x%x is not supported", revision); 1021 1022 return (DDI_FAILURE); 1023 } 1024 1025 if (ehcip->ehci_hc_soft_state == EHCI_CTLR_INIT_STATE) { 1026 1027 /* Initialize the Frame list base address area */ 1028 if (ehci_init_periodic_frame_lst_table(ehcip) != DDI_SUCCESS) { 1029 1030 return (DDI_FAILURE); 1031 } 1032 1033 /* 1034 * For performance reasons, do not insert anything into the 1035 * asynchronous list or activate the asynch list schedule until 1036 * there is a valid QH. 1037 */ 1038 ehcip->ehci_head_of_async_sched_list = NULL; 1039 1040 if ((ehcip->ehci_vendor_id == PCI_VENDOR_VIA) && 1041 (ehci_vt62x2_workaround & EHCI_VIA_ASYNC_SCHEDULE)) { 1042 /* 1043 * The driver is unable to reliably stop the asynch 1044 * list schedule on VIA VT6202 controllers, so we 1045 * always keep a dummy QH on the list. 1046 */ 1047 ehci_qh_t *dummy_async_qh = 1048 ehci_alloc_qh(ehcip, NULL, NULL); 1049 1050 Set_QH(dummy_async_qh->qh_link_ptr, 1051 ((ehci_qh_cpu_to_iommu(ehcip, dummy_async_qh) & 1052 EHCI_QH_LINK_PTR) | EHCI_QH_LINK_REF_QH)); 1053 1054 /* Set this QH to be the "head" of the circular list */ 1055 Set_QH(dummy_async_qh->qh_ctrl, 1056 Get_QH(dummy_async_qh->qh_ctrl) | 1057 EHCI_QH_CTRL_RECLAIM_HEAD); 1058 1059 Set_QH(dummy_async_qh->qh_next_qtd, 1060 EHCI_QH_NEXT_QTD_PTR_VALID); 1061 Set_QH(dummy_async_qh->qh_alt_next_qtd, 1062 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1063 1064 ehcip->ehci_head_of_async_sched_list = dummy_async_qh; 1065 ehcip->ehci_open_async_count++; 1066 } 1067 } 1068 1069 return (DDI_SUCCESS); 1070 } 1071 1072 1073 /* 1074 * ehci_init_workaround 1075 * 1076 * some workarounds during initializing ehci 1077 */ 1078 int 1079 ehci_init_workaround(ehci_state_t *ehcip) 1080 { 1081 /* 1082 * Acer Labs Inc. M5273 EHCI controller does not send 1083 * interrupts unless the Root hub ports are routed to the EHCI 1084 * host controller; so route the ports now, before we test for 1085 * the presence of SOFs interrupts. 1086 */ 1087 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1088 /* Route all Root hub ports to EHCI host controller */ 1089 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1090 } 1091 1092 /* 1093 * VIA chips have some issues and may not work reliably. 1094 * Revisions >= 0x80 are part of a southbridge and appear 1095 * to be reliable with the workaround. 1096 * For revisions < 0x80, if we were bound using class 1097 * complain, else proceed. This will allow the user to 1098 * bind ehci specifically to this chip and not have the 1099 * warnings 1100 */ 1101 if (ehcip->ehci_vendor_id == PCI_VENDOR_VIA) { 1102 1103 if (ehcip->ehci_rev_id >= PCI_VIA_REVISION_6212) { 1104 1105 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1106 "ehci_init_workaround: Applying VIA workarounds " 1107 "for the 6212 chip."); 1108 1109 } else if (strcmp(DEVI(ehcip->ehci_dip)->devi_binding_name, 1110 "pciclass,0c0320") == 0) { 1111 1112 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1113 "Due to recently discovered incompatibilities"); 1114 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1115 "with this USB controller, USB2.x transfer"); 1116 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1117 "support has been disabled. This device will"); 1118 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1119 "continue to function as a USB1.x controller."); 1120 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1121 "If you are interested in enabling USB2.x"); 1122 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1123 "support please, refer to the ehci(7D) man page."); 1124 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1125 "Please also refer to www.sun.com/io for"); 1126 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1127 "Solaris Ready products and to"); 1128 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1129 "www.sun.com/bigadmin/hcl for additional"); 1130 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1131 "compatible USB products."); 1132 1133 return (DDI_FAILURE); 1134 1135 } else if (ehci_vt62x2_workaround) { 1136 1137 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1138 "Applying VIA workarounds"); 1139 } 1140 } 1141 1142 return (DDI_SUCCESS); 1143 } 1144 1145 1146 /* 1147 * ehci_init_check_status 1148 * 1149 * Check if EHCI host controller is running 1150 */ 1151 int 1152 ehci_init_check_status(ehci_state_t *ehcip) 1153 { 1154 clock_t sof_time_wait; 1155 1156 /* 1157 * Get the number of clock ticks to wait. 1158 * This is based on the maximum time it takes for a frame list rollover 1159 * and maximum time wait for SOFs to begin. 1160 */ 1161 sof_time_wait = drv_usectohz((EHCI_NUM_PERIODIC_FRAME_LISTS * 1000) + 1162 EHCI_SOF_TIMEWAIT); 1163 1164 /* Tell the ISR to broadcast ehci_async_schedule_advance_cv */ 1165 ehcip->ehci_flags |= EHCI_CV_INTR; 1166 1167 /* We need to add a delay to allow the chip time to start running */ 1168 (void) cv_timedwait(&ehcip->ehci_async_schedule_advance_cv, 1169 &ehcip->ehci_int_mutex, ddi_get_lbolt() + sof_time_wait); 1170 1171 /* 1172 * Check EHCI host controller is running, otherwise return failure. 1173 */ 1174 if ((ehcip->ehci_flags & EHCI_CV_INTR) || 1175 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 1176 1177 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1178 "No SOF interrupts have been received, this USB EHCI host" 1179 "controller is unusable"); 1180 1181 /* 1182 * Route all Root hub ports to Classic host 1183 * controller, in case this is an unusable ALI M5273 1184 * EHCI controller. 1185 */ 1186 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1187 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1188 } 1189 1190 return (DDI_FAILURE); 1191 } 1192 1193 return (DDI_SUCCESS); 1194 } 1195 1196 1197 /* 1198 * ehci_init_ctlr: 1199 * 1200 * Initialize the Host Controller (HC). 1201 */ 1202 int 1203 ehci_init_ctlr(ehci_state_t *ehcip, 1204 int init_type) 1205 { 1206 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_init_ctlr:"); 1207 1208 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1209 1210 if (ehci_init_hardware(ehcip) != DDI_SUCCESS) { 1211 1212 return (DDI_FAILURE); 1213 } 1214 } 1215 1216 /* 1217 * Check for Asynchronous schedule park capability feature. If this 1218 * feature is supported, then, program ehci command register with 1219 * appropriate values.. 1220 */ 1221 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_ASYNC_SCHED_PARK_CAP) { 1222 1223 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1224 "ehci_init_ctlr: Async park mode is supported"); 1225 1226 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1227 (EHCI_CMD_ASYNC_PARK_ENABLE | 1228 EHCI_CMD_ASYNC_PARK_COUNT_3))); 1229 } 1230 1231 /* 1232 * Check for programmable periodic frame list feature. If this 1233 * feature is supported, then, program ehci command register with 1234 * 1024 frame list value. 1235 */ 1236 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_PROG_FRAME_LIST_FLAG) { 1237 1238 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1239 "ehci_init_ctlr: Variable programmable periodic " 1240 "frame list is supported"); 1241 1242 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1243 EHCI_CMD_FRAME_1024_SIZE)); 1244 } 1245 1246 /* 1247 * Currently EHCI driver doesn't support 64 bit addressing. 1248 * 1249 * If we are using 64 bit addressing capability, then, program 1250 * ehci_ctrl_segment register with 4 Gigabyte segment where all 1251 * of the interface data structures are allocated. 1252 */ 1253 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_64BIT_ADDR_CAP) { 1254 1255 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1256 "ehci_init_ctlr: EHCI driver doesn't support " 1257 "64 bit addressing"); 1258 } 1259 1260 /* 64 bit addressing is not support */ 1261 Set_OpReg(ehci_ctrl_segment, 0x00000000); 1262 1263 /* Turn on/off the schedulers */ 1264 ehci_toggle_scheduler(ehcip); 1265 1266 /* 1267 * Set the Periodic Frame List Base Address register with the 1268 * starting physical address of the Periodic Frame List. 1269 */ 1270 Set_OpReg(ehci_periodic_list_base, 1271 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 1272 EHCI_PERIODIC_LIST_BASE)); 1273 1274 /* 1275 * Set ehci_interrupt to enable all interrupts except Root 1276 * Hub Status change interrupt. 1277 */ 1278 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 1279 EHCI_INTR_FRAME_LIST_ROLLOVER | EHCI_INTR_USB_ERROR | 1280 EHCI_INTR_USB); 1281 1282 /* 1283 * Set the desired interrupt threshold and turn on EHCI host controller. 1284 */ 1285 Set_OpReg(ehci_command, 1286 ((Get_OpReg(ehci_command) & ~EHCI_CMD_INTR_THRESHOLD) | 1287 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 1288 1289 ASSERT(Get_OpReg(ehci_command) & EHCI_CMD_HOST_CTRL_RUN); 1290 1291 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1292 1293 if (ehci_init_workaround(ehcip) != DDI_SUCCESS) { 1294 1295 return (DDI_FAILURE); 1296 } 1297 1298 if (ehci_init_check_status(ehcip) != DDI_SUCCESS) { 1299 1300 return (DDI_FAILURE); 1301 } 1302 1303 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1304 "ehci_init_ctlr: SOF's have started"); 1305 } 1306 1307 /* Route all Root hub ports to EHCI host controller */ 1308 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1309 1310 /* Set host controller soft state to operational */ 1311 ehcip->ehci_hc_soft_state = EHCI_CTLR_OPERATIONAL_STATE; 1312 1313 return (DDI_SUCCESS); 1314 } 1315 1316 /* 1317 * ehci_take_control: 1318 * 1319 * Handshake to take EHCI control from BIOS if necessary. Its only valid for 1320 * x86 machines, because sparc doesn't have a BIOS. 1321 * On x86 machine, the take control process includes 1322 * o get the base address of the extended capability list 1323 * o find out the capability for handoff synchronization in the list. 1324 * o check if BIOS has owned the host controller. 1325 * o set the OS Owned semaphore bit, ask the BIOS to release the ownership. 1326 * o wait for a constant time and check if BIOS has relinquished control. 1327 */ 1328 /* ARGSUSED */ 1329 static int 1330 ehci_take_control(ehci_state_t *ehcip) 1331 { 1332 #if defined(__x86) 1333 uint32_t extended_cap; 1334 uint32_t extended_cap_offset; 1335 uint32_t extended_cap_id; 1336 uint_t retry; 1337 1338 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1339 "ehci_take_control:"); 1340 1341 /* 1342 * According EHCI Spec 2.2.4, get EECP base address from HCCPARAMS 1343 * register. 1344 */ 1345 extended_cap_offset = (Get_Cap(ehci_hcc_params) & EHCI_HCC_EECP) >> 1346 EHCI_HCC_EECP_SHIFT; 1347 1348 /* 1349 * According EHCI Spec 2.2.4, if the extended capability offset is 1350 * less than 40h then its not valid. This means we don't need to 1351 * worry about BIOS handoff. 1352 */ 1353 if (extended_cap_offset < EHCI_HCC_EECP_MIN_OFFSET) { 1354 1355 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1356 "ehci_take_control: Hardware doesn't support legacy."); 1357 1358 goto success; 1359 } 1360 1361 /* 1362 * According EHCI Spec 2.1.7, A zero offset indicates the 1363 * end of the extended capability list. 1364 */ 1365 while (extended_cap_offset) { 1366 1367 /* Get the extended capability value. */ 1368 extended_cap = pci_config_get32(ehcip->ehci_config_handle, 1369 extended_cap_offset); 1370 1371 /* Get the capability ID */ 1372 extended_cap_id = (extended_cap & EHCI_EX_CAP_ID) >> 1373 EHCI_EX_CAP_ID_SHIFT; 1374 1375 /* Check if the card support legacy */ 1376 if (extended_cap_id == EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1377 break; 1378 } 1379 1380 /* Get the offset of the next capability */ 1381 extended_cap_offset = (extended_cap & EHCI_EX_CAP_NEXT_PTR) >> 1382 EHCI_EX_CAP_NEXT_PTR_SHIFT; 1383 } 1384 1385 /* 1386 * Unable to find legacy support in hardware's extended capability list. 1387 * This means we don't need to worry about BIOS handoff. 1388 */ 1389 if (extended_cap_id != EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1390 1391 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1392 "ehci_take_control: Hardware doesn't support legacy"); 1393 1394 goto success; 1395 } 1396 1397 /* Check if BIOS has owned it. */ 1398 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1399 1400 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1401 "ehci_take_control: BIOS does not own EHCI"); 1402 1403 goto success; 1404 } 1405 1406 /* 1407 * According EHCI Spec 5.1, The OS driver initiates an ownership 1408 * request by setting the OS Owned semaphore to a one. The OS 1409 * waits for the BIOS Owned bit to go to a zero before attempting 1410 * to use the EHCI controller. The time that OS must wait for BIOS 1411 * to respond to the request for ownership is beyond the scope of 1412 * this specification. 1413 * It waits up to EHCI_TAKEOVER_WAIT_COUNT*EHCI_TAKEOVER_DELAY ms 1414 * for BIOS to release the ownership. 1415 */ 1416 extended_cap |= EHCI_LEGSUP_OS_OWNED_SEM; 1417 pci_config_put32(ehcip->ehci_config_handle, extended_cap_offset, 1418 extended_cap); 1419 1420 for (retry = 0; retry < EHCI_TAKEOVER_WAIT_COUNT; retry++) { 1421 1422 /* wait a special interval */ 1423 delay(drv_usectohz(EHCI_TAKEOVER_DELAY)); 1424 1425 /* Check to see if the BIOS has released the ownership */ 1426 extended_cap = pci_config_get32( 1427 ehcip->ehci_config_handle, extended_cap_offset); 1428 1429 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1430 1431 USB_DPRINTF_L3(PRINT_MASK_ATTA, 1432 ehcip->ehci_log_hdl, 1433 "ehci_take_control: BIOS has released " 1434 "the ownership. retry = %d", retry); 1435 1436 goto success; 1437 } 1438 1439 } 1440 1441 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1442 "ehci_take_control: take control from BIOS failed."); 1443 1444 return (USB_FAILURE); 1445 1446 success: 1447 1448 #endif /* __x86 */ 1449 return (USB_SUCCESS); 1450 } 1451 1452 1453 /* 1454 * ehci_init_periodic_frame_list_table : 1455 * 1456 * Allocate the system memory and initialize Host Controller 1457 * Periodic Frame List table area. The starting of the Periodic 1458 * Frame List Table area must be 4096 byte aligned. 1459 */ 1460 static int 1461 ehci_init_periodic_frame_lst_table(ehci_state_t *ehcip) 1462 { 1463 ddi_device_acc_attr_t dev_attr; 1464 size_t real_length; 1465 uint_t ccount; 1466 int result; 1467 1468 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1469 1470 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1471 "ehci_init_periodic_frame_lst_table:"); 1472 1473 /* The host controller will be little endian */ 1474 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1475 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1476 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1477 1478 /* Force the required 4K restrictive alignment */ 1479 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_PFL_ALIGNMENT; 1480 1481 /* Create space for the Periodic Frame List */ 1482 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 1483 DDI_DMA_SLEEP, 0, &ehcip->ehci_pflt_dma_handle) != DDI_SUCCESS) { 1484 1485 goto failure; 1486 } 1487 1488 if (ddi_dma_mem_alloc(ehcip->ehci_pflt_dma_handle, 1489 sizeof (ehci_periodic_frame_list_t), 1490 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 1491 0, (caddr_t *)&ehcip->ehci_periodic_frame_list_tablep, 1492 &real_length, &ehcip->ehci_pflt_mem_handle)) { 1493 1494 goto failure; 1495 } 1496 1497 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1498 "ehci_init_periodic_frame_lst_table: " 1499 "Real length %lu", real_length); 1500 1501 /* Map the whole Periodic Frame List into the I/O address space */ 1502 result = ddi_dma_addr_bind_handle(ehcip->ehci_pflt_dma_handle, 1503 NULL, (caddr_t)ehcip->ehci_periodic_frame_list_tablep, 1504 real_length, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1505 DDI_DMA_SLEEP, NULL, &ehcip->ehci_pflt_cookie, &ccount); 1506 1507 if (result == DDI_DMA_MAPPED) { 1508 /* The cookie count should be 1 */ 1509 if (ccount != 1) { 1510 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1511 "ehci_init_periodic_frame_lst_table: " 1512 "More than 1 cookie"); 1513 1514 goto failure; 1515 } 1516 } else { 1517 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 1518 1519 goto failure; 1520 } 1521 1522 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1523 "ehci_init_periodic_frame_lst_table: virtual 0x%p physical 0x%x", 1524 (void *)ehcip->ehci_periodic_frame_list_tablep, 1525 ehcip->ehci_pflt_cookie.dmac_address); 1526 1527 /* 1528 * DMA addresses for Periodic Frame List are bound. 1529 */ 1530 ehcip->ehci_dma_addr_bind_flag |= EHCI_PFLT_DMA_BOUND; 1531 1532 bzero((void *)ehcip->ehci_periodic_frame_list_tablep, real_length); 1533 1534 /* Initialize the Periodic Frame List */ 1535 ehci_build_interrupt_lattice(ehcip); 1536 1537 /* Reset Byte Alignment to Default */ 1538 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1539 1540 return (DDI_SUCCESS); 1541 failure: 1542 /* Byte alignment */ 1543 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1544 1545 return (DDI_FAILURE); 1546 } 1547 1548 1549 /* 1550 * ehci_build_interrupt_lattice: 1551 * 1552 * Construct the interrupt lattice tree using static Endpoint Descriptors 1553 * (QH). This interrupt lattice tree will have total of 32 interrupt QH 1554 * lists and the Host Controller (HC) processes one interrupt QH list in 1555 * every frame. The Host Controller traverses the periodic schedule by 1556 * constructing an array offset reference from the Periodic List Base Address 1557 * register and bits 12 to 3 of Frame Index register. It fetches the element 1558 * and begins traversing the graph of linked schedule data structures. 1559 */ 1560 static void 1561 ehci_build_interrupt_lattice(ehci_state_t *ehcip) 1562 { 1563 ehci_qh_t *list_array = ehcip->ehci_qh_pool_addr; 1564 ushort_t ehci_index[EHCI_NUM_PERIODIC_FRAME_LISTS]; 1565 ehci_periodic_frame_list_t *periodic_frame_list = 1566 ehcip->ehci_periodic_frame_list_tablep; 1567 ushort_t *temp, num_of_nodes; 1568 uintptr_t addr; 1569 int i, j, k; 1570 1571 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1572 "ehci_build_interrupt_lattice:"); 1573 1574 /* 1575 * Reserve the first 63 Endpoint Descriptor (QH) structures 1576 * in the pool as static endpoints & these are required for 1577 * constructing interrupt lattice tree. 1578 */ 1579 for (i = 0; i < EHCI_NUM_STATIC_NODES; i++) { 1580 Set_QH(list_array[i].qh_state, EHCI_QH_STATIC); 1581 Set_QH(list_array[i].qh_status, EHCI_QH_STS_HALTED); 1582 Set_QH(list_array[i].qh_next_qtd, EHCI_QH_NEXT_QTD_PTR_VALID); 1583 Set_QH(list_array[i].qh_alt_next_qtd, 1584 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1585 } 1586 1587 /* 1588 * Make sure that last Endpoint on the periodic frame list terminates 1589 * periodic schedule. 1590 */ 1591 Set_QH(list_array[0].qh_link_ptr, EHCI_QH_LINK_PTR_VALID); 1592 1593 /* Build the interrupt lattice tree */ 1594 for (i = 0; i < (EHCI_NUM_STATIC_NODES / 2); i++) { 1595 /* 1596 * The next pointer in the host controller endpoint 1597 * descriptor must contain an iommu address. Calculate 1598 * the offset into the cpu address and add this to the 1599 * starting iommu address. 1600 */ 1601 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *)&list_array[i]); 1602 1603 Set_QH(list_array[2*i + 1].qh_link_ptr, 1604 addr | EHCI_QH_LINK_REF_QH); 1605 Set_QH(list_array[2*i + 2].qh_link_ptr, 1606 addr | EHCI_QH_LINK_REF_QH); 1607 } 1608 1609 /* Build the tree bottom */ 1610 temp = (unsigned short *) 1611 kmem_zalloc(EHCI_NUM_PERIODIC_FRAME_LISTS * 2, KM_SLEEP); 1612 1613 num_of_nodes = 1; 1614 1615 /* 1616 * Initialize the values which are used for setting up head pointers 1617 * for the 32ms scheduling lists which starts from the Periodic Frame 1618 * List. 1619 */ 1620 for (i = 0; i < ehci_log_2(EHCI_NUM_PERIODIC_FRAME_LISTS); i++) { 1621 for (j = 0, k = 0; k < num_of_nodes; k++, j++) { 1622 ehci_index[j++] = temp[k]; 1623 ehci_index[j] = temp[k] + ehci_pow_2(i); 1624 } 1625 1626 num_of_nodes *= 2; 1627 for (k = 0; k < num_of_nodes; k++) 1628 temp[k] = ehci_index[k]; 1629 } 1630 1631 kmem_free((void *)temp, (EHCI_NUM_PERIODIC_FRAME_LISTS * 2)); 1632 1633 /* 1634 * Initialize the interrupt list in the Periodic Frame List Table 1635 * so that it points to the bottom of the tree. 1636 */ 1637 for (i = 0, j = 0; i < ehci_pow_2(TREE_HEIGHT); i++) { 1638 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *) 1639 (&list_array[((EHCI_NUM_STATIC_NODES + 1) / 2) + i - 1])); 1640 1641 ASSERT(addr); 1642 1643 for (k = 0; k < ehci_pow_2(TREE_HEIGHT); k++) { 1644 Set_PFLT(periodic_frame_list-> 1645 ehci_periodic_frame_list_table[ehci_index[j++]], 1646 (uint32_t)(addr | EHCI_QH_LINK_REF_QH)); 1647 } 1648 } 1649 } 1650 1651 1652 /* 1653 * ehci_alloc_hcdi_ops: 1654 * 1655 * The HCDI interfaces or entry points are the software interfaces used by 1656 * the Universal Serial Bus Driver (USBA) to access the services of the 1657 * Host Controller Driver (HCD). During HCD initialization, inform USBA 1658 * about all available HCDI interfaces or entry points. 1659 */ 1660 usba_hcdi_ops_t * 1661 ehci_alloc_hcdi_ops(ehci_state_t *ehcip) 1662 { 1663 usba_hcdi_ops_t *usba_hcdi_ops; 1664 1665 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1666 "ehci_alloc_hcdi_ops:"); 1667 1668 usba_hcdi_ops = usba_alloc_hcdi_ops(); 1669 1670 usba_hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION; 1671 1672 usba_hcdi_ops->usba_hcdi_pm_support = ehci_hcdi_pm_support; 1673 usba_hcdi_ops->usba_hcdi_pipe_open = ehci_hcdi_pipe_open; 1674 usba_hcdi_ops->usba_hcdi_pipe_close = ehci_hcdi_pipe_close; 1675 1676 usba_hcdi_ops->usba_hcdi_pipe_reset = ehci_hcdi_pipe_reset; 1677 1678 usba_hcdi_ops->usba_hcdi_pipe_ctrl_xfer = ehci_hcdi_pipe_ctrl_xfer; 1679 usba_hcdi_ops->usba_hcdi_pipe_bulk_xfer = ehci_hcdi_pipe_bulk_xfer; 1680 usba_hcdi_ops->usba_hcdi_pipe_intr_xfer = ehci_hcdi_pipe_intr_xfer; 1681 usba_hcdi_ops->usba_hcdi_pipe_isoc_xfer = ehci_hcdi_pipe_isoc_xfer; 1682 1683 usba_hcdi_ops->usba_hcdi_bulk_transfer_size = 1684 ehci_hcdi_bulk_transfer_size; 1685 1686 usba_hcdi_ops->usba_hcdi_pipe_stop_intr_polling = 1687 ehci_hcdi_pipe_stop_intr_polling; 1688 usba_hcdi_ops->usba_hcdi_pipe_stop_isoc_polling = 1689 ehci_hcdi_pipe_stop_isoc_polling; 1690 1691 usba_hcdi_ops->usba_hcdi_get_current_frame_number = 1692 ehci_hcdi_get_current_frame_number; 1693 usba_hcdi_ops->usba_hcdi_get_max_isoc_pkts = 1694 ehci_hcdi_get_max_isoc_pkts; 1695 1696 usba_hcdi_ops->usba_hcdi_console_input_init = 1697 ehci_hcdi_polled_input_init; 1698 usba_hcdi_ops->usba_hcdi_console_input_enter = 1699 ehci_hcdi_polled_input_enter; 1700 usba_hcdi_ops->usba_hcdi_console_read = 1701 ehci_hcdi_polled_read; 1702 usba_hcdi_ops->usba_hcdi_console_input_exit = 1703 ehci_hcdi_polled_input_exit; 1704 usba_hcdi_ops->usba_hcdi_console_input_fini = 1705 ehci_hcdi_polled_input_fini; 1706 return (usba_hcdi_ops); 1707 } 1708 1709 1710 /* 1711 * Host Controller Driver (HCD) deinitialization functions 1712 */ 1713 1714 /* 1715 * ehci_cleanup: 1716 * 1717 * Cleanup on attach failure or detach 1718 */ 1719 int 1720 ehci_cleanup(ehci_state_t *ehcip) 1721 { 1722 ehci_trans_wrapper_t *tw; 1723 ehci_pipe_private_t *pp; 1724 ehci_qtd_t *qtd; 1725 int i, ctrl, rval; 1726 int flags = ehcip->ehci_flags; 1727 1728 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_cleanup:"); 1729 1730 if (flags & EHCI_RHREG) { 1731 /* Unload the root hub driver */ 1732 if (ehci_unload_root_hub_driver(ehcip) != USB_SUCCESS) { 1733 1734 return (DDI_FAILURE); 1735 } 1736 } 1737 1738 if (flags & EHCI_USBAREG) { 1739 /* Unregister this HCD instance with USBA */ 1740 usba_hcdi_unregister(ehcip->ehci_dip); 1741 } 1742 1743 if (flags & EHCI_INTR) { 1744 1745 mutex_enter(&ehcip->ehci_int_mutex); 1746 1747 /* Disable all EHCI QH list processing */ 1748 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1749 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | 1750 EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1751 1752 /* Disable all EHCI interrupts */ 1753 Set_OpReg(ehci_interrupt, 0); 1754 1755 /* wait for the next SOF */ 1756 (void) ehci_wait_for_sof(ehcip); 1757 1758 /* Route all Root hub ports to Classic host controller */ 1759 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1760 1761 /* Stop the EHCI host controller */ 1762 Set_OpReg(ehci_command, 1763 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1764 1765 /* Wait for sometime */ 1766 drv_usecwait(EHCI_TIMEWAIT); 1767 1768 mutex_exit(&ehcip->ehci_int_mutex); 1769 1770 ehci_rem_intrs(ehcip); 1771 } 1772 1773 /* Unmap the EHCI registers */ 1774 if (ehcip->ehci_caps_handle) { 1775 ddi_regs_map_free(&ehcip->ehci_caps_handle); 1776 } 1777 1778 if (ehcip->ehci_config_handle) { 1779 pci_config_teardown(&ehcip->ehci_config_handle); 1780 } 1781 1782 /* Free all the buffers */ 1783 if (ehcip->ehci_qtd_pool_addr && ehcip->ehci_qtd_pool_mem_handle) { 1784 for (i = 0; i < ehci_qtd_pool_size; i ++) { 1785 qtd = &ehcip->ehci_qtd_pool_addr[i]; 1786 ctrl = Get_QTD(ehcip-> 1787 ehci_qtd_pool_addr[i].qtd_state); 1788 1789 if ((ctrl != EHCI_QTD_FREE) && 1790 (ctrl != EHCI_QTD_DUMMY) && 1791 (qtd->qtd_trans_wrapper)) { 1792 1793 mutex_enter(&ehcip->ehci_int_mutex); 1794 1795 tw = (ehci_trans_wrapper_t *) 1796 EHCI_LOOKUP_ID((uint32_t) 1797 Get_QTD(qtd->qtd_trans_wrapper)); 1798 1799 /* Obtain the pipe private structure */ 1800 pp = tw->tw_pipe_private; 1801 1802 /* Stop the the transfer timer */ 1803 ehci_stop_xfer_timer(ehcip, tw, 1804 EHCI_REMOVE_XFER_ALWAYS); 1805 1806 ehci_deallocate_tw(ehcip, pp, tw); 1807 1808 mutex_exit(&ehcip->ehci_int_mutex); 1809 } 1810 } 1811 1812 /* 1813 * If EHCI_QTD_POOL_BOUND flag is set, then unbind 1814 * the handle for QTD pools. 1815 */ 1816 if ((ehcip->ehci_dma_addr_bind_flag & 1817 EHCI_QTD_POOL_BOUND) == EHCI_QTD_POOL_BOUND) { 1818 1819 rval = ddi_dma_unbind_handle( 1820 ehcip->ehci_qtd_pool_dma_handle); 1821 1822 ASSERT(rval == DDI_SUCCESS); 1823 } 1824 ddi_dma_mem_free(&ehcip->ehci_qtd_pool_mem_handle); 1825 } 1826 1827 /* Free the QTD pool */ 1828 if (ehcip->ehci_qtd_pool_dma_handle) { 1829 ddi_dma_free_handle(&ehcip->ehci_qtd_pool_dma_handle); 1830 } 1831 1832 if (ehcip->ehci_qh_pool_addr && ehcip->ehci_qh_pool_mem_handle) { 1833 /* 1834 * If EHCI_QH_POOL_BOUND flag is set, then unbind 1835 * the handle for QH pools. 1836 */ 1837 if ((ehcip->ehci_dma_addr_bind_flag & 1838 EHCI_QH_POOL_BOUND) == EHCI_QH_POOL_BOUND) { 1839 1840 rval = ddi_dma_unbind_handle( 1841 ehcip->ehci_qh_pool_dma_handle); 1842 1843 ASSERT(rval == DDI_SUCCESS); 1844 } 1845 1846 ddi_dma_mem_free(&ehcip->ehci_qh_pool_mem_handle); 1847 } 1848 1849 /* Free the QH pool */ 1850 if (ehcip->ehci_qh_pool_dma_handle) { 1851 ddi_dma_free_handle(&ehcip->ehci_qh_pool_dma_handle); 1852 } 1853 1854 /* Free the Periodic frame list table (PFLT) area */ 1855 if (ehcip->ehci_periodic_frame_list_tablep && 1856 ehcip->ehci_pflt_mem_handle) { 1857 /* 1858 * If EHCI_PFLT_DMA_BOUND flag is set, then unbind 1859 * the handle for PFLT. 1860 */ 1861 if ((ehcip->ehci_dma_addr_bind_flag & 1862 EHCI_PFLT_DMA_BOUND) == EHCI_PFLT_DMA_BOUND) { 1863 1864 rval = ddi_dma_unbind_handle( 1865 ehcip->ehci_pflt_dma_handle); 1866 1867 ASSERT(rval == DDI_SUCCESS); 1868 } 1869 1870 ddi_dma_mem_free(&ehcip->ehci_pflt_mem_handle); 1871 } 1872 1873 (void) ehci_isoc_cleanup(ehcip); 1874 1875 if (ehcip->ehci_pflt_dma_handle) { 1876 ddi_dma_free_handle(&ehcip->ehci_pflt_dma_handle); 1877 } 1878 1879 if (flags & EHCI_INTR) { 1880 /* Destroy the mutex */ 1881 mutex_destroy(&ehcip->ehci_int_mutex); 1882 1883 /* Destroy the async schedule advance condition variable */ 1884 cv_destroy(&ehcip->ehci_async_schedule_advance_cv); 1885 } 1886 1887 /* clean up kstat structs */ 1888 ehci_destroy_stats(ehcip); 1889 1890 /* Free ehci hcdi ops */ 1891 if (ehcip->ehci_hcdi_ops) { 1892 usba_free_hcdi_ops(ehcip->ehci_hcdi_ops); 1893 } 1894 1895 if (flags & EHCI_ZALLOC) { 1896 1897 usb_free_log_hdl(ehcip->ehci_log_hdl); 1898 1899 /* Remove all properties that might have been created */ 1900 ddi_prop_remove_all(ehcip->ehci_dip); 1901 1902 /* Free the soft state */ 1903 ddi_soft_state_free(ehci_statep, 1904 ddi_get_instance(ehcip->ehci_dip)); 1905 } 1906 1907 return (DDI_SUCCESS); 1908 } 1909 1910 1911 /* 1912 * ehci_rem_intrs: 1913 * 1914 * Unregister FIXED or MSI interrupts 1915 */ 1916 static void 1917 ehci_rem_intrs(ehci_state_t *ehcip) 1918 { 1919 int i; 1920 1921 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1922 "ehci_rem_intrs: interrupt type 0x%x", ehcip->ehci_intr_type); 1923 1924 /* Disable all interrupts */ 1925 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 1926 (void) ddi_intr_block_disable(ehcip->ehci_htable, 1927 ehcip->ehci_intr_cnt); 1928 } else { 1929 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1930 (void) ddi_intr_disable(ehcip->ehci_htable[i]); 1931 } 1932 } 1933 1934 /* Call ddi_intr_remove_handler() */ 1935 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1936 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 1937 (void) ddi_intr_free(ehcip->ehci_htable[i]); 1938 } 1939 1940 kmem_free(ehcip->ehci_htable, 1941 ehcip->ehci_intr_cnt * sizeof (ddi_intr_handle_t)); 1942 } 1943 1944 1945 /* 1946 * ehci_cpr_suspend 1947 */ 1948 int 1949 ehci_cpr_suspend(ehci_state_t *ehcip) 1950 { 1951 int i; 1952 1953 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1954 "ehci_cpr_suspend:"); 1955 1956 /* Call into the root hub and suspend it */ 1957 if (usba_hubdi_detach(ehcip->ehci_dip, DDI_SUSPEND) != DDI_SUCCESS) { 1958 1959 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1960 "ehci_cpr_suspend: root hub fails to suspend"); 1961 1962 return (DDI_FAILURE); 1963 } 1964 1965 /* Only root hub's intr pipe should be open at this time */ 1966 mutex_enter(&ehcip->ehci_int_mutex); 1967 1968 ASSERT(ehcip->ehci_open_pipe_count == 0); 1969 1970 /* Just wait till all resources are reclaimed */ 1971 i = 0; 1972 while ((ehcip->ehci_reclaim_list != NULL) && (i++ < 3)) { 1973 ehci_handle_endpoint_reclaimation(ehcip); 1974 (void) ehci_wait_for_sof(ehcip); 1975 } 1976 ASSERT(ehcip->ehci_reclaim_list == NULL); 1977 1978 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1979 "ehci_cpr_suspend: Disable HC QH list processing"); 1980 1981 /* Disable all EHCI QH list processing */ 1982 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1983 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1984 1985 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1986 "ehci_cpr_suspend: Disable HC interrupts"); 1987 1988 /* Disable all EHCI interrupts */ 1989 Set_OpReg(ehci_interrupt, 0); 1990 1991 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1992 "ehci_cpr_suspend: Wait for the next SOF"); 1993 1994 /* Wait for the next SOF */ 1995 if (ehci_wait_for_sof(ehcip) != USB_SUCCESS) { 1996 1997 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1998 "ehci_cpr_suspend: ehci host controller suspend failed"); 1999 2000 mutex_exit(&ehcip->ehci_int_mutex); 2001 return (DDI_FAILURE); 2002 } 2003 2004 /* 2005 * Stop the ehci host controller 2006 * if usb keyboard is not connected. 2007 */ 2008 if (ehcip->ehci_polled_kbd_count == 0) { 2009 Set_OpReg(ehci_command, 2010 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 2011 } 2012 2013 /* Set host controller soft state to suspend */ 2014 ehcip->ehci_hc_soft_state = EHCI_CTLR_SUSPEND_STATE; 2015 2016 mutex_exit(&ehcip->ehci_int_mutex); 2017 2018 return (DDI_SUCCESS); 2019 } 2020 2021 2022 /* 2023 * ehci_cpr_resume 2024 */ 2025 int 2026 ehci_cpr_resume(ehci_state_t *ehcip) 2027 { 2028 mutex_enter(&ehcip->ehci_int_mutex); 2029 2030 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2031 "ehci_cpr_resume: Restart the controller"); 2032 2033 /* Cleanup ehci specific information across cpr */ 2034 ehci_cpr_cleanup(ehcip); 2035 2036 /* Restart the controller */ 2037 if (ehci_init_ctlr(ehcip, EHCI_NORMAL_INITIALIZATION) != DDI_SUCCESS) { 2038 2039 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2040 "ehci_cpr_resume: ehci host controller resume failed "); 2041 2042 mutex_exit(&ehcip->ehci_int_mutex); 2043 2044 return (DDI_FAILURE); 2045 } 2046 2047 mutex_exit(&ehcip->ehci_int_mutex); 2048 2049 /* Now resume the root hub */ 2050 if (usba_hubdi_attach(ehcip->ehci_dip, DDI_RESUME) != DDI_SUCCESS) { 2051 2052 return (DDI_FAILURE); 2053 } 2054 2055 return (DDI_SUCCESS); 2056 } 2057 2058 2059 /* 2060 * Bandwidth Allocation functions 2061 */ 2062 2063 /* 2064 * ehci_allocate_bandwidth: 2065 * 2066 * Figure out whether or not this interval may be supported. Return the index 2067 * into the lattice if it can be supported. Return allocation failure if it 2068 * can not be supported. 2069 */ 2070 int 2071 ehci_allocate_bandwidth( 2072 ehci_state_t *ehcip, 2073 usba_pipe_handle_data_t *ph, 2074 uint_t *pnode, 2075 uchar_t *smask, 2076 uchar_t *cmask) 2077 { 2078 int error = USB_SUCCESS; 2079 2080 /* This routine is protected by the ehci_int_mutex */ 2081 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2082 2083 /* Reset the pnode to the last checked pnode */ 2084 *pnode = 0; 2085 2086 /* Allocate high speed bandwidth */ 2087 if ((error = ehci_allocate_high_speed_bandwidth(ehcip, 2088 ph, pnode, smask, cmask)) != USB_SUCCESS) { 2089 2090 return (error); 2091 } 2092 2093 /* 2094 * For low/full speed usb devices, allocate classic TT bandwidth 2095 * in additional to high speed bandwidth. 2096 */ 2097 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2098 2099 /* Allocate classic TT bandwidth */ 2100 if ((error = ehci_allocate_classic_tt_bandwidth( 2101 ehcip, ph, *pnode)) != USB_SUCCESS) { 2102 2103 /* Deallocate high speed bandwidth */ 2104 ehci_deallocate_high_speed_bandwidth( 2105 ehcip, ph, *pnode, *smask, *cmask); 2106 } 2107 } 2108 2109 return (error); 2110 } 2111 2112 2113 /* 2114 * ehci_allocate_high_speed_bandwidth: 2115 * 2116 * Allocate high speed bandwidth for the low/full/high speed interrupt and 2117 * isochronous endpoints. 2118 */ 2119 static int 2120 ehci_allocate_high_speed_bandwidth( 2121 ehci_state_t *ehcip, 2122 usba_pipe_handle_data_t *ph, 2123 uint_t *pnode, 2124 uchar_t *smask, 2125 uchar_t *cmask) 2126 { 2127 uint_t sbandwidth, cbandwidth; 2128 int interval; 2129 usb_ep_descr_t *endpoint = &ph->p_ep; 2130 usba_device_t *child_ud; 2131 usb_port_status_t port_status; 2132 int error; 2133 2134 /* This routine is protected by the ehci_int_mutex */ 2135 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2136 2137 /* Get child's usba device structure */ 2138 child_ud = ph->p_usba_device; 2139 2140 mutex_enter(&child_ud->usb_mutex); 2141 2142 /* Get the current usb device's port status */ 2143 port_status = ph->p_usba_device->usb_port_status; 2144 2145 mutex_exit(&child_ud->usb_mutex); 2146 2147 /* 2148 * Calculate the length in bytes of a transaction on this 2149 * periodic endpoint. Return failure if maximum packet is 2150 * zero. 2151 */ 2152 error = ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2153 port_status, &sbandwidth, &cbandwidth); 2154 if (error != USB_SUCCESS) { 2155 2156 return (error); 2157 } 2158 2159 /* 2160 * Adjust polling interval to be a power of 2. 2161 * If this interval can't be supported, return 2162 * allocation failure. 2163 */ 2164 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2165 if (interval == USB_FAILURE) { 2166 2167 return (USB_FAILURE); 2168 } 2169 2170 if (port_status == USBA_HIGH_SPEED_DEV) { 2171 /* Allocate bandwidth for high speed devices, except ITD */ 2172 error = ehci_find_bestfit_hs_mask(ehcip, smask, pnode, 2173 endpoint, sbandwidth, interval); 2174 *cmask = 0x00; 2175 2176 } else { 2177 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2178 USB_EP_ATTR_INTR) { 2179 2180 /* Allocate bandwidth for low speed interrupt */ 2181 error = ehci_find_bestfit_ls_intr_mask(ehcip, 2182 smask, cmask, pnode, sbandwidth, cbandwidth, 2183 interval); 2184 } else { 2185 if ((endpoint->bEndpointAddress & 2186 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2187 2188 /* Allocate bandwidth for sitd in */ 2189 error = ehci_find_bestfit_sitd_in_mask(ehcip, 2190 smask, cmask, pnode, sbandwidth, cbandwidth, 2191 interval); 2192 } else { 2193 2194 /* Allocate bandwidth for sitd out */ 2195 error = ehci_find_bestfit_sitd_out_mask(ehcip, 2196 smask, pnode, sbandwidth, interval); 2197 *cmask = 0x00; 2198 } 2199 } 2200 } 2201 2202 if (error != USB_SUCCESS) { 2203 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2204 "ehci_allocate_high_speed_bandwidth: Reached maximum " 2205 "bandwidth value and cannot allocate bandwidth for a " 2206 "given high-speed periodic endpoint"); 2207 2208 return (USB_NO_BANDWIDTH); 2209 } 2210 2211 return (error); 2212 } 2213 2214 2215 /* 2216 * ehci_allocate_classic_tt_speed_bandwidth: 2217 * 2218 * Allocate classic TT bandwidth for the low/full speed interrupt and 2219 * isochronous endpoints. 2220 */ 2221 static int 2222 ehci_allocate_classic_tt_bandwidth( 2223 ehci_state_t *ehcip, 2224 usba_pipe_handle_data_t *ph, 2225 uint_t pnode) 2226 { 2227 uint_t bandwidth, min; 2228 uint_t height, leftmost, list; 2229 usb_ep_descr_t *endpoint = &ph->p_ep; 2230 usba_device_t *child_ud, *parent_ud; 2231 usb_port_status_t port_status; 2232 int i, interval; 2233 2234 /* This routine is protected by the ehci_int_mutex */ 2235 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2236 2237 /* Get child's usba device structure */ 2238 child_ud = ph->p_usba_device; 2239 2240 mutex_enter(&child_ud->usb_mutex); 2241 2242 /* Get the current usb device's port status */ 2243 port_status = child_ud->usb_port_status; 2244 2245 /* Get the parent high speed hub's usba device structure */ 2246 parent_ud = child_ud->usb_hs_hub_usba_dev; 2247 2248 mutex_exit(&child_ud->usb_mutex); 2249 2250 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2251 "ehci_allocate_classic_tt_bandwidth: " 2252 "child_ud 0x%p parent_ud 0x%p", child_ud, parent_ud); 2253 2254 /* 2255 * Calculate the length in bytes of a transaction on this 2256 * periodic endpoint. Return failure if maximum packet is 2257 * zero. 2258 */ 2259 if (ehci_compute_classic_bandwidth(endpoint, 2260 port_status, &bandwidth) != USB_SUCCESS) { 2261 2262 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2263 "ehci_allocate_classic_tt_bandwidth: Periodic endpoint " 2264 "with zero endpoint maximum packet size is not supported"); 2265 2266 return (USB_NOT_SUPPORTED); 2267 } 2268 2269 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2270 "ehci_allocate_classic_tt_bandwidth: bandwidth %d", bandwidth); 2271 2272 mutex_enter(&parent_ud->usb_mutex); 2273 2274 /* 2275 * If the length in bytes plus the allocated bandwidth exceeds 2276 * the maximum, return bandwidth allocation failure. 2277 */ 2278 if ((parent_ud->usb_hs_hub_min_bandwidth + bandwidth) > 2279 FS_PERIODIC_BANDWIDTH) { 2280 2281 mutex_exit(&parent_ud->usb_mutex); 2282 2283 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2284 "ehci_allocate_classic_tt_bandwidth: Reached maximum " 2285 "bandwidth value and cannot allocate bandwidth for a " 2286 "given low/full speed periodic endpoint"); 2287 2288 return (USB_NO_BANDWIDTH); 2289 } 2290 2291 mutex_exit(&parent_ud->usb_mutex); 2292 2293 /* Adjust polling interval to be a power of 2 */ 2294 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2295 2296 /* Find the height in the tree */ 2297 height = ehci_lattice_height(interval); 2298 2299 /* Find the leftmost leaf in the subtree specified by the node. */ 2300 leftmost = ehci_leftmost_leaf(pnode, height); 2301 2302 mutex_enter(&parent_ud->usb_mutex); 2303 2304 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2305 list = ehci_index[leftmost + i]; 2306 2307 if ((parent_ud->usb_hs_hub_bandwidth[list] + 2308 bandwidth) > FS_PERIODIC_BANDWIDTH) { 2309 2310 mutex_exit(&parent_ud->usb_mutex); 2311 2312 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2313 "ehci_allocate_classic_tt_bandwidth: Reached " 2314 "maximum bandwidth value and cannot allocate " 2315 "bandwidth for low/full periodic endpoint"); 2316 2317 return (USB_NO_BANDWIDTH); 2318 } 2319 } 2320 2321 /* 2322 * All the leaves for this node must be updated with the bandwidth. 2323 */ 2324 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2325 list = ehci_index[leftmost + i]; 2326 parent_ud->usb_hs_hub_bandwidth[list] += bandwidth; 2327 } 2328 2329 /* Find the leaf with the smallest allocated bandwidth */ 2330 min = parent_ud->usb_hs_hub_bandwidth[0]; 2331 2332 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2333 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2334 min = parent_ud->usb_hs_hub_bandwidth[i]; 2335 } 2336 } 2337 2338 /* Save the minimum for later use */ 2339 parent_ud->usb_hs_hub_min_bandwidth = min; 2340 2341 mutex_exit(&parent_ud->usb_mutex); 2342 2343 return (USB_SUCCESS); 2344 } 2345 2346 2347 /* 2348 * ehci_deallocate_bandwidth: 2349 * 2350 * Deallocate bandwidth for the given node in the lattice and the length 2351 * of transfer. 2352 */ 2353 void 2354 ehci_deallocate_bandwidth( 2355 ehci_state_t *ehcip, 2356 usba_pipe_handle_data_t *ph, 2357 uint_t pnode, 2358 uchar_t smask, 2359 uchar_t cmask) 2360 { 2361 /* This routine is protected by the ehci_int_mutex */ 2362 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2363 2364 ehci_deallocate_high_speed_bandwidth(ehcip, ph, pnode, smask, cmask); 2365 2366 /* 2367 * For low/full speed usb devices, deallocate classic TT bandwidth 2368 * in additional to high speed bandwidth. 2369 */ 2370 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2371 2372 /* Deallocate classic TT bandwidth */ 2373 ehci_deallocate_classic_tt_bandwidth(ehcip, ph, pnode); 2374 } 2375 } 2376 2377 2378 /* 2379 * ehci_deallocate_high_speed_bandwidth: 2380 * 2381 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2382 */ 2383 static void 2384 ehci_deallocate_high_speed_bandwidth( 2385 ehci_state_t *ehcip, 2386 usba_pipe_handle_data_t *ph, 2387 uint_t pnode, 2388 uchar_t smask, 2389 uchar_t cmask) 2390 { 2391 uint_t height, leftmost; 2392 uint_t list_count; 2393 uint_t sbandwidth, cbandwidth; 2394 int interval; 2395 usb_ep_descr_t *endpoint = &ph->p_ep; 2396 usba_device_t *child_ud; 2397 usb_port_status_t port_status; 2398 2399 /* This routine is protected by the ehci_int_mutex */ 2400 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2401 2402 /* Get child's usba device structure */ 2403 child_ud = ph->p_usba_device; 2404 2405 mutex_enter(&child_ud->usb_mutex); 2406 2407 /* Get the current usb device's port status */ 2408 port_status = ph->p_usba_device->usb_port_status; 2409 2410 mutex_exit(&child_ud->usb_mutex); 2411 2412 (void) ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2413 port_status, &sbandwidth, &cbandwidth); 2414 2415 /* Adjust polling interval to be a power of 2 */ 2416 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2417 2418 /* Find the height in the tree */ 2419 height = ehci_lattice_height(interval); 2420 2421 /* 2422 * Find the leftmost leaf in the subtree specified by the node 2423 */ 2424 leftmost = ehci_leftmost_leaf(pnode, height); 2425 2426 list_count = EHCI_NUM_INTR_QH_LISTS/interval; 2427 2428 /* Delete the bandwidth from the appropriate lists */ 2429 if (port_status == USBA_HIGH_SPEED_DEV) { 2430 2431 ehci_update_bw_availability(ehcip, -sbandwidth, 2432 leftmost, list_count, smask); 2433 } else { 2434 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2435 USB_EP_ATTR_INTR) { 2436 2437 ehci_update_bw_availability(ehcip, -sbandwidth, 2438 leftmost, list_count, smask); 2439 ehci_update_bw_availability(ehcip, -cbandwidth, 2440 leftmost, list_count, cmask); 2441 } else { 2442 if ((endpoint->bEndpointAddress & 2443 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2444 2445 ehci_update_bw_availability(ehcip, -sbandwidth, 2446 leftmost, list_count, smask); 2447 ehci_update_bw_availability(ehcip, 2448 -MAX_UFRAME_SITD_XFER, leftmost, 2449 list_count, cmask); 2450 } else { 2451 2452 ehci_update_bw_availability(ehcip, 2453 -MAX_UFRAME_SITD_XFER, leftmost, 2454 list_count, smask); 2455 } 2456 } 2457 } 2458 } 2459 2460 /* 2461 * ehci_deallocate_classic_tt_bandwidth: 2462 * 2463 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2464 */ 2465 static void 2466 ehci_deallocate_classic_tt_bandwidth( 2467 ehci_state_t *ehcip, 2468 usba_pipe_handle_data_t *ph, 2469 uint_t pnode) 2470 { 2471 uint_t bandwidth, height, leftmost, list, min; 2472 int i, interval; 2473 usb_ep_descr_t *endpoint = &ph->p_ep; 2474 usba_device_t *child_ud, *parent_ud; 2475 usb_port_status_t port_status; 2476 2477 /* This routine is protected by the ehci_int_mutex */ 2478 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2479 2480 /* Get child's usba device structure */ 2481 child_ud = ph->p_usba_device; 2482 2483 mutex_enter(&child_ud->usb_mutex); 2484 2485 /* Get the current usb device's port status */ 2486 port_status = child_ud->usb_port_status; 2487 2488 /* Get the parent high speed hub's usba device structure */ 2489 parent_ud = child_ud->usb_hs_hub_usba_dev; 2490 2491 mutex_exit(&child_ud->usb_mutex); 2492 2493 /* Obtain the bandwidth */ 2494 (void) ehci_compute_classic_bandwidth(endpoint, 2495 port_status, &bandwidth); 2496 2497 /* Adjust polling interval to be a power of 2 */ 2498 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2499 2500 /* Find the height in the tree */ 2501 height = ehci_lattice_height(interval); 2502 2503 /* Find the leftmost leaf in the subtree specified by the node */ 2504 leftmost = ehci_leftmost_leaf(pnode, height); 2505 2506 mutex_enter(&parent_ud->usb_mutex); 2507 2508 /* Delete the bandwidth from the appropriate lists */ 2509 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2510 list = ehci_index[leftmost + i]; 2511 parent_ud->usb_hs_hub_bandwidth[list] -= bandwidth; 2512 } 2513 2514 /* Find the leaf with the smallest allocated bandwidth */ 2515 min = parent_ud->usb_hs_hub_bandwidth[0]; 2516 2517 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2518 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2519 min = parent_ud->usb_hs_hub_bandwidth[i]; 2520 } 2521 } 2522 2523 /* Save the minimum for later use */ 2524 parent_ud->usb_hs_hub_min_bandwidth = min; 2525 2526 mutex_exit(&parent_ud->usb_mutex); 2527 } 2528 2529 2530 /* 2531 * ehci_compute_high_speed_bandwidth: 2532 * 2533 * Given a periodic endpoint (interrupt or isochronous) determine the total 2534 * bandwidth for one transaction. The EHCI host controller traverses the 2535 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2536 * services an endpoint, only a single transaction attempt is made. The HC 2537 * moves to the next Endpoint Descriptor after the first transaction attempt 2538 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2539 * Transfer Descriptor is inserted into the lattice, we will only count the 2540 * number of bytes for one transaction. 2541 * 2542 * The following are the formulas used for calculating bandwidth in terms 2543 * bytes and it is for the single USB high speed transaction. The protocol 2544 * overheads will be different for each of type of USB transfer & all these 2545 * formulas & protocol overheads are derived from the 5.11.3 section of the 2546 * USB 2.0 Specification. 2547 * 2548 * High-Speed: 2549 * Protocol overhead + ((MaxPktSz * 7)/6) + Host_Delay 2550 * 2551 * Split Transaction: (Low/Full speed devices connected behind usb2.0 hub) 2552 * 2553 * Protocol overhead + Split transaction overhead + 2554 * ((MaxPktSz * 7)/6) + Host_Delay; 2555 */ 2556 /* ARGSUSED */ 2557 static int 2558 ehci_compute_high_speed_bandwidth( 2559 ehci_state_t *ehcip, 2560 usb_ep_descr_t *endpoint, 2561 usb_port_status_t port_status, 2562 uint_t *sbandwidth, 2563 uint_t *cbandwidth) 2564 { 2565 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2566 2567 /* Return failure if endpoint maximum packet is zero */ 2568 if (maxpacketsize == 0) { 2569 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2570 "ehci_allocate_high_speed_bandwidth: Periodic endpoint " 2571 "with zero endpoint maximum packet size is not supported"); 2572 2573 return (USB_NOT_SUPPORTED); 2574 } 2575 2576 /* Add bit-stuffing overhead */ 2577 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2578 2579 /* Add Host Controller specific delay to required bandwidth */ 2580 *sbandwidth = EHCI_HOST_CONTROLLER_DELAY; 2581 2582 /* Add xfer specific protocol overheads */ 2583 if ((endpoint->bmAttributes & 2584 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2585 /* High speed interrupt transaction */ 2586 *sbandwidth += HS_NON_ISOC_PROTO_OVERHEAD; 2587 } else { 2588 /* Isochronous transaction */ 2589 *sbandwidth += HS_ISOC_PROTO_OVERHEAD; 2590 } 2591 2592 /* 2593 * For low/full speed devices, add split transaction specific 2594 * overheads. 2595 */ 2596 if (port_status != USBA_HIGH_SPEED_DEV) { 2597 /* 2598 * Add start and complete split transaction 2599 * tokens overheads. 2600 */ 2601 *cbandwidth = *sbandwidth + COMPLETE_SPLIT_OVERHEAD; 2602 *sbandwidth += START_SPLIT_OVERHEAD; 2603 2604 /* Add data overhead depending on data direction */ 2605 if ((endpoint->bEndpointAddress & 2606 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2607 *cbandwidth += maxpacketsize; 2608 } else { 2609 if ((endpoint->bmAttributes & 2610 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 2611 /* There is no compete splits for out */ 2612 *cbandwidth = 0; 2613 } 2614 *sbandwidth += maxpacketsize; 2615 } 2616 } else { 2617 uint_t xactions; 2618 2619 /* Get the max transactions per microframe */ 2620 xactions = ((maxpacketsize & USB_EP_MAX_XACTS_MASK) >> 2621 USB_EP_MAX_XACTS_SHIFT) + 1; 2622 2623 /* High speed transaction */ 2624 *sbandwidth += maxpacketsize; 2625 2626 /* Calculate bandwidth per micro-frame */ 2627 *sbandwidth *= xactions; 2628 2629 *cbandwidth = 0; 2630 } 2631 2632 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2633 "ehci_allocate_high_speed_bandwidth: " 2634 "Start split bandwidth %d Complete split bandwidth %d", 2635 *sbandwidth, *cbandwidth); 2636 2637 return (USB_SUCCESS); 2638 } 2639 2640 2641 /* 2642 * ehci_compute_classic_bandwidth: 2643 * 2644 * Given a periodic endpoint (interrupt or isochronous) determine the total 2645 * bandwidth for one transaction. The EHCI host controller traverses the 2646 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2647 * services an endpoint, only a single transaction attempt is made. The HC 2648 * moves to the next Endpoint Descriptor after the first transaction attempt 2649 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2650 * Transfer Descriptor is inserted into the lattice, we will only count the 2651 * number of bytes for one transaction. 2652 * 2653 * The following are the formulas used for calculating bandwidth in terms 2654 * bytes and it is for the single USB high speed transaction. The protocol 2655 * overheads will be different for each of type of USB transfer & all these 2656 * formulas & protocol overheads are derived from the 5.11.3 section of the 2657 * USB 2.0 Specification. 2658 * 2659 * Low-Speed: 2660 * Protocol overhead + Hub LS overhead + 2661 * (Low Speed clock * ((MaxPktSz * 7)/6)) + TT_Delay 2662 * 2663 * Full-Speed: 2664 * Protocol overhead + ((MaxPktSz * 7)/6) + TT_Delay 2665 */ 2666 /* ARGSUSED */ 2667 static int 2668 ehci_compute_classic_bandwidth( 2669 usb_ep_descr_t *endpoint, 2670 usb_port_status_t port_status, 2671 uint_t *bandwidth) 2672 { 2673 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2674 2675 /* 2676 * If endpoint maximum packet is zero, then return immediately. 2677 */ 2678 if (maxpacketsize == 0) { 2679 2680 return (USB_NOT_SUPPORTED); 2681 } 2682 2683 /* Add TT delay to required bandwidth */ 2684 *bandwidth = TT_DELAY; 2685 2686 /* Add bit-stuffing overhead */ 2687 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2688 2689 switch (port_status) { 2690 case USBA_LOW_SPEED_DEV: 2691 /* Low speed interrupt transaction */ 2692 *bandwidth += (LOW_SPEED_PROTO_OVERHEAD + 2693 HUB_LOW_SPEED_PROTO_OVERHEAD + 2694 (LOW_SPEED_CLOCK * maxpacketsize)); 2695 break; 2696 case USBA_FULL_SPEED_DEV: 2697 /* Full speed transaction */ 2698 *bandwidth += maxpacketsize; 2699 2700 /* Add xfer specific protocol overheads */ 2701 if ((endpoint->bmAttributes & 2702 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2703 /* Full speed interrupt transaction */ 2704 *bandwidth += FS_NON_ISOC_PROTO_OVERHEAD; 2705 } else { 2706 /* Isochronous and input transaction */ 2707 if ((endpoint->bEndpointAddress & 2708 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2709 *bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD; 2710 } else { 2711 /* Isochronous and output transaction */ 2712 *bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD; 2713 } 2714 } 2715 break; 2716 } 2717 2718 return (USB_SUCCESS); 2719 } 2720 2721 2722 /* 2723 * ehci_adjust_polling_interval: 2724 * 2725 * Adjust bandwidth according usb device speed. 2726 */ 2727 /* ARGSUSED */ 2728 int 2729 ehci_adjust_polling_interval( 2730 ehci_state_t *ehcip, 2731 usb_ep_descr_t *endpoint, 2732 usb_port_status_t port_status) 2733 { 2734 uint_t interval; 2735 int i = 0; 2736 2737 /* Get the polling interval */ 2738 interval = endpoint->bInterval; 2739 2740 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2741 "ehci_adjust_polling_interval: Polling interval 0x%x", interval); 2742 2743 /* 2744 * According USB 2.0 Specifications, a high-speed endpoint's 2745 * polling intervals are specified interms of 125us or micro 2746 * frame, where as full/low endpoint's polling intervals are 2747 * specified in milliseconds. 2748 * 2749 * A high speed interrupt/isochronous endpoints can specify 2750 * desired polling interval between 1 to 16 micro-frames, 2751 * where as full/low endpoints can specify between 1 to 255 2752 * milliseconds. 2753 */ 2754 switch (port_status) { 2755 case USBA_LOW_SPEED_DEV: 2756 /* 2757 * Low speed endpoints are limited to specifying 2758 * only 8ms to 255ms in this driver. If a device 2759 * reports a polling interval that is less than 8ms, 2760 * it will use 8 ms instead. 2761 */ 2762 if (interval < LS_MIN_POLL_INTERVAL) { 2763 2764 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2765 "Low speed endpoint's poll interval of %d ms " 2766 "is below threshold. Rounding up to %d ms", 2767 interval, LS_MIN_POLL_INTERVAL); 2768 2769 interval = LS_MIN_POLL_INTERVAL; 2770 } 2771 2772 /* 2773 * Return an error if the polling interval is greater 2774 * than 255ms. 2775 */ 2776 if (interval > LS_MAX_POLL_INTERVAL) { 2777 2778 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2779 "Low speed endpoint's poll interval is " 2780 "greater than %d ms", LS_MAX_POLL_INTERVAL); 2781 2782 return (USB_FAILURE); 2783 } 2784 break; 2785 2786 case USBA_FULL_SPEED_DEV: 2787 /* 2788 * Return an error if the polling interval is less 2789 * than 1ms and greater than 255ms. 2790 */ 2791 if ((interval < FS_MIN_POLL_INTERVAL) && 2792 (interval > FS_MAX_POLL_INTERVAL)) { 2793 2794 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2795 "Full speed endpoint's poll interval must " 2796 "be between %d and %d ms", FS_MIN_POLL_INTERVAL, 2797 FS_MAX_POLL_INTERVAL); 2798 2799 return (USB_FAILURE); 2800 } 2801 break; 2802 case USBA_HIGH_SPEED_DEV: 2803 /* 2804 * Return an error if the polling interval is less 1 2805 * and greater than 16. Convert this value to 125us 2806 * units using 2^(bInterval -1). refer usb 2.0 spec 2807 * page 51 for details. 2808 */ 2809 if ((interval < HS_MIN_POLL_INTERVAL) && 2810 (interval > HS_MAX_POLL_INTERVAL)) { 2811 2812 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2813 "High speed endpoint's poll interval " 2814 "must be between %d and %d units", 2815 HS_MIN_POLL_INTERVAL, HS_MAX_POLL_INTERVAL); 2816 2817 return (USB_FAILURE); 2818 } 2819 2820 /* Adjust high speed device polling interval */ 2821 interval = 2822 ehci_adjust_high_speed_polling_interval(ehcip, endpoint); 2823 2824 break; 2825 } 2826 2827 /* 2828 * If polling interval is greater than 32ms, 2829 * adjust polling interval equal to 32ms. 2830 */ 2831 if (interval > EHCI_NUM_INTR_QH_LISTS) { 2832 interval = EHCI_NUM_INTR_QH_LISTS; 2833 } 2834 2835 /* 2836 * Find the nearest power of 2 that's less 2837 * than interval. 2838 */ 2839 while ((ehci_pow_2(i)) <= interval) { 2840 i++; 2841 } 2842 2843 return (ehci_pow_2((i - 1))); 2844 } 2845 2846 2847 /* 2848 * ehci_adjust_high_speed_polling_interval: 2849 */ 2850 /* ARGSUSED */ 2851 static int 2852 ehci_adjust_high_speed_polling_interval( 2853 ehci_state_t *ehcip, 2854 usb_ep_descr_t *endpoint) 2855 { 2856 uint_t interval; 2857 2858 /* Get the polling interval */ 2859 interval = ehci_pow_2(endpoint->bInterval - 1); 2860 2861 /* 2862 * Convert polling interval from micro seconds 2863 * to milli seconds. 2864 */ 2865 if (interval <= EHCI_MAX_UFRAMES) { 2866 interval = 1; 2867 } else { 2868 interval = interval/EHCI_MAX_UFRAMES; 2869 } 2870 2871 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2872 "ehci_adjust_high_speed_polling_interval: " 2873 "High speed adjusted interval 0x%x", interval); 2874 2875 return (interval); 2876 } 2877 2878 2879 /* 2880 * ehci_lattice_height: 2881 * 2882 * Given the requested bandwidth, find the height in the tree at which the 2883 * nodes for this bandwidth fall. The height is measured as the number of 2884 * nodes from the leaf to the level specified by bandwidth The root of the 2885 * tree is at height TREE_HEIGHT. 2886 */ 2887 static uint_t 2888 ehci_lattice_height(uint_t interval) 2889 { 2890 return (TREE_HEIGHT - (ehci_log_2(interval))); 2891 } 2892 2893 2894 /* 2895 * ehci_lattice_parent: 2896 * 2897 * Given a node in the lattice, find the index of the parent node 2898 */ 2899 static uint_t 2900 ehci_lattice_parent(uint_t node) 2901 { 2902 if ((node % 2) == 0) { 2903 2904 return ((node/2) - 1); 2905 } else { 2906 2907 return ((node + 1)/2 - 1); 2908 } 2909 } 2910 2911 2912 /* 2913 * ehci_find_periodic_node: 2914 * 2915 * Based on the "real" array leaf node and interval, get the periodic node. 2916 */ 2917 static uint_t 2918 ehci_find_periodic_node(uint_t leaf, int interval) { 2919 uint_t lattice_leaf; 2920 uint_t height = ehci_lattice_height(interval); 2921 uint_t pnode; 2922 int i; 2923 2924 /* Get the leaf number in the lattice */ 2925 lattice_leaf = leaf + EHCI_NUM_INTR_QH_LISTS - 1; 2926 2927 /* Get the node in the lattice based on the height and leaf */ 2928 pnode = lattice_leaf; 2929 for (i = 0; i < height; i++) { 2930 pnode = ehci_lattice_parent(pnode); 2931 } 2932 2933 return (pnode); 2934 } 2935 2936 2937 /* 2938 * ehci_leftmost_leaf: 2939 * 2940 * Find the leftmost leaf in the subtree specified by the node. Height refers 2941 * to number of nodes from the bottom of the tree to the node, including the 2942 * node. 2943 * 2944 * The formula for a zero based tree is: 2945 * 2^H * Node + 2^H - 1 2946 * The leaf of the tree is an array, convert the number for the array. 2947 * Subtract the size of nodes not in the array 2948 * 2^H * Node + 2^H - 1 - (EHCI_NUM_INTR_QH_LISTS - 1) = 2949 * 2^H * Node + 2^H - EHCI_NUM_INTR_QH_LISTS = 2950 * 2^H * (Node + 1) - EHCI_NUM_INTR_QH_LISTS 2951 * 0 2952 * 1 2 2953 * 0 1 2 3 2954 */ 2955 static uint_t 2956 ehci_leftmost_leaf( 2957 uint_t node, 2958 uint_t height) 2959 { 2960 return ((ehci_pow_2(height) * (node + 1)) - EHCI_NUM_INTR_QH_LISTS); 2961 } 2962 2963 2964 /* 2965 * ehci_pow_2: 2966 * 2967 * Compute 2 to the power 2968 */ 2969 static uint_t 2970 ehci_pow_2(uint_t x) 2971 { 2972 if (x == 0) { 2973 2974 return (1); 2975 } else { 2976 2977 return (2 << (x - 1)); 2978 } 2979 } 2980 2981 2982 /* 2983 * ehci_log_2: 2984 * 2985 * Compute log base 2 of x 2986 */ 2987 static uint_t 2988 ehci_log_2(uint_t x) 2989 { 2990 int i = 0; 2991 2992 while (x != 1) { 2993 x = x >> 1; 2994 i++; 2995 } 2996 2997 return (i); 2998 } 2999 3000 3001 /* 3002 * ehci_find_bestfit_hs_mask: 3003 * 3004 * Find the smask and cmask in the bandwidth allocation, and update the 3005 * bandwidth allocation. 3006 */ 3007 static int 3008 ehci_find_bestfit_hs_mask( 3009 ehci_state_t *ehcip, 3010 uchar_t *smask, 3011 uint_t *pnode, 3012 usb_ep_descr_t *endpoint, 3013 uint_t bandwidth, 3014 int interval) 3015 { 3016 int i; 3017 uint_t elements, index; 3018 int array_leaf, best_array_leaf; 3019 uint_t node_bandwidth, best_node_bandwidth; 3020 uint_t leaf_count; 3021 uchar_t bw_mask; 3022 uchar_t best_smask; 3023 3024 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3025 "ehci_find_bestfit_hs_mask: "); 3026 3027 /* Get all the valid smasks */ 3028 switch (ehci_pow_2(endpoint->bInterval - 1)) { 3029 case EHCI_INTR_1US_POLL: 3030 index = EHCI_1US_MASK_INDEX; 3031 elements = EHCI_INTR_1US_POLL; 3032 break; 3033 case EHCI_INTR_2US_POLL: 3034 index = EHCI_2US_MASK_INDEX; 3035 elements = EHCI_INTR_2US_POLL; 3036 break; 3037 case EHCI_INTR_4US_POLL: 3038 index = EHCI_4US_MASK_INDEX; 3039 elements = EHCI_INTR_4US_POLL; 3040 break; 3041 case EHCI_INTR_XUS_POLL: 3042 default: 3043 index = EHCI_XUS_MASK_INDEX; 3044 elements = EHCI_INTR_XUS_POLL; 3045 break; 3046 } 3047 3048 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3049 3050 /* 3051 * Because of the way the leaves are setup, we will automatically 3052 * hit the leftmost leaf of every possible node with this interval. 3053 */ 3054 best_smask = 0x00; 3055 best_node_bandwidth = 0; 3056 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3057 /* Find the bandwidth mask */ 3058 node_bandwidth = ehci_calculate_bw_availability_mask(ehcip, 3059 bandwidth, ehci_index[array_leaf], leaf_count, &bw_mask); 3060 3061 /* 3062 * If this node cannot support our requirements skip to the 3063 * next leaf. 3064 */ 3065 if (bw_mask == 0x00) { 3066 continue; 3067 } 3068 3069 /* 3070 * Now make sure our bandwidth requirements can be 3071 * satisfied with one of smasks in this node. 3072 */ 3073 *smask = 0x00; 3074 for (i = index; i < (index + elements); i++) { 3075 /* Check the start split mask value */ 3076 if (ehci_start_split_mask[index] & bw_mask) { 3077 *smask = ehci_start_split_mask[index]; 3078 break; 3079 } 3080 } 3081 3082 /* 3083 * If an appropriate smask is found save the information if: 3084 * o best_smask has not been found yet. 3085 * - or - 3086 * o This is the node with the least amount of bandwidth 3087 */ 3088 if ((*smask != 0x00) && 3089 ((best_smask == 0x00) || 3090 (best_node_bandwidth > node_bandwidth))) { 3091 3092 best_node_bandwidth = node_bandwidth; 3093 best_array_leaf = array_leaf; 3094 best_smask = *smask; 3095 } 3096 } 3097 3098 /* 3099 * If we find node that can handle the bandwidth populate the 3100 * appropriate variables and return success. 3101 */ 3102 if (best_smask) { 3103 *smask = best_smask; 3104 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3105 interval); 3106 ehci_update_bw_availability(ehcip, bandwidth, 3107 ehci_index[best_array_leaf], leaf_count, best_smask); 3108 3109 return (USB_SUCCESS); 3110 } 3111 3112 return (USB_FAILURE); 3113 } 3114 3115 3116 /* 3117 * ehci_find_bestfit_ls_intr_mask: 3118 * 3119 * Find the smask and cmask in the bandwidth allocation. 3120 */ 3121 static int 3122 ehci_find_bestfit_ls_intr_mask( 3123 ehci_state_t *ehcip, 3124 uchar_t *smask, 3125 uchar_t *cmask, 3126 uint_t *pnode, 3127 uint_t sbandwidth, 3128 uint_t cbandwidth, 3129 int interval) 3130 { 3131 int i; 3132 uint_t elements, index; 3133 int array_leaf, best_array_leaf; 3134 uint_t node_sbandwidth, node_cbandwidth; 3135 uint_t best_node_bandwidth; 3136 uint_t leaf_count; 3137 uchar_t bw_smask, bw_cmask; 3138 uchar_t best_smask, best_cmask; 3139 3140 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3141 "ehci_find_bestfit_ls_intr_mask: "); 3142 3143 /* For low and full speed devices */ 3144 index = EHCI_XUS_MASK_INDEX; 3145 elements = EHCI_INTR_4MS_POLL; 3146 3147 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3148 3149 /* 3150 * Because of the way the leaves are setup, we will automatically 3151 * hit the leftmost leaf of every possible node with this interval. 3152 */ 3153 best_smask = 0x00; 3154 best_node_bandwidth = 0; 3155 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3156 /* Find the bandwidth mask */ 3157 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3158 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3159 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3160 cbandwidth, ehci_index[array_leaf], leaf_count, &bw_cmask); 3161 3162 /* 3163 * If this node cannot support our requirements skip to the 3164 * next leaf. 3165 */ 3166 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3167 continue; 3168 } 3169 3170 /* 3171 * Now make sure our bandwidth requirements can be 3172 * satisfied with one of smasks in this node. 3173 */ 3174 *smask = 0x00; 3175 *cmask = 0x00; 3176 for (i = index; i < (index + elements); i++) { 3177 /* Check the start split mask value */ 3178 if ((ehci_start_split_mask[index] & bw_smask) && 3179 (ehci_intr_complete_split_mask[index] & bw_cmask)) { 3180 *smask = ehci_start_split_mask[index]; 3181 *cmask = ehci_intr_complete_split_mask[index]; 3182 break; 3183 } 3184 } 3185 3186 /* 3187 * If an appropriate smask is found save the information if: 3188 * o best_smask has not been found yet. 3189 * - or - 3190 * o This is the node with the least amount of bandwidth 3191 */ 3192 if ((*smask != 0x00) && 3193 ((best_smask == 0x00) || 3194 (best_node_bandwidth > 3195 (node_sbandwidth + node_cbandwidth)))) { 3196 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3197 best_array_leaf = array_leaf; 3198 best_smask = *smask; 3199 best_cmask = *cmask; 3200 } 3201 } 3202 3203 /* 3204 * If we find node that can handle the bandwidth populate the 3205 * appropriate variables and return success. 3206 */ 3207 if (best_smask) { 3208 *smask = best_smask; 3209 *cmask = best_cmask; 3210 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3211 interval); 3212 ehci_update_bw_availability(ehcip, sbandwidth, 3213 ehci_index[best_array_leaf], leaf_count, best_smask); 3214 ehci_update_bw_availability(ehcip, cbandwidth, 3215 ehci_index[best_array_leaf], leaf_count, best_cmask); 3216 3217 return (USB_SUCCESS); 3218 } 3219 3220 return (USB_FAILURE); 3221 } 3222 3223 3224 /* 3225 * ehci_find_bestfit_sitd_in_mask: 3226 * 3227 * Find the smask and cmask in the bandwidth allocation. 3228 */ 3229 static int 3230 ehci_find_bestfit_sitd_in_mask( 3231 ehci_state_t *ehcip, 3232 uchar_t *smask, 3233 uchar_t *cmask, 3234 uint_t *pnode, 3235 uint_t sbandwidth, 3236 uint_t cbandwidth, 3237 int interval) 3238 { 3239 int i, uFrames, found; 3240 int array_leaf, best_array_leaf; 3241 uint_t node_sbandwidth, node_cbandwidth; 3242 uint_t best_node_bandwidth; 3243 uint_t leaf_count; 3244 uchar_t bw_smask, bw_cmask; 3245 uchar_t best_smask, best_cmask; 3246 3247 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3248 "ehci_find_bestfit_sitd_in_mask: "); 3249 3250 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3251 3252 /* 3253 * Because of the way the leaves are setup, we will automatically 3254 * hit the leftmost leaf of every possible node with this interval. 3255 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3256 */ 3257 /* 3258 * Need to add an additional 2 uFrames, if the "L"ast 3259 * complete split is before uFrame 6. See section 3260 * 11.8.4 in USB 2.0 Spec. Currently we do not support 3261 * the "Back Ptr" which means we support on IN of 3262 * ~4*MAX_UFRAME_SITD_XFER bandwidth/ 3263 */ 3264 uFrames = (cbandwidth / MAX_UFRAME_SITD_XFER) + 2; 3265 if (cbandwidth % MAX_UFRAME_SITD_XFER) { 3266 uFrames++; 3267 } 3268 if (uFrames > 6) { 3269 3270 return (USB_FAILURE); 3271 } 3272 *smask = 0x1; 3273 *cmask = 0x00; 3274 for (i = 0; i < uFrames; i++) { 3275 *cmask = *cmask << 1; 3276 *cmask |= 0x1; 3277 } 3278 /* cmask must start 2 frames after the smask */ 3279 *cmask = *cmask << 2; 3280 3281 found = 0; 3282 best_smask = 0x00; 3283 best_node_bandwidth = 0; 3284 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3285 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3286 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3287 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3288 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3289 &bw_cmask); 3290 3291 /* 3292 * If this node cannot support our requirements skip to the 3293 * next leaf. 3294 */ 3295 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3296 continue; 3297 } 3298 3299 for (i = 0; i < (EHCI_MAX_UFRAMES - uFrames - 2); i++) { 3300 if ((*smask & bw_smask) && (*cmask & bw_cmask)) { 3301 found = 1; 3302 break; 3303 } 3304 *smask = *smask << 1; 3305 *cmask = *cmask << 1; 3306 } 3307 3308 /* 3309 * If an appropriate smask is found save the information if: 3310 * o best_smask has not been found yet. 3311 * - or - 3312 * o This is the node with the least amount of bandwidth 3313 */ 3314 if (found && 3315 ((best_smask == 0x00) || 3316 (best_node_bandwidth > 3317 (node_sbandwidth + node_cbandwidth)))) { 3318 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3319 best_array_leaf = array_leaf; 3320 best_smask = *smask; 3321 best_cmask = *cmask; 3322 } 3323 } 3324 3325 /* 3326 * If we find node that can handle the bandwidth populate the 3327 * appropriate variables and return success. 3328 */ 3329 if (best_smask) { 3330 *smask = best_smask; 3331 *cmask = best_cmask; 3332 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3333 interval); 3334 ehci_update_bw_availability(ehcip, sbandwidth, 3335 ehci_index[best_array_leaf], leaf_count, best_smask); 3336 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3337 ehci_index[best_array_leaf], leaf_count, best_cmask); 3338 3339 return (USB_SUCCESS); 3340 } 3341 3342 return (USB_FAILURE); 3343 } 3344 3345 3346 /* 3347 * ehci_find_bestfit_sitd_out_mask: 3348 * 3349 * Find the smask in the bandwidth allocation. 3350 */ 3351 static int 3352 ehci_find_bestfit_sitd_out_mask( 3353 ehci_state_t *ehcip, 3354 uchar_t *smask, 3355 uint_t *pnode, 3356 uint_t sbandwidth, 3357 int interval) 3358 { 3359 int i, uFrames, found; 3360 int array_leaf, best_array_leaf; 3361 uint_t node_sbandwidth; 3362 uint_t best_node_bandwidth; 3363 uint_t leaf_count; 3364 uchar_t bw_smask; 3365 uchar_t best_smask; 3366 3367 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3368 "ehci_find_bestfit_sitd_out_mask: "); 3369 3370 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3371 3372 /* 3373 * Because of the way the leaves are setup, we will automatically 3374 * hit the leftmost leaf of every possible node with this interval. 3375 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3376 */ 3377 *smask = 0x00; 3378 uFrames = sbandwidth / MAX_UFRAME_SITD_XFER; 3379 if (sbandwidth % MAX_UFRAME_SITD_XFER) { 3380 uFrames++; 3381 } 3382 for (i = 0; i < uFrames; i++) { 3383 *smask = *smask << 1; 3384 *smask |= 0x1; 3385 } 3386 3387 found = 0; 3388 best_smask = 0x00; 3389 best_node_bandwidth = 0; 3390 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3391 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3392 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3393 &bw_smask); 3394 3395 /* 3396 * If this node cannot support our requirements skip to the 3397 * next leaf. 3398 */ 3399 if (bw_smask == 0x00) { 3400 continue; 3401 } 3402 3403 /* You cannot have a start split on the 8th uFrame */ 3404 for (i = 0; (*smask & 0x80) == 0; i++) { 3405 if (*smask & bw_smask) { 3406 found = 1; 3407 break; 3408 } 3409 *smask = *smask << 1; 3410 } 3411 3412 /* 3413 * If an appropriate smask is found save the information if: 3414 * o best_smask has not been found yet. 3415 * - or - 3416 * o This is the node with the least amount of bandwidth 3417 */ 3418 if (found && 3419 ((best_smask == 0x00) || 3420 (best_node_bandwidth > node_sbandwidth))) { 3421 best_node_bandwidth = node_sbandwidth; 3422 best_array_leaf = array_leaf; 3423 best_smask = *smask; 3424 } 3425 } 3426 3427 /* 3428 * If we find node that can handle the bandwidth populate the 3429 * appropriate variables and return success. 3430 */ 3431 if (best_smask) { 3432 *smask = best_smask; 3433 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3434 interval); 3435 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3436 ehci_index[best_array_leaf], leaf_count, best_smask); 3437 3438 return (USB_SUCCESS); 3439 } 3440 3441 return (USB_FAILURE); 3442 } 3443 3444 3445 /* 3446 * ehci_calculate_bw_availability_mask: 3447 * 3448 * Returns the "total bandwidth used" in this node. 3449 * Populates bw_mask with the uFrames that can support the bandwidth. 3450 * 3451 * If all the Frames cannot support this bandwidth, then bw_mask 3452 * will return 0x00 and the "total bandwidth used" will be invalid. 3453 */ 3454 static uint_t 3455 ehci_calculate_bw_availability_mask( 3456 ehci_state_t *ehcip, 3457 uint_t bandwidth, 3458 int leaf, 3459 int leaf_count, 3460 uchar_t *bw_mask) 3461 { 3462 int i, j; 3463 uchar_t bw_uframe; 3464 int uframe_total; 3465 ehci_frame_bandwidth_t *fbp; 3466 uint_t total_bandwidth = 0; 3467 3468 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3469 "ehci_calculate_bw_availability_mask: leaf %d leaf count %d", 3470 leaf, leaf_count); 3471 3472 /* Start by saying all uFrames are available */ 3473 *bw_mask = 0xFF; 3474 3475 for (i = 0; (i < leaf_count) || (*bw_mask == 0x00); i++) { 3476 fbp = &ehcip->ehci_frame_bandwidth[leaf + i]; 3477 3478 total_bandwidth += fbp->ehci_allocated_frame_bandwidth; 3479 3480 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3481 /* 3482 * If the uFrame in bw_mask is available check to see if 3483 * it can support the additional bandwidth. 3484 */ 3485 bw_uframe = (*bw_mask & (0x1 << j)); 3486 uframe_total = 3487 fbp->ehci_micro_frame_bandwidth[j] + 3488 bandwidth; 3489 if ((bw_uframe) && 3490 (uframe_total > HS_PERIODIC_BANDWIDTH)) { 3491 *bw_mask = *bw_mask & ~bw_uframe; 3492 } 3493 } 3494 } 3495 3496 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3497 "ehci_calculate_bw_availability_mask: bandwidth mask 0x%x", 3498 *bw_mask); 3499 3500 return (total_bandwidth); 3501 } 3502 3503 3504 /* 3505 * ehci_update_bw_availability: 3506 * 3507 * The leftmost leaf needs to be in terms of array position and 3508 * not the actual lattice position. 3509 */ 3510 static void 3511 ehci_update_bw_availability( 3512 ehci_state_t *ehcip, 3513 int bandwidth, 3514 int leftmost_leaf, 3515 int leaf_count, 3516 uchar_t mask) 3517 { 3518 int i, j; 3519 ehci_frame_bandwidth_t *fbp; 3520 int uFrame_bandwidth[8]; 3521 3522 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3523 "ehci_update_bw_availability: " 3524 "leaf %d count %d bandwidth 0x%x mask 0x%x", 3525 leftmost_leaf, leaf_count, bandwidth, mask); 3526 3527 ASSERT(leftmost_leaf < 32); 3528 ASSERT(leftmost_leaf >= 0); 3529 3530 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3531 if (mask & 0x1) { 3532 uFrame_bandwidth[j] = bandwidth; 3533 } else { 3534 uFrame_bandwidth[j] = 0; 3535 } 3536 3537 mask = mask >> 1; 3538 } 3539 3540 /* Updated all the effected leafs with the bandwidth */ 3541 for (i = 0; i < leaf_count; i++) { 3542 fbp = &ehcip->ehci_frame_bandwidth[leftmost_leaf + i]; 3543 3544 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3545 fbp->ehci_micro_frame_bandwidth[j] += 3546 uFrame_bandwidth[j]; 3547 fbp->ehci_allocated_frame_bandwidth += 3548 uFrame_bandwidth[j]; 3549 } 3550 } 3551 } 3552 3553 /* 3554 * Miscellaneous functions 3555 */ 3556 3557 /* 3558 * ehci_obtain_state: 3559 * 3560 * NOTE: This function is also called from POLLED MODE. 3561 */ 3562 ehci_state_t * 3563 ehci_obtain_state(dev_info_t *dip) 3564 { 3565 int instance = ddi_get_instance(dip); 3566 3567 ehci_state_t *state = ddi_get_soft_state(ehci_statep, instance); 3568 3569 ASSERT(state != NULL); 3570 3571 return (state); 3572 } 3573 3574 3575 /* 3576 * ehci_state_is_operational: 3577 * 3578 * Check the Host controller state and return proper values. 3579 */ 3580 int 3581 ehci_state_is_operational(ehci_state_t *ehcip) 3582 { 3583 int val; 3584 3585 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3586 3587 switch (ehcip->ehci_hc_soft_state) { 3588 case EHCI_CTLR_INIT_STATE: 3589 case EHCI_CTLR_SUSPEND_STATE: 3590 val = USB_FAILURE; 3591 break; 3592 case EHCI_CTLR_OPERATIONAL_STATE: 3593 val = USB_SUCCESS; 3594 break; 3595 case EHCI_CTLR_ERROR_STATE: 3596 val = USB_HC_HARDWARE_ERROR; 3597 break; 3598 default: 3599 val = USB_FAILURE; 3600 break; 3601 } 3602 3603 return (val); 3604 } 3605 3606 3607 /* 3608 * ehci_do_soft_reset 3609 * 3610 * Do soft reset of ehci host controller. 3611 */ 3612 int 3613 ehci_do_soft_reset(ehci_state_t *ehcip) 3614 { 3615 usb_frame_number_t before_frame_number, after_frame_number; 3616 ehci_regs_t *ehci_save_regs; 3617 3618 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3619 3620 /* Increment host controller error count */ 3621 ehcip->ehci_hc_error++; 3622 3623 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3624 "ehci_do_soft_reset:" 3625 "Reset ehci host controller 0x%x", ehcip->ehci_hc_error); 3626 3627 /* 3628 * Allocate space for saving current Host Controller 3629 * registers. Don't do any recovery if allocation 3630 * fails. 3631 */ 3632 ehci_save_regs = (ehci_regs_t *) 3633 kmem_zalloc(sizeof (ehci_regs_t), KM_NOSLEEP); 3634 3635 if (ehci_save_regs == NULL) { 3636 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3637 "ehci_do_soft_reset: kmem_zalloc failed"); 3638 3639 return (USB_FAILURE); 3640 } 3641 3642 /* Save current ehci registers */ 3643 ehci_save_regs->ehci_command = Get_OpReg(ehci_command); 3644 ehci_save_regs->ehci_interrupt = Get_OpReg(ehci_interrupt); 3645 ehci_save_regs->ehci_ctrl_segment = Get_OpReg(ehci_ctrl_segment); 3646 ehci_save_regs->ehci_async_list_addr = Get_OpReg(ehci_async_list_addr); 3647 ehci_save_regs->ehci_config_flag = Get_OpReg(ehci_config_flag); 3648 ehci_save_regs->ehci_periodic_list_base = 3649 Get_OpReg(ehci_periodic_list_base); 3650 3651 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3652 "ehci_do_soft_reset: Save reg = 0x%p", ehci_save_regs); 3653 3654 /* Disable all list processing and interrupts */ 3655 Set_OpReg(ehci_command, Get_OpReg(ehci_command) & 3656 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE)); 3657 3658 /* Disable all EHCI interrupts */ 3659 Set_OpReg(ehci_interrupt, 0); 3660 3661 /* Wait for few milliseconds */ 3662 drv_usecwait(EHCI_SOF_TIMEWAIT); 3663 3664 /* Do light soft reset of ehci host controller */ 3665 Set_OpReg(ehci_command, 3666 Get_OpReg(ehci_command) | EHCI_CMD_LIGHT_HC_RESET); 3667 3668 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3669 "ehci_do_soft_reset: Reset in progress"); 3670 3671 /* Wait for reset to complete */ 3672 drv_usecwait(EHCI_RESET_TIMEWAIT); 3673 3674 /* 3675 * Restore previous saved EHCI register value 3676 * into the current EHCI registers. 3677 */ 3678 Set_OpReg(ehci_ctrl_segment, (uint32_t) 3679 ehci_save_regs->ehci_ctrl_segment); 3680 3681 Set_OpReg(ehci_periodic_list_base, (uint32_t) 3682 ehci_save_regs->ehci_periodic_list_base); 3683 3684 Set_OpReg(ehci_async_list_addr, (uint32_t) 3685 ehci_save_regs->ehci_async_list_addr); 3686 3687 Set_OpReg(ehci_config_flag, (uint32_t) 3688 ehci_save_regs->ehci_config_flag); 3689 3690 /* Enable both Asynchronous and Periodic Schedule if necessary */ 3691 ehci_toggle_scheduler(ehcip); 3692 3693 /* 3694 * Set ehci_interrupt to enable all interrupts except Root 3695 * Hub Status change and frame list rollover interrupts. 3696 */ 3697 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 3698 EHCI_INTR_FRAME_LIST_ROLLOVER | 3699 EHCI_INTR_USB_ERROR | 3700 EHCI_INTR_USB); 3701 3702 /* 3703 * Deallocate the space that allocated for saving 3704 * HC registers. 3705 */ 3706 kmem_free((void *) ehci_save_regs, sizeof (ehci_regs_t)); 3707 3708 /* 3709 * Set the desired interrupt threshold, frame list size (if 3710 * applicable) and turn EHCI host controller. 3711 */ 3712 Set_OpReg(ehci_command, ((Get_OpReg(ehci_command) & 3713 ~EHCI_CMD_INTR_THRESHOLD) | 3714 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 3715 3716 /* Wait 10ms for EHCI to start sending SOF */ 3717 drv_usecwait(EHCI_RESET_TIMEWAIT); 3718 3719 /* 3720 * Get the current usb frame number before waiting for 3721 * few milliseconds. 3722 */ 3723 before_frame_number = ehci_get_current_frame_number(ehcip); 3724 3725 /* Wait for few milliseconds */ 3726 drv_usecwait(EHCI_SOF_TIMEWAIT); 3727 3728 /* 3729 * Get the current usb frame number after waiting for 3730 * few milliseconds. 3731 */ 3732 after_frame_number = ehci_get_current_frame_number(ehcip); 3733 3734 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3735 "ehci_do_soft_reset: Before Frame Number 0x%llx " 3736 "After Frame Number 0x%llx", 3737 before_frame_number, after_frame_number); 3738 3739 if ((after_frame_number <= before_frame_number) && 3740 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 3741 3742 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3743 "ehci_do_soft_reset: Soft reset failed"); 3744 3745 return (USB_FAILURE); 3746 } 3747 3748 return (USB_SUCCESS); 3749 } 3750 3751 3752 /* 3753 * ehci_get_xfer_attrs: 3754 * 3755 * Get the attributes of a particular xfer. 3756 * 3757 * NOTE: This function is also called from POLLED MODE. 3758 */ 3759 usb_req_attrs_t 3760 ehci_get_xfer_attrs( 3761 ehci_state_t *ehcip, 3762 ehci_pipe_private_t *pp, 3763 ehci_trans_wrapper_t *tw) 3764 { 3765 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 3766 usb_req_attrs_t attrs = USB_ATTRS_NONE; 3767 3768 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3769 "ehci_get_xfer_attrs:"); 3770 3771 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 3772 case USB_EP_ATTR_CONTROL: 3773 attrs = ((usb_ctrl_req_t *) 3774 tw->tw_curr_xfer_reqp)->ctrl_attributes; 3775 break; 3776 case USB_EP_ATTR_BULK: 3777 attrs = ((usb_bulk_req_t *) 3778 tw->tw_curr_xfer_reqp)->bulk_attributes; 3779 break; 3780 case USB_EP_ATTR_INTR: 3781 attrs = ((usb_intr_req_t *) 3782 tw->tw_curr_xfer_reqp)->intr_attributes; 3783 break; 3784 } 3785 3786 return (attrs); 3787 } 3788 3789 3790 /* 3791 * ehci_get_current_frame_number: 3792 * 3793 * Get the current software based usb frame number. 3794 */ 3795 usb_frame_number_t 3796 ehci_get_current_frame_number(ehci_state_t *ehcip) 3797 { 3798 usb_frame_number_t usb_frame_number; 3799 usb_frame_number_t ehci_fno, micro_frame_number; 3800 3801 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3802 3803 ehci_fno = ehcip->ehci_fno; 3804 micro_frame_number = Get_OpReg(ehci_frame_index) & 0x3FFF; 3805 3806 /* 3807 * Calculate current software based usb frame number. 3808 * 3809 * This code accounts for the fact that frame number is 3810 * updated by the Host Controller before the ehci driver 3811 * gets an FrameListRollover interrupt that will adjust 3812 * Frame higher part. 3813 * 3814 * Refer ehci specification 1.0, section 2.3.2, page 21. 3815 */ 3816 micro_frame_number = ((micro_frame_number & 0x1FFF) | 3817 ehci_fno) + (((micro_frame_number & 0x3FFF) ^ 3818 ehci_fno) & 0x2000); 3819 3820 /* 3821 * Micro Frame number is equivalent to 125 usec. Eight 3822 * Micro Frame numbers are equivalent to one millsecond 3823 * or one usb frame number. 3824 */ 3825 usb_frame_number = micro_frame_number >> 3826 EHCI_uFRAMES_PER_USB_FRAME_SHIFT; 3827 3828 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3829 "ehci_get_current_frame_number: " 3830 "Current usb uframe number = 0x%llx " 3831 "Current usb frame number = 0x%llx", 3832 micro_frame_number, usb_frame_number); 3833 3834 return (usb_frame_number); 3835 } 3836 3837 3838 /* 3839 * ehci_cpr_cleanup: 3840 * 3841 * Cleanup ehci state and other ehci specific informations across 3842 * Check Point Resume (CPR). 3843 */ 3844 static void 3845 ehci_cpr_cleanup(ehci_state_t *ehcip) 3846 { 3847 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3848 3849 /* Reset software part of usb frame number */ 3850 ehcip->ehci_fno = 0; 3851 } 3852 3853 3854 /* 3855 * ehci_wait_for_sof: 3856 * 3857 * Wait for couple of SOF interrupts 3858 */ 3859 int 3860 ehci_wait_for_sof(ehci_state_t *ehcip) 3861 { 3862 usb_frame_number_t before_frame_number, after_frame_number; 3863 int error = USB_SUCCESS; 3864 3865 USB_DPRINTF_L4(PRINT_MASK_LISTS, 3866 ehcip->ehci_log_hdl, "ehci_wait_for_sof"); 3867 3868 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3869 3870 error = ehci_state_is_operational(ehcip); 3871 3872 if (error != USB_SUCCESS) { 3873 3874 return (error); 3875 } 3876 3877 /* Get the current usb frame number before waiting for two SOFs */ 3878 before_frame_number = ehci_get_current_frame_number(ehcip); 3879 3880 mutex_exit(&ehcip->ehci_int_mutex); 3881 3882 /* Wait for few milliseconds */ 3883 delay(drv_usectohz(EHCI_SOF_TIMEWAIT)); 3884 3885 mutex_enter(&ehcip->ehci_int_mutex); 3886 3887 /* Get the current usb frame number after woken up */ 3888 after_frame_number = ehci_get_current_frame_number(ehcip); 3889 3890 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3891 "ehci_wait_for_sof: framenumber: before 0x%llx " 3892 "after 0x%llx", before_frame_number, after_frame_number); 3893 3894 /* Return failure, if usb frame number has not been changed */ 3895 if (after_frame_number <= before_frame_number) { 3896 3897 if ((ehci_do_soft_reset(ehcip)) != USB_SUCCESS) { 3898 3899 USB_DPRINTF_L0(PRINT_MASK_LISTS, 3900 ehcip->ehci_log_hdl, "No SOF interrupts"); 3901 3902 /* Set host controller soft state to error */ 3903 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 3904 3905 return (USB_FAILURE); 3906 } 3907 3908 /* Get new usb frame number */ 3909 after_frame_number = before_frame_number = 3910 ehci_get_current_frame_number(ehcip); 3911 } 3912 3913 ASSERT(after_frame_number > before_frame_number); 3914 3915 return (USB_SUCCESS); 3916 } 3917 3918 3919 /* 3920 * ehci_toggle_scheduler: 3921 * 3922 * Turn scheduler based on pipe open count. 3923 */ 3924 void 3925 ehci_toggle_scheduler(ehci_state_t *ehcip) { 3926 uint_t temp_reg, cmd_reg; 3927 3928 cmd_reg = Get_OpReg(ehci_command); 3929 temp_reg = cmd_reg; 3930 3931 /* 3932 * Enable/Disable asynchronous scheduler, and 3933 * turn on/off async list door bell 3934 */ 3935 if (ehcip->ehci_open_async_count) { 3936 if (!(cmd_reg & EHCI_CMD_ASYNC_SCHED_ENABLE)) { 3937 /* 3938 * For some reason this address might get nulled out by 3939 * the ehci chip. Set it here just in case it is null. 3940 */ 3941 Set_OpReg(ehci_async_list_addr, 3942 ehci_qh_cpu_to_iommu(ehcip, 3943 ehcip->ehci_head_of_async_sched_list)); 3944 } 3945 cmd_reg |= EHCI_CMD_ASYNC_SCHED_ENABLE; 3946 } else { 3947 cmd_reg &= ~EHCI_CMD_ASYNC_SCHED_ENABLE; 3948 } 3949 3950 if (ehcip->ehci_open_periodic_count) { 3951 if (!(cmd_reg & EHCI_CMD_PERIODIC_SCHED_ENABLE)) { 3952 /* 3953 * For some reason this address get's nulled out by 3954 * the ehci chip. Set it here just in case it is null. 3955 */ 3956 Set_OpReg(ehci_periodic_list_base, 3957 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 3958 0xFFFFF000)); 3959 } 3960 cmd_reg |= EHCI_CMD_PERIODIC_SCHED_ENABLE; 3961 } else { 3962 cmd_reg &= ~EHCI_CMD_PERIODIC_SCHED_ENABLE; 3963 } 3964 3965 /* Just an optimization */ 3966 if (temp_reg != cmd_reg) { 3967 Set_OpReg(ehci_command, cmd_reg); 3968 } 3969 } 3970 3971 /* 3972 * ehci print functions 3973 */ 3974 3975 /* 3976 * ehci_print_caps: 3977 */ 3978 void 3979 ehci_print_caps(ehci_state_t *ehcip) 3980 { 3981 uint_t i; 3982 3983 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3984 "\n\tUSB 2.0 Host Controller Characteristics\n"); 3985 3986 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3987 "Caps Length: 0x%x Version: 0x%x\n", 3988 Get_8Cap(ehci_caps_length), Get_16Cap(ehci_version)); 3989 3990 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3991 "Structural Parameters\n"); 3992 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3993 "Port indicators: %s", (Get_Cap(ehci_hcs_params) & 3994 EHCI_HCS_PORT_INDICATOR) ? "Yes" : "No"); 3995 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3996 "No of Classic host controllers: 0x%x", 3997 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_COMP_CTRLS) 3998 >> EHCI_HCS_NUM_COMP_CTRL_SHIFT); 3999 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4000 "No of ports per Classic host controller: 0x%x", 4001 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS_CC) 4002 >> EHCI_HCS_NUM_PORTS_CC_SHIFT); 4003 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4004 "Port routing rules: %s", (Get_Cap(ehci_hcs_params) & 4005 EHCI_HCS_PORT_ROUTING_RULES) ? "Yes" : "No"); 4006 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4007 "Port power control: %s", (Get_Cap(ehci_hcs_params) & 4008 EHCI_HCS_PORT_POWER_CONTROL) ? "Yes" : "No"); 4009 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4010 "No of root hub ports: 0x%x\n", 4011 Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); 4012 4013 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4014 "Capability Parameters\n"); 4015 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4016 "EHCI extended capability: %s", (Get_Cap(ehci_hcc_params) & 4017 EHCI_HCC_EECP) ? "Yes" : "No"); 4018 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4019 "Isoch schedule threshold: 0x%x", 4020 Get_Cap(ehci_hcc_params) & EHCI_HCC_ISOCH_SCHED_THRESHOLD); 4021 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4022 "Async schedule park capability: %s", (Get_Cap(ehci_hcc_params) & 4023 EHCI_HCC_ASYNC_SCHED_PARK_CAP) ? "Yes" : "No"); 4024 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4025 "Programmable frame list flag: %s", (Get_Cap(ehci_hcc_params) & 4026 EHCI_HCC_PROG_FRAME_LIST_FLAG) ? "256/512/1024" : "1024"); 4027 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4028 "64bit addressing capability: %s\n", (Get_Cap(ehci_hcc_params) & 4029 EHCI_HCC_64BIT_ADDR_CAP) ? "Yes" : "No"); 4030 4031 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4032 "Classic Port Route Description"); 4033 4034 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4035 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4036 "\tPort Route 0x%x: 0x%x", i, Get_8Cap(ehci_port_route[i])); 4037 } 4038 } 4039 4040 4041 /* 4042 * ehci_print_regs: 4043 */ 4044 void 4045 ehci_print_regs(ehci_state_t *ehcip) 4046 { 4047 uint_t i; 4048 4049 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4050 "\n\tEHCI%d Operational Registers\n", 4051 ddi_get_instance(ehcip->ehci_dip)); 4052 4053 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4054 "Command: 0x%x Status: 0x%x", 4055 Get_OpReg(ehci_command), Get_OpReg(ehci_status)); 4056 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4057 "Interrupt: 0x%x Frame Index: 0x%x", 4058 Get_OpReg(ehci_interrupt), Get_OpReg(ehci_frame_index)); 4059 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4060 "Control Segment: 0x%x Periodic List Base: 0x%x", 4061 Get_OpReg(ehci_ctrl_segment), Get_OpReg(ehci_periodic_list_base)); 4062 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4063 "Async List Addr: 0x%x Config Flag: 0x%x", 4064 Get_OpReg(ehci_async_list_addr), Get_OpReg(ehci_config_flag)); 4065 4066 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4067 "Root Hub Port Status"); 4068 4069 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4070 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4071 "\tPort Status 0x%x: 0x%x ", i, 4072 Get_OpReg(ehci_rh_port_status[i])); 4073 } 4074 } 4075 4076 4077 /* 4078 * ehci_print_qh: 4079 */ 4080 void 4081 ehci_print_qh( 4082 ehci_state_t *ehcip, 4083 ehci_qh_t *qh) 4084 { 4085 uint_t i; 4086 4087 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4088 "ehci_print_qh: qh = 0x%p", (void *)qh); 4089 4090 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4091 "\tqh_link_ptr: 0x%x ", Get_QH(qh->qh_link_ptr)); 4092 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4093 "\tqh_ctrl: 0x%x ", Get_QH(qh->qh_ctrl)); 4094 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4095 "\tqh_split_ctrl: 0x%x ", Get_QH(qh->qh_split_ctrl)); 4096 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4097 "\tqh_curr_qtd: 0x%x ", Get_QH(qh->qh_curr_qtd)); 4098 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4099 "\tqh_next_qtd: 0x%x ", Get_QH(qh->qh_next_qtd)); 4100 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4101 "\tqh_alt_next_qtd: 0x%x ", Get_QH(qh->qh_alt_next_qtd)); 4102 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4103 "\tqh_status: 0x%x ", Get_QH(qh->qh_status)); 4104 4105 for (i = 0; i < 5; i++) { 4106 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4107 "\tqh_buf[%d]: 0x%x ", i, Get_QH(qh->qh_buf[i])); 4108 } 4109 4110 for (i = 0; i < 5; i++) { 4111 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4112 "\tqh_buf_high[%d]: 0x%x ", 4113 i, Get_QH(qh->qh_buf_high[i])); 4114 } 4115 4116 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4117 "\tqh_dummy_qtd: 0x%x ", Get_QH(qh->qh_dummy_qtd)); 4118 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4119 "\tqh_prev: 0x%x ", Get_QH(qh->qh_prev)); 4120 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4121 "\tqh_state: 0x%x ", Get_QH(qh->qh_state)); 4122 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4123 "\tqh_reclaim_next: 0x%x ", Get_QH(qh->qh_reclaim_next)); 4124 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4125 "\tqh_reclaim_frame: 0x%x ", Get_QH(qh->qh_reclaim_frame)); 4126 } 4127 4128 4129 /* 4130 * ehci_print_qtd: 4131 */ 4132 void 4133 ehci_print_qtd( 4134 ehci_state_t *ehcip, 4135 ehci_qtd_t *qtd) 4136 { 4137 uint_t i; 4138 4139 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4140 "ehci_print_qtd: qtd = 0x%p", (void *)qtd); 4141 4142 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4143 "\tqtd_next_qtd: 0x%x ", Get_QTD(qtd->qtd_next_qtd)); 4144 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4145 "\tqtd_alt_next_qtd: 0x%x ", Get_QTD(qtd->qtd_alt_next_qtd)); 4146 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4147 "\tqtd_ctrl: 0x%x ", Get_QTD(qtd->qtd_ctrl)); 4148 4149 for (i = 0; i < 5; i++) { 4150 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4151 "\tqtd_buf[%d]: 0x%x ", i, Get_QTD(qtd->qtd_buf[i])); 4152 } 4153 4154 for (i = 0; i < 5; i++) { 4155 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4156 "\tqtd_buf_high[%d]: 0x%x ", 4157 i, Get_QTD(qtd->qtd_buf_high[i])); 4158 } 4159 4160 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4161 "\tqtd_trans_wrapper: 0x%x ", Get_QTD(qtd->qtd_trans_wrapper)); 4162 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4163 "\tqtd_tw_next_qtd: 0x%x ", Get_QTD(qtd->qtd_tw_next_qtd)); 4164 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4165 "\tqtd_active_qtd_next: 0x%x ", Get_QTD(qtd->qtd_active_qtd_next)); 4166 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4167 "\tqtd_active_qtd_prev: 0x%x ", Get_QTD(qtd->qtd_active_qtd_prev)); 4168 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4169 "\tqtd_state: 0x%x ", Get_QTD(qtd->qtd_state)); 4170 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4171 "\tqtd_ctrl_phase: 0x%x ", Get_QTD(qtd->qtd_ctrl_phase)); 4172 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4173 "\tqtd_xfer_offs: 0x%x ", Get_QTD(qtd->qtd_xfer_offs)); 4174 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4175 "\tqtd_xfer_len: 0x%x ", Get_QTD(qtd->qtd_xfer_len)); 4176 } 4177 4178 /* 4179 * ehci kstat functions 4180 */ 4181 4182 /* 4183 * ehci_create_stats: 4184 * 4185 * Allocate and initialize the ehci kstat structures 4186 */ 4187 void 4188 ehci_create_stats(ehci_state_t *ehcip) 4189 { 4190 char kstatname[KSTAT_STRLEN]; 4191 const char *dname = ddi_driver_name(ehcip->ehci_dip); 4192 char *usbtypes[USB_N_COUNT_KSTATS] = 4193 {"ctrl", "isoch", "bulk", "intr"}; 4194 uint_t instance = ehcip->ehci_instance; 4195 ehci_intrs_stats_t *isp; 4196 int i; 4197 4198 if (EHCI_INTRS_STATS(ehcip) == NULL) { 4199 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs", 4200 dname, instance); 4201 EHCI_INTRS_STATS(ehcip) = kstat_create("usba", instance, 4202 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED, 4203 sizeof (ehci_intrs_stats_t) / sizeof (kstat_named_t), 4204 KSTAT_FLAG_PERSISTENT); 4205 4206 if (EHCI_INTRS_STATS(ehcip)) { 4207 isp = EHCI_INTRS_STATS_DATA(ehcip); 4208 kstat_named_init(&isp->ehci_sts_total, 4209 "Interrupts Total", KSTAT_DATA_UINT64); 4210 kstat_named_init(&isp->ehci_sts_not_claimed, 4211 "Not Claimed", KSTAT_DATA_UINT64); 4212 kstat_named_init(&isp->ehci_sts_async_sched_status, 4213 "Async schedule status", KSTAT_DATA_UINT64); 4214 kstat_named_init(&isp->ehci_sts_periodic_sched_status, 4215 "Periodic sched status", KSTAT_DATA_UINT64); 4216 kstat_named_init(&isp->ehci_sts_empty_async_schedule, 4217 "Empty async schedule", KSTAT_DATA_UINT64); 4218 kstat_named_init(&isp->ehci_sts_host_ctrl_halted, 4219 "Host controller Halted", KSTAT_DATA_UINT64); 4220 kstat_named_init(&isp->ehci_sts_async_advance_intr, 4221 "Intr on async advance", KSTAT_DATA_UINT64); 4222 kstat_named_init(&isp->ehci_sts_host_system_error_intr, 4223 "Host system error", KSTAT_DATA_UINT64); 4224 kstat_named_init(&isp->ehci_sts_frm_list_rollover_intr, 4225 "Frame list rollover", KSTAT_DATA_UINT64); 4226 kstat_named_init(&isp->ehci_sts_rh_port_change_intr, 4227 "Port change detect", KSTAT_DATA_UINT64); 4228 kstat_named_init(&isp->ehci_sts_usb_error_intr, 4229 "USB error interrupt", KSTAT_DATA_UINT64); 4230 kstat_named_init(&isp->ehci_sts_usb_intr, 4231 "USB interrupt", KSTAT_DATA_UINT64); 4232 4233 EHCI_INTRS_STATS(ehcip)->ks_private = ehcip; 4234 EHCI_INTRS_STATS(ehcip)->ks_update = nulldev; 4235 kstat_install(EHCI_INTRS_STATS(ehcip)); 4236 } 4237 } 4238 4239 if (EHCI_TOTAL_STATS(ehcip) == NULL) { 4240 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total", 4241 dname, instance); 4242 EHCI_TOTAL_STATS(ehcip) = kstat_create("usba", instance, 4243 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1, 4244 KSTAT_FLAG_PERSISTENT); 4245 4246 if (EHCI_TOTAL_STATS(ehcip)) { 4247 kstat_install(EHCI_TOTAL_STATS(ehcip)); 4248 } 4249 } 4250 4251 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4252 if (ehcip->ehci_count_stats[i] == NULL) { 4253 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s", 4254 dname, instance, usbtypes[i]); 4255 ehcip->ehci_count_stats[i] = kstat_create("usba", 4256 instance, kstatname, "usb_byte_count", 4257 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 4258 4259 if (ehcip->ehci_count_stats[i]) { 4260 kstat_install(ehcip->ehci_count_stats[i]); 4261 } 4262 } 4263 } 4264 } 4265 4266 4267 /* 4268 * ehci_destroy_stats: 4269 * 4270 * Clean up ehci kstat structures 4271 */ 4272 void 4273 ehci_destroy_stats(ehci_state_t *ehcip) 4274 { 4275 int i; 4276 4277 if (EHCI_INTRS_STATS(ehcip)) { 4278 kstat_delete(EHCI_INTRS_STATS(ehcip)); 4279 EHCI_INTRS_STATS(ehcip) = NULL; 4280 } 4281 4282 if (EHCI_TOTAL_STATS(ehcip)) { 4283 kstat_delete(EHCI_TOTAL_STATS(ehcip)); 4284 EHCI_TOTAL_STATS(ehcip) = NULL; 4285 } 4286 4287 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4288 if (ehcip->ehci_count_stats[i]) { 4289 kstat_delete(ehcip->ehci_count_stats[i]); 4290 ehcip->ehci_count_stats[i] = NULL; 4291 } 4292 } 4293 } 4294 4295 4296 /* 4297 * ehci_do_intrs_stats: 4298 * 4299 * ehci status information 4300 */ 4301 void 4302 ehci_do_intrs_stats( 4303 ehci_state_t *ehcip, 4304 int val) 4305 { 4306 if (EHCI_INTRS_STATS(ehcip)) { 4307 EHCI_INTRS_STATS_DATA(ehcip)->ehci_sts_total.value.ui64++; 4308 switch (val) { 4309 case EHCI_STS_ASYNC_SCHED_STATUS: 4310 EHCI_INTRS_STATS_DATA(ehcip)-> 4311 ehci_sts_async_sched_status.value.ui64++; 4312 break; 4313 case EHCI_STS_PERIODIC_SCHED_STATUS: 4314 EHCI_INTRS_STATS_DATA(ehcip)-> 4315 ehci_sts_periodic_sched_status.value.ui64++; 4316 break; 4317 case EHCI_STS_EMPTY_ASYNC_SCHEDULE: 4318 EHCI_INTRS_STATS_DATA(ehcip)-> 4319 ehci_sts_empty_async_schedule.value.ui64++; 4320 break; 4321 case EHCI_STS_HOST_CTRL_HALTED: 4322 EHCI_INTRS_STATS_DATA(ehcip)-> 4323 ehci_sts_host_ctrl_halted.value.ui64++; 4324 break; 4325 case EHCI_STS_ASYNC_ADVANCE_INTR: 4326 EHCI_INTRS_STATS_DATA(ehcip)-> 4327 ehci_sts_async_advance_intr.value.ui64++; 4328 break; 4329 case EHCI_STS_HOST_SYSTEM_ERROR_INTR: 4330 EHCI_INTRS_STATS_DATA(ehcip)-> 4331 ehci_sts_host_system_error_intr.value.ui64++; 4332 break; 4333 case EHCI_STS_FRM_LIST_ROLLOVER_INTR: 4334 EHCI_INTRS_STATS_DATA(ehcip)-> 4335 ehci_sts_frm_list_rollover_intr.value.ui64++; 4336 break; 4337 case EHCI_STS_RH_PORT_CHANGE_INTR: 4338 EHCI_INTRS_STATS_DATA(ehcip)-> 4339 ehci_sts_rh_port_change_intr.value.ui64++; 4340 break; 4341 case EHCI_STS_USB_ERROR_INTR: 4342 EHCI_INTRS_STATS_DATA(ehcip)-> 4343 ehci_sts_usb_error_intr.value.ui64++; 4344 break; 4345 case EHCI_STS_USB_INTR: 4346 EHCI_INTRS_STATS_DATA(ehcip)-> 4347 ehci_sts_usb_intr.value.ui64++; 4348 break; 4349 default: 4350 EHCI_INTRS_STATS_DATA(ehcip)-> 4351 ehci_sts_not_claimed.value.ui64++; 4352 break; 4353 } 4354 } 4355 } 4356 4357 4358 /* 4359 * ehci_do_byte_stats: 4360 * 4361 * ehci data xfer information 4362 */ 4363 void 4364 ehci_do_byte_stats( 4365 ehci_state_t *ehcip, 4366 size_t len, 4367 uint8_t attr, 4368 uint8_t addr) 4369 { 4370 uint8_t type = attr & USB_EP_ATTR_MASK; 4371 uint8_t dir = addr & USB_EP_DIR_MASK; 4372 4373 if (dir == USB_EP_DIR_IN) { 4374 EHCI_TOTAL_STATS_DATA(ehcip)->reads++; 4375 EHCI_TOTAL_STATS_DATA(ehcip)->nread += len; 4376 switch (type) { 4377 case USB_EP_ATTR_CONTROL: 4378 EHCI_CTRL_STATS(ehcip)->reads++; 4379 EHCI_CTRL_STATS(ehcip)->nread += len; 4380 break; 4381 case USB_EP_ATTR_BULK: 4382 EHCI_BULK_STATS(ehcip)->reads++; 4383 EHCI_BULK_STATS(ehcip)->nread += len; 4384 break; 4385 case USB_EP_ATTR_INTR: 4386 EHCI_INTR_STATS(ehcip)->reads++; 4387 EHCI_INTR_STATS(ehcip)->nread += len; 4388 break; 4389 case USB_EP_ATTR_ISOCH: 4390 EHCI_ISOC_STATS(ehcip)->reads++; 4391 EHCI_ISOC_STATS(ehcip)->nread += len; 4392 break; 4393 } 4394 } else if (dir == USB_EP_DIR_OUT) { 4395 EHCI_TOTAL_STATS_DATA(ehcip)->writes++; 4396 EHCI_TOTAL_STATS_DATA(ehcip)->nwritten += len; 4397 switch (type) { 4398 case USB_EP_ATTR_CONTROL: 4399 EHCI_CTRL_STATS(ehcip)->writes++; 4400 EHCI_CTRL_STATS(ehcip)->nwritten += len; 4401 break; 4402 case USB_EP_ATTR_BULK: 4403 EHCI_BULK_STATS(ehcip)->writes++; 4404 EHCI_BULK_STATS(ehcip)->nwritten += len; 4405 break; 4406 case USB_EP_ATTR_INTR: 4407 EHCI_INTR_STATS(ehcip)->writes++; 4408 EHCI_INTR_STATS(ehcip)->nwritten += len; 4409 break; 4410 case USB_EP_ATTR_ISOCH: 4411 EHCI_ISOC_STATS(ehcip)->writes++; 4412 EHCI_ISOC_STATS(ehcip)->nwritten += len; 4413 break; 4414 } 4415 } 4416 } 4417