xref: /illumos-gate/usr/src/uts/common/io/skd/skd.h (revision f52228b8)
1*f52228b8SJoe Beteta /*
2*f52228b8SJoe Beteta  * This file and its contents are supplied under the terms of the
3*f52228b8SJoe Beteta  * Common Development and Distribution License ("CDDL"), version 1.0.
4*f52228b8SJoe Beteta  * You may only use this file in accordance with the terms of version
5*f52228b8SJoe Beteta  * 1.0 of the CDDL.
6*f52228b8SJoe Beteta  *
7*f52228b8SJoe Beteta  * A full copy of the text of the CDDL should have accompanied this
8*f52228b8SJoe Beteta  * source.  A copy of the CDDL is also available via the Internet at
9*f52228b8SJoe Beteta  * http://www.illumos.org/license/CDDL.
10*f52228b8SJoe Beteta  */
11*f52228b8SJoe Beteta 
12*f52228b8SJoe Beteta /*
13*f52228b8SJoe Beteta  * Copyright 2013 STEC, Inc.  All rights reserved.
14*f52228b8SJoe Beteta  * Copyright 2014 Nexenta Systems, Inc.  All rights reserved.
15*f52228b8SJoe Beteta  */
16*f52228b8SJoe Beteta 
17*f52228b8SJoe Beteta #ifndef _SKD_H
18*f52228b8SJoe Beteta #define	_SKD_H
19*f52228b8SJoe Beteta 
20*f52228b8SJoe Beteta #include	<sys/types.h>
21*f52228b8SJoe Beteta #include	<sys/stropts.h>
22*f52228b8SJoe Beteta #include	<sys/stream.h>
23*f52228b8SJoe Beteta #include	<sys/cmn_err.h>
24*f52228b8SJoe Beteta #include	<sys/kmem.h>
25*f52228b8SJoe Beteta #include	<sys/modctl.h>
26*f52228b8SJoe Beteta #include	<sys/ddi.h>
27*f52228b8SJoe Beteta #include	<sys/sunddi.h>
28*f52228b8SJoe Beteta #include	<sys/strsun.h>
29*f52228b8SJoe Beteta #include	<sys/kstat.h>
30*f52228b8SJoe Beteta #include 	<sys/conf.h>
31*f52228b8SJoe Beteta #include 	<sys/debug.h>
32*f52228b8SJoe Beteta #include 	<sys/modctl.h>
33*f52228b8SJoe Beteta #include 	<sys/errno.h>
34*f52228b8SJoe Beteta #include 	<sys/pci.h>
35*f52228b8SJoe Beteta #include 	<sys/memlist.h>
36*f52228b8SJoe Beteta #include 	<sys/param.h>
37*f52228b8SJoe Beteta #include	<sys/queue.h>
38*f52228b8SJoe Beteta 
39*f52228b8SJoe Beteta #define	DRV_NAME 	"skd"
40*f52228b8SJoe Beteta #define	DRV_VERSION 	"2.2.1"
41*f52228b8SJoe Beteta #define	DRV_BUILD_ID 	"0264"
42*f52228b8SJoe Beteta #define	PFX DRV_NAME    ": "
43*f52228b8SJoe Beteta #define	DRV_BIN_VERSION 0x100
44*f52228b8SJoe Beteta #define	DRV_VER_COMPL   DRV_VERSION "." DRV_BUILD_ID
45*f52228b8SJoe Beteta #define	VERSIONSTR 	DRV_VERSION
46*f52228b8SJoe Beteta 
47*f52228b8SJoe Beteta 
48*f52228b8SJoe Beteta #define	SG_BOUNDARY		0x20000
49*f52228b8SJoe Beteta 
50*f52228b8SJoe Beteta 
51*f52228b8SJoe Beteta #ifdef _BIG_ENDIAN
52*f52228b8SJoe Beteta #define	be64_to_cpu(x) (x)
53*f52228b8SJoe Beteta #define	be32_to_cpu(x) (x)
54*f52228b8SJoe Beteta #define	cpu_to_be64(x) (x)
55*f52228b8SJoe Beteta #define	cpu_to_be32(x) (x)
56*f52228b8SJoe Beteta #else
57*f52228b8SJoe Beteta #define	be64_to_cpu(x) BSWAP_64(x)
58*f52228b8SJoe Beteta #define	be32_to_cpu(x) BSWAP_32(x)
59*f52228b8SJoe Beteta #define	cpu_to_be64(x) BSWAP_64(x)
60*f52228b8SJoe Beteta #define	cpu_to_be32(x) BSWAP_32(x)
61*f52228b8SJoe Beteta #endif
62*f52228b8SJoe Beteta 
63*f52228b8SJoe Beteta #define	ATYPE_64BIT		0
64*f52228b8SJoe Beteta #define	ATYPE_32BIT		1
65*f52228b8SJoe Beteta 
66*f52228b8SJoe Beteta #define	BIT_0			0x00001
67*f52228b8SJoe Beteta #define	BIT_1			0x00002
68*f52228b8SJoe Beteta #define	BIT_2			0x00004
69*f52228b8SJoe Beteta #define	BIT_3			0x00008
70*f52228b8SJoe Beteta #define	BIT_4			0x00010
71*f52228b8SJoe Beteta #define	BIT_5			0x00020
72*f52228b8SJoe Beteta #define	BIT_6			0x00040
73*f52228b8SJoe Beteta #define	BIT_7			0x00080
74*f52228b8SJoe Beteta #define	BIT_8			0x00100
75*f52228b8SJoe Beteta #define	BIT_9			0x00200
76*f52228b8SJoe Beteta #define	BIT_10			0x00400
77*f52228b8SJoe Beteta #define	BIT_11			0x00800
78*f52228b8SJoe Beteta #define	BIT_12			0x01000
79*f52228b8SJoe Beteta #define	BIT_13			0x02000
80*f52228b8SJoe Beteta #define	BIT_14			0x04000
81*f52228b8SJoe Beteta #define	BIT_15			0x08000
82*f52228b8SJoe Beteta #define	BIT_16			0x10000
83*f52228b8SJoe Beteta #define	BIT_17			0x20000
84*f52228b8SJoe Beteta #define	BIT_18			0x40000
85*f52228b8SJoe Beteta #define	BIT_19			0x80000
86*f52228b8SJoe Beteta 
87*f52228b8SJoe Beteta /* Attach progress flags */
88*f52228b8SJoe Beteta #define	SKD_ATTACHED			BIT_0
89*f52228b8SJoe Beteta #define	SKD_SOFT_STATE_ALLOCED		BIT_1
90*f52228b8SJoe Beteta #define	SKD_CONFIG_SPACE_SETUP		BIT_3
91*f52228b8SJoe Beteta #define	SKD_IOBASE_MAPPED		BIT_4
92*f52228b8SJoe Beteta #define	SKD_IOMAP_IOBASE_MAPPED		BIT_5
93*f52228b8SJoe Beteta #define	SKD_REGS_MAPPED			BIT_6
94*f52228b8SJoe Beteta #define	SKD_DEV_IOBASE_MAPPED		BIT_7
95*f52228b8SJoe Beteta #define	SKD_CONSTRUCTED			BIT_8
96*f52228b8SJoe Beteta #define	SKD_PROBED			BIT_9
97*f52228b8SJoe Beteta #define	SKD_INTR_ADDED			BIT_10
98*f52228b8SJoe Beteta #define	SKD_PATHNAME_ALLOCED		BIT_11
99*f52228b8SJoe Beteta #define	SKD_SUSPENDED			BIT_12
100*f52228b8SJoe Beteta #define	SKD_CMD_ABORT_TMO		BIT_13
101*f52228b8SJoe Beteta #define	SKD_MUTEX_INITED		BIT_14
102*f52228b8SJoe Beteta #define	SKD_MUTEX_DESTROYED		BIT_15
103*f52228b8SJoe Beteta 
104*f52228b8SJoe Beteta #define	SKD_IODONE_WIOC			1	/* I/O done */
105*f52228b8SJoe Beteta #define	SKD_IODONE_WNIOC		2	/* I/O NOT done */
106*f52228b8SJoe Beteta #define	SKD_IODONE_WDEBUG		3	/* I/O - debug stuff */
107*f52228b8SJoe Beteta 
108*f52228b8SJoe Beteta #ifdef SKD_PM
109*f52228b8SJoe Beteta #define	MAX_POWER_LEVEL			0
110*f52228b8SJoe Beteta #define	LOW_POWER_LEVEL			(BIT_1 | BIT_0)
111*f52228b8SJoe Beteta #endif
112*f52228b8SJoe Beteta 
113*f52228b8SJoe Beteta #define	SKD_MSIX_AIF		0x0
114*f52228b8SJoe Beteta #define	SKD_MSIX_RSPQ		0x1
115*f52228b8SJoe Beteta #define	SKD_MSIX_MAXAIF		SKD_MSIX_RSPQ + 1
116*f52228b8SJoe Beteta 
117*f52228b8SJoe Beteta /*
118*f52228b8SJoe Beteta  * Stuff from Linux
119*f52228b8SJoe Beteta  */
120*f52228b8SJoe Beteta #define	SAM_STAT_GOOD			0x00
121*f52228b8SJoe Beteta #define	SAM_STAT_CHECK_CONDITION	0x02
122*f52228b8SJoe Beteta 
123*f52228b8SJoe Beteta #define	TEST_UNIT_READY		0x00
124*f52228b8SJoe Beteta #define	INQUIRY			0x12
125*f52228b8SJoe Beteta #define	INQUIRY2		(0x12 + 0xe0)
126*f52228b8SJoe Beteta #define	READ_CAPACITY		0x25
127*f52228b8SJoe Beteta #define	READ_CAPACITY_EXT	0x9e
128*f52228b8SJoe Beteta #define	SYNCHRONIZE_CACHE	0x35
129*f52228b8SJoe Beteta 
130*f52228b8SJoe Beteta /*
131*f52228b8SJoe Beteta  *  SENSE KEYS
132*f52228b8SJoe Beteta  */
133*f52228b8SJoe Beteta #define	NO_SENSE	    0x00
134*f52228b8SJoe Beteta #define	RECOVERED_ERROR	    0x01
135*f52228b8SJoe Beteta #define	UNIT_ATTENTION	    0x06
136*f52228b8SJoe Beteta #define	ABORTED_COMMAND	    0x0b
137*f52228b8SJoe Beteta 
138*f52228b8SJoe Beteta typedef struct dma_mem_t {
139*f52228b8SJoe Beteta 	void			*bp;
140*f52228b8SJoe Beteta 	ddi_acc_handle_t	acc_handle;
141*f52228b8SJoe Beteta 	ddi_dma_handle_t	dma_handle;
142*f52228b8SJoe Beteta 	ddi_dma_cookie_t	cookie;
143*f52228b8SJoe Beteta 	ddi_dma_cookie_t	*cookies;
144*f52228b8SJoe Beteta 	uint32_t		size;
145*f52228b8SJoe Beteta } dma_mem_t;
146*f52228b8SJoe Beteta 
147*f52228b8SJoe Beteta #define	SKD_WRITEL(DEV, VAL, OFF)	skd_reg_write32(DEV, VAL, OFF)
148*f52228b8SJoe Beteta #define	SKD_READL(DEV, OFF)		skd_reg_read32(DEV, OFF)
149*f52228b8SJoe Beteta #define	SKD_WRITEQ(DEV, VAL, OFF)	skd_reg_write64(DEV, VAL, OFF)
150*f52228b8SJoe Beteta 
151*f52228b8SJoe Beteta /* Capability lists */
152*f52228b8SJoe Beteta #define	PCI_CAP_ID_EXP		0x10	/* PCI Express */
153*f52228b8SJoe Beteta 
154*f52228b8SJoe Beteta /*
155*f52228b8SJoe Beteta  * End Stuff from Linux
156*f52228b8SJoe Beteta  */
157*f52228b8SJoe Beteta 
158*f52228b8SJoe Beteta #define	SKD_DMA_MAXXFER			(2048 * DEV_BSIZE)
159*f52228b8SJoe Beteta 
160*f52228b8SJoe Beteta #define	SKD_DMA_LOW_ADDRESS		(uint64_t)0
161*f52228b8SJoe Beteta #define	SKD_DMA_HIGH_64BIT_ADDRESS	(uint64_t)0xffffffffffffffff
162*f52228b8SJoe Beteta #define	SKD_DMA_HIGH_32BIT_ADDRESS	(uint64_t)0xffffffff
163*f52228b8SJoe Beteta #define	SKD_DMA_XFER_COUNTER		(uint64_t)0xffffffff
164*f52228b8SJoe Beteta #define	SKD_DMA_ADDRESS_ALIGNMENT	(uint64_t)SG_BOUNDARY
165*f52228b8SJoe Beteta #define	SKD_DMA_BURSTSIZES		0xff
166*f52228b8SJoe Beteta #define	SKD_DMA_MIN_XFER_SIZE		1
167*f52228b8SJoe Beteta #define	SKD_DMA_MAX_XFER_SIZE		(uint64_t)0xfffffe00
168*f52228b8SJoe Beteta #define	SKD_DMA_SEGMENT_BOUNDARY	(uint64_t)0xffffffff
169*f52228b8SJoe Beteta #define	SKD_DMA_SG_LIST_LENGTH		256
170*f52228b8SJoe Beteta #define	SKD_DMA_XFER_FLAGS		0
171*f52228b8SJoe Beteta #define	SKD_DMA_GRANULARITY		512 /* 1 */
172*f52228b8SJoe Beteta 
173*f52228b8SJoe Beteta #define	PCI_VENDOR_ID_STEC  0x1B39
174*f52228b8SJoe Beteta #define	PCI_DEVICE_ID_SUMO  0x0001
175*f52228b8SJoe Beteta 
176*f52228b8SJoe Beteta #define	SKD_N_FITMSG_BYTES	(512u)
177*f52228b8SJoe Beteta 
178*f52228b8SJoe Beteta #define	SKD_N_SPECIAL_CONTEXT	64u
179*f52228b8SJoe Beteta #define	SKD_N_SPECIAL_FITMSG_BYTES (128u)
180*f52228b8SJoe Beteta #define	SKD_N_SPECIAL_DATA_BYTES  (8u*1024u)
181*f52228b8SJoe Beteta 
182*f52228b8SJoe Beteta 
183*f52228b8SJoe Beteta /*
184*f52228b8SJoe Beteta  * SG elements are 32 bytes, so we can make this 4096 and still be under the
185*f52228b8SJoe Beteta  * 128KB limit.	 That allows 4096*4K = 16M xfer size
186*f52228b8SJoe Beteta  */
187*f52228b8SJoe Beteta #define	SKD_N_SG_PER_REQ_DEFAULT 256u
188*f52228b8SJoe Beteta #define	SKD_N_SG_PER_SPECIAL	256u
189*f52228b8SJoe Beteta 
190*f52228b8SJoe Beteta #define	SKD_N_COMPLETION_ENTRY		256u
191*f52228b8SJoe Beteta #define	SKD_N_READ_CAP_BYTES		(8u)
192*f52228b8SJoe Beteta #define	SKD_N_READ_CAP_EXT_BYTES	(16)
193*f52228b8SJoe Beteta 
194*f52228b8SJoe Beteta #define	SKD_N_INTERNAL_BYTES   (512u)
195*f52228b8SJoe Beteta 
196*f52228b8SJoe Beteta /* 5 bits of uniqifier, 0xF800 */
197*f52228b8SJoe Beteta #define	SKD_ID_INCR		(0x400)
198*f52228b8SJoe Beteta #define	SKD_ID_TABLE_MASK	(3u << 8u)
199*f52228b8SJoe Beteta #define	SKD_ID_RW_REQUEST	(0u << 8u)
200*f52228b8SJoe Beteta #define	SKD_ID_INTERNAL		(1u << 8u)
201*f52228b8SJoe Beteta #define	SKD_ID_FIT_MSG		(3u << 8u)
202*f52228b8SJoe Beteta #define	SKD_ID_SLOT_MASK	0x00FFu
203*f52228b8SJoe Beteta #define	SKD_ID_SLOT_AND_TABLE_MASK 0x03FFu
204*f52228b8SJoe Beteta 
205*f52228b8SJoe Beteta #define	SKD_N_TIMEOUT_SLOT	8u
206*f52228b8SJoe Beteta #define	SKD_TIMEOUT_SLOT_MASK	7u
207*f52228b8SJoe Beteta 
208*f52228b8SJoe Beteta #define	SKD_TIMER_SECONDS(seconds) (seconds)
209*f52228b8SJoe Beteta #define	SKD_TIMER_MINUTES(minutes) ((minutes)*(60))
210*f52228b8SJoe Beteta 
211*f52228b8SJoe Beteta /*
212*f52228b8SJoe Beteta  * NOTE:  INTR_LOCK() should be held prior to grabbing WAITQ_LOCK() if both
213*f52228b8SJoe Beteta  * are needed.
214*f52228b8SJoe Beteta  */
215*f52228b8SJoe Beteta #define	INTR_LOCK(skdev)		mutex_enter(&skdev->skd_intr_mutex)
216*f52228b8SJoe Beteta #define	INTR_UNLOCK(skdev)		mutex_exit(&skdev->skd_intr_mutex)
217*f52228b8SJoe Beteta #define	INTR_LOCK_HELD(skdev)		MUTEX_HELD(&skdev->skd_intr_mutex)
218*f52228b8SJoe Beteta 
219*f52228b8SJoe Beteta #define	WAITQ_LOCK(skdev) \
220*f52228b8SJoe Beteta 	mutex_enter(&skdev->waitqueue_mutex)
221*f52228b8SJoe Beteta #define	WAITQ_UNLOCK(skdev) \
222*f52228b8SJoe Beteta 	mutex_exit(&skdev->waitqueue_mutex)
223*f52228b8SJoe Beteta #define	WAITQ_LOCK_HELD(skdev) \
224*f52228b8SJoe Beteta 	MUTEX_HELD(&skdev->waitqueue_mutex)
225*f52228b8SJoe Beteta 
226*f52228b8SJoe Beteta #define	ADAPTER_STATE_LOCK(skdev)	mutex_enter(&skdev->skd_lock_mutex)
227*f52228b8SJoe Beteta #define	ADAPTER_STATE_UNLOCK(skdev)	mutex_exit(&skdev->skd_lock_mutex)
228*f52228b8SJoe Beteta 
229*f52228b8SJoe Beteta enum skd_drvr_state {
230*f52228b8SJoe Beteta 	SKD_DRVR_STATE_LOAD,			/* 0 when driver first loaded */
231*f52228b8SJoe Beteta 	SKD_DRVR_STATE_IDLE,			/* 1 when device goes offline */
232*f52228b8SJoe Beteta 	SKD_DRVR_STATE_BUSY,			/* 2 */
233*f52228b8SJoe Beteta 	SKD_DRVR_STATE_STARTING,		/* 3 */
234*f52228b8SJoe Beteta 	SKD_DRVR_STATE_ONLINE,			/* 4 */
235*f52228b8SJoe Beteta 	SKD_DRVR_STATE_PAUSING,			/* 5 */
236*f52228b8SJoe Beteta 	SKD_DRVR_STATE_PAUSED,			/* 6 */
237*f52228b8SJoe Beteta 	SKD_DRVR_STATE_DRAINING_TIMEOUT,	/* 7 */
238*f52228b8SJoe Beteta 	SKD_DRVR_STATE_RESTARTING,		/* 8 */
239*f52228b8SJoe Beteta 	SKD_DRVR_STATE_RESUMING,		/* 9 */
240*f52228b8SJoe Beteta 	SKD_DRVR_STATE_STOPPING,	/* 10 when driver is unloading */
241*f52228b8SJoe Beteta 	SKD_DRVR_STATE_FAULT,			/* 11 */
242*f52228b8SJoe Beteta 	SKD_DRVR_STATE_DISAPPEARED,		/* 12 */
243*f52228b8SJoe Beteta 	SKD_DRVR_STATE_PROTOCOL_MISMATCH,	/* 13 */
244*f52228b8SJoe Beteta 	SKD_DRVR_STATE_BUSY_ERASE,		/* 14 */
245*f52228b8SJoe Beteta 	SKD_DRVR_STATE_BUSY_SANITIZE,		/* 15 */
246*f52228b8SJoe Beteta 	SKD_DRVR_STATE_BUSY_IMMINENT,		/* 16 */
247*f52228b8SJoe Beteta 	SKD_DRVR_STATE_WAIT_BOOT,		/* 17 */
248*f52228b8SJoe Beteta 	SKD_DRVR_STATE_SYNCING			/* 18 */
249*f52228b8SJoe Beteta };
250*f52228b8SJoe Beteta 
251*f52228b8SJoe Beteta #define	SKD_WAIT_BOOT_TO 90u
252*f52228b8SJoe Beteta #define	SKD_STARTING_TO	 248u
253*f52228b8SJoe Beteta 
254*f52228b8SJoe Beteta enum skd_req_state {
255*f52228b8SJoe Beteta 	SKD_REQ_STATE_IDLE,
256*f52228b8SJoe Beteta 	SKD_REQ_STATE_SETUP,
257*f52228b8SJoe Beteta 	SKD_REQ_STATE_BUSY,
258*f52228b8SJoe Beteta 	SKD_REQ_STATE_COMPLETED,
259*f52228b8SJoe Beteta 	SKD_REQ_STATE_TIMEOUT,
260*f52228b8SJoe Beteta 	SKD_REQ_STATE_ABORTED,
261*f52228b8SJoe Beteta };
262*f52228b8SJoe Beteta 
263*f52228b8SJoe Beteta enum skd_fit_msg_state {
264*f52228b8SJoe Beteta 	SKD_MSG_STATE_IDLE,
265*f52228b8SJoe Beteta 	SKD_MSG_STATE_BUSY,
266*f52228b8SJoe Beteta };
267*f52228b8SJoe Beteta 
268*f52228b8SJoe Beteta enum skd_check_status_action {
269*f52228b8SJoe Beteta 	SKD_CHECK_STATUS_REPORT_GOOD,
270*f52228b8SJoe Beteta 	SKD_CHECK_STATUS_REPORT_SMART_ALERT,
271*f52228b8SJoe Beteta 	SKD_CHECK_STATUS_REQUEUE_REQUEST,
272*f52228b8SJoe Beteta 	SKD_CHECK_STATUS_REPORT_ERROR,
273*f52228b8SJoe Beteta 	SKD_CHECK_STATUS_BUSY_IMMINENT,
274*f52228b8SJoe Beteta };
275*f52228b8SJoe Beteta 
276*f52228b8SJoe Beteta /* NOTE:  mbu_t users should name this field "mbu". */
277*f52228b8SJoe Beteta typedef union {
278*f52228b8SJoe Beteta 	uint8_t *mb8;
279*f52228b8SJoe Beteta 	uint64_t *mb64;
280*f52228b8SJoe Beteta } mbu_t;
281*f52228b8SJoe Beteta #define	msg_buf mbu.mb8
282*f52228b8SJoe Beteta #define	msg_buf64 mbu.mb64
283*f52228b8SJoe Beteta 
284*f52228b8SJoe Beteta struct skd_fitmsg_context {
285*f52228b8SJoe Beteta 	enum skd_fit_msg_state state;
286*f52228b8SJoe Beteta 	struct skd_fitmsg_context *next;
287*f52228b8SJoe Beteta 	uint32_t	id;
288*f52228b8SJoe Beteta 	uint16_t	outstanding;
289*f52228b8SJoe Beteta 	uint32_t	length;
290*f52228b8SJoe Beteta 	uint32_t	offset;
291*f52228b8SJoe Beteta 	mbu_t		mbu;	/* msg_buf & msg_buf64 */
292*f52228b8SJoe Beteta 	dma_mem_t	mb_dma_address;
293*f52228b8SJoe Beteta };
294*f52228b8SJoe Beteta 
295*f52228b8SJoe Beteta struct skd_request_context {
296*f52228b8SJoe Beteta 	enum skd_req_state		state;
297*f52228b8SJoe Beteta 	struct skd_request_context	*next;
298*f52228b8SJoe Beteta 	uint16_t			did_complete;
299*f52228b8SJoe Beteta 	uint16_t			id;
300*f52228b8SJoe Beteta 	uint32_t			fitmsg_id;
301*f52228b8SJoe Beteta 	struct skd_buf_private		*pbuf;
302*f52228b8SJoe Beteta 	uint32_t			timeout_stamp;
303*f52228b8SJoe Beteta 	uint8_t				sg_data_dir;
304*f52228b8SJoe Beteta 	uint32_t			n_sg;
305*f52228b8SJoe Beteta 	ddi_dma_handle_t		io_dma_handle;
306*f52228b8SJoe Beteta 	struct fit_sg_descriptor	*sksg_list;
307*f52228b8SJoe Beteta 	dma_mem_t			sksg_dma_address;
308*f52228b8SJoe Beteta 	struct fit_completion_entry_v1	completion;
309*f52228b8SJoe Beteta 	struct fit_comp_error_info	err_info;
310*f52228b8SJoe Beteta 	int				total_sg_bcount;
311*f52228b8SJoe Beteta };
312*f52228b8SJoe Beteta 
313*f52228b8SJoe Beteta #define	SKD_DATA_DIR_HOST_TO_CARD	1
314*f52228b8SJoe Beteta #define	SKD_DATA_DIR_CARD_TO_HOST	2
315*f52228b8SJoe Beteta 
316*f52228b8SJoe Beteta struct skd_special_context {
317*f52228b8SJoe Beteta 	struct skd_request_context req;
318*f52228b8SJoe Beteta 	uint8_t			   orphaned;
319*f52228b8SJoe Beteta 	uint32_t		   sg_byte_count;
320*f52228b8SJoe Beteta 	void			   *data_buf;
321*f52228b8SJoe Beteta 	dma_mem_t		   db_dma_address;
322*f52228b8SJoe Beteta 	mbu_t			   mbu;	/* msg_buf & msg_buf64 */
323*f52228b8SJoe Beteta 	dma_mem_t		   mb_dma_address;
324*f52228b8SJoe Beteta 	int			   io_pending;
325*f52228b8SJoe Beteta };
326*f52228b8SJoe Beteta 
327*f52228b8SJoe Beteta typedef struct skd_buf_private {
328*f52228b8SJoe Beteta 	SIMPLEQ_ENTRY(skd_buf_private) sq;
329*f52228b8SJoe Beteta 	struct skd_request_context *skreq;
330*f52228b8SJoe Beteta 	bd_xfer_t *x_xfer;
331*f52228b8SJoe Beteta 	int dir;
332*f52228b8SJoe Beteta } skd_buf_private_t;
333*f52228b8SJoe Beteta 
334*f52228b8SJoe Beteta SIMPLEQ_HEAD(waitqueue, skd_buf_private);
335*f52228b8SJoe Beteta 
336*f52228b8SJoe Beteta typedef struct skd_device skd_device_t;
337*f52228b8SJoe Beteta 
338*f52228b8SJoe Beteta struct skd_device {
339*f52228b8SJoe Beteta 	int		irq_type;
340*f52228b8SJoe Beteta 	int		gendisk_on;
341*f52228b8SJoe Beteta 	int		sync_done;
342*f52228b8SJoe Beteta 
343*f52228b8SJoe Beteta 	char		name[32];
344*f52228b8SJoe Beteta 
345*f52228b8SJoe Beteta 	enum		skd_drvr_state state;
346*f52228b8SJoe Beteta 	uint32_t		drive_state;
347*f52228b8SJoe Beteta 
348*f52228b8SJoe Beteta 	uint32_t	queue_depth_busy;
349*f52228b8SJoe Beteta 	uint32_t	queue_depth_limit;
350*f52228b8SJoe Beteta 	uint32_t	queue_depth_lowat;
351*f52228b8SJoe Beteta 	uint32_t	soft_queue_depth_limit;
352*f52228b8SJoe Beteta 	uint32_t	hard_queue_depth_limit;
353*f52228b8SJoe Beteta 
354*f52228b8SJoe Beteta 	uint32_t	num_fitmsg_context;
355*f52228b8SJoe Beteta 	uint32_t	num_req_context;
356*f52228b8SJoe Beteta 
357*f52228b8SJoe Beteta 	uint32_t	timeout_slot[SKD_N_TIMEOUT_SLOT];
358*f52228b8SJoe Beteta 	uint32_t	timeout_stamp;
359*f52228b8SJoe Beteta 
360*f52228b8SJoe Beteta 	struct skd_fitmsg_context *skmsg_free_list;
361*f52228b8SJoe Beteta 	struct skd_fitmsg_context *skmsg_table;
362*f52228b8SJoe Beteta 
363*f52228b8SJoe Beteta 	struct skd_request_context *skreq_free_list;
364*f52228b8SJoe Beteta 	struct skd_request_context *skreq_table;
365*f52228b8SJoe Beteta 	struct skd_special_context internal_skspcl;
366*f52228b8SJoe Beteta 
367*f52228b8SJoe Beteta 	uint64_t	read_cap_last_lba;
368*f52228b8SJoe Beteta 	uint32_t	read_cap_blocksize;
369*f52228b8SJoe Beteta 	int		read_cap_is_valid;
370*f52228b8SJoe Beteta 	int		inquiry_is_valid;
371*f52228b8SJoe Beteta 	char		inq_serial_num[13]; /* 12 chars plus null term */
372*f52228b8SJoe Beteta 	char		inq_vendor_id[9];
373*f52228b8SJoe Beteta 	char		inq_product_id[17];
374*f52228b8SJoe Beteta 	char		inq_product_rev[5];
375*f52228b8SJoe Beteta 	char		id_str[128]; /* holds a composite name (pci + sernum) */
376*f52228b8SJoe Beteta 
377*f52228b8SJoe Beteta 	uint8_t		skcomp_cycle;
378*f52228b8SJoe Beteta 	uint32_t	skcomp_ix;
379*f52228b8SJoe Beteta 	struct fit_completion_entry_v1 *skcomp_table;
380*f52228b8SJoe Beteta 	struct fit_comp_error_info *skerr_table;
381*f52228b8SJoe Beteta 	dma_mem_t	cq_dma_address;
382*f52228b8SJoe Beteta 
383*f52228b8SJoe Beteta 	uint32_t	timer_active;
384*f52228b8SJoe Beteta 	uint32_t	timer_countdown;
385*f52228b8SJoe Beteta 	uint32_t	timer_substate;
386*f52228b8SJoe Beteta 
387*f52228b8SJoe Beteta 	int		sgs_per_request;
388*f52228b8SJoe Beteta 	uint32_t	last_mtd;
389*f52228b8SJoe Beteta 
390*f52228b8SJoe Beteta 	uint32_t	proto_ver;
391*f52228b8SJoe Beteta 
392*f52228b8SJoe Beteta 	int		dbg_level;
393*f52228b8SJoe Beteta 
394*f52228b8SJoe Beteta 	uint32_t	timo_slot;
395*f52228b8SJoe Beteta 
396*f52228b8SJoe Beteta 	ddi_acc_handle_t	pci_handle;
397*f52228b8SJoe Beteta 	ddi_acc_handle_t	iobase_handle;
398*f52228b8SJoe Beteta 	ddi_acc_handle_t	iomap_handle;
399*f52228b8SJoe Beteta 	caddr_t			iobase;
400*f52228b8SJoe Beteta 	caddr_t			iomap_iobase;
401*f52228b8SJoe Beteta 
402*f52228b8SJoe Beteta 	ddi_acc_handle_t	dev_handle;
403*f52228b8SJoe Beteta 	caddr_t			dev_iobase;
404*f52228b8SJoe Beteta 	int			dev_memsize;
405*f52228b8SJoe Beteta 
406*f52228b8SJoe Beteta 	char			*pathname;
407*f52228b8SJoe Beteta 
408*f52228b8SJoe Beteta 	dev_info_t		*dip;
409*f52228b8SJoe Beteta 
410*f52228b8SJoe Beteta 	int			instance;
411*f52228b8SJoe Beteta 	uint16_t		vendor_id;
412*f52228b8SJoe Beteta 	uint16_t		device_id;
413*f52228b8SJoe Beteta 
414*f52228b8SJoe Beteta 	kmutex_t		skd_lock_mutex;
415*f52228b8SJoe Beteta 	kmutex_t		skd_intr_mutex;
416*f52228b8SJoe Beteta 	kmutex_t		skd_fit_mutex;
417*f52228b8SJoe Beteta 
418*f52228b8SJoe Beteta 	uint32_t		flags;
419*f52228b8SJoe Beteta 
420*f52228b8SJoe Beteta #ifdef SKD_PM
421*f52228b8SJoe Beteta 	uint8_t			power_level;
422*f52228b8SJoe Beteta #endif
423*f52228b8SJoe Beteta 
424*f52228b8SJoe Beteta 	/* AIF (Advanced Interrupt Framework) support */
425*f52228b8SJoe Beteta 	ddi_intr_handle_t	*htable;
426*f52228b8SJoe Beteta 	uint32_t		hsize;
427*f52228b8SJoe Beteta 	int32_t			intr_cnt;
428*f52228b8SJoe Beteta 	uint32_t		intr_pri;
429*f52228b8SJoe Beteta 	int32_t			intr_cap;
430*f52228b8SJoe Beteta 
431*f52228b8SJoe Beteta 	uint64_t		Nblocks;
432*f52228b8SJoe Beteta 
433*f52228b8SJoe Beteta 	ddi_iblock_cookie_t	iblock_cookie;
434*f52228b8SJoe Beteta 
435*f52228b8SJoe Beteta 	int		n_req;
436*f52228b8SJoe Beteta 	uint32_t	progress;
437*f52228b8SJoe Beteta 	uint64_t	intr_cntr;
438*f52228b8SJoe Beteta 	uint64_t	fitmsg_sent1;
439*f52228b8SJoe Beteta 	uint64_t	fitmsg_sent2;
440*f52228b8SJoe Beteta 	uint64_t	active_cmds;
441*f52228b8SJoe Beteta 
442*f52228b8SJoe Beteta 	kmutex_t	skd_internalio_mutex;
443*f52228b8SJoe Beteta 	kcondvar_t	cv_waitq;
444*f52228b8SJoe Beteta 
445*f52228b8SJoe Beteta 	kmutex_t	waitqueue_mutex;
446*f52228b8SJoe Beteta 	struct waitqueue waitqueue;
447*f52228b8SJoe Beteta 	int		disks_initialized;
448*f52228b8SJoe Beteta 
449*f52228b8SJoe Beteta 	ddi_devid_t	s1120_devid;
450*f52228b8SJoe Beteta 	char		devid_str[80];
451*f52228b8SJoe Beteta 
452*f52228b8SJoe Beteta 	uint32_t	d_blkshift;
453*f52228b8SJoe Beteta 
454*f52228b8SJoe Beteta 	int		attached;
455*f52228b8SJoe Beteta 
456*f52228b8SJoe Beteta 	int		ios_queued;
457*f52228b8SJoe Beteta 	int		ios_started;
458*f52228b8SJoe Beteta 	int		ios_completed;
459*f52228b8SJoe Beteta 	int		ios_errors;
460*f52228b8SJoe Beteta 	int		iodone_wioc;
461*f52228b8SJoe Beteta 	int		iodone_wnioc;
462*f52228b8SJoe Beteta 	int		iodone_wdebug;
463*f52228b8SJoe Beteta 	int		iodone_unknown;
464*f52228b8SJoe Beteta 
465*f52228b8SJoe Beteta 	bd_handle_t	s_bdh;
466*f52228b8SJoe Beteta 	int		bd_attached;
467*f52228b8SJoe Beteta 
468*f52228b8SJoe Beteta #ifdef USE_SKE_EMULATOR
469*f52228b8SJoe Beteta 	ske_device_t *ske_handle;
470*f52228b8SJoe Beteta #endif
471*f52228b8SJoe Beteta 
472*f52228b8SJoe Beteta 	timeout_id_t	skd_timer_timeout_id;
473*f52228b8SJoe Beteta };
474*f52228b8SJoe Beteta 
475*f52228b8SJoe Beteta static void skd_disable_interrupts(struct skd_device *skdev);
476*f52228b8SJoe Beteta static void skd_isr_completion_posted(struct skd_device *skdev);
477*f52228b8SJoe Beteta static void skd_recover_requests(struct skd_device *skdev);
478*f52228b8SJoe Beteta static void skd_log_skdev(struct skd_device *skdev, const char *event);
479*f52228b8SJoe Beteta static void skd_restart_device(struct skd_device *skdev);
480*f52228b8SJoe Beteta static void skd_destruct(struct skd_device *skdev);
481*f52228b8SJoe Beteta static int skd_unquiesce_dev(struct skd_device *skdev);
482*f52228b8SJoe Beteta static void skd_send_special_fitmsg(struct skd_device *skdev,
483*f52228b8SJoe Beteta     struct skd_special_context *skspcl);
484*f52228b8SJoe Beteta static void skd_end_request(struct skd_device *skdev,
485*f52228b8SJoe Beteta     struct skd_request_context *skreq, int error);
486*f52228b8SJoe Beteta static void skd_log_skmsg(struct skd_device *skdev,
487*f52228b8SJoe Beteta     struct skd_fitmsg_context *skmsg, const char *event);
488*f52228b8SJoe Beteta static void skd_log_skreq(struct skd_device *skdev,
489*f52228b8SJoe Beteta     struct skd_request_context *skreq, const char *event);
490*f52228b8SJoe Beteta static void skd_send_fitmsg(struct skd_device *skdev,
491*f52228b8SJoe Beteta     struct skd_fitmsg_context *skmsg);
492*f52228b8SJoe Beteta 
493*f52228b8SJoe Beteta static const char *skd_drive_state_to_str(int state);
494*f52228b8SJoe Beteta static const char *skd_skdev_state_to_str(enum skd_drvr_state state);
495*f52228b8SJoe Beteta 
496*f52228b8SJoe Beteta #endif /* _SKD_H */
497