1*49ef7e06SGarrett D'Amore /* 2*49ef7e06SGarrett D'Amore * Copyright (c) 2007-2015 Solarflare Communications Inc. 3*49ef7e06SGarrett D'Amore * All rights reserved. 4*49ef7e06SGarrett D'Amore * 5*49ef7e06SGarrett D'Amore * Redistribution and use in source and binary forms, with or without 6*49ef7e06SGarrett D'Amore * modification, are permitted provided that the following conditions are met: 7*49ef7e06SGarrett D'Amore * 8*49ef7e06SGarrett D'Amore * 1. Redistributions of source code must retain the above copyright notice, 9*49ef7e06SGarrett D'Amore * this list of conditions and the following disclaimer. 10*49ef7e06SGarrett D'Amore * 2. Redistributions in binary form must reproduce the above copyright notice, 11*49ef7e06SGarrett D'Amore * this list of conditions and the following disclaimer in the documentation 12*49ef7e06SGarrett D'Amore * and/or other materials provided with the distribution. 13*49ef7e06SGarrett D'Amore * 14*49ef7e06SGarrett D'Amore * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15*49ef7e06SGarrett D'Amore * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16*49ef7e06SGarrett D'Amore * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17*49ef7e06SGarrett D'Amore * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18*49ef7e06SGarrett D'Amore * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19*49ef7e06SGarrett D'Amore * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20*49ef7e06SGarrett D'Amore * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21*49ef7e06SGarrett D'Amore * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22*49ef7e06SGarrett D'Amore * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23*49ef7e06SGarrett D'Amore * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24*49ef7e06SGarrett D'Amore * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25*49ef7e06SGarrett D'Amore * 26*49ef7e06SGarrett D'Amore * The views and conclusions contained in the software and documentation are 27*49ef7e06SGarrett D'Amore * those of the authors and should not be interpreted as representing official 28*49ef7e06SGarrett D'Amore * policies, either expressed or implied, of the FreeBSD Project. 29*49ef7e06SGarrett D'Amore */ 30*49ef7e06SGarrett D'Amore 31*49ef7e06SGarrett D'Amore #ifndef _SYS_SIENA_FLASH_H 32*49ef7e06SGarrett D'Amore #define _SYS_SIENA_FLASH_H 33*49ef7e06SGarrett D'Amore 34*49ef7e06SGarrett D'Amore #pragma pack(1) 35*49ef7e06SGarrett D'Amore 36*49ef7e06SGarrett D'Amore /* Fixed locations near the start of flash (which may be in the internal PHY 37*49ef7e06SGarrett D'Amore * firmware header) point to the boot header. 38*49ef7e06SGarrett D'Amore * 39*49ef7e06SGarrett D'Amore * - parsed by MC boot ROM and firmware 40*49ef7e06SGarrett D'Amore * - reserved (but not parsed) by PHY firmware 41*49ef7e06SGarrett D'Amore * - opaque to driver 42*49ef7e06SGarrett D'Amore */ 43*49ef7e06SGarrett D'Amore 44*49ef7e06SGarrett D'Amore #define SIENA_MC_BOOT_PHY_FW_HDR_LEN (0x20) 45*49ef7e06SGarrett D'Amore 46*49ef7e06SGarrett D'Amore #define SIENA_MC_BOOT_PTR_LOCATION (0x18) /* First thing we try to boot */ 47*49ef7e06SGarrett D'Amore #define SIENA_MC_BOOT_ALT_PTR_LOCATION (0x1c) /* Alternative if that fails */ 48*49ef7e06SGarrett D'Amore 49*49ef7e06SGarrett D'Amore #define SIENA_MC_BOOT_HDR_LEN (0x200) 50*49ef7e06SGarrett D'Amore 51*49ef7e06SGarrett D'Amore #define SIENA_MC_BOOT_MAGIC (0x51E4A001) 52*49ef7e06SGarrett D'Amore #define SIENA_MC_BOOT_VERSION (1) 53*49ef7e06SGarrett D'Amore 54*49ef7e06SGarrett D'Amore 55*49ef7e06SGarrett D'Amore /*Structures supporting an arbitrary number of binary blobs in the flash image 56*49ef7e06SGarrett D'Amore intended to house code and tables for the satellite cpus*/ 57*49ef7e06SGarrett D'Amore /*thanks to random.org for:*/ 58*49ef7e06SGarrett D'Amore #define BLOBS_HEADER_MAGIC (0xBDA3BBD4) 59*49ef7e06SGarrett D'Amore #define BLOB_HEADER_MAGIC (0xA1478A91) 60*49ef7e06SGarrett D'Amore 61*49ef7e06SGarrett D'Amore typedef struct blobs_hdr_s { /* GENERATED BY scripts/genfwdef */ 62*49ef7e06SGarrett D'Amore efx_dword_t magic; 63*49ef7e06SGarrett D'Amore efx_dword_t no_of_blobs; 64*49ef7e06SGarrett D'Amore } blobs_hdr_t; 65*49ef7e06SGarrett D'Amore 66*49ef7e06SGarrett D'Amore typedef struct blob_hdr_s { /* GENERATED BY scripts/genfwdef */ 67*49ef7e06SGarrett D'Amore efx_dword_t magic; 68*49ef7e06SGarrett D'Amore efx_dword_t cpu_type; 69*49ef7e06SGarrett D'Amore efx_dword_t build_variant; 70*49ef7e06SGarrett D'Amore efx_dword_t offset; 71*49ef7e06SGarrett D'Amore efx_dword_t length; 72*49ef7e06SGarrett D'Amore efx_dword_t checksum; 73*49ef7e06SGarrett D'Amore } blob_hdr_t; 74*49ef7e06SGarrett D'Amore 75*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_TXDI_TEXT (0) 76*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_RXDI_TEXT (1) 77*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_TXDP_TEXT (2) 78*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_RXDP_TEXT (3) 79*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_RXHRSL_HR_LUT (4) 80*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_RXHRSL_HR_LUT_CFG (5) 81*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_TXHRSL_HR_LUT (6) 82*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_TXHRSL_HR_LUT_CFG (7) 83*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_RXHRSL_HR_PGM (8) 84*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_RXHRSL_SL_PGM (9) 85*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_TXHRSL_HR_PGM (10) 86*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_TXHRSL_SL_PGM (11) 87*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_RXDI_VTBL0 (12) 88*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_TXDI_VTBL0 (13) 89*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_RXDI_VTBL1 (14) 90*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_TXDI_VTBL1 (15) 91*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_DUMPSPEC (32) 92*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_MC_XIP (33) 93*49ef7e06SGarrett D'Amore 94*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_INVALID (31) 95*49ef7e06SGarrett D'Amore 96*49ef7e06SGarrett D'Amore /* 97*49ef7e06SGarrett D'Amore * The upper four bits of the CPU type field specify the compression 98*49ef7e06SGarrett D'Amore * algorithm used for this blob. 99*49ef7e06SGarrett D'Amore */ 100*49ef7e06SGarrett D'Amore #define BLOB_COMPRESSION_MASK (0xf0000000) 101*49ef7e06SGarrett D'Amore #define BLOB_CPU_TYPE_MASK (0x0fffffff) 102*49ef7e06SGarrett D'Amore 103*49ef7e06SGarrett D'Amore #define BLOB_COMPRESSION_NONE (0x00000000) /* Stored as is */ 104*49ef7e06SGarrett D'Amore #define BLOB_COMPRESSION_LZ (0x10000000) /* see lib/lzdecoder.c */ 105*49ef7e06SGarrett D'Amore 106*49ef7e06SGarrett D'Amore typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */ 107*49ef7e06SGarrett D'Amore efx_dword_t magic; /* = SIENA_MC_BOOT_MAGIC */ 108*49ef7e06SGarrett D'Amore efx_word_t hdr_version; /* this structure definition is version 1 */ 109*49ef7e06SGarrett D'Amore efx_byte_t board_type; 110*49ef7e06SGarrett D'Amore efx_byte_t firmware_version_a; 111*49ef7e06SGarrett D'Amore efx_byte_t firmware_version_b; 112*49ef7e06SGarrett D'Amore efx_byte_t firmware_version_c; 113*49ef7e06SGarrett D'Amore efx_word_t checksum; /* of whole header area + firmware image */ 114*49ef7e06SGarrett D'Amore efx_word_t firmware_version_d; 115*49ef7e06SGarrett D'Amore efx_byte_t mcfw_subtype; 116*49ef7e06SGarrett D'Amore efx_byte_t generation; /* Valid for medford, SBZ for earlier chips */ 117*49ef7e06SGarrett D'Amore efx_dword_t firmware_text_offset; /* offset to firmware .text */ 118*49ef7e06SGarrett D'Amore efx_dword_t firmware_text_size; /* length of firmware .text, in bytes */ 119*49ef7e06SGarrett D'Amore efx_dword_t firmware_data_offset; /* offset to firmware .data */ 120*49ef7e06SGarrett D'Amore efx_dword_t firmware_data_size; /* length of firmware .data, in bytes */ 121*49ef7e06SGarrett D'Amore efx_byte_t spi_rate; /* SPI rate for reading image, 0 is BootROM default */ 122*49ef7e06SGarrett D'Amore efx_byte_t spi_phase_adj; /* SPI SDO/SCL phase adjustment, 0 is default (no adj) */ 123*49ef7e06SGarrett D'Amore efx_word_t xpm_sector; /* The sector that contains the key, or 0xffff if unsigned (medford) SBZ (earlier) */ 124*49ef7e06SGarrett D'Amore efx_dword_t reserved_c[7]; /* (set to 0) */ 125*49ef7e06SGarrett D'Amore } siena_mc_boot_hdr_t; 126*49ef7e06SGarrett D'Amore 127*49ef7e06SGarrett D'Amore #define SIENA_MC_BOOT_HDR_PADDING \ 128*49ef7e06SGarrett D'Amore (SIENA_MC_BOOT_HDR_LEN - sizeof(siena_mc_boot_hdr_t)) 129*49ef7e06SGarrett D'Amore 130*49ef7e06SGarrett D'Amore #define SIENA_MC_STATIC_CONFIG_MAGIC (0xBDCF5555) 131*49ef7e06SGarrett D'Amore #define SIENA_MC_STATIC_CONFIG_VERSION (0) 132*49ef7e06SGarrett D'Amore 133*49ef7e06SGarrett D'Amore typedef struct siena_mc_static_config_hdr_s { /* GENERATED BY scripts/genfwdef */ 134*49ef7e06SGarrett D'Amore efx_dword_t magic; /* = SIENA_MC_STATIC_CONFIG_MAGIC */ 135*49ef7e06SGarrett D'Amore efx_word_t length; /* of header area (i.e. not including VPD) */ 136*49ef7e06SGarrett D'Amore efx_byte_t version; 137*49ef7e06SGarrett D'Amore efx_byte_t csum; /* over header area (i.e. not including VPD) */ 138*49ef7e06SGarrett D'Amore efx_dword_t static_vpd_offset; 139*49ef7e06SGarrett D'Amore efx_dword_t static_vpd_length; 140*49ef7e06SGarrett D'Amore efx_dword_t capabilities; 141*49ef7e06SGarrett D'Amore efx_byte_t mac_addr_base[6]; 142*49ef7e06SGarrett D'Amore efx_byte_t green_mode_cal; /* Green mode calibration result */ 143*49ef7e06SGarrett D'Amore efx_byte_t green_mode_valid; /* Whether cal holds a valid value */ 144*49ef7e06SGarrett D'Amore efx_word_t mac_addr_count; 145*49ef7e06SGarrett D'Amore efx_word_t mac_addr_stride; 146*49ef7e06SGarrett D'Amore efx_word_t calibrated_vref; /* Vref as measured during production */ 147*49ef7e06SGarrett D'Amore efx_word_t adc_vref; /* Vref as read by ADC */ 148*49ef7e06SGarrett D'Amore efx_dword_t reserved2[1]; /* (write as zero) */ 149*49ef7e06SGarrett D'Amore efx_dword_t num_dbi_items; 150*49ef7e06SGarrett D'Amore struct { 151*49ef7e06SGarrett D'Amore efx_word_t addr; 152*49ef7e06SGarrett D'Amore efx_word_t byte_enables; 153*49ef7e06SGarrett D'Amore efx_dword_t value; 154*49ef7e06SGarrett D'Amore } dbi[]; 155*49ef7e06SGarrett D'Amore } siena_mc_static_config_hdr_t; 156*49ef7e06SGarrett D'Amore 157*49ef7e06SGarrett D'Amore #define SIENA_MC_DYNAMIC_CONFIG_MAGIC (0xBDCFDDDD) 158*49ef7e06SGarrett D'Amore #define SIENA_MC_DYNAMIC_CONFIG_VERSION (0) 159*49ef7e06SGarrett D'Amore 160*49ef7e06SGarrett D'Amore typedef struct siena_mc_fw_version_s { /* GENERATED BY scripts/genfwdef */ 161*49ef7e06SGarrett D'Amore efx_dword_t fw_subtype; 162*49ef7e06SGarrett D'Amore efx_word_t version_w; 163*49ef7e06SGarrett D'Amore efx_word_t version_x; 164*49ef7e06SGarrett D'Amore efx_word_t version_y; 165*49ef7e06SGarrett D'Amore efx_word_t version_z; 166*49ef7e06SGarrett D'Amore } siena_mc_fw_version_t; 167*49ef7e06SGarrett D'Amore 168*49ef7e06SGarrett D'Amore typedef struct siena_mc_dynamic_config_hdr_s { /* GENERATED BY scripts/genfwdef */ 169*49ef7e06SGarrett D'Amore efx_dword_t magic; /* = SIENA_MC_DYNAMIC_CONFIG_MAGIC */ 170*49ef7e06SGarrett D'Amore efx_word_t length; /* of header area (i.e. not including VPD) */ 171*49ef7e06SGarrett D'Amore efx_byte_t version; 172*49ef7e06SGarrett D'Amore efx_byte_t csum; /* over header area (i.e. not including VPD) */ 173*49ef7e06SGarrett D'Amore efx_dword_t dynamic_vpd_offset; 174*49ef7e06SGarrett D'Amore efx_dword_t dynamic_vpd_length; 175*49ef7e06SGarrett D'Amore efx_dword_t num_fw_version_items; 176*49ef7e06SGarrett D'Amore siena_mc_fw_version_t fw_version[]; 177*49ef7e06SGarrett D'Amore } siena_mc_dynamic_config_hdr_t; 178*49ef7e06SGarrett D'Amore 179*49ef7e06SGarrett D'Amore #define SIENA_MC_EXPROM_SINGLE_MAGIC (0xAA55) /* little-endian uint16_t */ 180*49ef7e06SGarrett D'Amore 181*49ef7e06SGarrett D'Amore #define SIENA_MC_EXPROM_COMBO_MAGIC (0xB0070102) /* little-endian uint32_t */ 182*49ef7e06SGarrett D'Amore #define SIENA_MC_EXPROM_COMBO_V2_MAGIC (0xB0070103) /* little-endian uint32_t */ 183*49ef7e06SGarrett D'Amore 184*49ef7e06SGarrett D'Amore typedef struct siena_mc_combo_rom_hdr_s { /* GENERATED BY scripts/genfwdef */ 185*49ef7e06SGarrett D'Amore efx_dword_t magic; /* = SIENA_MC_EXPROM_COMBO_MAGIC or SIENA_MC_EXPROM_COMBO_V2_MAGIC */ 186*49ef7e06SGarrett D'Amore union { 187*49ef7e06SGarrett D'Amore struct { 188*49ef7e06SGarrett D'Amore efx_dword_t len1; /* length of first image */ 189*49ef7e06SGarrett D'Amore efx_dword_t len2; /* length of second image */ 190*49ef7e06SGarrett D'Amore efx_dword_t off1; /* offset of first byte to edit to combine images */ 191*49ef7e06SGarrett D'Amore efx_dword_t off2; /* offset of second byte to edit to combine images */ 192*49ef7e06SGarrett D'Amore efx_word_t infoblk0_off;/* infoblk offset */ 193*49ef7e06SGarrett D'Amore efx_word_t infoblk1_off;/* infoblk offset */ 194*49ef7e06SGarrett D'Amore efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */ 195*49ef7e06SGarrett D'Amore efx_byte_t reserved[7];/* (set to 0) */ 196*49ef7e06SGarrett D'Amore } v1; 197*49ef7e06SGarrett D'Amore struct { 198*49ef7e06SGarrett D'Amore efx_dword_t len1; /* length of first image */ 199*49ef7e06SGarrett D'Amore efx_dword_t len2; /* length of second image */ 200*49ef7e06SGarrett D'Amore efx_dword_t off1; /* offset of first byte to edit to combine images */ 201*49ef7e06SGarrett D'Amore efx_dword_t off2; /* offset of second byte to edit to combine images */ 202*49ef7e06SGarrett D'Amore efx_word_t infoblk_off;/* infoblk start offset */ 203*49ef7e06SGarrett D'Amore efx_word_t infoblk_count;/* infoblk count */ 204*49ef7e06SGarrett D'Amore efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */ 205*49ef7e06SGarrett D'Amore efx_byte_t reserved[7];/* (set to 0) */ 206*49ef7e06SGarrett D'Amore } v2; 207*49ef7e06SGarrett D'Amore } data; 208*49ef7e06SGarrett D'Amore } siena_mc_combo_rom_hdr_t; 209*49ef7e06SGarrett D'Amore 210*49ef7e06SGarrett D'Amore #pragma pack() 211*49ef7e06SGarrett D'Amore 212*49ef7e06SGarrett D'Amore #endif /* _SYS_SIENA_FLASH_H */ 213