1*49ef7e06SGarrett D'Amore /*
2*49ef7e06SGarrett D'Amore * Copyright (c) 2015 Solarflare Communications Inc.
3*49ef7e06SGarrett D'Amore * All rights reserved.
4*49ef7e06SGarrett D'Amore *
5*49ef7e06SGarrett D'Amore * Redistribution and use in source and binary forms, with or without
6*49ef7e06SGarrett D'Amore * modification, are permitted provided that the following conditions are met:
7*49ef7e06SGarrett D'Amore *
8*49ef7e06SGarrett D'Amore * 1. Redistributions of source code must retain the above copyright notice,
9*49ef7e06SGarrett D'Amore * this list of conditions and the following disclaimer.
10*49ef7e06SGarrett D'Amore * 2. Redistributions in binary form must reproduce the above copyright notice,
11*49ef7e06SGarrett D'Amore * this list of conditions and the following disclaimer in the documentation
12*49ef7e06SGarrett D'Amore * and/or other materials provided with the distribution.
13*49ef7e06SGarrett D'Amore *
14*49ef7e06SGarrett D'Amore * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15*49ef7e06SGarrett D'Amore * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16*49ef7e06SGarrett D'Amore * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17*49ef7e06SGarrett D'Amore * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18*49ef7e06SGarrett D'Amore * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19*49ef7e06SGarrett D'Amore * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20*49ef7e06SGarrett D'Amore * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21*49ef7e06SGarrett D'Amore * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22*49ef7e06SGarrett D'Amore * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23*49ef7e06SGarrett D'Amore * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24*49ef7e06SGarrett D'Amore * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25*49ef7e06SGarrett D'Amore *
26*49ef7e06SGarrett D'Amore * The views and conclusions contained in the software and documentation are
27*49ef7e06SGarrett D'Amore * those of the authors and should not be interpreted as representing official
28*49ef7e06SGarrett D'Amore * policies, either expressed or implied, of the FreeBSD Project.
29*49ef7e06SGarrett D'Amore */
30*49ef7e06SGarrett D'Amore
31*49ef7e06SGarrett D'Amore #include "efx.h"
32*49ef7e06SGarrett D'Amore #include "efx_impl.h"
33*49ef7e06SGarrett D'Amore
34*49ef7e06SGarrett D'Amore
35*49ef7e06SGarrett D'Amore #if EFSYS_OPT_MEDFORD
36*49ef7e06SGarrett D'Amore
37*49ef7e06SGarrett D'Amore static __checkReturn efx_rc_t
efx_mcdi_get_rxdp_config(__in efx_nic_t * enp,__out uint32_t * end_paddingp)38*49ef7e06SGarrett D'Amore efx_mcdi_get_rxdp_config(
39*49ef7e06SGarrett D'Amore __in efx_nic_t *enp,
40*49ef7e06SGarrett D'Amore __out uint32_t *end_paddingp)
41*49ef7e06SGarrett D'Amore {
42*49ef7e06SGarrett D'Amore efx_mcdi_req_t req;
43*49ef7e06SGarrett D'Amore uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
44*49ef7e06SGarrett D'Amore MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
45*49ef7e06SGarrett D'Amore uint32_t end_padding;
46*49ef7e06SGarrett D'Amore efx_rc_t rc;
47*49ef7e06SGarrett D'Amore
48*49ef7e06SGarrett D'Amore (void) memset(payload, 0, sizeof (payload));
49*49ef7e06SGarrett D'Amore req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
50*49ef7e06SGarrett D'Amore req.emr_in_buf = payload;
51*49ef7e06SGarrett D'Amore req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
52*49ef7e06SGarrett D'Amore req.emr_out_buf = payload;
53*49ef7e06SGarrett D'Amore req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
54*49ef7e06SGarrett D'Amore
55*49ef7e06SGarrett D'Amore efx_mcdi_execute(enp, &req);
56*49ef7e06SGarrett D'Amore if (req.emr_rc != 0) {
57*49ef7e06SGarrett D'Amore rc = req.emr_rc;
58*49ef7e06SGarrett D'Amore goto fail1;
59*49ef7e06SGarrett D'Amore }
60*49ef7e06SGarrett D'Amore
61*49ef7e06SGarrett D'Amore if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
62*49ef7e06SGarrett D'Amore GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
63*49ef7e06SGarrett D'Amore /* RX DMA end padding is disabled */
64*49ef7e06SGarrett D'Amore end_padding = 0;
65*49ef7e06SGarrett D'Amore } else {
66*49ef7e06SGarrett D'Amore switch(MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
67*49ef7e06SGarrett D'Amore GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
68*49ef7e06SGarrett D'Amore case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
69*49ef7e06SGarrett D'Amore end_padding = 64;
70*49ef7e06SGarrett D'Amore break;
71*49ef7e06SGarrett D'Amore case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
72*49ef7e06SGarrett D'Amore end_padding = 128;
73*49ef7e06SGarrett D'Amore break;
74*49ef7e06SGarrett D'Amore case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
75*49ef7e06SGarrett D'Amore end_padding = 256;
76*49ef7e06SGarrett D'Amore break;
77*49ef7e06SGarrett D'Amore default:
78*49ef7e06SGarrett D'Amore rc = ENOTSUP;
79*49ef7e06SGarrett D'Amore goto fail2;
80*49ef7e06SGarrett D'Amore }
81*49ef7e06SGarrett D'Amore }
82*49ef7e06SGarrett D'Amore
83*49ef7e06SGarrett D'Amore *end_paddingp = end_padding;
84*49ef7e06SGarrett D'Amore
85*49ef7e06SGarrett D'Amore return (0);
86*49ef7e06SGarrett D'Amore
87*49ef7e06SGarrett D'Amore fail2:
88*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail2);
89*49ef7e06SGarrett D'Amore fail1:
90*49ef7e06SGarrett D'Amore EFSYS_PROBE1(fail1, efx_rc_t, rc);
91*49ef7e06SGarrett D'Amore
92*49ef7e06SGarrett D'Amore return (rc);
93*49ef7e06SGarrett D'Amore }
94*49ef7e06SGarrett D'Amore
95*49ef7e06SGarrett D'Amore __checkReturn efx_rc_t
medford_board_cfg(__in efx_nic_t * enp)96*49ef7e06SGarrett D'Amore medford_board_cfg(
97*49ef7e06SGarrett D'Amore __in efx_nic_t *enp)
98*49ef7e06SGarrett D'Amore {
99*49ef7e06SGarrett D'Amore efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
100*49ef7e06SGarrett D'Amore efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
101*49ef7e06SGarrett D'Amore uint8_t mac_addr[6] = { 0 };
102*49ef7e06SGarrett D'Amore uint32_t board_type = 0;
103*49ef7e06SGarrett D'Amore ef10_link_state_t els;
104*49ef7e06SGarrett D'Amore efx_port_t *epp = &(enp->en_port);
105*49ef7e06SGarrett D'Amore uint32_t port;
106*49ef7e06SGarrett D'Amore uint32_t pf;
107*49ef7e06SGarrett D'Amore uint32_t vf;
108*49ef7e06SGarrett D'Amore uint32_t mask;
109*49ef7e06SGarrett D'Amore uint32_t sysclk;
110*49ef7e06SGarrett D'Amore uint32_t base, nvec;
111*49ef7e06SGarrett D'Amore uint32_t end_padding;
112*49ef7e06SGarrett D'Amore efx_rc_t rc;
113*49ef7e06SGarrett D'Amore
114*49ef7e06SGarrett D'Amore /*
115*49ef7e06SGarrett D'Amore * FIXME: Likely to be incomplete and incorrect.
116*49ef7e06SGarrett D'Amore * Parts of this should be shared with Huntington.
117*49ef7e06SGarrett D'Amore */
118*49ef7e06SGarrett D'Amore
119*49ef7e06SGarrett D'Amore if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
120*49ef7e06SGarrett D'Amore goto fail1;
121*49ef7e06SGarrett D'Amore
122*49ef7e06SGarrett D'Amore /*
123*49ef7e06SGarrett D'Amore * NOTE: The MCDI protocol numbers ports from zero.
124*49ef7e06SGarrett D'Amore * The common code MCDI interface numbers ports from one.
125*49ef7e06SGarrett D'Amore */
126*49ef7e06SGarrett D'Amore emip->emi_port = port + 1;
127*49ef7e06SGarrett D'Amore
128*49ef7e06SGarrett D'Amore if ((rc = ef10_external_port_mapping(enp, port,
129*49ef7e06SGarrett D'Amore &encp->enc_external_port)) != 0)
130*49ef7e06SGarrett D'Amore goto fail2;
131*49ef7e06SGarrett D'Amore
132*49ef7e06SGarrett D'Amore /*
133*49ef7e06SGarrett D'Amore * Get PCIe function number from firmware (used for
134*49ef7e06SGarrett D'Amore * per-function privilege and dynamic config info).
135*49ef7e06SGarrett D'Amore * - PCIe PF: pf = PF number, vf = 0xffff.
136*49ef7e06SGarrett D'Amore * - PCIe VF: pf = parent PF, vf = VF number.
137*49ef7e06SGarrett D'Amore */
138*49ef7e06SGarrett D'Amore if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
139*49ef7e06SGarrett D'Amore goto fail3;
140*49ef7e06SGarrett D'Amore
141*49ef7e06SGarrett D'Amore encp->enc_pf = pf;
142*49ef7e06SGarrett D'Amore encp->enc_vf = vf;
143*49ef7e06SGarrett D'Amore
144*49ef7e06SGarrett D'Amore /* MAC address for this function */
145*49ef7e06SGarrett D'Amore if (EFX_PCI_FUNCTION_IS_PF(encp)) {
146*49ef7e06SGarrett D'Amore rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
147*49ef7e06SGarrett D'Amore if ((rc == 0) && (mac_addr[0] & 0x02)) {
148*49ef7e06SGarrett D'Amore /*
149*49ef7e06SGarrett D'Amore * If the static config does not include a global MAC
150*49ef7e06SGarrett D'Amore * address pool then the board may return a locally
151*49ef7e06SGarrett D'Amore * administered MAC address (this should only happen on
152*49ef7e06SGarrett D'Amore * incorrectly programmed boards).
153*49ef7e06SGarrett D'Amore */
154*49ef7e06SGarrett D'Amore rc = EINVAL;
155*49ef7e06SGarrett D'Amore }
156*49ef7e06SGarrett D'Amore } else {
157*49ef7e06SGarrett D'Amore rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
158*49ef7e06SGarrett D'Amore }
159*49ef7e06SGarrett D'Amore if (rc != 0)
160*49ef7e06SGarrett D'Amore goto fail4;
161*49ef7e06SGarrett D'Amore
162*49ef7e06SGarrett D'Amore EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
163*49ef7e06SGarrett D'Amore
164*49ef7e06SGarrett D'Amore /* Board configuration */
165*49ef7e06SGarrett D'Amore rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
166*49ef7e06SGarrett D'Amore if (rc != 0) {
167*49ef7e06SGarrett D'Amore /* Unprivileged functions may not be able to read board cfg */
168*49ef7e06SGarrett D'Amore if (rc == EACCES)
169*49ef7e06SGarrett D'Amore board_type = 0;
170*49ef7e06SGarrett D'Amore else
171*49ef7e06SGarrett D'Amore goto fail5;
172*49ef7e06SGarrett D'Amore }
173*49ef7e06SGarrett D'Amore
174*49ef7e06SGarrett D'Amore encp->enc_board_type = board_type;
175*49ef7e06SGarrett D'Amore encp->enc_clk_mult = 1; /* not used for Medford */
176*49ef7e06SGarrett D'Amore
177*49ef7e06SGarrett D'Amore /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
178*49ef7e06SGarrett D'Amore if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
179*49ef7e06SGarrett D'Amore goto fail6;
180*49ef7e06SGarrett D'Amore
181*49ef7e06SGarrett D'Amore /* Obtain the default PHY advertised capabilities */
182*49ef7e06SGarrett D'Amore if ((rc = ef10_phy_get_link(enp, &els)) != 0)
183*49ef7e06SGarrett D'Amore goto fail7;
184*49ef7e06SGarrett D'Amore epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
185*49ef7e06SGarrett D'Amore epp->ep_adv_cap_mask = els.els_adv_cap_mask;
186*49ef7e06SGarrett D'Amore
187*49ef7e06SGarrett D'Amore if (EFX_PCI_FUNCTION_IS_VF(encp)) {
188*49ef7e06SGarrett D'Amore /*
189*49ef7e06SGarrett D'Amore * Interrupt testing does not work for VFs. See bug50084.
190*49ef7e06SGarrett D'Amore * FIXME: Does this still apply to Medford?
191*49ef7e06SGarrett D'Amore */
192*49ef7e06SGarrett D'Amore encp->enc_bug41750_workaround = B_TRUE;
193*49ef7e06SGarrett D'Amore }
194*49ef7e06SGarrett D'Amore
195*49ef7e06SGarrett D'Amore /* Chained multicast is always enabled on Medford */
196*49ef7e06SGarrett D'Amore encp->enc_bug26807_workaround = B_TRUE;
197*49ef7e06SGarrett D'Amore
198*49ef7e06SGarrett D'Amore /* Get sysclk frequency (in MHz). */
199*49ef7e06SGarrett D'Amore if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
200*49ef7e06SGarrett D'Amore goto fail8;
201*49ef7e06SGarrett D'Amore
202*49ef7e06SGarrett D'Amore /*
203*49ef7e06SGarrett D'Amore * The timer quantum is 1536 sysclk cycles, documented for the
204*49ef7e06SGarrett D'Amore * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
205*49ef7e06SGarrett D'Amore */
206*49ef7e06SGarrett D'Amore encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
207*49ef7e06SGarrett D'Amore encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
208*49ef7e06SGarrett D'Amore FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
209*49ef7e06SGarrett D'Amore
210*49ef7e06SGarrett D'Amore /* Check capabilities of running datapath firmware */
211*49ef7e06SGarrett D'Amore if ((rc = ef10_get_datapath_caps(enp)) != 0)
212*49ef7e06SGarrett D'Amore goto fail9;
213*49ef7e06SGarrett D'Amore
214*49ef7e06SGarrett D'Amore /* Alignment for receive packet DMA buffers */
215*49ef7e06SGarrett D'Amore encp->enc_rx_buf_align_start = 1;
216*49ef7e06SGarrett D'Amore
217*49ef7e06SGarrett D'Amore /* Get the RX DMA end padding alignment configuration */
218*49ef7e06SGarrett D'Amore if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0)
219*49ef7e06SGarrett D'Amore goto fail10;
220*49ef7e06SGarrett D'Amore encp->enc_rx_buf_align_end = end_padding;
221*49ef7e06SGarrett D'Amore
222*49ef7e06SGarrett D'Amore /* Alignment for WPTR updates */
223*49ef7e06SGarrett D'Amore encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
224*49ef7e06SGarrett D'Amore
225*49ef7e06SGarrett D'Amore /*
226*49ef7e06SGarrett D'Amore * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
227*49ef7e06SGarrett D'Amore * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
228*49ef7e06SGarrett D'Amore * resources (allocated to this PCIe function), which is zero until
229*49ef7e06SGarrett D'Amore * after we have allocated VIs.
230*49ef7e06SGarrett D'Amore */
231*49ef7e06SGarrett D'Amore encp->enc_evq_limit = 1024;
232*49ef7e06SGarrett D'Amore encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
233*49ef7e06SGarrett D'Amore encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
234*49ef7e06SGarrett D'Amore
235*49ef7e06SGarrett D'Amore encp->enc_buftbl_limit = 0xFFFFFFFF;
236*49ef7e06SGarrett D'Amore
237*49ef7e06SGarrett D'Amore encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
238*49ef7e06SGarrett D'Amore encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
239*49ef7e06SGarrett D'Amore encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
240*49ef7e06SGarrett D'Amore
241*49ef7e06SGarrett D'Amore /*
242*49ef7e06SGarrett D'Amore * Get the current privilege mask. Note that this may be modified
243*49ef7e06SGarrett D'Amore * dynamically, so this value is informational only. DO NOT use
244*49ef7e06SGarrett D'Amore * the privilege mask to check for sufficient privileges, as that
245*49ef7e06SGarrett D'Amore * can result in time-of-check/time-of-use bugs.
246*49ef7e06SGarrett D'Amore */
247*49ef7e06SGarrett D'Amore if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
248*49ef7e06SGarrett D'Amore goto fail11;
249*49ef7e06SGarrett D'Amore encp->enc_privilege_mask = mask;
250*49ef7e06SGarrett D'Amore
251*49ef7e06SGarrett D'Amore /* Get interrupt vector limits */
252*49ef7e06SGarrett D'Amore if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
253*49ef7e06SGarrett D'Amore if (EFX_PCI_FUNCTION_IS_PF(encp))
254*49ef7e06SGarrett D'Amore goto fail12;
255*49ef7e06SGarrett D'Amore
256*49ef7e06SGarrett D'Amore /* Ignore error (cannot query vector limits from a VF). */
257*49ef7e06SGarrett D'Amore base = 0;
258*49ef7e06SGarrett D'Amore nvec = 1024;
259*49ef7e06SGarrett D'Amore }
260*49ef7e06SGarrett D'Amore encp->enc_intr_vec_base = base;
261*49ef7e06SGarrett D'Amore encp->enc_intr_limit = nvec;
262*49ef7e06SGarrett D'Amore
263*49ef7e06SGarrett D'Amore /*
264*49ef7e06SGarrett D'Amore * Maximum number of bytes into the frame the TCP header can start for
265*49ef7e06SGarrett D'Amore * firmware assisted TSO to work.
266*49ef7e06SGarrett D'Amore */
267*49ef7e06SGarrett D'Amore encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
268*49ef7e06SGarrett D'Amore
269*49ef7e06SGarrett D'Amore /*
270*49ef7e06SGarrett D'Amore * Medford stores a single global copy of VPD, not per-PF as on
271*49ef7e06SGarrett D'Amore * Huntington.
272*49ef7e06SGarrett D'Amore */
273*49ef7e06SGarrett D'Amore encp->enc_vpd_is_global = B_TRUE;
274*49ef7e06SGarrett D'Amore
275*49ef7e06SGarrett D'Amore return (0);
276*49ef7e06SGarrett D'Amore
277*49ef7e06SGarrett D'Amore fail12:
278*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail12);
279*49ef7e06SGarrett D'Amore fail11:
280*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail11);
281*49ef7e06SGarrett D'Amore fail10:
282*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail10);
283*49ef7e06SGarrett D'Amore fail9:
284*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail9);
285*49ef7e06SGarrett D'Amore fail8:
286*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail8);
287*49ef7e06SGarrett D'Amore fail7:
288*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail7);
289*49ef7e06SGarrett D'Amore fail6:
290*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail6);
291*49ef7e06SGarrett D'Amore fail5:
292*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail5);
293*49ef7e06SGarrett D'Amore fail4:
294*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail4);
295*49ef7e06SGarrett D'Amore fail3:
296*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail3);
297*49ef7e06SGarrett D'Amore fail2:
298*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail2);
299*49ef7e06SGarrett D'Amore fail1:
300*49ef7e06SGarrett D'Amore EFSYS_PROBE1(fail1, efx_rc_t, rc);
301*49ef7e06SGarrett D'Amore
302*49ef7e06SGarrett D'Amore return (rc);
303*49ef7e06SGarrett D'Amore }
304*49ef7e06SGarrett D'Amore
305*49ef7e06SGarrett D'Amore #endif /* EFSYS_OPT_MEDFORD */
306