1*49ef7e06SGarrett D'Amore /*
2*49ef7e06SGarrett D'Amore * Copyright (c) 2012-2015 Solarflare Communications Inc.
3*49ef7e06SGarrett D'Amore * All rights reserved.
4*49ef7e06SGarrett D'Amore *
5*49ef7e06SGarrett D'Amore * Redistribution and use in source and binary forms, with or without
6*49ef7e06SGarrett D'Amore * modification, are permitted provided that the following conditions are met:
7*49ef7e06SGarrett D'Amore *
8*49ef7e06SGarrett D'Amore * 1. Redistributions of source code must retain the above copyright notice,
9*49ef7e06SGarrett D'Amore * this list of conditions and the following disclaimer.
10*49ef7e06SGarrett D'Amore * 2. Redistributions in binary form must reproduce the above copyright notice,
11*49ef7e06SGarrett D'Amore * this list of conditions and the following disclaimer in the documentation
12*49ef7e06SGarrett D'Amore * and/or other materials provided with the distribution.
13*49ef7e06SGarrett D'Amore *
14*49ef7e06SGarrett D'Amore * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15*49ef7e06SGarrett D'Amore * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16*49ef7e06SGarrett D'Amore * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17*49ef7e06SGarrett D'Amore * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18*49ef7e06SGarrett D'Amore * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19*49ef7e06SGarrett D'Amore * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20*49ef7e06SGarrett D'Amore * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21*49ef7e06SGarrett D'Amore * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22*49ef7e06SGarrett D'Amore * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23*49ef7e06SGarrett D'Amore * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24*49ef7e06SGarrett D'Amore * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25*49ef7e06SGarrett D'Amore *
26*49ef7e06SGarrett D'Amore * The views and conclusions contained in the software and documentation are
27*49ef7e06SGarrett D'Amore * those of the authors and should not be interpreted as representing official
28*49ef7e06SGarrett D'Amore * policies, either expressed or implied, of the FreeBSD Project.
29*49ef7e06SGarrett D'Amore */
30*49ef7e06SGarrett D'Amore
31*49ef7e06SGarrett D'Amore #include "efx.h"
32*49ef7e06SGarrett D'Amore #include "efx_impl.h"
33*49ef7e06SGarrett D'Amore #if EFSYS_OPT_MON_STATS
34*49ef7e06SGarrett D'Amore #include "mcdi_mon.h"
35*49ef7e06SGarrett D'Amore #endif
36*49ef7e06SGarrett D'Amore
37*49ef7e06SGarrett D'Amore #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
38*49ef7e06SGarrett D'Amore
39*49ef7e06SGarrett D'Amore #if EFSYS_OPT_QSTATS
40*49ef7e06SGarrett D'Amore #define EFX_EV_QSTAT_INCR(_eep, _stat) \
41*49ef7e06SGarrett D'Amore do { \
42*49ef7e06SGarrett D'Amore (_eep)->ee_stat[_stat]++; \
43*49ef7e06SGarrett D'Amore _NOTE(CONSTANTCONDITION) \
44*49ef7e06SGarrett D'Amore } while (B_FALSE)
45*49ef7e06SGarrett D'Amore #else
46*49ef7e06SGarrett D'Amore #define EFX_EV_QSTAT_INCR(_eep, _stat)
47*49ef7e06SGarrett D'Amore #endif
48*49ef7e06SGarrett D'Amore
49*49ef7e06SGarrett D'Amore
50*49ef7e06SGarrett D'Amore static __checkReturn boolean_t
51*49ef7e06SGarrett D'Amore ef10_ev_rx(
52*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
53*49ef7e06SGarrett D'Amore __in efx_qword_t *eqp,
54*49ef7e06SGarrett D'Amore __in const efx_ev_callbacks_t *eecp,
55*49ef7e06SGarrett D'Amore __in_opt void *arg);
56*49ef7e06SGarrett D'Amore
57*49ef7e06SGarrett D'Amore static __checkReturn boolean_t
58*49ef7e06SGarrett D'Amore ef10_ev_tx(
59*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
60*49ef7e06SGarrett D'Amore __in efx_qword_t *eqp,
61*49ef7e06SGarrett D'Amore __in const efx_ev_callbacks_t *eecp,
62*49ef7e06SGarrett D'Amore __in_opt void *arg);
63*49ef7e06SGarrett D'Amore
64*49ef7e06SGarrett D'Amore static __checkReturn boolean_t
65*49ef7e06SGarrett D'Amore ef10_ev_driver(
66*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
67*49ef7e06SGarrett D'Amore __in efx_qword_t *eqp,
68*49ef7e06SGarrett D'Amore __in const efx_ev_callbacks_t *eecp,
69*49ef7e06SGarrett D'Amore __in_opt void *arg);
70*49ef7e06SGarrett D'Amore
71*49ef7e06SGarrett D'Amore static __checkReturn boolean_t
72*49ef7e06SGarrett D'Amore ef10_ev_drv_gen(
73*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
74*49ef7e06SGarrett D'Amore __in efx_qword_t *eqp,
75*49ef7e06SGarrett D'Amore __in const efx_ev_callbacks_t *eecp,
76*49ef7e06SGarrett D'Amore __in_opt void *arg);
77*49ef7e06SGarrett D'Amore
78*49ef7e06SGarrett D'Amore static __checkReturn boolean_t
79*49ef7e06SGarrett D'Amore ef10_ev_mcdi(
80*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
81*49ef7e06SGarrett D'Amore __in efx_qword_t *eqp,
82*49ef7e06SGarrett D'Amore __in const efx_ev_callbacks_t *eecp,
83*49ef7e06SGarrett D'Amore __in_opt void *arg);
84*49ef7e06SGarrett D'Amore
85*49ef7e06SGarrett D'Amore
86*49ef7e06SGarrett D'Amore static __checkReturn efx_rc_t
efx_mcdi_init_evq(__in efx_nic_t * enp,__in unsigned int instance,__in efsys_mem_t * esmp,__in size_t nevs,__in uint32_t irq,__out_opt uint32_t * irqp)87*49ef7e06SGarrett D'Amore efx_mcdi_init_evq(
88*49ef7e06SGarrett D'Amore __in efx_nic_t *enp,
89*49ef7e06SGarrett D'Amore __in unsigned int instance,
90*49ef7e06SGarrett D'Amore __in efsys_mem_t *esmp,
91*49ef7e06SGarrett D'Amore __in size_t nevs,
92*49ef7e06SGarrett D'Amore __in uint32_t irq,
93*49ef7e06SGarrett D'Amore __out_opt uint32_t *irqp)
94*49ef7e06SGarrett D'Amore {
95*49ef7e06SGarrett D'Amore efx_mcdi_req_t req;
96*49ef7e06SGarrett D'Amore uint8_t payload[
97*49ef7e06SGarrett D'Amore MAX(MC_CMD_INIT_EVQ_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
98*49ef7e06SGarrett D'Amore MC_CMD_INIT_EVQ_OUT_LEN)];
99*49ef7e06SGarrett D'Amore efx_qword_t *dma_addr;
100*49ef7e06SGarrett D'Amore uint64_t addr;
101*49ef7e06SGarrett D'Amore int npages;
102*49ef7e06SGarrett D'Amore int i;
103*49ef7e06SGarrett D'Amore int supports_rx_batching;
104*49ef7e06SGarrett D'Amore efx_rc_t rc;
105*49ef7e06SGarrett D'Amore
106*49ef7e06SGarrett D'Amore npages = EFX_EVQ_NBUFS(nevs);
107*49ef7e06SGarrett D'Amore if (MC_CMD_INIT_EVQ_IN_LEN(npages) > MC_CMD_INIT_EVQ_IN_LENMAX) {
108*49ef7e06SGarrett D'Amore rc = EINVAL;
109*49ef7e06SGarrett D'Amore goto fail1;
110*49ef7e06SGarrett D'Amore }
111*49ef7e06SGarrett D'Amore
112*49ef7e06SGarrett D'Amore (void) memset(payload, 0, sizeof (payload));
113*49ef7e06SGarrett D'Amore req.emr_cmd = MC_CMD_INIT_EVQ;
114*49ef7e06SGarrett D'Amore req.emr_in_buf = payload;
115*49ef7e06SGarrett D'Amore req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages);
116*49ef7e06SGarrett D'Amore req.emr_out_buf = payload;
117*49ef7e06SGarrett D'Amore req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN;
118*49ef7e06SGarrett D'Amore
119*49ef7e06SGarrett D'Amore MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs);
120*49ef7e06SGarrett D'Amore MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance);
121*49ef7e06SGarrett D'Amore MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq);
122*49ef7e06SGarrett D'Amore
123*49ef7e06SGarrett D'Amore /*
124*49ef7e06SGarrett D'Amore * On Huntington RX and TX event batching can only be requested
125*49ef7e06SGarrett D'Amore * together (even if the datapath firmware doesn't actually support RX
126*49ef7e06SGarrett D'Amore * batching).
127*49ef7e06SGarrett D'Amore * Cut through is incompatible with RX batching and so enabling cut
128*49ef7e06SGarrett D'Amore * through disables RX batching (but it does not affect TX batching).
129*49ef7e06SGarrett D'Amore *
130*49ef7e06SGarrett D'Amore * So always enable RX and TX event batching, and enable cut through
131*49ef7e06SGarrett D'Amore * if RX event batching isn't supported (i.e. on low latency firmware).
132*49ef7e06SGarrett D'Amore */
133*49ef7e06SGarrett D'Amore supports_rx_batching = enp->en_nic_cfg.enc_rx_batching_enabled ? 1 : 0;
134*49ef7e06SGarrett D'Amore MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS,
135*49ef7e06SGarrett D'Amore INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
136*49ef7e06SGarrett D'Amore INIT_EVQ_IN_FLAG_RPTR_DOS, 0,
137*49ef7e06SGarrett D'Amore INIT_EVQ_IN_FLAG_INT_ARMD, 0,
138*49ef7e06SGarrett D'Amore INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_batching,
139*49ef7e06SGarrett D'Amore INIT_EVQ_IN_FLAG_RX_MERGE, 1,
140*49ef7e06SGarrett D'Amore INIT_EVQ_IN_FLAG_TX_MERGE, 1);
141*49ef7e06SGarrett D'Amore
142*49ef7e06SGarrett D'Amore MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
143*49ef7e06SGarrett D'Amore MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
144*49ef7e06SGarrett D'Amore MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0);
145*49ef7e06SGarrett D'Amore MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0);
146*49ef7e06SGarrett D'Amore
147*49ef7e06SGarrett D'Amore MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE,
148*49ef7e06SGarrett D'Amore MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
149*49ef7e06SGarrett D'Amore MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0);
150*49ef7e06SGarrett D'Amore
151*49ef7e06SGarrett D'Amore dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR);
152*49ef7e06SGarrett D'Amore addr = EFSYS_MEM_ADDR(esmp);
153*49ef7e06SGarrett D'Amore
154*49ef7e06SGarrett D'Amore for (i = 0; i < npages; i++) {
155*49ef7e06SGarrett D'Amore EFX_POPULATE_QWORD_2(*dma_addr,
156*49ef7e06SGarrett D'Amore EFX_DWORD_1, (uint32_t)(addr >> 32),
157*49ef7e06SGarrett D'Amore EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
158*49ef7e06SGarrett D'Amore
159*49ef7e06SGarrett D'Amore dma_addr++;
160*49ef7e06SGarrett D'Amore addr += EFX_BUF_SIZE;
161*49ef7e06SGarrett D'Amore }
162*49ef7e06SGarrett D'Amore
163*49ef7e06SGarrett D'Amore efx_mcdi_execute(enp, &req);
164*49ef7e06SGarrett D'Amore
165*49ef7e06SGarrett D'Amore if (req.emr_rc != 0) {
166*49ef7e06SGarrett D'Amore rc = req.emr_rc;
167*49ef7e06SGarrett D'Amore goto fail2;
168*49ef7e06SGarrett D'Amore }
169*49ef7e06SGarrett D'Amore
170*49ef7e06SGarrett D'Amore if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {
171*49ef7e06SGarrett D'Amore rc = EMSGSIZE;
172*49ef7e06SGarrett D'Amore goto fail3;
173*49ef7e06SGarrett D'Amore }
174*49ef7e06SGarrett D'Amore
175*49ef7e06SGarrett D'Amore if (irqp != NULL)
176*49ef7e06SGarrett D'Amore *irqp = MCDI_OUT_DWORD(req, INIT_EVQ_OUT_IRQ);
177*49ef7e06SGarrett D'Amore
178*49ef7e06SGarrett D'Amore return (0);
179*49ef7e06SGarrett D'Amore
180*49ef7e06SGarrett D'Amore fail3:
181*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail3);
182*49ef7e06SGarrett D'Amore fail2:
183*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail2);
184*49ef7e06SGarrett D'Amore fail1:
185*49ef7e06SGarrett D'Amore EFSYS_PROBE1(fail1, efx_rc_t, rc);
186*49ef7e06SGarrett D'Amore
187*49ef7e06SGarrett D'Amore return (rc);
188*49ef7e06SGarrett D'Amore }
189*49ef7e06SGarrett D'Amore
190*49ef7e06SGarrett D'Amore static __checkReturn efx_rc_t
efx_mcdi_fini_evq(__in efx_nic_t * enp,__in uint32_t instance)191*49ef7e06SGarrett D'Amore efx_mcdi_fini_evq(
192*49ef7e06SGarrett D'Amore __in efx_nic_t *enp,
193*49ef7e06SGarrett D'Amore __in uint32_t instance)
194*49ef7e06SGarrett D'Amore {
195*49ef7e06SGarrett D'Amore efx_mcdi_req_t req;
196*49ef7e06SGarrett D'Amore uint8_t payload[MAX(MC_CMD_FINI_EVQ_IN_LEN,
197*49ef7e06SGarrett D'Amore MC_CMD_FINI_EVQ_OUT_LEN)];
198*49ef7e06SGarrett D'Amore efx_rc_t rc;
199*49ef7e06SGarrett D'Amore
200*49ef7e06SGarrett D'Amore (void) memset(payload, 0, sizeof (payload));
201*49ef7e06SGarrett D'Amore req.emr_cmd = MC_CMD_FINI_EVQ;
202*49ef7e06SGarrett D'Amore req.emr_in_buf = payload;
203*49ef7e06SGarrett D'Amore req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN;
204*49ef7e06SGarrett D'Amore req.emr_out_buf = payload;
205*49ef7e06SGarrett D'Amore req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN;
206*49ef7e06SGarrett D'Amore
207*49ef7e06SGarrett D'Amore MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance);
208*49ef7e06SGarrett D'Amore
209*49ef7e06SGarrett D'Amore efx_mcdi_execute(enp, &req);
210*49ef7e06SGarrett D'Amore
211*49ef7e06SGarrett D'Amore if (req.emr_rc != 0) {
212*49ef7e06SGarrett D'Amore rc = req.emr_rc;
213*49ef7e06SGarrett D'Amore goto fail1;
214*49ef7e06SGarrett D'Amore }
215*49ef7e06SGarrett D'Amore
216*49ef7e06SGarrett D'Amore return (0);
217*49ef7e06SGarrett D'Amore
218*49ef7e06SGarrett D'Amore fail1:
219*49ef7e06SGarrett D'Amore EFSYS_PROBE1(fail1, efx_rc_t, rc);
220*49ef7e06SGarrett D'Amore
221*49ef7e06SGarrett D'Amore return (rc);
222*49ef7e06SGarrett D'Amore }
223*49ef7e06SGarrett D'Amore
224*49ef7e06SGarrett D'Amore
225*49ef7e06SGarrett D'Amore
226*49ef7e06SGarrett D'Amore __checkReturn efx_rc_t
ef10_ev_init(__in efx_nic_t * enp)227*49ef7e06SGarrett D'Amore ef10_ev_init(
228*49ef7e06SGarrett D'Amore __in efx_nic_t *enp)
229*49ef7e06SGarrett D'Amore {
230*49ef7e06SGarrett D'Amore _NOTE(ARGUNUSED(enp))
231*49ef7e06SGarrett D'Amore return (0);
232*49ef7e06SGarrett D'Amore }
233*49ef7e06SGarrett D'Amore
234*49ef7e06SGarrett D'Amore void
ef10_ev_fini(__in efx_nic_t * enp)235*49ef7e06SGarrett D'Amore ef10_ev_fini(
236*49ef7e06SGarrett D'Amore __in efx_nic_t *enp)
237*49ef7e06SGarrett D'Amore {
238*49ef7e06SGarrett D'Amore _NOTE(ARGUNUSED(enp))
239*49ef7e06SGarrett D'Amore }
240*49ef7e06SGarrett D'Amore
241*49ef7e06SGarrett D'Amore __checkReturn efx_rc_t
ef10_ev_qcreate(__in efx_nic_t * enp,__in unsigned int index,__in efsys_mem_t * esmp,__in size_t n,__in uint32_t id,__in efx_evq_t * eep)242*49ef7e06SGarrett D'Amore ef10_ev_qcreate(
243*49ef7e06SGarrett D'Amore __in efx_nic_t *enp,
244*49ef7e06SGarrett D'Amore __in unsigned int index,
245*49ef7e06SGarrett D'Amore __in efsys_mem_t *esmp,
246*49ef7e06SGarrett D'Amore __in size_t n,
247*49ef7e06SGarrett D'Amore __in uint32_t id,
248*49ef7e06SGarrett D'Amore __in efx_evq_t *eep)
249*49ef7e06SGarrett D'Amore {
250*49ef7e06SGarrett D'Amore efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
251*49ef7e06SGarrett D'Amore uint32_t irq;
252*49ef7e06SGarrett D'Amore efx_rc_t rc;
253*49ef7e06SGarrett D'Amore
254*49ef7e06SGarrett D'Amore _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
255*49ef7e06SGarrett D'Amore EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
256*49ef7e06SGarrett D'Amore EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
257*49ef7e06SGarrett D'Amore
258*49ef7e06SGarrett D'Amore if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
259*49ef7e06SGarrett D'Amore rc = EINVAL;
260*49ef7e06SGarrett D'Amore goto fail1;
261*49ef7e06SGarrett D'Amore }
262*49ef7e06SGarrett D'Amore
263*49ef7e06SGarrett D'Amore if (index >= encp->enc_evq_limit) {
264*49ef7e06SGarrett D'Amore rc = EINVAL;
265*49ef7e06SGarrett D'Amore goto fail2;
266*49ef7e06SGarrett D'Amore }
267*49ef7e06SGarrett D'Amore
268*49ef7e06SGarrett D'Amore /* Set up the handler table */
269*49ef7e06SGarrett D'Amore eep->ee_rx = ef10_ev_rx;
270*49ef7e06SGarrett D'Amore eep->ee_tx = ef10_ev_tx;
271*49ef7e06SGarrett D'Amore eep->ee_driver = ef10_ev_driver;
272*49ef7e06SGarrett D'Amore eep->ee_drv_gen = ef10_ev_drv_gen;
273*49ef7e06SGarrett D'Amore eep->ee_mcdi = ef10_ev_mcdi;
274*49ef7e06SGarrett D'Amore
275*49ef7e06SGarrett D'Amore /*
276*49ef7e06SGarrett D'Amore * Set up the event queue
277*49ef7e06SGarrett D'Amore * NOTE: ignore the returned IRQ param as firmware does not set it.
278*49ef7e06SGarrett D'Amore */
279*49ef7e06SGarrett D'Amore irq = index; /* INIT_EVQ expects function-relative vector number */
280*49ef7e06SGarrett D'Amore if ((rc = efx_mcdi_init_evq(enp, index, esmp, n, irq, NULL)) != 0)
281*49ef7e06SGarrett D'Amore goto fail3;
282*49ef7e06SGarrett D'Amore
283*49ef7e06SGarrett D'Amore return (0);
284*49ef7e06SGarrett D'Amore
285*49ef7e06SGarrett D'Amore fail3:
286*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail3);
287*49ef7e06SGarrett D'Amore fail2:
288*49ef7e06SGarrett D'Amore EFSYS_PROBE(fail2);
289*49ef7e06SGarrett D'Amore fail1:
290*49ef7e06SGarrett D'Amore EFSYS_PROBE1(fail1, efx_rc_t, rc);
291*49ef7e06SGarrett D'Amore
292*49ef7e06SGarrett D'Amore return (rc);
293*49ef7e06SGarrett D'Amore }
294*49ef7e06SGarrett D'Amore
295*49ef7e06SGarrett D'Amore void
ef10_ev_qdestroy(__in efx_evq_t * eep)296*49ef7e06SGarrett D'Amore ef10_ev_qdestroy(
297*49ef7e06SGarrett D'Amore __in efx_evq_t *eep)
298*49ef7e06SGarrett D'Amore {
299*49ef7e06SGarrett D'Amore efx_nic_t *enp = eep->ee_enp;
300*49ef7e06SGarrett D'Amore
301*49ef7e06SGarrett D'Amore EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
302*49ef7e06SGarrett D'Amore enp->en_family == EFX_FAMILY_MEDFORD);
303*49ef7e06SGarrett D'Amore
304*49ef7e06SGarrett D'Amore (void) efx_mcdi_fini_evq(eep->ee_enp, eep->ee_index);
305*49ef7e06SGarrett D'Amore }
306*49ef7e06SGarrett D'Amore
307*49ef7e06SGarrett D'Amore __checkReturn efx_rc_t
ef10_ev_qprime(__in efx_evq_t * eep,__in unsigned int count)308*49ef7e06SGarrett D'Amore ef10_ev_qprime(
309*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
310*49ef7e06SGarrett D'Amore __in unsigned int count)
311*49ef7e06SGarrett D'Amore {
312*49ef7e06SGarrett D'Amore efx_nic_t *enp = eep->ee_enp;
313*49ef7e06SGarrett D'Amore uint32_t rptr;
314*49ef7e06SGarrett D'Amore efx_dword_t dword;
315*49ef7e06SGarrett D'Amore
316*49ef7e06SGarrett D'Amore rptr = count & eep->ee_mask;
317*49ef7e06SGarrett D'Amore
318*49ef7e06SGarrett D'Amore if (enp->en_nic_cfg.enc_bug35388_workaround) {
319*49ef7e06SGarrett D'Amore EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS >
320*49ef7e06SGarrett D'Amore (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
321*49ef7e06SGarrett D'Amore EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS <
322*49ef7e06SGarrett D'Amore (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
323*49ef7e06SGarrett D'Amore
324*49ef7e06SGarrett D'Amore EFX_POPULATE_DWORD_2(dword,
325*49ef7e06SGarrett D'Amore ERF_DD_EVQ_IND_RPTR_FLAGS,
326*49ef7e06SGarrett D'Amore EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
327*49ef7e06SGarrett D'Amore ERF_DD_EVQ_IND_RPTR,
328*49ef7e06SGarrett D'Amore (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
329*49ef7e06SGarrett D'Amore EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
330*49ef7e06SGarrett D'Amore &dword, B_FALSE);
331*49ef7e06SGarrett D'Amore
332*49ef7e06SGarrett D'Amore EFX_POPULATE_DWORD_2(dword,
333*49ef7e06SGarrett D'Amore ERF_DD_EVQ_IND_RPTR_FLAGS,
334*49ef7e06SGarrett D'Amore EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
335*49ef7e06SGarrett D'Amore ERF_DD_EVQ_IND_RPTR,
336*49ef7e06SGarrett D'Amore rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
337*49ef7e06SGarrett D'Amore EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
338*49ef7e06SGarrett D'Amore &dword, B_FALSE);
339*49ef7e06SGarrett D'Amore } else {
340*49ef7e06SGarrett D'Amore EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
341*49ef7e06SGarrett D'Amore EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
342*49ef7e06SGarrett D'Amore &dword, B_FALSE);
343*49ef7e06SGarrett D'Amore }
344*49ef7e06SGarrett D'Amore
345*49ef7e06SGarrett D'Amore return (0);
346*49ef7e06SGarrett D'Amore }
347*49ef7e06SGarrett D'Amore
348*49ef7e06SGarrett D'Amore static __checkReturn efx_rc_t
efx_mcdi_driver_event(__in efx_nic_t * enp,__in uint32_t evq,__in efx_qword_t data)349*49ef7e06SGarrett D'Amore efx_mcdi_driver_event(
350*49ef7e06SGarrett D'Amore __in efx_nic_t *enp,
351*49ef7e06SGarrett D'Amore __in uint32_t evq,
352*49ef7e06SGarrett D'Amore __in efx_qword_t data)
353*49ef7e06SGarrett D'Amore {
354*49ef7e06SGarrett D'Amore efx_mcdi_req_t req;
355*49ef7e06SGarrett D'Amore uint8_t payload[MAX(MC_CMD_DRIVER_EVENT_IN_LEN,
356*49ef7e06SGarrett D'Amore MC_CMD_DRIVER_EVENT_OUT_LEN)];
357*49ef7e06SGarrett D'Amore efx_rc_t rc;
358*49ef7e06SGarrett D'Amore
359*49ef7e06SGarrett D'Amore req.emr_cmd = MC_CMD_DRIVER_EVENT;
360*49ef7e06SGarrett D'Amore req.emr_in_buf = payload;
361*49ef7e06SGarrett D'Amore req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
362*49ef7e06SGarrett D'Amore req.emr_out_buf = payload;
363*49ef7e06SGarrett D'Amore req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
364*49ef7e06SGarrett D'Amore
365*49ef7e06SGarrett D'Amore MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
366*49ef7e06SGarrett D'Amore
367*49ef7e06SGarrett D'Amore MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
368*49ef7e06SGarrett D'Amore EFX_QWORD_FIELD(data, EFX_DWORD_0));
369*49ef7e06SGarrett D'Amore MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
370*49ef7e06SGarrett D'Amore EFX_QWORD_FIELD(data, EFX_DWORD_1));
371*49ef7e06SGarrett D'Amore
372*49ef7e06SGarrett D'Amore efx_mcdi_execute(enp, &req);
373*49ef7e06SGarrett D'Amore
374*49ef7e06SGarrett D'Amore if (req.emr_rc != 0) {
375*49ef7e06SGarrett D'Amore rc = req.emr_rc;
376*49ef7e06SGarrett D'Amore goto fail1;
377*49ef7e06SGarrett D'Amore }
378*49ef7e06SGarrett D'Amore
379*49ef7e06SGarrett D'Amore return (0);
380*49ef7e06SGarrett D'Amore
381*49ef7e06SGarrett D'Amore fail1:
382*49ef7e06SGarrett D'Amore EFSYS_PROBE1(fail1, efx_rc_t, rc);
383*49ef7e06SGarrett D'Amore
384*49ef7e06SGarrett D'Amore return (rc);
385*49ef7e06SGarrett D'Amore }
386*49ef7e06SGarrett D'Amore
387*49ef7e06SGarrett D'Amore void
ef10_ev_qpost(__in efx_evq_t * eep,__in uint16_t data)388*49ef7e06SGarrett D'Amore ef10_ev_qpost(
389*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
390*49ef7e06SGarrett D'Amore __in uint16_t data)
391*49ef7e06SGarrett D'Amore {
392*49ef7e06SGarrett D'Amore efx_nic_t *enp = eep->ee_enp;
393*49ef7e06SGarrett D'Amore efx_qword_t event;
394*49ef7e06SGarrett D'Amore
395*49ef7e06SGarrett D'Amore EFX_POPULATE_QWORD_3(event,
396*49ef7e06SGarrett D'Amore ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
397*49ef7e06SGarrett D'Amore ESF_DZ_DRV_SUB_CODE, 0,
398*49ef7e06SGarrett D'Amore ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
399*49ef7e06SGarrett D'Amore
400*49ef7e06SGarrett D'Amore (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
401*49ef7e06SGarrett D'Amore }
402*49ef7e06SGarrett D'Amore
403*49ef7e06SGarrett D'Amore __checkReturn efx_rc_t
ef10_ev_qmoderate(__in efx_evq_t * eep,__in unsigned int us)404*49ef7e06SGarrett D'Amore ef10_ev_qmoderate(
405*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
406*49ef7e06SGarrett D'Amore __in unsigned int us)
407*49ef7e06SGarrett D'Amore {
408*49ef7e06SGarrett D'Amore efx_nic_t *enp = eep->ee_enp;
409*49ef7e06SGarrett D'Amore efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
410*49ef7e06SGarrett D'Amore efx_dword_t dword;
411*49ef7e06SGarrett D'Amore uint32_t timer_val, mode;
412*49ef7e06SGarrett D'Amore efx_rc_t rc;
413*49ef7e06SGarrett D'Amore
414*49ef7e06SGarrett D'Amore if (us > encp->enc_evq_timer_max_us) {
415*49ef7e06SGarrett D'Amore rc = EINVAL;
416*49ef7e06SGarrett D'Amore goto fail1;
417*49ef7e06SGarrett D'Amore }
418*49ef7e06SGarrett D'Amore
419*49ef7e06SGarrett D'Amore /* If the value is zero then disable the timer */
420*49ef7e06SGarrett D'Amore if (us == 0) {
421*49ef7e06SGarrett D'Amore timer_val = 0;
422*49ef7e06SGarrett D'Amore mode = FFE_CZ_TIMER_MODE_DIS;
423*49ef7e06SGarrett D'Amore } else {
424*49ef7e06SGarrett D'Amore /* Calculate the timer value in quanta */
425*49ef7e06SGarrett D'Amore timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns;
426*49ef7e06SGarrett D'Amore
427*49ef7e06SGarrett D'Amore /* Moderation value is base 0 so we need to deduct 1 */
428*49ef7e06SGarrett D'Amore if (timer_val > 0)
429*49ef7e06SGarrett D'Amore timer_val--;
430*49ef7e06SGarrett D'Amore
431*49ef7e06SGarrett D'Amore mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
432*49ef7e06SGarrett D'Amore }
433*49ef7e06SGarrett D'Amore
434*49ef7e06SGarrett D'Amore if (encp->enc_bug35388_workaround) {
435*49ef7e06SGarrett D'Amore EFX_POPULATE_DWORD_3(dword,
436*49ef7e06SGarrett D'Amore ERF_DD_EVQ_IND_TIMER_FLAGS,
437*49ef7e06SGarrett D'Amore EFE_DD_EVQ_IND_TIMER_FLAGS,
438*49ef7e06SGarrett D'Amore ERF_DD_EVQ_IND_TIMER_MODE, mode,
439*49ef7e06SGarrett D'Amore ERF_DD_EVQ_IND_TIMER_VAL, timer_val);
440*49ef7e06SGarrett D'Amore EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT,
441*49ef7e06SGarrett D'Amore eep->ee_index, &dword, 0);
442*49ef7e06SGarrett D'Amore } else {
443*49ef7e06SGarrett D'Amore EFX_POPULATE_DWORD_2(dword,
444*49ef7e06SGarrett D'Amore ERF_DZ_TC_TIMER_MODE, mode,
445*49ef7e06SGarrett D'Amore ERF_DZ_TC_TIMER_VAL, timer_val);
446*49ef7e06SGarrett D'Amore EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_TMR_REG,
447*49ef7e06SGarrett D'Amore eep->ee_index, &dword, 0);
448*49ef7e06SGarrett D'Amore }
449*49ef7e06SGarrett D'Amore
450*49ef7e06SGarrett D'Amore return (0);
451*49ef7e06SGarrett D'Amore
452*49ef7e06SGarrett D'Amore fail1:
453*49ef7e06SGarrett D'Amore EFSYS_PROBE1(fail1, efx_rc_t, rc);
454*49ef7e06SGarrett D'Amore
455*49ef7e06SGarrett D'Amore return (rc);
456*49ef7e06SGarrett D'Amore }
457*49ef7e06SGarrett D'Amore
458*49ef7e06SGarrett D'Amore
459*49ef7e06SGarrett D'Amore #if EFSYS_OPT_QSTATS
460*49ef7e06SGarrett D'Amore void
ef10_ev_qstats_update(__in efx_evq_t * eep,__inout_ecount (EV_NQSTATS)efsys_stat_t * stat)461*49ef7e06SGarrett D'Amore ef10_ev_qstats_update(
462*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
463*49ef7e06SGarrett D'Amore __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
464*49ef7e06SGarrett D'Amore {
465*49ef7e06SGarrett D'Amore unsigned int id;
466*49ef7e06SGarrett D'Amore
467*49ef7e06SGarrett D'Amore for (id = 0; id < EV_NQSTATS; id++) {
468*49ef7e06SGarrett D'Amore efsys_stat_t *essp = &stat[id];
469*49ef7e06SGarrett D'Amore
470*49ef7e06SGarrett D'Amore EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
471*49ef7e06SGarrett D'Amore eep->ee_stat[id] = 0;
472*49ef7e06SGarrett D'Amore }
473*49ef7e06SGarrett D'Amore }
474*49ef7e06SGarrett D'Amore #endif /* EFSYS_OPT_QSTATS */
475*49ef7e06SGarrett D'Amore
476*49ef7e06SGarrett D'Amore
477*49ef7e06SGarrett D'Amore static __checkReturn boolean_t
ef10_ev_rx(__in efx_evq_t * eep,__in efx_qword_t * eqp,__in const efx_ev_callbacks_t * eecp,__in_opt void * arg)478*49ef7e06SGarrett D'Amore ef10_ev_rx(
479*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
480*49ef7e06SGarrett D'Amore __in efx_qword_t *eqp,
481*49ef7e06SGarrett D'Amore __in const efx_ev_callbacks_t *eecp,
482*49ef7e06SGarrett D'Amore __in_opt void *arg)
483*49ef7e06SGarrett D'Amore {
484*49ef7e06SGarrett D'Amore efx_nic_t *enp = eep->ee_enp;
485*49ef7e06SGarrett D'Amore uint32_t size;
486*49ef7e06SGarrett D'Amore uint32_t label;
487*49ef7e06SGarrett D'Amore uint32_t mac_class;
488*49ef7e06SGarrett D'Amore uint32_t eth_tag_class;
489*49ef7e06SGarrett D'Amore uint32_t l3_class;
490*49ef7e06SGarrett D'Amore uint32_t l4_class;
491*49ef7e06SGarrett D'Amore uint32_t next_read_lbits;
492*49ef7e06SGarrett D'Amore uint16_t flags;
493*49ef7e06SGarrett D'Amore boolean_t cont;
494*49ef7e06SGarrett D'Amore boolean_t should_abort;
495*49ef7e06SGarrett D'Amore efx_evq_rxq_state_t *eersp;
496*49ef7e06SGarrett D'Amore unsigned int desc_count;
497*49ef7e06SGarrett D'Amore unsigned int last_used_id;
498*49ef7e06SGarrett D'Amore
499*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX);
500*49ef7e06SGarrett D'Amore
501*49ef7e06SGarrett D'Amore /* Discard events after RXQ/TXQ errors */
502*49ef7e06SGarrett D'Amore if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
503*49ef7e06SGarrett D'Amore return (B_FALSE);
504*49ef7e06SGarrett D'Amore
505*49ef7e06SGarrett D'Amore /* Basic packet information */
506*49ef7e06SGarrett D'Amore size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
507*49ef7e06SGarrett D'Amore next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
508*49ef7e06SGarrett D'Amore label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
509*49ef7e06SGarrett D'Amore eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
510*49ef7e06SGarrett D'Amore mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
511*49ef7e06SGarrett D'Amore l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
512*49ef7e06SGarrett D'Amore l4_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L4_CLASS);
513*49ef7e06SGarrett D'Amore cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
514*49ef7e06SGarrett D'Amore
515*49ef7e06SGarrett D'Amore if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
516*49ef7e06SGarrett D'Amore /* Drop this event */
517*49ef7e06SGarrett D'Amore return (B_FALSE);
518*49ef7e06SGarrett D'Amore }
519*49ef7e06SGarrett D'Amore flags = 0;
520*49ef7e06SGarrett D'Amore
521*49ef7e06SGarrett D'Amore if (cont != 0) {
522*49ef7e06SGarrett D'Amore /*
523*49ef7e06SGarrett D'Amore * This may be part of a scattered frame, or it may be a
524*49ef7e06SGarrett D'Amore * truncated frame if scatter is disabled on this RXQ.
525*49ef7e06SGarrett D'Amore * Overlength frames can be received if e.g. a VF is configured
526*49ef7e06SGarrett D'Amore * for 1500 MTU but connected to a port set to 9000 MTU
527*49ef7e06SGarrett D'Amore * (see bug56567).
528*49ef7e06SGarrett D'Amore * FIXME: There is not yet any driver that supports scatter on
529*49ef7e06SGarrett D'Amore * Huntington. Scatter support is required for OSX.
530*49ef7e06SGarrett D'Amore */
531*49ef7e06SGarrett D'Amore flags |= EFX_PKT_CONT;
532*49ef7e06SGarrett D'Amore }
533*49ef7e06SGarrett D'Amore
534*49ef7e06SGarrett D'Amore if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
535*49ef7e06SGarrett D'Amore flags |= EFX_PKT_UNICAST;
536*49ef7e06SGarrett D'Amore
537*49ef7e06SGarrett D'Amore /* Increment the count of descriptors read */
538*49ef7e06SGarrett D'Amore eersp = &eep->ee_rxq_state[label];
539*49ef7e06SGarrett D'Amore desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
540*49ef7e06SGarrett D'Amore EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
541*49ef7e06SGarrett D'Amore eersp->eers_rx_read_ptr += desc_count;
542*49ef7e06SGarrett D'Amore
543*49ef7e06SGarrett D'Amore /*
544*49ef7e06SGarrett D'Amore * FIXME: add error checking to make sure this a batched event.
545*49ef7e06SGarrett D'Amore * This could also be an aborted scatter, see Bug36629.
546*49ef7e06SGarrett D'Amore */
547*49ef7e06SGarrett D'Amore if (desc_count > 1) {
548*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
549*49ef7e06SGarrett D'Amore flags |= EFX_PKT_PREFIX_LEN;
550*49ef7e06SGarrett D'Amore }
551*49ef7e06SGarrett D'Amore
552*49ef7e06SGarrett D'Amore /* Calculate the index of the the last descriptor consumed */
553*49ef7e06SGarrett D'Amore last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
554*49ef7e06SGarrett D'Amore
555*49ef7e06SGarrett D'Amore /* Check for errors that invalidate checksum and L3/L4 fields */
556*49ef7e06SGarrett D'Amore if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECC_ERR) != 0) {
557*49ef7e06SGarrett D'Amore /* RX frame truncated (error flag is misnamed) */
558*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
559*49ef7e06SGarrett D'Amore flags |= EFX_DISCARD;
560*49ef7e06SGarrett D'Amore goto deliver;
561*49ef7e06SGarrett D'Amore }
562*49ef7e06SGarrett D'Amore if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
563*49ef7e06SGarrett D'Amore /* Bad Ethernet frame CRC */
564*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
565*49ef7e06SGarrett D'Amore flags |= EFX_DISCARD;
566*49ef7e06SGarrett D'Amore goto deliver;
567*49ef7e06SGarrett D'Amore }
568*49ef7e06SGarrett D'Amore if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
569*49ef7e06SGarrett D'Amore /*
570*49ef7e06SGarrett D'Amore * Hardware parse failed, due to malformed headers
571*49ef7e06SGarrett D'Amore * or headers that are too long for the parser.
572*49ef7e06SGarrett D'Amore * Headers and checksums must be validated by the host.
573*49ef7e06SGarrett D'Amore */
574*49ef7e06SGarrett D'Amore // TODO: EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
575*49ef7e06SGarrett D'Amore goto deliver;
576*49ef7e06SGarrett D'Amore }
577*49ef7e06SGarrett D'Amore
578*49ef7e06SGarrett D'Amore if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
579*49ef7e06SGarrett D'Amore (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
580*49ef7e06SGarrett D'Amore flags |= EFX_PKT_VLAN_TAGGED;
581*49ef7e06SGarrett D'Amore }
582*49ef7e06SGarrett D'Amore
583*49ef7e06SGarrett D'Amore switch (l3_class) {
584*49ef7e06SGarrett D'Amore case ESE_DZ_L3_CLASS_IP4:
585*49ef7e06SGarrett D'Amore case ESE_DZ_L3_CLASS_IP4_FRAG:
586*49ef7e06SGarrett D'Amore flags |= EFX_PKT_IPV4;
587*49ef7e06SGarrett D'Amore if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
588*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
589*49ef7e06SGarrett D'Amore } else {
590*49ef7e06SGarrett D'Amore flags |= EFX_CKSUM_IPV4;
591*49ef7e06SGarrett D'Amore }
592*49ef7e06SGarrett D'Amore
593*49ef7e06SGarrett D'Amore if (l4_class == ESE_DZ_L4_CLASS_TCP) {
594*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
595*49ef7e06SGarrett D'Amore flags |= EFX_PKT_TCP;
596*49ef7e06SGarrett D'Amore } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
597*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
598*49ef7e06SGarrett D'Amore flags |= EFX_PKT_UDP;
599*49ef7e06SGarrett D'Amore } else {
600*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
601*49ef7e06SGarrett D'Amore }
602*49ef7e06SGarrett D'Amore break;
603*49ef7e06SGarrett D'Amore
604*49ef7e06SGarrett D'Amore case ESE_DZ_L3_CLASS_IP6:
605*49ef7e06SGarrett D'Amore case ESE_DZ_L3_CLASS_IP6_FRAG:
606*49ef7e06SGarrett D'Amore flags |= EFX_PKT_IPV6;
607*49ef7e06SGarrett D'Amore
608*49ef7e06SGarrett D'Amore if (l4_class == ESE_DZ_L4_CLASS_TCP) {
609*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
610*49ef7e06SGarrett D'Amore flags |= EFX_PKT_TCP;
611*49ef7e06SGarrett D'Amore } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
612*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
613*49ef7e06SGarrett D'Amore flags |= EFX_PKT_UDP;
614*49ef7e06SGarrett D'Amore } else {
615*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
616*49ef7e06SGarrett D'Amore }
617*49ef7e06SGarrett D'Amore break;
618*49ef7e06SGarrett D'Amore
619*49ef7e06SGarrett D'Amore default:
620*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
621*49ef7e06SGarrett D'Amore break;
622*49ef7e06SGarrett D'Amore }
623*49ef7e06SGarrett D'Amore
624*49ef7e06SGarrett D'Amore if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
625*49ef7e06SGarrett D'Amore if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
626*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
627*49ef7e06SGarrett D'Amore } else {
628*49ef7e06SGarrett D'Amore flags |= EFX_CKSUM_TCPUDP;
629*49ef7e06SGarrett D'Amore }
630*49ef7e06SGarrett D'Amore }
631*49ef7e06SGarrett D'Amore
632*49ef7e06SGarrett D'Amore deliver:
633*49ef7e06SGarrett D'Amore /* If we're not discarding the packet then it is ok */
634*49ef7e06SGarrett D'Amore if (~flags & EFX_DISCARD)
635*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
636*49ef7e06SGarrett D'Amore
637*49ef7e06SGarrett D'Amore EFSYS_ASSERT(eecp->eec_rx != NULL);
638*49ef7e06SGarrett D'Amore should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
639*49ef7e06SGarrett D'Amore
640*49ef7e06SGarrett D'Amore return (should_abort);
641*49ef7e06SGarrett D'Amore }
642*49ef7e06SGarrett D'Amore
643*49ef7e06SGarrett D'Amore static __checkReturn boolean_t
ef10_ev_tx(__in efx_evq_t * eep,__in efx_qword_t * eqp,__in const efx_ev_callbacks_t * eecp,__in_opt void * arg)644*49ef7e06SGarrett D'Amore ef10_ev_tx(
645*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
646*49ef7e06SGarrett D'Amore __in efx_qword_t *eqp,
647*49ef7e06SGarrett D'Amore __in const efx_ev_callbacks_t *eecp,
648*49ef7e06SGarrett D'Amore __in_opt void *arg)
649*49ef7e06SGarrett D'Amore {
650*49ef7e06SGarrett D'Amore efx_nic_t *enp = eep->ee_enp;
651*49ef7e06SGarrett D'Amore uint32_t id;
652*49ef7e06SGarrett D'Amore uint32_t label;
653*49ef7e06SGarrett D'Amore boolean_t should_abort;
654*49ef7e06SGarrett D'Amore
655*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_TX);
656*49ef7e06SGarrett D'Amore
657*49ef7e06SGarrett D'Amore /* Discard events after RXQ/TXQ errors */
658*49ef7e06SGarrett D'Amore if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
659*49ef7e06SGarrett D'Amore return (B_FALSE);
660*49ef7e06SGarrett D'Amore
661*49ef7e06SGarrett D'Amore if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
662*49ef7e06SGarrett D'Amore /* Drop this event */
663*49ef7e06SGarrett D'Amore return (B_FALSE);
664*49ef7e06SGarrett D'Amore }
665*49ef7e06SGarrett D'Amore
666*49ef7e06SGarrett D'Amore /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
667*49ef7e06SGarrett D'Amore id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
668*49ef7e06SGarrett D'Amore label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
669*49ef7e06SGarrett D'Amore
670*49ef7e06SGarrett D'Amore EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
671*49ef7e06SGarrett D'Amore
672*49ef7e06SGarrett D'Amore EFSYS_ASSERT(eecp->eec_tx != NULL);
673*49ef7e06SGarrett D'Amore should_abort = eecp->eec_tx(arg, label, id);
674*49ef7e06SGarrett D'Amore
675*49ef7e06SGarrett D'Amore return (should_abort);
676*49ef7e06SGarrett D'Amore }
677*49ef7e06SGarrett D'Amore
678*49ef7e06SGarrett D'Amore static __checkReturn boolean_t
ef10_ev_driver(__in efx_evq_t * eep,__in efx_qword_t * eqp,__in const efx_ev_callbacks_t * eecp,__in_opt void * arg)679*49ef7e06SGarrett D'Amore ef10_ev_driver(
680*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
681*49ef7e06SGarrett D'Amore __in efx_qword_t *eqp,
682*49ef7e06SGarrett D'Amore __in const efx_ev_callbacks_t *eecp,
683*49ef7e06SGarrett D'Amore __in_opt void *arg)
684*49ef7e06SGarrett D'Amore {
685*49ef7e06SGarrett D'Amore unsigned int code;
686*49ef7e06SGarrett D'Amore boolean_t should_abort;
687*49ef7e06SGarrett D'Amore
688*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
689*49ef7e06SGarrett D'Amore should_abort = B_FALSE;
690*49ef7e06SGarrett D'Amore
691*49ef7e06SGarrett D'Amore code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
692*49ef7e06SGarrett D'Amore switch (code) {
693*49ef7e06SGarrett D'Amore case ESE_DZ_DRV_TIMER_EV: {
694*49ef7e06SGarrett D'Amore uint32_t id;
695*49ef7e06SGarrett D'Amore
696*49ef7e06SGarrett D'Amore id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
697*49ef7e06SGarrett D'Amore
698*49ef7e06SGarrett D'Amore EFSYS_ASSERT(eecp->eec_timer != NULL);
699*49ef7e06SGarrett D'Amore should_abort = eecp->eec_timer(arg, id);
700*49ef7e06SGarrett D'Amore break;
701*49ef7e06SGarrett D'Amore }
702*49ef7e06SGarrett D'Amore
703*49ef7e06SGarrett D'Amore case ESE_DZ_DRV_WAKE_UP_EV: {
704*49ef7e06SGarrett D'Amore uint32_t id;
705*49ef7e06SGarrett D'Amore
706*49ef7e06SGarrett D'Amore id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
707*49ef7e06SGarrett D'Amore
708*49ef7e06SGarrett D'Amore EFSYS_ASSERT(eecp->eec_wake_up != NULL);
709*49ef7e06SGarrett D'Amore should_abort = eecp->eec_wake_up(arg, id);
710*49ef7e06SGarrett D'Amore break;
711*49ef7e06SGarrett D'Amore }
712*49ef7e06SGarrett D'Amore
713*49ef7e06SGarrett D'Amore case ESE_DZ_DRV_START_UP_EV:
714*49ef7e06SGarrett D'Amore EFSYS_ASSERT(eecp->eec_initialized != NULL);
715*49ef7e06SGarrett D'Amore should_abort = eecp->eec_initialized(arg);
716*49ef7e06SGarrett D'Amore break;
717*49ef7e06SGarrett D'Amore
718*49ef7e06SGarrett D'Amore default:
719*49ef7e06SGarrett D'Amore EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
720*49ef7e06SGarrett D'Amore uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
721*49ef7e06SGarrett D'Amore uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
722*49ef7e06SGarrett D'Amore break;
723*49ef7e06SGarrett D'Amore }
724*49ef7e06SGarrett D'Amore
725*49ef7e06SGarrett D'Amore return (should_abort);
726*49ef7e06SGarrett D'Amore }
727*49ef7e06SGarrett D'Amore
728*49ef7e06SGarrett D'Amore static __checkReturn boolean_t
ef10_ev_drv_gen(__in efx_evq_t * eep,__in efx_qword_t * eqp,__in const efx_ev_callbacks_t * eecp,__in_opt void * arg)729*49ef7e06SGarrett D'Amore ef10_ev_drv_gen(
730*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
731*49ef7e06SGarrett D'Amore __in efx_qword_t *eqp,
732*49ef7e06SGarrett D'Amore __in const efx_ev_callbacks_t *eecp,
733*49ef7e06SGarrett D'Amore __in_opt void *arg)
734*49ef7e06SGarrett D'Amore {
735*49ef7e06SGarrett D'Amore uint32_t data;
736*49ef7e06SGarrett D'Amore boolean_t should_abort;
737*49ef7e06SGarrett D'Amore
738*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
739*49ef7e06SGarrett D'Amore should_abort = B_FALSE;
740*49ef7e06SGarrett D'Amore
741*49ef7e06SGarrett D'Amore data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
742*49ef7e06SGarrett D'Amore if (data >= ((uint32_t)1 << 16)) {
743*49ef7e06SGarrett D'Amore EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
744*49ef7e06SGarrett D'Amore uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
745*49ef7e06SGarrett D'Amore uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
746*49ef7e06SGarrett D'Amore
747*49ef7e06SGarrett D'Amore return (B_TRUE);
748*49ef7e06SGarrett D'Amore }
749*49ef7e06SGarrett D'Amore
750*49ef7e06SGarrett D'Amore EFSYS_ASSERT(eecp->eec_software != NULL);
751*49ef7e06SGarrett D'Amore should_abort = eecp->eec_software(arg, (uint16_t)data);
752*49ef7e06SGarrett D'Amore
753*49ef7e06SGarrett D'Amore return (should_abort);
754*49ef7e06SGarrett D'Amore }
755*49ef7e06SGarrett D'Amore
756*49ef7e06SGarrett D'Amore static __checkReturn boolean_t
ef10_ev_mcdi(__in efx_evq_t * eep,__in efx_qword_t * eqp,__in const efx_ev_callbacks_t * eecp,__in_opt void * arg)757*49ef7e06SGarrett D'Amore ef10_ev_mcdi(
758*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
759*49ef7e06SGarrett D'Amore __in efx_qword_t *eqp,
760*49ef7e06SGarrett D'Amore __in const efx_ev_callbacks_t *eecp,
761*49ef7e06SGarrett D'Amore __in_opt void *arg)
762*49ef7e06SGarrett D'Amore {
763*49ef7e06SGarrett D'Amore efx_nic_t *enp = eep->ee_enp;
764*49ef7e06SGarrett D'Amore unsigned code;
765*49ef7e06SGarrett D'Amore boolean_t should_abort = B_FALSE;
766*49ef7e06SGarrett D'Amore
767*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
768*49ef7e06SGarrett D'Amore
769*49ef7e06SGarrett D'Amore code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
770*49ef7e06SGarrett D'Amore switch (code) {
771*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_BADSSERT:
772*49ef7e06SGarrett D'Amore efx_mcdi_ev_death(enp, EINTR);
773*49ef7e06SGarrett D'Amore break;
774*49ef7e06SGarrett D'Amore
775*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_CMDDONE:
776*49ef7e06SGarrett D'Amore efx_mcdi_ev_cpl(enp,
777*49ef7e06SGarrett D'Amore MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
778*49ef7e06SGarrett D'Amore MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
779*49ef7e06SGarrett D'Amore MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
780*49ef7e06SGarrett D'Amore break;
781*49ef7e06SGarrett D'Amore
782*49ef7e06SGarrett D'Amore #if EFSYS_OPT_MCDI_PROXY_AUTH
783*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_PROXY_RESPONSE:
784*49ef7e06SGarrett D'Amore /*
785*49ef7e06SGarrett D'Amore * This event notifies a function that an authorization request
786*49ef7e06SGarrett D'Amore * has been processed. If the request was authorized then the
787*49ef7e06SGarrett D'Amore * function can now re-send the original MCDI request.
788*49ef7e06SGarrett D'Amore * See SF-113652-SW "SR-IOV Proxied Network Access Control".
789*49ef7e06SGarrett D'Amore */
790*49ef7e06SGarrett D'Amore efx_mcdi_ev_proxy_response(enp,
791*49ef7e06SGarrett D'Amore MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
792*49ef7e06SGarrett D'Amore MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
793*49ef7e06SGarrett D'Amore break;
794*49ef7e06SGarrett D'Amore #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
795*49ef7e06SGarrett D'Amore
796*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_LINKCHANGE: {
797*49ef7e06SGarrett D'Amore efx_link_mode_t link_mode;
798*49ef7e06SGarrett D'Amore
799*49ef7e06SGarrett D'Amore ef10_phy_link_ev(enp, eqp, &link_mode);
800*49ef7e06SGarrett D'Amore should_abort = eecp->eec_link_change(arg, link_mode);
801*49ef7e06SGarrett D'Amore break;
802*49ef7e06SGarrett D'Amore }
803*49ef7e06SGarrett D'Amore
804*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_SENSOREVT: {
805*49ef7e06SGarrett D'Amore #if EFSYS_OPT_MON_STATS
806*49ef7e06SGarrett D'Amore efx_mon_stat_t id;
807*49ef7e06SGarrett D'Amore efx_mon_stat_value_t value;
808*49ef7e06SGarrett D'Amore efx_rc_t rc;
809*49ef7e06SGarrett D'Amore
810*49ef7e06SGarrett D'Amore /* Decode monitor stat for MCDI sensor (if supported) */
811*49ef7e06SGarrett D'Amore if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
812*49ef7e06SGarrett D'Amore /* Report monitor stat change */
813*49ef7e06SGarrett D'Amore should_abort = eecp->eec_monitor(arg, id, value);
814*49ef7e06SGarrett D'Amore } else if (rc == ENOTSUP) {
815*49ef7e06SGarrett D'Amore should_abort = eecp->eec_exception(arg,
816*49ef7e06SGarrett D'Amore EFX_EXCEPTION_UNKNOWN_SENSOREVT,
817*49ef7e06SGarrett D'Amore MCDI_EV_FIELD(eqp, DATA));
818*49ef7e06SGarrett D'Amore } else {
819*49ef7e06SGarrett D'Amore EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
820*49ef7e06SGarrett D'Amore }
821*49ef7e06SGarrett D'Amore #endif
822*49ef7e06SGarrett D'Amore break;
823*49ef7e06SGarrett D'Amore }
824*49ef7e06SGarrett D'Amore
825*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_SCHEDERR:
826*49ef7e06SGarrett D'Amore /* Informational only */
827*49ef7e06SGarrett D'Amore break;
828*49ef7e06SGarrett D'Amore
829*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_REBOOT:
830*49ef7e06SGarrett D'Amore /* Falcon/Siena only (should not been seen with Huntington). */
831*49ef7e06SGarrett D'Amore efx_mcdi_ev_death(enp, EIO);
832*49ef7e06SGarrett D'Amore break;
833*49ef7e06SGarrett D'Amore
834*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_MC_REBOOT:
835*49ef7e06SGarrett D'Amore /* MC_REBOOT event is used for Huntington (EF10) and later. */
836*49ef7e06SGarrett D'Amore efx_mcdi_ev_death(enp, EIO);
837*49ef7e06SGarrett D'Amore break;
838*49ef7e06SGarrett D'Amore
839*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_MAC_STATS_DMA:
840*49ef7e06SGarrett D'Amore #if EFSYS_OPT_MAC_STATS
841*49ef7e06SGarrett D'Amore if (eecp->eec_mac_stats != NULL) {
842*49ef7e06SGarrett D'Amore eecp->eec_mac_stats(arg,
843*49ef7e06SGarrett D'Amore MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
844*49ef7e06SGarrett D'Amore }
845*49ef7e06SGarrett D'Amore #endif
846*49ef7e06SGarrett D'Amore break;
847*49ef7e06SGarrett D'Amore
848*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_FWALERT: {
849*49ef7e06SGarrett D'Amore uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
850*49ef7e06SGarrett D'Amore
851*49ef7e06SGarrett D'Amore if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
852*49ef7e06SGarrett D'Amore should_abort = eecp->eec_exception(arg,
853*49ef7e06SGarrett D'Amore EFX_EXCEPTION_FWALERT_SRAM,
854*49ef7e06SGarrett D'Amore MCDI_EV_FIELD(eqp, FWALERT_DATA));
855*49ef7e06SGarrett D'Amore else
856*49ef7e06SGarrett D'Amore should_abort = eecp->eec_exception(arg,
857*49ef7e06SGarrett D'Amore EFX_EXCEPTION_UNKNOWN_FWALERT,
858*49ef7e06SGarrett D'Amore MCDI_EV_FIELD(eqp, DATA));
859*49ef7e06SGarrett D'Amore break;
860*49ef7e06SGarrett D'Amore }
861*49ef7e06SGarrett D'Amore
862*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_TX_ERR: {
863*49ef7e06SGarrett D'Amore /*
864*49ef7e06SGarrett D'Amore * After a TXQ error is detected, firmware sends a TX_ERR event.
865*49ef7e06SGarrett D'Amore * This may be followed by TX completions (which we discard),
866*49ef7e06SGarrett D'Amore * and then finally by a TX_FLUSH event. Firmware destroys the
867*49ef7e06SGarrett D'Amore * TXQ automatically after sending the TX_FLUSH event.
868*49ef7e06SGarrett D'Amore */
869*49ef7e06SGarrett D'Amore enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
870*49ef7e06SGarrett D'Amore
871*49ef7e06SGarrett D'Amore EFSYS_PROBE1(tx_descq_err, uint32_t, MCDI_EV_FIELD(eqp, DATA));
872*49ef7e06SGarrett D'Amore
873*49ef7e06SGarrett D'Amore /* Inform the driver that a reset is required. */
874*49ef7e06SGarrett D'Amore eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
875*49ef7e06SGarrett D'Amore MCDI_EV_FIELD(eqp, TX_ERR_DATA));
876*49ef7e06SGarrett D'Amore break;
877*49ef7e06SGarrett D'Amore }
878*49ef7e06SGarrett D'Amore
879*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_TX_FLUSH: {
880*49ef7e06SGarrett D'Amore uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
881*49ef7e06SGarrett D'Amore
882*49ef7e06SGarrett D'Amore /*
883*49ef7e06SGarrett D'Amore * EF10 firmware sends two TX_FLUSH events: one to the txq's
884*49ef7e06SGarrett D'Amore * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
885*49ef7e06SGarrett D'Amore * We want to wait for all completions, so ignore the events
886*49ef7e06SGarrett D'Amore * with TX_FLUSH_TO_DRIVER.
887*49ef7e06SGarrett D'Amore */
888*49ef7e06SGarrett D'Amore if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
889*49ef7e06SGarrett D'Amore should_abort = B_FALSE;
890*49ef7e06SGarrett D'Amore break;
891*49ef7e06SGarrett D'Amore }
892*49ef7e06SGarrett D'Amore
893*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
894*49ef7e06SGarrett D'Amore
895*49ef7e06SGarrett D'Amore EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
896*49ef7e06SGarrett D'Amore
897*49ef7e06SGarrett D'Amore EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
898*49ef7e06SGarrett D'Amore should_abort = eecp->eec_txq_flush_done(arg, txq_index);
899*49ef7e06SGarrett D'Amore break;
900*49ef7e06SGarrett D'Amore }
901*49ef7e06SGarrett D'Amore
902*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_RX_ERR: {
903*49ef7e06SGarrett D'Amore /*
904*49ef7e06SGarrett D'Amore * After an RXQ error is detected, firmware sends an RX_ERR
905*49ef7e06SGarrett D'Amore * event. This may be followed by RX events (which we discard),
906*49ef7e06SGarrett D'Amore * and then finally by an RX_FLUSH event. Firmware destroys the
907*49ef7e06SGarrett D'Amore * RXQ automatically after sending the RX_FLUSH event.
908*49ef7e06SGarrett D'Amore */
909*49ef7e06SGarrett D'Amore enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
910*49ef7e06SGarrett D'Amore
911*49ef7e06SGarrett D'Amore EFSYS_PROBE1(rx_descq_err, uint32_t, MCDI_EV_FIELD(eqp, DATA));
912*49ef7e06SGarrett D'Amore
913*49ef7e06SGarrett D'Amore /* Inform the driver that a reset is required. */
914*49ef7e06SGarrett D'Amore eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
915*49ef7e06SGarrett D'Amore MCDI_EV_FIELD(eqp, RX_ERR_DATA));
916*49ef7e06SGarrett D'Amore break;
917*49ef7e06SGarrett D'Amore }
918*49ef7e06SGarrett D'Amore
919*49ef7e06SGarrett D'Amore case MCDI_EVENT_CODE_RX_FLUSH: {
920*49ef7e06SGarrett D'Amore uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
921*49ef7e06SGarrett D'Amore
922*49ef7e06SGarrett D'Amore /*
923*49ef7e06SGarrett D'Amore * EF10 firmware sends two RX_FLUSH events: one to the rxq's
924*49ef7e06SGarrett D'Amore * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
925*49ef7e06SGarrett D'Amore * We want to wait for all completions, so ignore the events
926*49ef7e06SGarrett D'Amore * with RX_FLUSH_TO_DRIVER.
927*49ef7e06SGarrett D'Amore */
928*49ef7e06SGarrett D'Amore if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
929*49ef7e06SGarrett D'Amore should_abort = B_FALSE;
930*49ef7e06SGarrett D'Amore break;
931*49ef7e06SGarrett D'Amore }
932*49ef7e06SGarrett D'Amore
933*49ef7e06SGarrett D'Amore EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
934*49ef7e06SGarrett D'Amore
935*49ef7e06SGarrett D'Amore EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
936*49ef7e06SGarrett D'Amore
937*49ef7e06SGarrett D'Amore EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
938*49ef7e06SGarrett D'Amore should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
939*49ef7e06SGarrett D'Amore break;
940*49ef7e06SGarrett D'Amore }
941*49ef7e06SGarrett D'Amore
942*49ef7e06SGarrett D'Amore default:
943*49ef7e06SGarrett D'Amore EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
944*49ef7e06SGarrett D'Amore uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
945*49ef7e06SGarrett D'Amore uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
946*49ef7e06SGarrett D'Amore break;
947*49ef7e06SGarrett D'Amore }
948*49ef7e06SGarrett D'Amore
949*49ef7e06SGarrett D'Amore return (should_abort);
950*49ef7e06SGarrett D'Amore }
951*49ef7e06SGarrett D'Amore
952*49ef7e06SGarrett D'Amore void
ef10_ev_rxlabel_init(__in efx_evq_t * eep,__in efx_rxq_t * erp,__in unsigned int label)953*49ef7e06SGarrett D'Amore ef10_ev_rxlabel_init(
954*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
955*49ef7e06SGarrett D'Amore __in efx_rxq_t *erp,
956*49ef7e06SGarrett D'Amore __in unsigned int label)
957*49ef7e06SGarrett D'Amore {
958*49ef7e06SGarrett D'Amore efx_evq_rxq_state_t *eersp;
959*49ef7e06SGarrett D'Amore
960*49ef7e06SGarrett D'Amore EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
961*49ef7e06SGarrett D'Amore eersp = &eep->ee_rxq_state[label];
962*49ef7e06SGarrett D'Amore
963*49ef7e06SGarrett D'Amore EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
964*49ef7e06SGarrett D'Amore
965*49ef7e06SGarrett D'Amore eersp->eers_rx_read_ptr = 0;
966*49ef7e06SGarrett D'Amore eersp->eers_rx_mask = erp->er_mask;
967*49ef7e06SGarrett D'Amore }
968*49ef7e06SGarrett D'Amore
969*49ef7e06SGarrett D'Amore void
ef10_ev_rxlabel_fini(__in efx_evq_t * eep,__in unsigned int label)970*49ef7e06SGarrett D'Amore ef10_ev_rxlabel_fini(
971*49ef7e06SGarrett D'Amore __in efx_evq_t *eep,
972*49ef7e06SGarrett D'Amore __in unsigned int label)
973*49ef7e06SGarrett D'Amore {
974*49ef7e06SGarrett D'Amore efx_evq_rxq_state_t *eersp;
975*49ef7e06SGarrett D'Amore
976*49ef7e06SGarrett D'Amore EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
977*49ef7e06SGarrett D'Amore eersp = &eep->ee_rxq_state[label];
978*49ef7e06SGarrett D'Amore
979*49ef7e06SGarrett D'Amore EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
980*49ef7e06SGarrett D'Amore
981*49ef7e06SGarrett D'Amore eersp->eers_rx_read_ptr = 0;
982*49ef7e06SGarrett D'Amore eersp->eers_rx_mask = 0;
983*49ef7e06SGarrett D'Amore }
984*49ef7e06SGarrett D'Amore
985*49ef7e06SGarrett D'Amore #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
986