xref: /illumos-gate/usr/src/uts/common/io/rtw/rtwvar.h (revision d3351b34)
1a72f7ea6Sql /*
29aa73b68SQin Michael Li  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
3a72f7ea6Sql  * Use is subject to license terms.
4*d3351b34SJohn Levon  *
5*d3351b34SJohn Levon  * Copyright 2019 Joyent, Inc.
6a72f7ea6Sql  */
7a72f7ea6Sql /*
8a72f7ea6Sql  * Copyright (c) 2004, 2005 David Young.  All rights reserved.
9a72f7ea6Sql  *
10a72f7ea6Sql  * Driver for the Realtek RTL8180 802.11 MAC/BBP by David Young.
11a72f7ea6Sql  *
12a72f7ea6Sql  * Redistribution and use in source and binary forms, with or without
13a72f7ea6Sql  * modification, are permitted provided that the following conditions
14a72f7ea6Sql  * are met:
15a72f7ea6Sql  * 1. Redistributions of source code must retain the above copyright
16a72f7ea6Sql  *    notice, this list of conditions and the following disclaimer.
17a72f7ea6Sql  * 2. Redistributions in binary form must reproduce the above copyright
18a72f7ea6Sql  *    notice, this list of conditions and the following disclaimer in the
19a72f7ea6Sql  *    documentation and/or other materials provided with the distribution.
20a72f7ea6Sql  * 3. The name of David Young may not be used to endorse or promote
21a72f7ea6Sql  *    products derived from this software without specific prior
22a72f7ea6Sql  *    written permission.
23a72f7ea6Sql  *
24a72f7ea6Sql  * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
25a72f7ea6Sql  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26a72f7ea6Sql  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
27a72f7ea6Sql  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
28a72f7ea6Sql  * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29a72f7ea6Sql  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
30a72f7ea6Sql  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31a72f7ea6Sql  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32a72f7ea6Sql  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33a72f7ea6Sql  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34a72f7ea6Sql  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
35a72f7ea6Sql  * OF SUCH DAMAGE.
36a72f7ea6Sql  */
37a72f7ea6Sql #ifndef _RTWVAR_H_
38a72f7ea6Sql #define	_RTWVAR_H_
39a72f7ea6Sql 
409aa73b68SQin Michael Li #ifdef __cplusplus
419aa73b68SQin Michael Li extern "C" {
429aa73b68SQin Michael Li #endif
439aa73b68SQin Michael Li 
44a72f7ea6Sql #include <sys/list.h>
45a72f7ea6Sql #include <sys/net80211.h>
46a72f7ea6Sql 
47a72f7ea6Sql #ifndef __func__
48a72f7ea6Sql #define	__func__ ""
49a72f7ea6Sql #endif
50a72f7ea6Sql 
51a72f7ea6Sql extern void rtw_dbg(uint32_t dbg_flags, const int8_t *fmt, ...);
52a72f7ea6Sql 
53a72f7ea6Sql #define	RTW_DEBUG_TUNE		0x000001
54a72f7ea6Sql #define	RTW_DEBUG_PKTFILT	0x000002
55a72f7ea6Sql #define	RTW_DEBUG_XMIT		0x000004
56a72f7ea6Sql #define	RTW_DEBUG_DMA		0x000008
57a72f7ea6Sql #define	RTW_DEBUG_NODE		0x000010
58a72f7ea6Sql #define	RTW_DEBUG_PWR		0x000020
59a72f7ea6Sql #define	RTW_DEBUG_ATTACH	0x000040
60a72f7ea6Sql #define	RTW_DEBUG_REGDUMP	0x000080
61a72f7ea6Sql #define	RTW_DEBUG_ACCESS	0x000100
62a72f7ea6Sql #define	RTW_DEBUG_RESET		0x000200
63a72f7ea6Sql #define	RTW_DEBUG_INIT		0x000400
64a72f7ea6Sql #define	RTW_DEBUG_PKTDUMP	0x000800
65a72f7ea6Sql #define	RTW_DEBUG_RECV		0x001000
66a72f7ea6Sql #define	RTW_DEBUG_RECV_DESC	0x002000
67a72f7ea6Sql #define	RTW_DEBUG_IOSTATE	0x004000
68a72f7ea6Sql #define	RTW_DEBUG_INTR		0x008000
69a72f7ea6Sql #define	RTW_DEBUG_PHY		0x010000
70a72f7ea6Sql #define	RTW_DEBUG_PHYIO		0x020000
71a72f7ea6Sql #define	RTW_DEBUG_PHYBITIO	0x040000
72a72f7ea6Sql #define	RTW_DEBUG_TIMEOUT	0x080000
73a72f7ea6Sql #define	RTW_DEBUG_BUGS		0x100000
74a72f7ea6Sql #define	RTW_DEBUG_BEACON	0x200000
75a72f7ea6Sql #define	RTW_DEBUG_WIFICFG	0x400000
76a72f7ea6Sql #define	RTW_DEBUG_80211		0x800000
77a72f7ea6Sql #define	RTW_DEBUG_MAX		0xffffff
78a72f7ea6Sql 
79a72f7ea6Sql #ifdef DEBUG
80a72f7ea6Sql #define	RTW_DPRINTF \
81a72f7ea6Sql 	rtw_dbg
82a72f7ea6Sql #else /* DEBUG */
83*d3351b34SJohn Levon #define	RTW_DPRINTF(...) (void)(0)
84a72f7ea6Sql #endif /* DEBUG */
85a72f7ea6Sql 
86a72f7ea6Sql enum rtw_locale {
87a72f7ea6Sql 	RTW_LOCALE_USA = 0,
88a72f7ea6Sql 	RTW_LOCALE_EUROPE,
89a72f7ea6Sql 	RTW_LOCALE_JAPAN,
90a72f7ea6Sql 	RTW_LOCALE_UNKNOWN
91a72f7ea6Sql };
92a72f7ea6Sql 
93a72f7ea6Sql enum rtw_rfchipid {
94a72f7ea6Sql 	RTW_RFCHIPID_RESERVED = 0,
95a72f7ea6Sql 	RTW_RFCHIPID_INTERSIL = 1,
96a72f7ea6Sql 	RTW_RFCHIPID_RFMD = 2,
97a72f7ea6Sql 	RTW_RFCHIPID_PHILIPS = 3,
98a72f7ea6Sql 	RTW_RFCHIPID_MAXIM = 4,
99a72f7ea6Sql 	RTW_RFCHIPID_GCT = 5
100a72f7ea6Sql };
101a72f7ea6Sql 
102a72f7ea6Sql /*
103a72f7ea6Sql  * sc_flags
104a72f7ea6Sql  */
105a72f7ea6Sql #define	RTW_F_ENABLED		0x00000001	/* chip is enabled */
106a72f7ea6Sql #define	RTW_F_DIGPHY		0x00000002	/* digital PHY */
107a72f7ea6Sql #define	RTW_F_DFLANTB		0x00000004	/* B antenna is default */
108a72f7ea6Sql #define	RTW_F_ANTDIV		0x00000010	/* h/w antenna diversity */
109a72f7ea6Sql #define	RTW_F_9356SROM		0x00000020	/* 93c56 SROM */
110a72f7ea6Sql #define	RTW_F_SLEEP		0x00000040	/* chip is asleep */
111a72f7ea6Sql #define	RTW_F_INVALID		0x00000080	/* chip is absent */
1129aa73b68SQin Michael Li #define	RTW_F_SUSPEND		0x00000100	/* driver is suspended */
1139aa73b68SQin Michael Li #define	RTW_F_PLUMBED		0x00000200	/* driver is plumbed */
114a72f7ea6Sql #define	RTW_F_ATTACHED		0x01000000	/* driver is attached */
115a72f7ea6Sql /*
116a72f7ea6Sql  * all PHY flags
117a72f7ea6Sql  */
118a72f7ea6Sql #define	RTW_F_ALLPHY		(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV)
119a72f7ea6Sql 
120a72f7ea6Sql enum rtw_access {RTW_ACCESS_NONE = 0,
121a72f7ea6Sql 		RTW_ACCESS_CONFIG = 1,
122a72f7ea6Sql 		RTW_ACCESS_ANAPARM = 2};
123a72f7ea6Sql 
124a72f7ea6Sql struct rtw_regs {
125a72f7ea6Sql 	ddi_acc_handle_t	r_handle;
126a72f7ea6Sql 	caddr_t			r_base;
127a72f7ea6Sql 	enum rtw_access		r_access;
128a72f7ea6Sql };
129a72f7ea6Sql 
130a72f7ea6Sql #define	RTW_SR_GET(sr, ofs) \
131a72f7ea6Sql 	(((sr)->sr_content[(ofs)/2] >> (((ofs) % 2 == 0) ? 0 : 8)) & 0xff)
132a72f7ea6Sql 
133a72f7ea6Sql #define	RTW_SR_GET16(sr, ofs) \
134a72f7ea6Sql 	(RTW_SR_GET((sr), (ofs)) | (RTW_SR_GET((sr), (ofs) + 1) << 8))
135a72f7ea6Sql 
136a72f7ea6Sql struct rtw_srom {
137a72f7ea6Sql 	uint16_t		*sr_content;
138a72f7ea6Sql 	uint16_t		sr_size;
139a72f7ea6Sql };
140a72f7ea6Sql 
141a72f7ea6Sql 
142a72f7ea6Sql #define	RTW_NTXPRI	4	/* number of Tx priorities */
143a72f7ea6Sql #define	RTW_TXPRILO	0
144a72f7ea6Sql #define	RTW_TXPRIMD	1
145a72f7ea6Sql #define	RTW_TXPRIHI	2
146a72f7ea6Sql #define	RTW_TXPRIBCN	3	/* beacon priority */
147a72f7ea6Sql 
148a72f7ea6Sql #define	RTW_MAXPKTSEGS		64	/* Max 64 segments per Tx packet */
149a72f7ea6Sql 
150a72f7ea6Sql /*
151a72f7ea6Sql  * Note well: the descriptor rings must begin on RTW_DESC_ALIGNMENT
152a72f7ea6Sql  * boundaries.  I allocate them consecutively from one buffer, so
153a72f7ea6Sql  * just round up.
154a72f7ea6Sql  */
155a72f7ea6Sql #define	RTW_TXQLENLO	64	/* low-priority queue length */
156a72f7ea6Sql #define	RTW_TXQLENMD	64	/* medium-priority */
157a72f7ea6Sql #define	RTW_TXQLENHI	64	/* high-priority */
158a72f7ea6Sql #define	RTW_TXQLENBCN	2	/* beacon */
159a72f7ea6Sql 
160a72f7ea6Sql #define	RTW_NTXDESCLO	RTW_TXQLENLO
161a72f7ea6Sql #define	RTW_NTXDESCMD	RTW_TXQLENMD
162a72f7ea6Sql #define	RTW_NTXDESCHI	RTW_TXQLENHI
163a72f7ea6Sql #define	RTW_NTXDESCBCN	RTW_TXQLENBCN
164a72f7ea6Sql 
165a72f7ea6Sql #define	RTW_NTXDESCTOTAL	(RTW_NTXDESCLO + RTW_NTXDESCMD + \
166a72f7ea6Sql 				RTW_NTXDESCHI + RTW_NTXDESCBCN)
167a72f7ea6Sql 
168a72f7ea6Sql #define	RTW_RXQLEN	64
169a72f7ea6Sql #define	RTW_DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl,\
170a72f7ea6Sql 	(area).offset, (area).alength, (flag)))
171a72f7ea6Sql 
172a72f7ea6Sql #define	RTW_DMA_SYNC_DESC(area, offset, len, flag) \
173a72f7ea6Sql 	((void) ddi_dma_sync((area).dma_hdl, offset, len, (flag)))
174a72f7ea6Sql 
175a72f7ea6Sql #define	RTW_MINC(x, y) (x) = ((x + 1) % y)
176a72f7ea6Sql #define	list_empty(a) ((a)->list_head.list_next == &(a)->list_head)
177a72f7ea6Sql 
178a72f7ea6Sql typedef struct dma_area {
179a72f7ea6Sql 	ddi_acc_handle_t	acc_hdl;	/* handle for memory */
180a72f7ea6Sql 	caddr_t			mem_va;		/* CPU VA of memory */
181a72f7ea6Sql 	uint32_t		nslots;		/* number of slots */
182a72f7ea6Sql 	uint32_t		size;		/* size per slot */
183a72f7ea6Sql 	size_t			alength;	/* allocated size */
184a72f7ea6Sql 						/* >= product of above */
185a72f7ea6Sql 
186a72f7ea6Sql 	ddi_dma_handle_t	dma_hdl;	/* DMA handle */
187a72f7ea6Sql 	offset_t		offset;		/* relative to handle */
188a72f7ea6Sql 	ddi_dma_cookie_t	cookie;		/* associated cookie */
189a72f7ea6Sql 	uint32_t		ncookies;	/* must be 1 */
190a72f7ea6Sql 	uint32_t		token;		/* arbitrary identifier */
191a72f7ea6Sql } dma_area_t;						/* 0x50 (80) bytes */
192a72f7ea6Sql 
193a72f7ea6Sql struct rtw_txbuf {
194a72f7ea6Sql 	struct rtw_txdesc	*txdesc;	/* virtual addr of desc */
195a72f7ea6Sql 	uint32_t		bf_daddr;	/* physical addr of desc */
196a72f7ea6Sql 	uint32_t		next_bf_daddr;	/* physical addr of next desc */
197a72f7ea6Sql 	dma_area_t		bf_dma;		/* dma area for buf */
198a72f7ea6Sql 	struct ieee80211_node	*bf_in;		/* pointer to the node */
199a72f7ea6Sql 	list_node_t		bf_node;
200a72f7ea6Sql 	uint32_t		order;
201a72f7ea6Sql };
202a72f7ea6Sql 
203a72f7ea6Sql struct rtw_rxbuf {
204a72f7ea6Sql 	struct rtw_rxdesc	*rxdesc;	/* virtual addr of desc */
205a72f7ea6Sql 	uint32_t		bf_daddr;	/* physical addr of desc */
206a72f7ea6Sql 	dma_area_t		bf_dma;		/* dma area for buf */
207a72f7ea6Sql };
208a72f7ea6Sql 
209a72f7ea6Sql struct rtw_txq {
210a72f7ea6Sql 	struct	rtw_txdesc	*txdesc_h;
211a72f7ea6Sql 	struct	rtw_txbuf	*txbuf_h;
212a72f7ea6Sql 	uint32_t		tx_prod;
213a72f7ea6Sql 	uint32_t		tx_cons;
214a72f7ea6Sql 	uint32_t		tx_nfree;
215a72f7ea6Sql 	kmutex_t		txbuf_lock;
216a72f7ea6Sql 	list_t			tx_free_list;
217a72f7ea6Sql 	list_t			tx_dirty_list;
218a72f7ea6Sql };
219a72f7ea6Sql 
220a72f7ea6Sql struct rtw_descs {
221a72f7ea6Sql 	struct rtw_txdesc	hd_txlo[RTW_NTXDESCLO];
222a72f7ea6Sql 	struct rtw_txdesc	hd_txmd[RTW_NTXDESCMD];
223a72f7ea6Sql 	struct rtw_txdesc	hd_txhi[RTW_NTXDESCHI];
224a72f7ea6Sql 	struct rtw_rxdesc	hd_rx[RTW_RXQLEN];
225a72f7ea6Sql 	struct rtw_txdesc	hd_bcn[RTW_NTXDESCBCN];
226a72f7ea6Sql };
227a72f7ea6Sql #define	RTW_DESC_OFFSET(ring, i)	offsetof(struct rtw_descs, ring[i])
228a72f7ea6Sql #define	RTW_RING_OFFSET(ring)		RTW_DESC_OFFSET(ring, 0)
229a72f7ea6Sql #define	RTW_RING_BASE(baseaddr0, ring) \
230a72f7ea6Sql 	(baseaddr0 + RTW_RING_OFFSET(ring))
231a72f7ea6Sql 
232a72f7ea6Sql /*
233a72f7ea6Sql  * One Time Unit (TU) is 1Kus = 1024 microseconds.
234a72f7ea6Sql  */
235a72f7ea6Sql #define	IEEE80211_DUR_TU		1024
236a72f7ea6Sql 
237a72f7ea6Sql /*
238a72f7ea6Sql  * IEEE 802.11b durations for DSSS PHY in microseconds
239a72f7ea6Sql  */
240a72f7ea6Sql #define	IEEE80211_DUR_DS_LONG_PREAMBLE	144
241a72f7ea6Sql #define	IEEE80211_DUR_DS_SHORT_PREAMBLE	72
242a72f7ea6Sql 
243a72f7ea6Sql #define	IEEE80211_DUR_DS_SLOW_PLCPHDR	48
244a72f7ea6Sql #define	IEEE80211_DUR_DS_FAST_PLCPHDR	24
245a72f7ea6Sql #define	IEEE80211_DUR_DS_SLOW_ACK	112
246a72f7ea6Sql #define	IEEE80211_DUR_DS_FAST_ACK	56
247a72f7ea6Sql #define	IEEE80211_DUR_DS_SLOW_CTS	112
248a72f7ea6Sql #define	IEEE80211_DUR_DS_FAST_CTS	56
249a72f7ea6Sql 
250a72f7ea6Sql #define	IEEE80211_DUR_DS_SLOT		20
251a72f7ea6Sql #define	IEEE80211_DUR_DS_SIFS		10
252a72f7ea6Sql #define	IEEE80211_DUR_DS_PIFS	(IEEE80211_DUR_DS_SIFS + IEEE80211_DUR_DS_SLOT)
253a72f7ea6Sql #define	IEEE80211_DUR_DS_DIFS	(IEEE80211_DUR_DS_SIFS + \
254a72f7ea6Sql 				2 * IEEE80211_DUR_DS_SLOT)
255a72f7ea6Sql #define	IEEE80211_DUR_DS_EIFS	(IEEE80211_DUR_DS_SIFS + \
256a72f7ea6Sql 				IEEE80211_DUR_DS_SLOW_ACK + \
257a72f7ea6Sql 				IEEE80211_DUR_DS_LONG_PREAMBLE + \
258a72f7ea6Sql 				IEEE80211_DUR_DS_SLOW_PLCPHDR + \
259a72f7ea6Sql 				IEEE80211_DUR_DIFS)
260a72f7ea6Sql 
261a72f7ea6Sql /*
262a72f7ea6Sql  * 802.11 frame duration definitions.
263a72f7ea6Sql  */
264a72f7ea6Sql struct rtw_ieee80211_duration {
265a72f7ea6Sql 	uint16_t	d_rts_dur;
266a72f7ea6Sql 	uint16_t	d_data_dur;
267a72f7ea6Sql 	uint16_t	d_plcp_len;
268a72f7ea6Sql 	uint8_t		d_residue;	/* unused octets in time slot */
269a72f7ea6Sql 	uint8_t		resv;
270a72f7ea6Sql };
271a72f7ea6Sql 
272a72f7ea6Sql 
273a72f7ea6Sql #ifdef RTW_RADIOTAP
274a72f7ea6Sql /*
275a72f7ea6Sql  * Radio capture format for RTL8180.
276a72f7ea6Sql  */
277a72f7ea6Sql 
278a72f7ea6Sql #define	RTW_RX_RADIOTAP_PRESENT					\
279a72f7ea6Sql 	((1 << IEEE80211_RADIOTAP_TSFT)			|	\
280a72f7ea6Sql 	(1 << IEEE80211_RADIOTAP_FLAGS)		|	\
281a72f7ea6Sql 	(1 << IEEE80211_RADIOTAP_RATE)			|	\
282a72f7ea6Sql 	(1 << IEEE80211_RADIOTAP_CHANNEL)		|	\
283a72f7ea6Sql 	(1 << IEEE80211_RADIOTAP_LOCK_QUALITY)		|	\
284a72f7ea6Sql 	(1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)		|	\
285a72f7ea6Sql 	0)
286a72f7ea6Sql 
287a72f7ea6Sql struct rtw_rx_radiotap_header {
288a72f7ea6Sql 	struct ieee80211_radiotap_header	rr_ihdr;
289a72f7ea6Sql 	uint64_t				rr_tsft;
290a72f7ea6Sql 	uint8_t				rr_flags;
291a72f7ea6Sql 	uint8_t				rr_rate;
292a72f7ea6Sql 	uint16_t				rr_chan_freq;
293a72f7ea6Sql 	uint16_t				rr_chan_flags;
294a72f7ea6Sql 	uint16_t				rr_barker_lock;
295a72f7ea6Sql 	uint8_t				rr_antsignal;
296a72f7ea6Sql } __attribute__((__packed__));
297a72f7ea6Sql 
298a72f7ea6Sql #define	RTW_TX_RADIOTAP_PRESENT				\
299a72f7ea6Sql 	((1 << IEEE80211_RADIOTAP_FLAGS)	|	\
300a72f7ea6Sql 	(1 << IEEE80211_RADIOTAP_RATE)		|	\
301a72f7ea6Sql 	(1 << IEEE80211_RADIOTAP_CHANNEL)	|	\
302a72f7ea6Sql 	0)
303a72f7ea6Sql 
304a72f7ea6Sql struct rtw_tx_radiotap_header {
305a72f7ea6Sql 	struct ieee80211_radiotap_header	rt_ihdr;
306a72f7ea6Sql 	uint8_t				rt_flags;
307a72f7ea6Sql 	uint8_t				rt_rate;
308a72f7ea6Sql 	uint16_t				rt_chan_freq;
309a72f7ea6Sql 	uint16_t				rt_chan_flags;
310a72f7ea6Sql } __attribute__((__packed__));
311a72f7ea6Sql #endif
312a72f7ea6Sql 
313a72f7ea6Sql enum rtw_attach_state {FINISHED, FINISH_DESCMAP_LOAD, FINISH_DESCMAP_CREATE,
314a72f7ea6Sql 	FINISH_DESC_MAP, FINISH_DESC_ALLOC, FINISH_RXMAPS_CREATE,
315a72f7ea6Sql 	FINISH_TXMAPS_CREATE, FINISH_RESET, FINISH_READ_SROM, FINISH_PARSE_SROM,
316a72f7ea6Sql 	FINISH_RF_ATTACH, FINISH_ID_STA, FINISH_TXDESCBLK_SETUP,
317a72f7ea6Sql 	FINISH_TXCTLBLK_SETUP, DETACHED};
318a72f7ea6Sql 
319a72f7ea6Sql struct rtw_hooks {
320a72f7ea6Sql 	void			*rh_shutdown;	/* shutdown hook */
321a72f7ea6Sql 	void			*rh_power;	/* power management hook */
322a72f7ea6Sql };
323a72f7ea6Sql 
324a72f7ea6Sql enum rtw_pwrstate { RTW_OFF = 0, RTW_SLEEP, RTW_ON };
325a72f7ea6Sql 
326a72f7ea6Sql typedef void (*rtw_continuous_tx_cb_t)(void *arg, int);
327a72f7ea6Sql 
328a72f7ea6Sql struct rtw_phy {
329a72f7ea6Sql 	struct rtw_rf	*p_rf;
330a72f7ea6Sql 	struct rtw_regs	*p_regs;
331a72f7ea6Sql };
332a72f7ea6Sql 
333a72f7ea6Sql struct rtw_bbpset {
334a72f7ea6Sql 	uint_t	bb_antatten;
335a72f7ea6Sql 	uint_t	bb_chestlim;
336a72f7ea6Sql 	uint_t	bb_chsqlim;
337a72f7ea6Sql 	uint_t	bb_ifagcdet;
338a72f7ea6Sql 	uint_t	bb_ifagcini;
339a72f7ea6Sql 	uint_t	bb_ifagclimit;
340a72f7ea6Sql 	uint_t	bb_lnadet;
341a72f7ea6Sql 	uint_t	bb_sys1;
342a72f7ea6Sql 	uint_t	bb_sys2;
343a72f7ea6Sql 	uint_t	bb_sys3;
344a72f7ea6Sql 	uint_t	bb_trl;
345a72f7ea6Sql 	uint_t	bb_txagc;
346a72f7ea6Sql };
347a72f7ea6Sql 
348a72f7ea6Sql struct rtw_rf {
349a72f7ea6Sql 	void	(*rf_destroy)(struct rtw_rf *);
350a72f7ea6Sql 	/*
351a72f7ea6Sql 	 * args: frequency, txpower, power state
352a72f7ea6Sql 	 */
353a72f7ea6Sql 	int	(*rf_init)(struct rtw_rf *, uint_t, uint8_t, enum rtw_pwrstate);
354a72f7ea6Sql 	/*
355a72f7ea6Sql 	 * arg: power state
356a72f7ea6Sql 	 */
357a72f7ea6Sql 	int	(*rf_pwrstate)(struct rtw_rf *, enum rtw_pwrstate);
358a72f7ea6Sql 	/*
359a72f7ea6Sql 	 * arg: frequency
360a72f7ea6Sql 	 */
361a72f7ea6Sql 	int	(*rf_tune)(struct rtw_rf *, uint_t);
362a72f7ea6Sql 	/*
363a72f7ea6Sql 	 * arg: txpower
364a72f7ea6Sql 	 */
365a72f7ea6Sql 	int	(*rf_txpower)(struct rtw_rf *, uint8_t);
366a72f7ea6Sql 	rtw_continuous_tx_cb_t	rf_continuous_tx_cb;
367a72f7ea6Sql 	void			*rf_continuous_tx_arg;
368a72f7ea6Sql 	struct rtw_bbpset	rf_bbpset;
369a72f7ea6Sql };
370a72f7ea6Sql 
371a72f7ea6Sql typedef int (*rtw_rf_write_t)(struct rtw_regs *, enum rtw_rfchipid, uint_t,
372a72f7ea6Sql     uint32_t);
373a72f7ea6Sql 
374a72f7ea6Sql struct rtw_rfbus {
375a72f7ea6Sql 	struct rtw_regs		*b_regs;
376a72f7ea6Sql 	rtw_rf_write_t		b_write;
377a72f7ea6Sql };
378a72f7ea6Sql 
379a72f7ea6Sql struct rtw_max2820 {
380a72f7ea6Sql 	struct rtw_rf		mx_rf;
381a72f7ea6Sql 	struct rtw_rfbus	mx_bus;
382a72f7ea6Sql 	int			mx_is_a;	/* 1: MAX2820A/MAX2821A */
383a72f7ea6Sql };
384a72f7ea6Sql 
385a72f7ea6Sql struct rtw_sa2400 {
386a72f7ea6Sql 	struct rtw_rf		sa_rf;
387a72f7ea6Sql 	struct rtw_rfbus	sa_bus;
388a72f7ea6Sql 	int			sa_digphy;	/* 1: digital PHY */
389a72f7ea6Sql };
390a72f7ea6Sql 
391a72f7ea6Sql typedef void (*rtw_pwrstate_t)(struct rtw_regs *, enum rtw_pwrstate, int, int);
392a72f7ea6Sql 
393a72f7ea6Sql union rtw_keys {
394a72f7ea6Sql 	uint8_t		rk_keys[4][16];
395a72f7ea6Sql 	uint32_t	rk_words[16];
396a72f7ea6Sql };
397a72f7ea6Sql 
398a72f7ea6Sql #define	RTW_LED_SLOW_TICKS	MAX(1, hz/2)
399a72f7ea6Sql #define	RTW_LED_FAST_TICKS	MAX(1, hz/10)
400a72f7ea6Sql 
401a72f7ea6Sql struct rtw_led_state {
402a72f7ea6Sql #define	RTW_LED0	0x1
403a72f7ea6Sql #define	RTW_LED1	0x2
404a72f7ea6Sql 	uint8_t		ls_slowblink:2;
405a72f7ea6Sql 	uint8_t		ls_actblink:2;
406a72f7ea6Sql 	uint8_t		ls_default:2;
407a72f7ea6Sql 	uint8_t		ls_state;
408a72f7ea6Sql 	uint8_t		ls_event;
409a72f7ea6Sql #define	RTW_LED_S_RX	0x1
410a72f7ea6Sql #define	RTW_LED_S_TX	0x2
411a72f7ea6Sql #define	RTW_LED_S_SLOW	0x4
412a72f7ea6Sql };
413a72f7ea6Sql 
414a72f7ea6Sql typedef struct rtw_softc {
415a72f7ea6Sql 	ieee80211com_t		sc_ic;	/* IEEE 802.11 common */
416a72f7ea6Sql 	dev_info_t		*sc_dev; /* back pointer to dev_info_t */
417a72f7ea6Sql 	kmutex_t		sc_genlock;
418a72f7ea6Sql 	struct rtw_regs		sc_regs;
419a72f7ea6Sql 	ddi_acc_handle_t	sc_cfg_handle;
420a72f7ea6Sql 	caddr_t			sc_cfg_base;
421a72f7ea6Sql 	enum ieee80211_phymode	sc_curmode;
422a72f7ea6Sql 	uint32_t		sc_flags;
423a72f7ea6Sql 	uint32_t		sc_invalid;
424a72f7ea6Sql 	ddi_iblock_cookie_t	sc_iblock;
425a72f7ea6Sql 	uint32_t		sc_need_reschedule;
426a72f7ea6Sql 	uint16_t		sc_cachelsz;	/* cache line size */
427a72f7ea6Sql 	uchar_t			sc_macaddr[6];
428a72f7ea6Sql 
429a72f7ea6Sql 	enum rtw_rfchipid	sc_rfchipid;
430a72f7ea6Sql 	enum rtw_locale		sc_locale;
431a72f7ea6Sql 	uint8_t			sc_phydelay;
432a72f7ea6Sql 
433a72f7ea6Sql 	uint32_t		sc_dmabuf_size;
434a72f7ea6Sql 	dma_area_t		sc_desc_dma;
435a72f7ea6Sql 
436a72f7ea6Sql 	struct rtw_txq		sc_txq[RTW_NTXPRI];
437a72f7ea6Sql 
438a72f7ea6Sql 	struct	rtw_rxdesc	*rxdesc_h;
439a72f7ea6Sql 	struct  rtw_rxbuf	*rxbuf_h;
440a72f7ea6Sql 	uint32_t		rx_next;
441a72f7ea6Sql 	kmutex_t		rxbuf_lock;
442a72f7ea6Sql 	kmutex_t		sc_txlock;
443a72f7ea6Sql 
444a72f7ea6Sql 	struct rtw_srom		sc_srom;
445a72f7ea6Sql 	enum rtw_pwrstate	sc_pwrstate;
446a72f7ea6Sql 	rtw_pwrstate_t		sc_pwrstate_cb;
447a72f7ea6Sql 	struct rtw_rf		*sc_rf;
448a72f7ea6Sql 
449a72f7ea6Sql 	uint16_t		sc_inten;
450a72f7ea6Sql 
451a72f7ea6Sql 	void (*sc_intr_ack)(struct rtw_regs *);
452a72f7ea6Sql 
453a72f7ea6Sql 	int			(*sc_enable)(struct rtw_softc *);
454a72f7ea6Sql 	void			(*sc_disable)(struct rtw_softc *);
455a72f7ea6Sql 	void			(*sc_power)(struct rtw_softc *, int);
456a72f7ea6Sql 	struct rtw_hooks	sc_hooks;
457a72f7ea6Sql 
458a72f7ea6Sql 	uint_t			sc_cur_chan;
459a72f7ea6Sql 
460a72f7ea6Sql 	uint32_t		sc_tsfth;	/* most significant TSFT bits */
461a72f7ea6Sql 	uint32_t		sc_rcr;		/* RTW_RCR */
462a72f7ea6Sql 	uint8_t			sc_csthr;	/* carrier-sense threshold */
463a72f7ea6Sql 
464a72f7ea6Sql 	uint8_t			sc_rev;		/* PCI/Cardbus revision */
465a72f7ea6Sql 
466a72f7ea6Sql 	uint32_t		sc_anaparm;	/* register RTW_ANAPARM */
467a72f7ea6Sql #ifdef RTW_RADIOTAP
468a72f7ea6Sql 	union {
469a72f7ea6Sql 		struct rtw_rx_radiotap_header	tap;
470a72f7ea6Sql 		uint8_t			pad[64];
471a72f7ea6Sql 	} sc_rxtapu;
472a72f7ea6Sql 	union {
473a72f7ea6Sql 		struct rtw_tx_radiotap_header	tap;
474a72f7ea6Sql 		uint8_t			pad[64];
475a72f7ea6Sql 	} sc_txtapu;
476a72f7ea6Sql #endif
477a72f7ea6Sql 	union rtw_keys		sc_keys;
478a72f7ea6Sql 	int			sc_txkey;
479a72f7ea6Sql 	struct rtw_led_state	sc_led_state;
480a72f7ea6Sql 	int			sc_hwverid;
481a72f7ea6Sql 
482a72f7ea6Sql 	int			(*sc_newstate)(ieee80211com_t *,
483a72f7ea6Sql 					enum ieee80211_state, int);
484a72f7ea6Sql 
485a72f7ea6Sql 	timeout_id_t		sc_scan_id;
486a72f7ea6Sql 	timeout_id_t		sc_ratectl_id;
487a72f7ea6Sql 	uint32_t		sc_tx_ok;
488a72f7ea6Sql 	uint32_t		sc_tx_err;
489a72f7ea6Sql 	uint32_t		sc_tx_retr;
490a72f7ea6Sql 	uint32_t		sc_xmtretry;
491a72f7ea6Sql 	uint32_t		sc_noxmtbuf;
492a72f7ea6Sql 	uint32_t		sc_norcvbuf;
493a72f7ea6Sql 	uint32_t		sc_bytexmt64;
494a72f7ea6Sql 	uint32_t		sc_bytercv64;
495a72f7ea6Sql 	uint32_t		sc_pktxmt64;
496a72f7ea6Sql 	uint32_t		sc_pktrcv64;
497a72f7ea6Sql 	uint32_t		sc_intr;
498a72f7ea6Sql 	uint32_t		sc_ioerror;
499a72f7ea6Sql 	uint32_t		hw_start;
500a72f7ea6Sql 	uint32_t		hw_go;
501a72f7ea6Sql } rtw_softc_t;
502a72f7ea6Sql 
503a72f7ea6Sql #define	RTW_SC(ic) ((rtw_softc_t *)ic)
5049aa73b68SQin Michael Li #ifdef __cplusplus
5059aa73b68SQin Michael Li }
5069aa73b68SQin Michael Li #endif
507a72f7ea6Sql 
508a72f7ea6Sql #endif /* _RTWVAR_H_ */
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