1*14b24e2bSVaishali Kulkarni /* 2*14b24e2bSVaishali Kulkarni * CDDL HEADER START 3*14b24e2bSVaishali Kulkarni * 4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the 5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1, (the "License"). 6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 7*14b24e2bSVaishali Kulkarni * 8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0. 10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions 11*14b24e2bSVaishali Kulkarni * and limitations under the License. 12*14b24e2bSVaishali Kulkarni * 13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each 14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the 16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying 17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner] 18*14b24e2bSVaishali Kulkarni * 19*14b24e2bSVaishali Kulkarni * CDDL HEADER END 20*14b24e2bSVaishali Kulkarni */ 21*14b24e2bSVaishali Kulkarni 22*14b24e2bSVaishali Kulkarni /* 23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc. 24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development 25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1, (the "License"). 26*14b24e2bSVaishali Kulkarni 27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 28*14b24e2bSVaishali Kulkarni 29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available 30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0 31*14b24e2bSVaishali Kulkarni 32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and 33*14b24e2bSVaishali Kulkarni * limitations under the License. 34*14b24e2bSVaishali Kulkarni */ 35*14b24e2bSVaishali Kulkarni 36*14b24e2bSVaishali Kulkarni #ifndef _QEDE_FP_H 37*14b24e2bSVaishali Kulkarni #define _QEDE_FP_H 38*14b24e2bSVaishali Kulkarni 39*14b24e2bSVaishali Kulkarni #define RX_INDICATE_UPSTREAM(rx_ring, mp) \ 40*14b24e2bSVaishali Kulkarni mac_rx_ring(rx_ring->qede->mac_handle, \ 41*14b24e2bSVaishali Kulkarni rx_ring->mac_ring_handle, mp, \ 42*14b24e2bSVaishali Kulkarni rx_ring->mr_gen_num) 43*14b24e2bSVaishali Kulkarni 44*14b24e2bSVaishali Kulkarni #define MAX_TX_RING_SIZE 8192 45*14b24e2bSVaishali Kulkarni 46*14b24e2bSVaishali Kulkarni #define RESUME_TX(tx_ring) mac_tx_ring_update(tx_ring->qede->mac_handle, \ 47*14b24e2bSVaishali Kulkarni tx_ring->mac_ring_handle) 48*14b24e2bSVaishali Kulkarni 49*14b24e2bSVaishali Kulkarni #define CQE_FLAGS_ERR (PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK << \ 50*14b24e2bSVaishali Kulkarni PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT | \ 51*14b24e2bSVaishali Kulkarni PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK << \ 52*14b24e2bSVaishali Kulkarni PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT | \ 53*14b24e2bSVaishali Kulkarni PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK << \ 54*14b24e2bSVaishali Kulkarni PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT | \ 55*14b24e2bSVaishali Kulkarni PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK << \ 56*14b24e2bSVaishali Kulkarni PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) 57*14b24e2bSVaishali Kulkarni 58*14b24e2bSVaishali Kulkarni /* 59*14b24e2bSVaishali Kulkarni * VB: Keeping such perf. tuning macros as ifndefs so that 60*14b24e2bSVaishali Kulkarni * they can be collectively tuned from Makefile when exp. 61*14b24e2bSVaishali Kulkarni * are to be done 62*14b24e2bSVaishali Kulkarni */ 63*14b24e2bSVaishali Kulkarni #ifndef QEDE_POLL_ALL 64*14b24e2bSVaishali Kulkarni #define QEDE_POLL_ALL INT_MAX 65*14b24e2bSVaishali Kulkarni #endif 66*14b24e2bSVaishali Kulkarni #ifndef QEDE_MAX_RX_PKTS_PER_INTR 67*14b24e2bSVaishali Kulkarni #define QEDE_MAX_RX_PKTS_PER_INTR 128 68*14b24e2bSVaishali Kulkarni #endif 69*14b24e2bSVaishali Kulkarni 70*14b24e2bSVaishali Kulkarni #ifndef QEDE_TX_MAP_PATH_PAUSE_THRESHOLD 71*14b24e2bSVaishali Kulkarni #define QEDE_TX_MAP_PATH_PAUSE_THRESHOLD 128 72*14b24e2bSVaishali Kulkarni #endif 73*14b24e2bSVaishali Kulkarni 74*14b24e2bSVaishali Kulkarni #ifndef QEDE_TX_COPY_PATH_PAUSE_THRESHOLD 75*14b24e2bSVaishali Kulkarni #define QEDE_TX_COPY_PATH_PAUSE_THRESHOLD 8 76*14b24e2bSVaishali Kulkarni #endif 77*14b24e2bSVaishali Kulkarni 78*14b24e2bSVaishali Kulkarni #define ETHER_VLAN_HEADER_LEN sizeof (struct ether_vlan_header) 79*14b24e2bSVaishali Kulkarni #define ETHER_HEADER_LEN sizeof (struct ether_header) 80*14b24e2bSVaishali Kulkarni #define IP_HEADER_LEN sizeof (ipha_t) 81*14b24e2bSVaishali Kulkarni 82*14b24e2bSVaishali Kulkarni #ifndef MBLKL 83*14b24e2bSVaishali Kulkarni #define MBLKL(_mp_) ((uintptr_t)(_mp_)->b_wptr - (uintptr_t)(_mp_)->b_rptr) 84*14b24e2bSVaishali Kulkarni #endif 85*14b24e2bSVaishali Kulkarni 86*14b24e2bSVaishali Kulkarni #define UPDATE_RX_PROD(_ptr, data) \ 87*14b24e2bSVaishali Kulkarni internal_ram_wr(&(_ptr)->qede->edev.hwfns[0], \ 88*14b24e2bSVaishali Kulkarni (_ptr)->hw_rxq_prod_addr, sizeof (data), \ 89*14b24e2bSVaishali Kulkarni (u32 *)&data); 90*14b24e2bSVaishali Kulkarni 91*14b24e2bSVaishali Kulkarni #define BD_SET_ADDR_LEN(_bd, _addr, _len) \ 92*14b24e2bSVaishali Kulkarni do { \ 93*14b24e2bSVaishali Kulkarni (_bd)->addr.hi = HOST_TO_LE_32(U64_HI(_addr)); \ 94*14b24e2bSVaishali Kulkarni (_bd)->addr.lo = HOST_TO_LE_32(U64_LO(_addr)); \ 95*14b24e2bSVaishali Kulkarni (_bd)->nbytes = HOST_TO_LE_32(_len); \ 96*14b24e2bSVaishali Kulkarni } while (0) 97*14b24e2bSVaishali Kulkarni 98*14b24e2bSVaishali Kulkarni enum qede_xmit_mode { 99*14b24e2bSVaishali Kulkarni XMIT_MODE_UNUSED, 100*14b24e2bSVaishali Kulkarni USE_DMA_BIND, 101*14b24e2bSVaishali Kulkarni USE_BCOPY, 102*14b24e2bSVaishali Kulkarni USE_PULLUP 103*14b24e2bSVaishali Kulkarni }; 104*14b24e2bSVaishali Kulkarni 105*14b24e2bSVaishali Kulkarni enum qede_xmit_status { 106*14b24e2bSVaishali Kulkarni XMIT_FAILED, 107*14b24e2bSVaishali Kulkarni XMIT_DONE, 108*14b24e2bSVaishali Kulkarni XMIT_FALLBACK_BCOPY, 109*14b24e2bSVaishali Kulkarni XMIT_FALLBACK_PULLUP, 110*14b24e2bSVaishali Kulkarni XMIT_PAUSE_QUEUE, 111*14b24e2bSVaishali Kulkarni XMIT_TOO_MANY_COOKIES 112*14b24e2bSVaishali Kulkarni }; 113*14b24e2bSVaishali Kulkarni 114*14b24e2bSVaishali Kulkarni /* 115*14b24e2bSVaishali Kulkarni * Maintain the metadata of the 116*14b24e2bSVaishali Kulkarni * tx packet in one place 117*14b24e2bSVaishali Kulkarni */ 118*14b24e2bSVaishali Kulkarni typedef struct qede_tx_pktinfo_s { 119*14b24e2bSVaishali Kulkarni u32 total_len; 120*14b24e2bSVaishali Kulkarni u32 mblk_no; 121*14b24e2bSVaishali Kulkarni u32 cksum_flags; 122*14b24e2bSVaishali Kulkarni 123*14b24e2bSVaishali Kulkarni /* tso releated */ 124*14b24e2bSVaishali Kulkarni bool use_lso; 125*14b24e2bSVaishali Kulkarni u16 mss; 126*14b24e2bSVaishali Kulkarni 127*14b24e2bSVaishali Kulkarni bool pulled_up; 128*14b24e2bSVaishali Kulkarni 129*14b24e2bSVaishali Kulkarni /* hdr parse data */ 130*14b24e2bSVaishali Kulkarni u16 ether_type; 131*14b24e2bSVaishali Kulkarni u16 mac_hlen; 132*14b24e2bSVaishali Kulkarni u16 ip_hlen; 133*14b24e2bSVaishali Kulkarni u16 l4_hlen; 134*14b24e2bSVaishali Kulkarni u16 total_hlen; 135*14b24e2bSVaishali Kulkarni u16 l4_proto; 136*14b24e2bSVaishali Kulkarni u16 vlan_tag; 137*14b24e2bSVaishali Kulkarni } qede_tx_pktinfo_t; 138*14b24e2bSVaishali Kulkarni 139*14b24e2bSVaishali Kulkarni typedef struct qede_tx_bcopy_pkt_s { 140*14b24e2bSVaishali Kulkarni mblk_t *mp; 141*14b24e2bSVaishali Kulkarni ddi_acc_handle_t acc_handle; 142*14b24e2bSVaishali Kulkarni ddi_dma_handle_t dma_handle; 143*14b24e2bSVaishali Kulkarni u32 ncookies; 144*14b24e2bSVaishali Kulkarni u32 offset; 145*14b24e2bSVaishali Kulkarni u64 phys_addr; 146*14b24e2bSVaishali Kulkarni void *virt_addr; 147*14b24e2bSVaishali Kulkarni u32 padding; 148*14b24e2bSVaishali Kulkarni } qede_tx_bcopy_pkt_t; 149*14b24e2bSVaishali Kulkarni 150*14b24e2bSVaishali Kulkarni typedef struct qede_tx_bcopy_list_s { 151*14b24e2bSVaishali Kulkarni qede_tx_bcopy_pkt_t *bcopy_pool; 152*14b24e2bSVaishali Kulkarni qede_tx_bcopy_pkt_t *free_list[MAX_TX_RING_SIZE]; 153*14b24e2bSVaishali Kulkarni u16 head; 154*14b24e2bSVaishali Kulkarni u16 tail; 155*14b24e2bSVaishali Kulkarni kmutex_t lock; 156*14b24e2bSVaishali Kulkarni size_t size; 157*14b24e2bSVaishali Kulkarni } qede_tx_bcopy_list_t; 158*14b24e2bSVaishali Kulkarni 159*14b24e2bSVaishali Kulkarni typedef struct qede_dma_handle_entry_s { 160*14b24e2bSVaishali Kulkarni mblk_t *mp; 161*14b24e2bSVaishali Kulkarni ddi_dma_handle_t dma_handle; 162*14b24e2bSVaishali Kulkarni struct qede_dma_handle_entry_s *next; 163*14b24e2bSVaishali Kulkarni } qede_dma_handle_entry_t; 164*14b24e2bSVaishali Kulkarni 165*14b24e2bSVaishali Kulkarni typedef struct qede_dma_handles_list_s { 166*14b24e2bSVaishali Kulkarni qede_dma_handle_entry_t *dmah_pool; 167*14b24e2bSVaishali Kulkarni qede_dma_handle_entry_t *free_list[MAX_TX_RING_SIZE]; 168*14b24e2bSVaishali Kulkarni u16 head; 169*14b24e2bSVaishali Kulkarni u16 tail; 170*14b24e2bSVaishali Kulkarni kmutex_t lock; 171*14b24e2bSVaishali Kulkarni size_t size; 172*14b24e2bSVaishali Kulkarni } qede_dma_handles_list_t; 173*14b24e2bSVaishali Kulkarni 174*14b24e2bSVaishali Kulkarni typedef struct qede_tx_recycle_list_s { 175*14b24e2bSVaishali Kulkarni qede_tx_bcopy_pkt_t *bcopy_pkt; 176*14b24e2bSVaishali Kulkarni qede_dma_handle_entry_t *dmah_entry; 177*14b24e2bSVaishali Kulkarni } qede_tx_recycle_list_t; 178*14b24e2bSVaishali Kulkarni 179*14b24e2bSVaishali Kulkarni mblk_t *qede_ring_tx(void *arg, mblk_t *mp); 180*14b24e2bSVaishali Kulkarni 181*14b24e2bSVaishali Kulkarni #endif /* !_QEDE_FP_H */ 182