1*14b24e2bSVaishali Kulkarni /* 2*14b24e2bSVaishali Kulkarni * CDDL HEADER START 3*14b24e2bSVaishali Kulkarni * 4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the 5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1, (the "License"). 6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 7*14b24e2bSVaishali Kulkarni * 8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0. 10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions 11*14b24e2bSVaishali Kulkarni * and limitations under the License. 12*14b24e2bSVaishali Kulkarni * 13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each 14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the 16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying 17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner] 18*14b24e2bSVaishali Kulkarni * 19*14b24e2bSVaishali Kulkarni * CDDL HEADER END 20*14b24e2bSVaishali Kulkarni */ 21*14b24e2bSVaishali Kulkarni 22*14b24e2bSVaishali Kulkarni /* 23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc. 24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development 25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1, (the "License"). 26*14b24e2bSVaishali Kulkarni 27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 28*14b24e2bSVaishali Kulkarni 29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available 30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0 31*14b24e2bSVaishali Kulkarni 32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and 33*14b24e2bSVaishali Kulkarni * limitations under the License. 34*14b24e2bSVaishali Kulkarni */ 35*14b24e2bSVaishali Kulkarni 36*14b24e2bSVaishali Kulkarni /**************************************************************************** 37*14b24e2bSVaishali Kulkarni * 38*14b24e2bSVaishali Kulkarni * Name: nvm_cfg.h 39*14b24e2bSVaishali Kulkarni * 40*14b24e2bSVaishali Kulkarni * Description: NVM config file - Generated file from nvm cfg excel. 41*14b24e2bSVaishali Kulkarni * DO NOT MODIFY !!! 42*14b24e2bSVaishali Kulkarni * 43*14b24e2bSVaishali Kulkarni * Created: 3/15/2017 44*14b24e2bSVaishali Kulkarni * 45*14b24e2bSVaishali Kulkarni ****************************************************************************/ 46*14b24e2bSVaishali Kulkarni 47*14b24e2bSVaishali Kulkarni #ifndef NVM_CFG_H 48*14b24e2bSVaishali Kulkarni #define NVM_CFG_H 49*14b24e2bSVaishali Kulkarni 50*14b24e2bSVaishali Kulkarni #define NVM_CFG_version 0x81819 51*14b24e2bSVaishali Kulkarni 52*14b24e2bSVaishali Kulkarni #define NVM_CFG_new_option_seq 22 53*14b24e2bSVaishali Kulkarni 54*14b24e2bSVaishali Kulkarni #define NVM_CFG_removed_option_seq 1 55*14b24e2bSVaishali Kulkarni 56*14b24e2bSVaishali Kulkarni #define NVM_CFG_updated_value_seq 4 57*14b24e2bSVaishali Kulkarni 58*14b24e2bSVaishali Kulkarni struct nvm_cfg_mac_address 59*14b24e2bSVaishali Kulkarni { 60*14b24e2bSVaishali Kulkarni u32 mac_addr_hi; 61*14b24e2bSVaishali Kulkarni #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF 62*14b24e2bSVaishali Kulkarni #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 63*14b24e2bSVaishali Kulkarni u32 mac_addr_lo; 64*14b24e2bSVaishali Kulkarni }; 65*14b24e2bSVaishali Kulkarni 66*14b24e2bSVaishali Kulkarni /****************************************** 67*14b24e2bSVaishali Kulkarni * nvm_cfg1 structs 68*14b24e2bSVaishali Kulkarni ******************************************/ 69*14b24e2bSVaishali Kulkarni struct nvm_cfg1_glob 70*14b24e2bSVaishali Kulkarni { 71*14b24e2bSVaishali Kulkarni u32 generic_cont0; /* 0x0 */ 72*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F 73*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0 74*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0 75*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1 76*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2 77*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3 78*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 79*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 80*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 81*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 82*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 83*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 84*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 85*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 86*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 87*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 88*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000 89*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12 90*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0 91*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1 92*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000 93*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13 94*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000 95*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21 96*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000 97*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29 98*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0 99*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1 100*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000 101*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30 102*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0 103*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1 104*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_MASK 0x80000000 105*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_OFFSET 31 106*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_DISABLED 0x0 107*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_ENABLED 0x1 108*14b24e2bSVaishali Kulkarni u32 engineering_change[3]; /* 0x4 */ 109*14b24e2bSVaishali Kulkarni u32 manufacturing_id; /* 0x10 */ 110*14b24e2bSVaishali Kulkarni u32 serial_number[4]; /* 0x14 */ 111*14b24e2bSVaishali Kulkarni u32 pcie_cfg; /* 0x24 */ 112*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003 113*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0 114*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0 115*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1 116*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2 117*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004 118*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2 119*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0 120*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1 121*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018 122*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3 123*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0 124*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1 125*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2 126*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3 127*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK 0x00000020 128*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5 129*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0 130*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6 131*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00 132*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10 133*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0 134*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1 135*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2 136*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3 137*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000 138*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13 139*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000 140*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21 141*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000 142*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29 143*14b24e2bSVaishali Kulkarni /* Set the duration, in seconds, fan failure signal should be 144*14b24e2bSVaishali Kulkarni sampled */ 145*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK 0x80000000 146*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31 147*14b24e2bSVaishali Kulkarni u32 mgmt_traffic; /* 0x28 */ 148*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001 149*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0 150*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE 151*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1 152*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00 153*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9 154*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000 155*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17 156*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000 157*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25 158*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0 159*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1 160*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2 161*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000 162*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27 163*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0 164*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1 165*14b24e2bSVaishali Kulkarni /* Indicates whether external thermal sonsor is available */ 166*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000 167*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31 168*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0 169*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1 170*14b24e2bSVaishali Kulkarni u32 core_cfg; /* 0x2C */ 171*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF 172*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 173*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0 174*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1 175*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2 176*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3 177*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4 178*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5 179*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB 180*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC 181*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD 182*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE 183*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF 184*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100 185*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8 186*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0 187*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1 188*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200 189*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9 190*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0 191*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1 192*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00 193*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10 194*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000 195*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18 196*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000 197*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26 198*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0 199*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1 200*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2 201*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3 202*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000 203*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29 204*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0 205*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1 206*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_DCI_SUPPORT_MASK 0x80000000 207*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_DCI_SUPPORT_OFFSET 31 208*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_DCI_SUPPORT_DISABLED 0x0 209*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_DCI_SUPPORT_ENABLED 0x1 210*14b24e2bSVaishali Kulkarni u32 e_lane_cfg1; /* 0x30 */ 211*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F 212*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 213*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 214*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 215*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 216*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 217*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 218*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 219*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 220*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 221*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 222*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 223*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 224*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 225*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 226*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 227*14b24e2bSVaishali Kulkarni u32 e_lane_cfg2; /* 0x34 */ 228*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 229*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 230*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 231*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 232*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 233*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 234*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 235*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 236*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 237*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 238*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 239*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 240*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 241*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 242*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 243*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 244*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00 245*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8 246*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0 247*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1 248*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2 249*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000 250*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NCSI_OFFSET 12 251*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0 252*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1 253*14b24e2bSVaishali Kulkarni /* Maximum advertised pcie link width */ 254*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000 255*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16 256*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0 257*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1 258*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2 259*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3 260*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4 261*14b24e2bSVaishali Kulkarni /* ASPM L1 mode */ 262*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000 263*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20 264*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0 265*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1 266*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000 267*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22 268*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0 269*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1 270*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2 271*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3 272*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK 0x06000000 273*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25 274*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0 275*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1 276*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2 277*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3 278*14b24e2bSVaishali Kulkarni /* Set the PLDM sensor modes */ 279*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000 280*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27 281*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0 282*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1 283*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2 284*14b24e2bSVaishali Kulkarni /* Enable VDM interface */ 285*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_MASK 0x40000000 286*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_OFFSET 30 287*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_DISABLED 0x0 288*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_ENABLED 0x1 289*14b24e2bSVaishali Kulkarni /* ROL enable */ 290*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESET_ON_LAN_MASK 0x80000000 291*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESET_ON_LAN_OFFSET 31 292*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESET_ON_LAN_DISABLED 0x0 293*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RESET_ON_LAN_ENABLED 0x1 294*14b24e2bSVaishali Kulkarni u32 f_lane_cfg1; /* 0x38 */ 295*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F 296*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 297*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 298*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 299*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 300*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 301*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 302*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 303*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 304*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 305*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 306*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 307*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 308*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 309*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 310*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 311*14b24e2bSVaishali Kulkarni u32 f_lane_cfg2; /* 0x3C */ 312*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 313*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 314*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 315*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 316*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 317*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 318*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 319*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 320*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 321*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 322*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 323*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 324*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 325*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 326*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 327*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 328*14b24e2bSVaishali Kulkarni /* Control the period between two successive checks */ 329*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK 0x0000FF00 330*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8 331*14b24e2bSVaishali Kulkarni /* Set shutdown temperature */ 332*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK 0x00FF0000 333*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16 334*14b24e2bSVaishali Kulkarni /* Set max. count for over operational temperature */ 335*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000 336*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24 337*14b24e2bSVaishali Kulkarni u32 mps10_preemphasis; /* 0x40 */ 338*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF 339*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 340*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 341*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 342*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 343*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 344*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 345*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 346*14b24e2bSVaishali Kulkarni u32 mps10_driver_current; /* 0x44 */ 347*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF 348*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 349*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 350*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 351*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 352*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 353*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 354*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 355*14b24e2bSVaishali Kulkarni u32 mps25_preemphasis; /* 0x48 */ 356*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF 357*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 358*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 359*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 360*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 361*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 362*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 363*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 364*14b24e2bSVaishali Kulkarni u32 mps25_driver_current; /* 0x4C */ 365*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF 366*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 367*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 368*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 369*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 370*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 371*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 372*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 373*14b24e2bSVaishali Kulkarni u32 pci_id; /* 0x50 */ 374*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF 375*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0 376*14b24e2bSVaishali Kulkarni /* Set caution temperature */ 377*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_MASK 0x00FF0000 378*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET 16 379*14b24e2bSVaishali Kulkarni /* Set external thermal sensor I2C address */ 380*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK 0xFF000000 381*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24 382*14b24e2bSVaishali Kulkarni u32 pci_subsys_id; /* 0x54 */ 383*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF 384*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0 385*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000 386*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16 387*14b24e2bSVaishali Kulkarni u32 bar; /* 0x58 */ 388*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F 389*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0 390*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0 391*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1 392*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2 393*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3 394*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4 395*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5 396*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6 397*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7 398*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8 399*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9 400*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA 401*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB 402*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC 403*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD 404*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE 405*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF 406*14b24e2bSVaishali Kulkarni /* BB VF BAR2 size */ 407*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0 408*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4 409*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0 410*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1 411*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2 412*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3 413*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4 414*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5 415*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6 416*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7 417*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8 418*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9 419*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA 420*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB 421*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC 422*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD 423*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE 424*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF 425*14b24e2bSVaishali Kulkarni /* BB BAR2 size (global) */ 426*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00 427*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8 428*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0 429*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1 430*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2 431*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3 432*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4 433*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5 434*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6 435*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7 436*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8 437*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9 438*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA 439*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB 440*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC 441*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD 442*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE 443*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF 444*14b24e2bSVaishali Kulkarni /* Set the duration, in seconds, fan failure signal should be 445*14b24e2bSVaishali Kulkarni sampled */ 446*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000 447*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12 448*14b24e2bSVaishali Kulkarni /* This field defines the board total budget for bar2 when disabled 449*14b24e2bSVaishali Kulkarni the regular bar size is used. */ 450*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000 451*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16 452*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0 453*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1 454*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2 455*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3 456*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4 457*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5 458*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6 459*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7 460*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8 461*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9 462*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA 463*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB 464*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC 465*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD 466*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE 467*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF 468*14b24e2bSVaishali Kulkarni /* Enable/Disable Crash dump triggers */ 469*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000 470*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24 471*14b24e2bSVaishali Kulkarni u32 mps10_txfir_main; /* 0x5C */ 472*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF 473*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 474*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 475*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 476*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 477*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 478*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 479*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 480*14b24e2bSVaishali Kulkarni u32 mps10_txfir_post; /* 0x60 */ 481*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF 482*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 483*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 484*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 485*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 486*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 487*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 488*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 489*14b24e2bSVaishali Kulkarni u32 mps25_txfir_main; /* 0x64 */ 490*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF 491*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 492*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 493*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 494*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 495*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 496*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 497*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 498*14b24e2bSVaishali Kulkarni u32 mps25_txfir_post; /* 0x68 */ 499*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF 500*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 501*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 502*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 503*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 504*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 505*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 506*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 507*14b24e2bSVaishali Kulkarni u32 manufacture_ver; /* 0x6C */ 508*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F 509*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0 510*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0 511*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6 512*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000 513*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12 514*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000 515*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18 516*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000 517*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24 518*14b24e2bSVaishali Kulkarni /* Select package id method */ 519*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_MASK 0x40000000 520*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_OFFSET 30 521*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_NVRAM 0x0 522*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_IO_PINS 0x1 523*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RECOVERY_MODE_MASK 0x80000000 524*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RECOVERY_MODE_OFFSET 31 525*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RECOVERY_MODE_DISABLED 0x0 526*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RECOVERY_MODE_ENABLED 0x1 527*14b24e2bSVaishali Kulkarni u32 manufacture_time; /* 0x70 */ 528*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F 529*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0 530*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0 531*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6 532*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000 533*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12 534*14b24e2bSVaishali Kulkarni /* Max MSIX for Ethernet in default mode */ 535*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_MSIX_MASK 0x03FC0000 536*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_MSIX_OFFSET 18 537*14b24e2bSVaishali Kulkarni /* PF Mapping */ 538*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PF_MAPPING_MASK 0x0C000000 539*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PF_MAPPING_OFFSET 26 540*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS 0x0 541*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PF_MAPPING_FIXED 0x1 542*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_MASK 0x30000000 543*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_OFFSET 28 544*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_DISABLED 0x0 545*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_TI 0x1 546*14b24e2bSVaishali Kulkarni u32 led_global_settings; /* 0x74 */ 547*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F 548*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0 549*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0 550*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4 551*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00 552*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8 553*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000 554*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12 555*14b24e2bSVaishali Kulkarni /* Max. continues operating temperature */ 556*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_MASK 0x00FF0000 557*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_OFFSET 16 558*14b24e2bSVaishali Kulkarni /* GPIO which triggers run-time port swap according to the map 559*14b24e2bSVaishali Kulkarni specified in option 205 */ 560*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_MASK 0xFF000000 561*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_OFFSET 24 562*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_NA 0x0 563*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO0 0x1 564*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO1 0x2 565*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO2 0x3 566*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO3 0x4 567*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO4 0x5 568*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO5 0x6 569*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO6 0x7 570*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO7 0x8 571*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO8 0x9 572*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO9 0xA 573*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO10 0xB 574*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO11 0xC 575*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO12 0xD 576*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO13 0xE 577*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO14 0xF 578*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO15 0x10 579*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO16 0x11 580*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO17 0x12 581*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO18 0x13 582*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO19 0x14 583*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO20 0x15 584*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO21 0x16 585*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO22 0x17 586*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO23 0x18 587*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO24 0x19 588*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO25 0x1A 589*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO26 0x1B 590*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO27 0x1C 591*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO28 0x1D 592*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO29 0x1E 593*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO30 0x1F 594*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO31 0x20 595*14b24e2bSVaishali Kulkarni u32 generic_cont1; /* 0x78 */ 596*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF 597*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0 598*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00 599*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10 600*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000 601*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12 602*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000 603*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14 604*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000 605*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16 606*14b24e2bSVaishali Kulkarni /* Enable option 195 - Overriding the PCIe Preset value */ 607*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK 0x00040000 608*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_OFFSET 18 609*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED 0x0 610*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED 0x1 611*14b24e2bSVaishali Kulkarni /* PCIe Preset value - applies only if option 194 is enabled */ 612*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK 0x00780000 613*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_OFFSET 19 614*14b24e2bSVaishali Kulkarni /* Port mapping to be used when the run-time GPIO for port-swap is 615*14b24e2bSVaishali Kulkarni defined and set. */ 616*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_MASK 0x01800000 617*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_OFFSET 23 618*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_MASK 0x06000000 619*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_OFFSET 25 620*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_MASK 0x18000000 621*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_OFFSET 27 622*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK 0x60000000 623*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_OFFSET 29 624*14b24e2bSVaishali Kulkarni u32 mbi_version; /* 0x7C */ 625*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF 626*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 627*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00 628*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 629*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000 630*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 631*14b24e2bSVaishali Kulkarni /* If set to other than NA, 0 - Normal operation, 1 - Thermal event 632*14b24e2bSVaishali Kulkarni occurred */ 633*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_MASK 0xFF000000 634*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_OFFSET 24 635*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_NA 0x0 636*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO0 0x1 637*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO1 0x2 638*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO2 0x3 639*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO3 0x4 640*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO4 0x5 641*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO5 0x6 642*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO6 0x7 643*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO7 0x8 644*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO8 0x9 645*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO9 0xA 646*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO10 0xB 647*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO11 0xC 648*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO12 0xD 649*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO13 0xE 650*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO14 0xF 651*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO15 0x10 652*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO16 0x11 653*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO17 0x12 654*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO18 0x13 655*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO19 0x14 656*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO20 0x15 657*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO21 0x16 658*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO22 0x17 659*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO23 0x18 660*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO24 0x19 661*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO25 0x1A 662*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO26 0x1B 663*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO27 0x1C 664*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO28 0x1D 665*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO29 0x1E 666*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO30 0x1F 667*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO31 0x20 668*14b24e2bSVaishali Kulkarni u32 mbi_date; /* 0x80 */ 669*14b24e2bSVaishali Kulkarni u32 misc_sig; /* 0x84 */ 670*14b24e2bSVaishali Kulkarni /* Define the GPIO mapping to switch i2c mux */ 671*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF 672*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0 673*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00 674*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8 675*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0 676*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1 677*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2 678*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3 679*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4 680*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5 681*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6 682*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7 683*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8 684*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9 685*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA 686*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB 687*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC 688*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD 689*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE 690*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF 691*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10 692*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11 693*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12 694*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13 695*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14 696*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15 697*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16 698*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17 699*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18 700*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19 701*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A 702*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B 703*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C 704*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D 705*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E 706*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F 707*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20 708*14b24e2bSVaishali Kulkarni /* Interrupt signal used for SMBus/I2C management interface 709*14b24e2bSVaishali Kulkarni 710*14b24e2bSVaishali Kulkarni 0 = Interrupt event occurred 711*14b24e2bSVaishali Kulkarni 1 = Normal 712*14b24e2bSVaishali Kulkarni */ 713*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_MASK 0x00FF0000 714*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_OFFSET 16 715*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_NA 0x0 716*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO0 0x1 717*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO1 0x2 718*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO2 0x3 719*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO3 0x4 720*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO4 0x5 721*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO5 0x6 722*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO6 0x7 723*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO7 0x8 724*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO8 0x9 725*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO9 0xA 726*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO10 0xB 727*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO11 0xC 728*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO12 0xD 729*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO13 0xE 730*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO14 0xF 731*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO15 0x10 732*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO16 0x11 733*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO17 0x12 734*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO18 0x13 735*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO19 0x14 736*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO20 0x15 737*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO21 0x16 738*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO22 0x17 739*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO23 0x18 740*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO24 0x19 741*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO25 0x1A 742*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO26 0x1B 743*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO27 0x1C 744*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO28 0x1D 745*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO29 0x1E 746*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO30 0x1F 747*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO31 0x20 748*14b24e2bSVaishali Kulkarni /* Set aLOM FAN on GPIO */ 749*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_MASK 0xFF000000 750*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_OFFSET 24 751*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_NA 0x0 752*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO0 0x1 753*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO1 0x2 754*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO2 0x3 755*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO3 0x4 756*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO4 0x5 757*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO5 0x6 758*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO6 0x7 759*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO7 0x8 760*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO8 0x9 761*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO9 0xA 762*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO10 0xB 763*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO11 0xC 764*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO12 0xD 765*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO13 0xE 766*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO14 0xF 767*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO15 0x10 768*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO16 0x11 769*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO17 0x12 770*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO18 0x13 771*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO19 0x14 772*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO20 0x15 773*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO21 0x16 774*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO22 0x17 775*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO23 0x18 776*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO24 0x19 777*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO25 0x1A 778*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO26 0x1B 779*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO27 0x1C 780*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO28 0x1D 781*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO29 0x1E 782*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO30 0x1F 783*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO31 0x20 784*14b24e2bSVaishali Kulkarni u32 device_capabilities; /* 0x88 */ 785*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 786*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2 787*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4 788*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8 789*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10 790*14b24e2bSVaishali Kulkarni u32 power_dissipated; /* 0x8C */ 791*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF 792*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0 793*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00 794*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8 795*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000 796*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16 797*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000 798*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24 799*14b24e2bSVaishali Kulkarni u32 power_consumed; /* 0x90 */ 800*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF 801*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0 802*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00 803*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8 804*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000 805*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16 806*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000 807*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24 808*14b24e2bSVaishali Kulkarni u32 efi_version; /* 0x94 */ 809*14b24e2bSVaishali Kulkarni u32 multi_network_modes_capability; /* 0x98 */ 810*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1 811*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2 812*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4 813*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8 814*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10 815*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20 816*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40 817*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G 0x80 818*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100 819*14b24e2bSVaishali Kulkarni u32 nvm_cfg_version; /* 0x9C */ 820*14b24e2bSVaishali Kulkarni u32 nvm_cfg_new_option_seq; /* 0xA0 */ 821*14b24e2bSVaishali Kulkarni u32 nvm_cfg_removed_option_seq; /* 0xA4 */ 822*14b24e2bSVaishali Kulkarni u32 nvm_cfg_updated_value_seq; /* 0xA8 */ 823*14b24e2bSVaishali Kulkarni u32 extended_serial_number[8]; /* 0xAC */ 824*14b24e2bSVaishali Kulkarni u32 oem1_number[8]; /* 0xCC */ 825*14b24e2bSVaishali Kulkarni u32 oem2_number[8]; /* 0xEC */ 826*14b24e2bSVaishali Kulkarni u32 mps25_active_txfir_pre; /* 0x10C */ 827*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_MASK 0x000000FF 828*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_OFFSET 0 829*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_MASK 0x0000FF00 830*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_OFFSET 8 831*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_MASK 0x00FF0000 832*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_OFFSET 16 833*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_MASK 0xFF000000 834*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_OFFSET 24 835*14b24e2bSVaishali Kulkarni u32 mps25_active_txfir_main; /* 0x110 */ 836*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_MASK 0x000000FF 837*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_OFFSET 0 838*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_MASK 0x0000FF00 839*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_OFFSET 8 840*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_MASK 0x00FF0000 841*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_OFFSET 16 842*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_MASK 0xFF000000 843*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_OFFSET 24 844*14b24e2bSVaishali Kulkarni u32 mps25_active_txfir_post; /* 0x114 */ 845*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_MASK 0x000000FF 846*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_OFFSET 0 847*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_MASK 0x0000FF00 848*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_OFFSET 8 849*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_MASK 0x00FF0000 850*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_OFFSET 16 851*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_MASK 0xFF000000 852*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_OFFSET 24 853*14b24e2bSVaishali Kulkarni u32 features; /* 0x118 */ 854*14b24e2bSVaishali Kulkarni /* Set the Aux Fan on temperature */ 855*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_MASK 0x000000FF 856*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_OFFSET 0 857*14b24e2bSVaishali Kulkarni /* Set NC-SI package ID */ 858*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_MASK 0x0000FF00 859*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_OFFSET 8 860*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_NA 0x0 861*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO0 0x1 862*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO1 0x2 863*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO2 0x3 864*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO3 0x4 865*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO4 0x5 866*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO5 0x6 867*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO6 0x7 868*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO7 0x8 869*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO8 0x9 870*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO9 0xA 871*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO10 0xB 872*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO11 0xC 873*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO12 0xD 874*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO13 0xE 875*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO14 0xF 876*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO15 0x10 877*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO16 0x11 878*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO17 0x12 879*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO18 0x13 880*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO19 0x14 881*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO20 0x15 882*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO21 0x16 883*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO22 0x17 884*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO23 0x18 885*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO24 0x19 886*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO25 0x1A 887*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO26 0x1B 888*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO27 0x1C 889*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO28 0x1D 890*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO29 0x1E 891*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO30 0x1F 892*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO31 0x20 893*14b24e2bSVaishali Kulkarni /* PMBUS Clock GPIO */ 894*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_MASK 0x00FF0000 895*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_OFFSET 16 896*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_NA 0x0 897*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO0 0x1 898*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO1 0x2 899*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO2 0x3 900*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO3 0x4 901*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO4 0x5 902*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO5 0x6 903*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO6 0x7 904*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO7 0x8 905*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO8 0x9 906*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO9 0xA 907*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO10 0xB 908*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO11 0xC 909*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO12 0xD 910*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO13 0xE 911*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO14 0xF 912*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO15 0x10 913*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO16 0x11 914*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO17 0x12 915*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO18 0x13 916*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO19 0x14 917*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO20 0x15 918*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO21 0x16 919*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO22 0x17 920*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO23 0x18 921*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO24 0x19 922*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO25 0x1A 923*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO26 0x1B 924*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO27 0x1C 925*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO28 0x1D 926*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO29 0x1E 927*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO30 0x1F 928*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO31 0x20 929*14b24e2bSVaishali Kulkarni /* PMBUS Data GPIO */ 930*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_MASK 0xFF000000 931*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_OFFSET 24 932*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_NA 0x0 933*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO0 0x1 934*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO1 0x2 935*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO2 0x3 936*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO3 0x4 937*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO4 0x5 938*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO5 0x6 939*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO6 0x7 940*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO7 0x8 941*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO8 0x9 942*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO9 0xA 943*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO10 0xB 944*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO11 0xC 945*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO12 0xD 946*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO13 0xE 947*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO14 0xF 948*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO15 0x10 949*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO16 0x11 950*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO17 0x12 951*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO18 0x13 952*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO19 0x14 953*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO20 0x15 954*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO21 0x16 955*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO22 0x17 956*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO23 0x18 957*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO24 0x19 958*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO25 0x1A 959*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO26 0x1B 960*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO27 0x1C 961*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO28 0x1D 962*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO29 0x1E 963*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO30 0x1F 964*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO31 0x20 965*14b24e2bSVaishali Kulkarni u32 tx_rx_eq_25g_hlpc; /* 0x11C */ 966*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_MASK 0x000000FF 967*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_OFFSET 0 968*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_MASK 0x0000FF00 969*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_OFFSET 8 970*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_MASK 0x00FF0000 971*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_OFFSET 16 972*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_MASK 0xFF000000 973*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_OFFSET 24 974*14b24e2bSVaishali Kulkarni u32 tx_rx_eq_25g_llpc; /* 0x120 */ 975*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_MASK 0x000000FF 976*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_OFFSET 0 977*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_MASK 0x0000FF00 978*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_OFFSET 8 979*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_MASK 0x00FF0000 980*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_OFFSET 16 981*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_MASK 0xFF000000 982*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_OFFSET 24 983*14b24e2bSVaishali Kulkarni u32 tx_rx_eq_25g_ac; /* 0x124 */ 984*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_MASK 0x000000FF 985*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_OFFSET 0 986*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_MASK 0x0000FF00 987*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_OFFSET 8 988*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_MASK 0x00FF0000 989*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_OFFSET 16 990*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_MASK 0xFF000000 991*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_OFFSET 24 992*14b24e2bSVaishali Kulkarni u32 tx_rx_eq_10g_pc; /* 0x128 */ 993*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_MASK 0x000000FF 994*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_OFFSET 0 995*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_MASK 0x0000FF00 996*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_OFFSET 8 997*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_MASK 0x00FF0000 998*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_OFFSET 16 999*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_MASK 0xFF000000 1000*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_OFFSET 24 1001*14b24e2bSVaishali Kulkarni u32 tx_rx_eq_10g_ac; /* 0x12C */ 1002*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_MASK 0x000000FF 1003*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_OFFSET 0 1004*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_MASK 0x0000FF00 1005*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_OFFSET 8 1006*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_MASK 0x00FF0000 1007*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_OFFSET 16 1008*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_MASK 0xFF000000 1009*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_OFFSET 24 1010*14b24e2bSVaishali Kulkarni u32 tx_rx_eq_1g; /* 0x130 */ 1011*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_MASK 0x000000FF 1012*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_OFFSET 0 1013*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_MASK 0x0000FF00 1014*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_OFFSET 8 1015*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_MASK 0x00FF0000 1016*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_OFFSET 16 1017*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_MASK 0xFF000000 1018*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_OFFSET 24 1019*14b24e2bSVaishali Kulkarni u32 tx_rx_eq_25g_bt; /* 0x134 */ 1020*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_MASK 0x000000FF 1021*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_OFFSET 0 1022*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_MASK 0x0000FF00 1023*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_OFFSET 8 1024*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_MASK 0x00FF0000 1025*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_OFFSET 16 1026*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_MASK 0xFF000000 1027*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_OFFSET 24 1028*14b24e2bSVaishali Kulkarni u32 tx_rx_eq_10g_bt; /* 0x138 */ 1029*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_MASK 0x000000FF 1030*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_OFFSET 0 1031*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_MASK 0x0000FF00 1032*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_OFFSET 8 1033*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_MASK 0x00FF0000 1034*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_OFFSET 16 1035*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_MASK 0xFF000000 1036*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_OFFSET 24 1037*14b24e2bSVaishali Kulkarni u32 generic_cont4; /* 0x13C */ 1038*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_MASK 0x000000FF 1039*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_OFFSET 0 1040*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_NA 0x0 1041*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO0 0x1 1042*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO1 0x2 1043*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO2 0x3 1044*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO3 0x4 1045*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO4 0x5 1046*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO5 0x6 1047*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO6 0x7 1048*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO7 0x8 1049*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO8 0x9 1050*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO9 0xA 1051*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO10 0xB 1052*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO11 0xC 1053*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO12 0xD 1054*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO13 0xE 1055*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO14 0xF 1056*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO15 0x10 1057*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO16 0x11 1058*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO17 0x12 1059*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO18 0x13 1060*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO19 0x14 1061*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO20 0x15 1062*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO21 0x16 1063*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO22 0x17 1064*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO23 0x18 1065*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO24 0x19 1066*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO25 0x1A 1067*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO26 0x1B 1068*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO27 0x1C 1069*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO28 0x1D 1070*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E 1071*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F 1072*14b24e2bSVaishali Kulkarni #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20 1073*14b24e2bSVaishali Kulkarni u32 preboot_debug_mode_std; /* 0x140 */ 1074*14b24e2bSVaishali Kulkarni u32 preboot_debug_mode_ext; /* 0x144 */ 1075*14b24e2bSVaishali Kulkarni u32 reserved[56]; /* 0x148 */ 1076*14b24e2bSVaishali Kulkarni }; 1077*14b24e2bSVaishali Kulkarni 1078*14b24e2bSVaishali Kulkarni struct nvm_cfg1_path 1079*14b24e2bSVaishali Kulkarni { 1080*14b24e2bSVaishali Kulkarni u32 reserved[1]; /* 0x0 */ 1081*14b24e2bSVaishali Kulkarni }; 1082*14b24e2bSVaishali Kulkarni 1083*14b24e2bSVaishali Kulkarni struct nvm_cfg1_port 1084*14b24e2bSVaishali Kulkarni { 1085*14b24e2bSVaishali Kulkarni u32 reserved__m_relocated_to_option_123; /* 0x0 */ 1086*14b24e2bSVaishali Kulkarni u32 reserved__m_relocated_to_option_124; /* 0x4 */ 1087*14b24e2bSVaishali Kulkarni u32 generic_cont0; /* 0x8 */ 1088*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF 1089*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_OFFSET 0 1090*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0 1091*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1 1092*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2 1093*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3 1094*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4 1095*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5 1096*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6 1097*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7 1098*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8 1099*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9 1100*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA 1101*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB 1102*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC 1103*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD 1104*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE 1105*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF 1106*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10 1107*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00 1108*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8 1109*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 1110*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 1111*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 1112*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 1113*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 1114*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 1115*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 1116*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 1117*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 1118*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2 1119*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4 1120*14b24e2bSVaishali Kulkarni /* GPIO for HW reset the PHY. In case it is the same for all ports, 1121*14b24e2bSVaishali Kulkarni need to set same value for all ports */ 1122*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_MASK 0xFF000000 1123*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_OFFSET 24 1124*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_NA 0x0 1125*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0 0x1 1126*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1 0x2 1127*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2 0x3 1128*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3 0x4 1129*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4 0x5 1130*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5 0x6 1131*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6 0x7 1132*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7 0x8 1133*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8 0x9 1134*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9 0xA 1135*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10 0xB 1136*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11 0xC 1137*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12 0xD 1138*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13 0xE 1139*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14 0xF 1140*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15 0x10 1141*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16 0x11 1142*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17 0x12 1143*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18 0x13 1144*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19 0x14 1145*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20 0x15 1146*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21 0x16 1147*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22 0x17 1148*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23 0x18 1149*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24 0x19 1150*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25 0x1A 1151*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26 0x1B 1152*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27 0x1C 1153*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28 0x1D 1154*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29 0x1E 1155*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30 0x1F 1156*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31 0x20 1157*14b24e2bSVaishali Kulkarni u32 pcie_cfg; /* 0xC */ 1158*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007 1159*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED15_OFFSET 0 1160*14b24e2bSVaishali Kulkarni u32 features; /* 0x10 */ 1161*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001 1162*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0 1163*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0 1164*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1 1165*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002 1166*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1 1167*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0 1168*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1 1169*14b24e2bSVaishali Kulkarni u32 speed_cap_mask; /* 0x14 */ 1170*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1171*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1172*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1173*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1174*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1175*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1176*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1177*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1178*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1179*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1180*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1181*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1182*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1183*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1184*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1185*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1186*14b24e2bSVaishali Kulkarni u32 link_settings; /* 0x18 */ 1187*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F 1188*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 1189*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 1190*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 1191*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 1192*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 1193*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 1194*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 1195*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7 1196*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 1197*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 1198*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 1199*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 1200*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 1201*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780 1202*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7 1203*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0 1204*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1 1205*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2 1206*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4 1207*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5 1208*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6 1209*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7 1210*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800 1211*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11 1212*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1 1213*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2 1214*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4 1215*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000 1216*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14 1217*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0 1218*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1 1219*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000 1220*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15 1221*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0 1222*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1 1223*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000 1224*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17 1225*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0 1226*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1 1227*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2 1228*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7 1229*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_AN_MODE_MASK 0x00700000 1230*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_AN_MODE_OFFSET 20 1231*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_AN_MODE_NONE 0x0 1232*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_AN_MODE_10G_FIRECODE 0x1 1233*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE 0x2 1234*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_AN_MODE_10G_AND_25G_FIRECODE 0x3 1235*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS 0x4 1236*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS 0x5 1237*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FEC_AN_MODE_ALL 0x6 1238*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SMARTLINQ_MODE_MASK 0x00800000 1239*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SMARTLINQ_MODE_OFFSET 23 1240*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SMARTLINQ_MODE_DISABLED 0x0 1241*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SMARTLINQ_MODE_ENABLED 0x1 1242*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_MASK 0x01000000 1243*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_OFFSET 24 1244*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED 0x0 1245*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED 0x1 1246*14b24e2bSVaishali Kulkarni u32 phy_cfg; /* 0x1C */ 1247*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF 1248*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0 1249*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1 1250*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2 1251*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4 1252*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8 1253*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10 1254*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000 1255*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16 1256*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0 1257*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2 1258*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3 1259*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4 1260*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8 1261*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9 1262*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB 1263*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC 1264*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11 1265*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12 1266*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21 1267*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22 1268*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31 1269*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000 1270*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_MODE_OFFSET 24 1271*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_MODE_NONE 0x0 1272*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_MODE_CL73 0x1 1273*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_MODE_CL37 0x2 1274*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3 1275*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4 1276*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5 1277*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6 1278*14b24e2bSVaishali Kulkarni u32 mgmt_traffic; /* 0x20 */ 1279*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F 1280*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED61_OFFSET 0 1281*14b24e2bSVaishali Kulkarni u32 ext_phy; /* 0x24 */ 1282*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF 1283*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0 1284*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0 1285*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1 1286*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00 1287*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8 1288*14b24e2bSVaishali Kulkarni /* EEE power saving mode */ 1289*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000 1290*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16 1291*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0 1292*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1 1293*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2 1294*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3 1295*14b24e2bSVaishali Kulkarni u32 mba_cfg1; /* 0x28 */ 1296*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001 1297*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0 1298*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0 1299*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1 1300*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006 1301*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1 1302*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078 1303*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3 1304*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080 1305*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7 1306*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0 1307*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1 1308*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100 1309*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8 1310*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0 1311*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1 1312*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00 1313*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED5_OFFSET 9 1314*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000 1315*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17 1316*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0 1317*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1 1318*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2 1319*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4 1320*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5 1321*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6 1322*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7 1323*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000 1324*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21 1325*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_MASK 0x01000000 1326*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_OFFSET 24 1327*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_DISABLED 0x0 1328*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_ENABLED 0x1 1329*14b24e2bSVaishali Kulkarni u32 mba_cfg2; /* 0x2C */ 1330*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF 1331*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED65_OFFSET 0 1332*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000 1333*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED66_OFFSET 16 1334*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_MASK 0x01FE0000 1335*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_OFFSET 17 1336*14b24e2bSVaishali Kulkarni u32 vf_cfg; /* 0x30 */ 1337*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF 1338*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED8_OFFSET 0 1339*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000 1340*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED6_OFFSET 16 1341*14b24e2bSVaishali Kulkarni struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */ 1342*14b24e2bSVaishali Kulkarni u32 led_port_settings; /* 0x3C */ 1343*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF 1344*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0 1345*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00 1346*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8 1347*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000 1348*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16 1349*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1 1350*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2 1351*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_25G 0x4 1352*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_25G 0x8 1353*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_40G 0x8 1354*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_40G 0x10 1355*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G 0x10 1356*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G 0x20 1357*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40 1358*14b24e2bSVaishali Kulkarni u32 transceiver_00; /* 0x40 */ 1359*14b24e2bSVaishali Kulkarni /* Define for mapping of transceiver signal module absent */ 1360*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF 1361*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0 1362*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0 1363*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1 1364*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2 1365*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3 1366*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4 1367*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5 1368*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6 1369*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7 1370*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8 1371*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9 1372*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA 1373*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB 1374*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC 1375*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD 1376*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE 1377*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF 1378*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10 1379*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11 1380*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12 1381*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13 1382*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14 1383*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15 1384*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16 1385*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17 1386*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18 1387*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19 1388*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A 1389*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B 1390*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C 1391*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D 1392*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E 1393*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F 1394*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20 1395*14b24e2bSVaishali Kulkarni /* Define the GPIO mux settings to switch i2c mux to this port */ 1396*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00 1397*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8 1398*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000 1399*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12 1400*14b24e2bSVaishali Kulkarni u32 device_ids; /* 0x44 */ 1401*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF 1402*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0 1403*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00 1404*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8 1405*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000 1406*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16 1407*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000 1408*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24 1409*14b24e2bSVaishali Kulkarni u32 board_cfg; /* 0x48 */ 1410*14b24e2bSVaishali Kulkarni /* This field defines the board technology 1411*14b24e2bSVaishali Kulkarni (backpane,transceiver,external PHY) */ 1412*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF 1413*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0 1414*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0 1415*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1 1416*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2 1417*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3 1418*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4 1419*14b24e2bSVaishali Kulkarni /* This field defines the GPIO mapped to tx_disable signal in SFP */ 1420*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00 1421*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8 1422*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0 1423*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1 1424*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2 1425*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3 1426*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4 1427*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5 1428*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6 1429*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7 1430*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8 1431*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9 1432*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA 1433*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB 1434*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC 1435*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD 1436*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE 1437*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF 1438*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10 1439*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11 1440*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12 1441*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13 1442*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14 1443*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15 1444*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16 1445*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17 1446*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18 1447*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19 1448*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A 1449*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B 1450*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C 1451*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D 1452*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E 1453*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F 1454*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20 1455*14b24e2bSVaishali Kulkarni u32 mnm_10g_cap; /* 0x4C */ 1456*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1457*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1458*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1459*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1460*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1461*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1462*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1463*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1464*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1465*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1466*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1467*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1468*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1469*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1470*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1471*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1472*14b24e2bSVaishali Kulkarni u32 mnm_10g_ctrl; /* 0x50 */ 1473*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F 1474*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0 1475*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0 1476*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1 1477*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2 1478*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4 1479*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5 1480*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6 1481*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7 1482*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0 1483*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4 1484*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0 1485*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1 1486*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2 1487*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4 1488*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5 1489*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6 1490*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7 1491*14b24e2bSVaishali Kulkarni /* This field defines the board technology 1492*14b24e2bSVaishali Kulkarni (backpane,transceiver,external PHY) */ 1493*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00 1494*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8 1495*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0 1496*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1 1497*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2 1498*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3 1499*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4 1500*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1501*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16 1502*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0 1503*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2 1504*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3 1505*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4 1506*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8 1507*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9 1508*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB 1509*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC 1510*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11 1511*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12 1512*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21 1513*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22 1514*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31 1515*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000 1516*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24 1517*14b24e2bSVaishali Kulkarni u32 mnm_10g_misc; /* 0x54 */ 1518*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007 1519*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0 1520*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0 1521*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1 1522*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2 1523*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7 1524*14b24e2bSVaishali Kulkarni u32 mnm_25g_cap; /* 0x58 */ 1525*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1526*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1527*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1528*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1529*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1530*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1531*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1532*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1533*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1534*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1535*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1536*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1537*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1538*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1539*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1540*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1541*14b24e2bSVaishali Kulkarni u32 mnm_25g_ctrl; /* 0x5C */ 1542*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F 1543*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0 1544*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0 1545*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1 1546*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2 1547*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4 1548*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5 1549*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6 1550*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7 1551*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0 1552*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4 1553*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0 1554*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1 1555*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2 1556*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4 1557*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5 1558*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6 1559*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7 1560*14b24e2bSVaishali Kulkarni /* This field defines the board technology 1561*14b24e2bSVaishali Kulkarni (backpane,transceiver,external PHY) */ 1562*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00 1563*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8 1564*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0 1565*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1 1566*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2 1567*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3 1568*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4 1569*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1570*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16 1571*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0 1572*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2 1573*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3 1574*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4 1575*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8 1576*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9 1577*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB 1578*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC 1579*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11 1580*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12 1581*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21 1582*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22 1583*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31 1584*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000 1585*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24 1586*14b24e2bSVaishali Kulkarni u32 mnm_25g_misc; /* 0x60 */ 1587*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007 1588*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0 1589*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0 1590*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1 1591*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2 1592*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7 1593*14b24e2bSVaishali Kulkarni u32 mnm_40g_cap; /* 0x64 */ 1594*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1595*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1596*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1597*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1598*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1599*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1600*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1601*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1602*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1603*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1604*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1605*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1606*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1607*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1608*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1609*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1610*14b24e2bSVaishali Kulkarni u32 mnm_40g_ctrl; /* 0x68 */ 1611*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F 1612*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0 1613*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0 1614*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1 1615*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2 1616*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4 1617*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5 1618*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6 1619*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7 1620*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0 1621*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4 1622*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0 1623*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1 1624*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2 1625*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4 1626*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5 1627*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6 1628*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7 1629*14b24e2bSVaishali Kulkarni /* This field defines the board technology 1630*14b24e2bSVaishali Kulkarni (backpane,transceiver,external PHY) */ 1631*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00 1632*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8 1633*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0 1634*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1 1635*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2 1636*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3 1637*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4 1638*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1639*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16 1640*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0 1641*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2 1642*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3 1643*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4 1644*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8 1645*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9 1646*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB 1647*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC 1648*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11 1649*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12 1650*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21 1651*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22 1652*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31 1653*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000 1654*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24 1655*14b24e2bSVaishali Kulkarni u32 mnm_40g_misc; /* 0x6C */ 1656*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007 1657*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0 1658*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0 1659*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1 1660*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2 1661*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7 1662*14b24e2bSVaishali Kulkarni u32 mnm_50g_cap; /* 0x70 */ 1663*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1664*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1665*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1666*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1667*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1668*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1669*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1670*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1671*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1672*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1673*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1674*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1675*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1676*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1677*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1678*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1679*14b24e2bSVaishali Kulkarni u32 mnm_50g_ctrl; /* 0x74 */ 1680*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F 1681*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0 1682*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0 1683*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1 1684*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2 1685*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4 1686*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5 1687*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6 1688*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7 1689*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0 1690*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4 1691*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0 1692*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1 1693*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2 1694*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4 1695*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5 1696*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6 1697*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7 1698*14b24e2bSVaishali Kulkarni /* This field defines the board technology 1699*14b24e2bSVaishali Kulkarni (backpane,transceiver,external PHY) */ 1700*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00 1701*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8 1702*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0 1703*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1 1704*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2 1705*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3 1706*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4 1707*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1708*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16 1709*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0 1710*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2 1711*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3 1712*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4 1713*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8 1714*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9 1715*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB 1716*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC 1717*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11 1718*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12 1719*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21 1720*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22 1721*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31 1722*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000 1723*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24 1724*14b24e2bSVaishali Kulkarni u32 mnm_50g_misc; /* 0x78 */ 1725*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007 1726*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0 1727*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0 1728*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1 1729*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2 1730*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7 1731*14b24e2bSVaishali Kulkarni u32 mnm_100g_cap; /* 0x7C */ 1732*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK 0x0000FFFF 1733*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0 1734*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1 1735*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2 1736*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8 1737*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10 1738*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20 1739*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40 1740*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK 0xFFFF0000 1741*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16 1742*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1 1743*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2 1744*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8 1745*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10 1746*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20 1747*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40 1748*14b24e2bSVaishali Kulkarni u32 mnm_100g_ctrl; /* 0x80 */ 1749*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F 1750*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0 1751*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0 1752*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1 1753*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2 1754*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4 1755*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5 1756*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6 1757*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7 1758*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0 1759*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4 1760*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0 1761*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1 1762*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2 1763*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4 1764*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5 1765*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6 1766*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7 1767*14b24e2bSVaishali Kulkarni /* This field defines the board technology 1768*14b24e2bSVaishali Kulkarni (backpane,transceiver,external PHY) */ 1769*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00 1770*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8 1771*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0 1772*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1 1773*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2 1774*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3 1775*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4 1776*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1777*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16 1778*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0 1779*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2 1780*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3 1781*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4 1782*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8 1783*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9 1784*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB 1785*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC 1786*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11 1787*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12 1788*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21 1789*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22 1790*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31 1791*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000 1792*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24 1793*14b24e2bSVaishali Kulkarni u32 mnm_100g_misc; /* 0x84 */ 1794*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007 1795*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0 1796*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0 1797*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1 1798*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2 1799*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7 1800*14b24e2bSVaishali Kulkarni u32 temperature; /* 0x88 */ 1801*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK 0x000000FF 1802*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET 0 1803*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK 0x0000FF00 1804*14b24e2bSVaishali Kulkarni #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8 1805*14b24e2bSVaishali Kulkarni u32 reserved[115]; /* 0x8C */ 1806*14b24e2bSVaishali Kulkarni }; 1807*14b24e2bSVaishali Kulkarni 1808*14b24e2bSVaishali Kulkarni struct nvm_cfg1_func 1809*14b24e2bSVaishali Kulkarni { 1810*14b24e2bSVaishali Kulkarni struct nvm_cfg_mac_address mac_address; /* 0x0 */ 1811*14b24e2bSVaishali Kulkarni u32 rsrv1; /* 0x8 */ 1812*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF 1813*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0 1814*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000 1815*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16 1816*14b24e2bSVaishali Kulkarni u32 rsrv2; /* 0xC */ 1817*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF 1818*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0 1819*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000 1820*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16 1821*14b24e2bSVaishali Kulkarni u32 device_id; /* 0x10 */ 1822*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF 1823*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0 1824*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000 1825*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16 1826*14b24e2bSVaishali Kulkarni u32 cmn_cfg; /* 0x14 */ 1827*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007 1828*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0 1829*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0 1830*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3 1831*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4 1832*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7 1833*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8 1834*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3 1835*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000 1836*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19 1837*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0 1838*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1 1839*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2 1840*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3 1841*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000 1842*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23 1843*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000 1844*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31 1845*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0 1846*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1 1847*14b24e2bSVaishali Kulkarni u32 pci_cfg; /* 0x18 */ 1848*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F 1849*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0 1850*14b24e2bSVaishali Kulkarni /* AH VF BAR2 size */ 1851*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80 1852*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7 1853*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0 1854*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1 1855*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2 1856*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3 1857*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4 1858*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5 1859*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6 1860*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7 1861*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8 1862*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9 1863*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA 1864*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB 1865*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC 1866*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD 1867*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE 1868*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF 1869*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000 1870*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14 1871*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0 1872*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1 1873*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2 1874*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3 1875*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4 1876*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5 1877*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6 1878*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7 1879*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8 1880*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9 1881*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA 1882*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB 1883*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC 1884*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD 1885*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE 1886*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF 1887*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000 1888*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18 1889*14b24e2bSVaishali Kulkarni /* Hide function in npar mode */ 1890*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000 1891*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26 1892*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0 1893*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1 1894*14b24e2bSVaishali Kulkarni /* AH BAR2 size (per function) */ 1895*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000 1896*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27 1897*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0 1898*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5 1899*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6 1900*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7 1901*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8 1902*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9 1903*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA 1904*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB 1905*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC 1906*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD 1907*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE 1908*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF 1909*14b24e2bSVaishali Kulkarni struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */ 1910*14b24e2bSVaishali Kulkarni struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */ 1911*14b24e2bSVaishali Kulkarni u32 preboot_generic_cfg; /* 0x2C */ 1912*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF 1913*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0 1914*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000 1915*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16 1916*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_MASK 0x001E0000 1917*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_OFFSET 17 1918*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET 0x1 1919*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE 0x2 1920*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI 0x4 1921*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_RDMA 0x8 1922*14b24e2bSVaishali Kulkarni u32 features; /* 0x30 */ 1923*14b24e2bSVaishali Kulkarni /* RDMA protocol enablement */ 1924*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_MASK 0x00000003 1925*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_OFFSET 0 1926*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_NONE 0x0 1927*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_ROCE 0x1 1928*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_IWARP 0x2 1929*14b24e2bSVaishali Kulkarni #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_BOTH 0x3 1930*14b24e2bSVaishali Kulkarni u32 reserved[7]; /* 0x34 */ 1931*14b24e2bSVaishali Kulkarni }; 1932*14b24e2bSVaishali Kulkarni 1933*14b24e2bSVaishali Kulkarni struct nvm_cfg1 1934*14b24e2bSVaishali Kulkarni { 1935*14b24e2bSVaishali Kulkarni struct nvm_cfg1_glob glob; /* 0x0 */ 1936*14b24e2bSVaishali Kulkarni struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x228 */ 1937*14b24e2bSVaishali Kulkarni struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */ 1938*14b24e2bSVaishali Kulkarni struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */ 1939*14b24e2bSVaishali Kulkarni }; 1940*14b24e2bSVaishali Kulkarni 1941*14b24e2bSVaishali Kulkarni /****************************************** 1942*14b24e2bSVaishali Kulkarni * nvm_cfg structs 1943*14b24e2bSVaishali Kulkarni ******************************************/ 1944*14b24e2bSVaishali Kulkarni enum nvm_cfg_sections 1945*14b24e2bSVaishali Kulkarni { 1946*14b24e2bSVaishali Kulkarni NVM_CFG_SECTION_NVM_CFG1, 1947*14b24e2bSVaishali Kulkarni NVM_CFG_SECTION_MAX 1948*14b24e2bSVaishali Kulkarni }; 1949*14b24e2bSVaishali Kulkarni 1950*14b24e2bSVaishali Kulkarni struct nvm_cfg 1951*14b24e2bSVaishali Kulkarni { 1952*14b24e2bSVaishali Kulkarni u32 num_sections; 1953*14b24e2bSVaishali Kulkarni u32 sections_offset[NVM_CFG_SECTION_MAX]; 1954*14b24e2bSVaishali Kulkarni struct nvm_cfg1 cfg1; 1955*14b24e2bSVaishali Kulkarni }; 1956*14b24e2bSVaishali Kulkarni 1957*14b24e2bSVaishali Kulkarni #endif /* NVM_CFG_H */ 1958