1*14b24e2bSVaishali Kulkarni /*
2*14b24e2bSVaishali Kulkarni * CDDL HEADER START
3*14b24e2bSVaishali Kulkarni *
4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
7*14b24e2bSVaishali Kulkarni *
8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
11*14b24e2bSVaishali Kulkarni * and limitations under the License.
12*14b24e2bSVaishali Kulkarni *
13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
18*14b24e2bSVaishali Kulkarni *
19*14b24e2bSVaishali Kulkarni * CDDL HEADER END
20*14b24e2bSVaishali Kulkarni */
21*14b24e2bSVaishali Kulkarni 
22*14b24e2bSVaishali Kulkarni /*
23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
26*14b24e2bSVaishali Kulkarni 
27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
28*14b24e2bSVaishali Kulkarni 
29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
31*14b24e2bSVaishali Kulkarni 
32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
33*14b24e2bSVaishali Kulkarni * limitations under the License.
34*14b24e2bSVaishali Kulkarni */
35*14b24e2bSVaishali Kulkarni 
36*14b24e2bSVaishali Kulkarni #ifndef __TESTING__
37*14b24e2bSVaishali Kulkarni #define __TESTING__
38*14b24e2bSVaishali Kulkarni 
39*14b24e2bSVaishali Kulkarni struct CfcLoadErrorTestParams
40*14b24e2bSVaishali Kulkarni {
41*14b24e2bSVaishali Kulkarni 	u8 testType;
42*14b24e2bSVaishali Kulkarni 	u8 errorBits;
43*14b24e2bSVaishali Kulkarni 	__le16 reserved1;
44*14b24e2bSVaishali Kulkarni 	__le32 cid;
45*14b24e2bSVaishali Kulkarni 	__le32 tid;
46*14b24e2bSVaishali Kulkarni 	__le32 reserved2;
47*14b24e2bSVaishali Kulkarni 	u8 reserved3[96];
48*14b24e2bSVaishali Kulkarni };
49*14b24e2bSVaishali Kulkarni 
50*14b24e2bSVaishali Kulkarni 
51*14b24e2bSVaishali Kulkarni struct EngineIsolationTestDmaRequestParams
52*14b24e2bSVaishali Kulkarni {
53*14b24e2bSVaishali Kulkarni 	__le32 dmaParams0;
54*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_DLENGTH_MASK          0xFFFF
55*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_DLENGTH_SHIFT         0
56*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_STINDEX_MASK          0x1FF
57*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_STINDEX_SHIFT         16
58*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_STHINT_MASK           0x3
59*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_STHINT_SHIFT          25
60*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_TPHVALID_MASK         0x7
61*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_TPHVALID_SHIFT        27
62*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ENDIANITY_MASK        0x3
63*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ENDIANITY_SHIFT       30
64*14b24e2bSVaishali Kulkarni 	__le32 dmaParams1;
65*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ATC_MASK              0x7
66*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ATC_SHIFT             0
67*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_NOSNOOP_MASK          0x1
68*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_NOSNOOP_SHIFT         3
69*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_RELAXEDORDERING_MASK  0x1
70*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_RELAXEDORDERING_SHIFT 4
71*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ADDRTYPE_MASK         0x1
72*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ADDRTYPE_SHIFT        5
73*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_DONETYPE_MASK         0x1
74*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_DONETYPE_SHIFT        6
75*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_WAITFOREOP_MASK       0x1
76*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_WAITFOREOP_SHIFT      7
77*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_VQID_MASK             0x1F
78*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_VQID_SHIFT            8
79*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_LAST_MASK             0x7
80*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_LAST_SHIFT            13
81*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_OFID_MASK             0xFFFF
82*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_OFID_SHIFT            16
83*14b24e2bSVaishali Kulkarni 	__le32 dmaParams2;
84*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ADDRLO_MASK           0xFFFFFFFF
85*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ADDRLO_SHIFT          0
86*14b24e2bSVaishali Kulkarni 	__le32 dmaParams3;
87*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ADDRHI_MASK           0xFFFFFFFF
88*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ADDRHI_SHIFT          0
89*14b24e2bSVaishali Kulkarni 	u8 immediateCount /* user should ensure that rest of the paramters agree (if needed) with the number of immediate dwords specified here */;
90*14b24e2bSVaishali Kulkarni 	u8 unusedPad8;
91*14b24e2bSVaishali Kulkarni 	__le16 unusedPad16;
92*14b24e2bSVaishali Kulkarni 	__le32 unusedPad;
93*14b24e2bSVaishali Kulkarni 	__le32 immediateDataValues[16];
94*14b24e2bSVaishali Kulkarni };
95*14b24e2bSVaishali Kulkarni 
96*14b24e2bSVaishali Kulkarni 
97*14b24e2bSVaishali Kulkarni enum EngineIsolationTestGrcAccessType
98*14b24e2bSVaishali Kulkarni {
99*14b24e2bSVaishali Kulkarni 	GRC_ACCESS_READ=1,
100*14b24e2bSVaishali Kulkarni 	GRC_ACCESS_WRITE=2,
101*14b24e2bSVaishali Kulkarni 	MAX_ENGINEISOLATIONTESTGRCACCESSTYPE
102*14b24e2bSVaishali Kulkarni };
103*14b24e2bSVaishali Kulkarni 
104*14b24e2bSVaishali Kulkarni 
105*14b24e2bSVaishali Kulkarni struct EngineIsolationTestRequestParamsGrc
106*14b24e2bSVaishali Kulkarni {
107*14b24e2bSVaishali Kulkarni 	__le32 reg00Value /* Value to write to register, or value read back from register */;
108*14b24e2bSVaishali Kulkarni 	u8 requestType;
109*14b24e2bSVaishali Kulkarni 	u8 unused8;
110*14b24e2bSVaishali Kulkarni 	__le16 opaqueFid;
111*14b24e2bSVaishali Kulkarni 	__le32 regField;
112*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSGRC_REG00ADDR_MASK  0x7FFFFF
113*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSGRC_REG00ADDR_SHIFT 0
114*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSGRC_UNUSED9_MASK    0x1FF
115*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSGRC_UNUSED9_SHIFT   23
116*14b24e2bSVaishali Kulkarni 	__le32 unused32;
117*14b24e2bSVaishali Kulkarni 	__le32 unusedPad[22];
118*14b24e2bSVaishali Kulkarni };
119*14b24e2bSVaishali Kulkarni 
120*14b24e2bSVaishali Kulkarni struct EngineIsolationTestRequestParamsSdmDma
121*14b24e2bSVaishali Kulkarni {
122*14b24e2bSVaishali Kulkarni 	__le32 hdrFields;
123*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_LENGTH_MASK  0xFFF /* (hdr) dma hdr length */
124*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_LENGTH_SHIFT 0
125*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_SRC_MASK     0xF /* (hdr) dma src (type) */
126*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_SRC_SHIFT    12
127*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_DST_MASK     0xF /* (hdr) dma dst (type) */
128*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_DST_SHIFT    16
129*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_UNUSED_MASK  0xFFF /* (hdr) dma dst (type) */
130*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_UNUSED_SHIFT 20
131*14b24e2bSVaishali Kulkarni 	__le16 address /* (hdr) Short address in DMA hdr */;
132*14b24e2bSVaishali Kulkarni 	__le16 unused16;
133*14b24e2bSVaishali Kulkarni 	struct EngineIsolationTestDmaRequestParams dmaParams;
134*14b24e2bSVaishali Kulkarni 	__le32 unused128[2];
135*14b24e2bSVaishali Kulkarni };
136*14b24e2bSVaishali Kulkarni 
137*14b24e2bSVaishali Kulkarni struct EngineIsolationTestRequestParamsPrmDma
138*14b24e2bSVaishali Kulkarni {
139*14b24e2bSVaishali Kulkarni 	__le32 hdr0;
140*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_PB_MASK             0x1 /* (hdr) pbFlag */
141*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_PB_SHIFT            0
142*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_DIF_MASK            0x1 /* (hdr) difFlag */
143*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_DIF_SHIFT           1
144*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_TR_MASK             0x1 /* (hdr) tr flag */
145*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_TR_SHIFT            2
146*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_LDRENQTRIG_MASK     0x1 /* (hdr) ldrEnqTrigFlag */
147*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_LDRENQTRIG_SHIFT    3
148*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_LDRDONETRIG_MASK    0x1 /* (hdr) ldrDoneTrigFlag */
149*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_LDRDONETRIG_SHIFT   4
150*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_WAITYEVENT_MASK     0x1 /* (hdr) waitYeventFlag */
151*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_WAITYEVENT_SHIFT    5
152*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_WAITUEVENT_MASK     0x1 /* (hdr) waitUeventFlag */
153*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_WAITUEVENT_SHIFT    6
154*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_PTUMODE_MASK        0x1 /* (hdr) ptuMode */
155*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_PTUMODE_SHIFT       7
156*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_CMDLENGTH_MASK      0xFF /* (hdr) cmd length */
157*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_CMDLENGTH_SHIFT     8
158*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_SRC_MASK            0x7 /* (hdr) src */
159*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_SRC_SHIFT           16
160*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_DST_MASK            0x1 /* (hdr) dst */
161*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_DST_SHIFT           19
162*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBNUMREL_MASK      0x3FF /* (hdr) brbNumRel */
163*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBNUMREL_SHIFT     20
164*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBSRCREADREL_MASK  0x3 /* (hdr) brbSrcReadRel */
165*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBSRCREADREL_SHIFT 30
166*14b24e2bSVaishali Kulkarni 	__le32 hdr1;
167*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_SLENGTH_MASK        0xFF /* (hdr) slength */
168*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_SLENGTH_SHIFT       0
169*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_INSERTPAD_MASK      0x1 /* (hdr) insertPad */
170*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_INSERTPAD_SHIFT     8
171*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_REQTYPE_MASK        0x3 /* (hdr) reqType */
172*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_REQTYPE_SHIFT       9
173*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_UNUSED5_MASK        0x1F
174*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_UNUSED5_SHIFT       11
175*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBOFFSET_MASK      0xFFFF /* (hdr) brbOffset */
176*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBOFFSET_SHIFT     16
177*14b24e2bSVaishali Kulkarni 	__le32 hdr2;
178*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBDEBUG_MASK       0xFFFF /* (hdr) brbDebug */
179*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBDEBUG_SHIFT      0
180*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBSTARTBLK_MASK    0xFFFF /* (hdr) brbStartBlk */
181*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBSTARTBLK_SHIFT   16
182*14b24e2bSVaishali Kulkarni 	__le32 dmaParamsPrmSpecific;
183*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_DISCARD_MASK        0x1
184*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_DISCARD_SHIFT       0
185*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_PADCL_MASK          0x1
186*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_PADCL_SHIFT         1
187*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_UNUSED30_MASK       0x3FFFFFFF
188*14b24e2bSVaishali Kulkarni #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_UNUSED30_SHIFT      2
189*14b24e2bSVaishali Kulkarni 	struct EngineIsolationTestDmaRequestParams dmaParams;
190*14b24e2bSVaishali Kulkarni };
191*14b24e2bSVaishali Kulkarni 
192*14b24e2bSVaishali Kulkarni union EngineIsolationTestSpecific
193*14b24e2bSVaishali Kulkarni {
194*14b24e2bSVaishali Kulkarni 	struct EngineIsolationTestRequestParamsGrc grcAccess;
195*14b24e2bSVaishali Kulkarni 	struct EngineIsolationTestRequestParamsSdmDma sdmDma;
196*14b24e2bSVaishali Kulkarni 	struct EngineIsolationTestRequestParamsPrmDma prmDma;
197*14b24e2bSVaishali Kulkarni };
198*14b24e2bSVaishali Kulkarni 
199*14b24e2bSVaishali Kulkarni struct EngineIsolationTestRequestParams
200*14b24e2bSVaishali Kulkarni {
201*14b24e2bSVaishali Kulkarni 	u8 testType;
202*14b24e2bSVaishali Kulkarni 	u8 status /* user should set to idle, and then keep checking as long as status remains busy */;
203*14b24e2bSVaishali Kulkarni 	__le16 unused16;
204*14b24e2bSVaishali Kulkarni 	__le32 unused32;
205*14b24e2bSVaishali Kulkarni 	union EngineIsolationTestSpecific testSpecific;
206*14b24e2bSVaishali Kulkarni };
207*14b24e2bSVaishali Kulkarni 
208*14b24e2bSVaishali Kulkarni 
209*14b24e2bSVaishali Kulkarni 
210*14b24e2bSVaishali Kulkarni 
211*14b24e2bSVaishali Kulkarni 
212*14b24e2bSVaishali Kulkarni 
213*14b24e2bSVaishali Kulkarni enum EngineIsolationTestStatusType
214*14b24e2bSVaishali Kulkarni {
215*14b24e2bSVaishali Kulkarni 	TEST_STATUS_IDLE=0,
216*14b24e2bSVaishali Kulkarni 	TEST_STATUS_BUSY=1,
217*14b24e2bSVaishali Kulkarni 	TEST_STATUS_SUCCESS=2,
218*14b24e2bSVaishali Kulkarni 	TEST_STATUS_FAILURE=255,
219*14b24e2bSVaishali Kulkarni 	MAX_ENGINEISOLATIONTESTSTATUSTYPE
220*14b24e2bSVaishali Kulkarni };
221*14b24e2bSVaishali Kulkarni 
222*14b24e2bSVaishali Kulkarni 
223*14b24e2bSVaishali Kulkarni enum EngineIsolationTestType
224*14b24e2bSVaishali Kulkarni {
225*14b24e2bSVaishali Kulkarni 	TEST_TYPE_SDM_GRC_ACCESS=1,
226*14b24e2bSVaishali Kulkarni 	TEST_TYPE_SDM_DMA=2,
227*14b24e2bSVaishali Kulkarni 	TEST_TYPE_PRM_DMA=3,
228*14b24e2bSVaishali Kulkarni 	MAX_ENGINEISOLATIONTESTTYPE
229*14b24e2bSVaishali Kulkarni };
230*14b24e2bSVaishali Kulkarni 
231*14b24e2bSVaishali Kulkarni 
232*14b24e2bSVaishali Kulkarni struct IntegTestDataHdr
233*14b24e2bSVaishali Kulkarni {
234*14b24e2bSVaishali Kulkarni 	u8 opcode;
235*14b24e2bSVaishali Kulkarni 	u8 enable;
236*14b24e2bSVaishali Kulkarni 	u8 reserved[6];
237*14b24e2bSVaishali Kulkarni };
238*14b24e2bSVaishali Kulkarni 
239*14b24e2bSVaishali Kulkarni struct LatencyMeasurementParams
240*14b24e2bSVaishali Kulkarni {
241*14b24e2bSVaishali Kulkarni 	__le32 numMeasurements /* Number of measurements to conduct. Will be rounded down to nearest power of 2 */;
242*14b24e2bSVaishali Kulkarni 	__le32 meanMeasurement /* Average time of all measurements in 40ns units */;
243*14b24e2bSVaishali Kulkarni 	__le32 minMeasurement /* Minimum time taken in 40ns units */;
244*14b24e2bSVaishali Kulkarni 	__le32 maxMeasurement /* Maximum time taken in 40ns units */;
245*14b24e2bSVaishali Kulkarni 	__le32 delay /* Time to wait between measurements in us */;
246*14b24e2bSVaishali Kulkarni 	__le32 addrLo /* DMA address. Will be set by first PF to load */;
247*14b24e2bSVaishali Kulkarni 	__le32 addrHi /* DMA address. Will be set by first PF to load */;
248*14b24e2bSVaishali Kulkarni 	u8 pfId /* PF id. Will be set by first PF to load */;
249*14b24e2bSVaishali Kulkarni 	u8 done /* Bit indicating measurement is done */;
250*14b24e2bSVaishali Kulkarni 	u8 error /* Bit indicating there was an error during the measurement */;
251*14b24e2bSVaishali Kulkarni 	u8 reserved;
252*14b24e2bSVaishali Kulkarni 	__le32 reserved1[20];
253*14b24e2bSVaishali Kulkarni };
254*14b24e2bSVaishali Kulkarni 
255*14b24e2bSVaishali Kulkarni struct PramParityErrorTestParams
256*14b24e2bSVaishali Kulkarni {
257*14b24e2bSVaishali Kulkarni 	__le32 done;
258*14b24e2bSVaishali Kulkarni 	__le32 reserved;
259*14b24e2bSVaishali Kulkarni 	u8 reserved1[104];
260*14b24e2bSVaishali Kulkarni };
261*14b24e2bSVaishali Kulkarni 
262*14b24e2bSVaishali Kulkarni struct PqTxQueuePciAccess
263*14b24e2bSVaishali Kulkarni {
264*14b24e2bSVaishali Kulkarni 	__le32 pause;
265*14b24e2bSVaishali Kulkarni 	__le16 queueId;
266*14b24e2bSVaishali Kulkarni 	__le16 reserved0;
267*14b24e2bSVaishali Kulkarni 	u8 reserved1[104];
268*14b24e2bSVaishali Kulkarni };
269*14b24e2bSVaishali Kulkarni 
270*14b24e2bSVaishali Kulkarni struct PfcTestParams
271*14b24e2bSVaishali Kulkarni {
272*14b24e2bSVaishali Kulkarni 	u8 pause;
273*14b24e2bSVaishali Kulkarni 	u8 portId;
274*14b24e2bSVaishali Kulkarni 	u8 tcPauseBitmap;
275*14b24e2bSVaishali Kulkarni 	u8 reserved0[5];
276*14b24e2bSVaishali Kulkarni 	u8 reserved1[104];
277*14b24e2bSVaishali Kulkarni };
278*14b24e2bSVaishali Kulkarni 
279*14b24e2bSVaishali Kulkarni struct QmInterfacesTestParams
280*14b24e2bSVaishali Kulkarni {
281*14b24e2bSVaishali Kulkarni 	__le16 connection_icid;
282*14b24e2bSVaishali Kulkarni 	__le16 connection_fid;
283*14b24e2bSVaishali Kulkarni 	__le32 counter;
284*14b24e2bSVaishali Kulkarni 	__le32 dataValid;
285*14b24e2bSVaishali Kulkarni 	__le32 incomingCid;
286*14b24e2bSVaishali Kulkarni 	u8 reserved[96];
287*14b24e2bSVaishali Kulkarni };
288*14b24e2bSVaishali Kulkarni 
289*14b24e2bSVaishali Kulkarni struct SflowTestParams
290*14b24e2bSVaishali Kulkarni {
291*14b24e2bSVaishali Kulkarni 	u8 header[32];
292*14b24e2bSVaishali Kulkarni 	u8 headerSize;
293*14b24e2bSVaishali Kulkarni 	u8 sendFactor;
294*14b24e2bSVaishali Kulkarni 	u8 reserved[6];
295*14b24e2bSVaishali Kulkarni 	u8 reserved1[72];
296*14b24e2bSVaishali Kulkarni };
297*14b24e2bSVaishali Kulkarni 
298*14b24e2bSVaishali Kulkarni struct IntegTestEdpmIntfEnParams
299*14b24e2bSVaishali Kulkarni {
300*14b24e2bSVaishali Kulkarni 	u8 releaseExistInQm;
301*14b24e2bSVaishali Kulkarni 	u8 existInQmReleased;
302*14b24e2bSVaishali Kulkarni 	u8 setXoffState;
303*14b24e2bSVaishali Kulkarni 	u8 setXonState;
304*14b24e2bSVaishali Kulkarni 	u8 reserved[4];
305*14b24e2bSVaishali Kulkarni 	u8 reserved1[104];
306*14b24e2bSVaishali Kulkarni };
307*14b24e2bSVaishali Kulkarni 
308*14b24e2bSVaishali Kulkarni struct VfcStressTestParams
309*14b24e2bSVaishali Kulkarni {
310*14b24e2bSVaishali Kulkarni 	__le32 done;
311*14b24e2bSVaishali Kulkarni 	__le32 status;
312*14b24e2bSVaishali Kulkarni 	__le32 last_index;
313*14b24e2bSVaishali Kulkarni 	__le32 mac_filter_cnt;
314*14b24e2bSVaishali Kulkarni 	__le32 vlan_filter_cnt;
315*14b24e2bSVaishali Kulkarni 	__le32 pair_filter_cnt;
316*14b24e2bSVaishali Kulkarni 	u8 reserved[88];
317*14b24e2bSVaishali Kulkarni };
318*14b24e2bSVaishali Kulkarni 
319*14b24e2bSVaishali Kulkarni struct UnmaskSdmTestParams
320*14b24e2bSVaishali Kulkarni {
321*14b24e2bSVaishali Kulkarni 	u8 sdmUnmaskIntIndex /* SDM aggregative interrupt index to unmask */;
322*14b24e2bSVaishali Kulkarni 	u8 reserved[111];
323*14b24e2bSVaishali Kulkarni };
324*14b24e2bSVaishali Kulkarni 
325*14b24e2bSVaishali Kulkarni struct QcnRlTestParams
326*14b24e2bSVaishali Kulkarni {
327*14b24e2bSVaishali Kulkarni 	__le32 done;
328*14b24e2bSVaishali Kulkarni 	__le32 status;
329*14b24e2bSVaishali Kulkarni 	u8 rl_id;
330*14b24e2bSVaishali Kulkarni 	u8 cmd;
331*14b24e2bSVaishali Kulkarni 	__le16 val;
332*14b24e2bSVaishali Kulkarni 	__le32 repeat_cnt;
333*14b24e2bSVaishali Kulkarni 	__le32 repeat_interval_us;
334*14b24e2bSVaishali Kulkarni 	__le16 force_dcqcn_alpha;
335*14b24e2bSVaishali Kulkarni 	__le16 reserved;
336*14b24e2bSVaishali Kulkarni 	__le32 reserved1[22];
337*14b24e2bSVaishali Kulkarni };
338*14b24e2bSVaishali Kulkarni 
339*14b24e2bSVaishali Kulkarni union IntegTestDataParams
340*14b24e2bSVaishali Kulkarni {
341*14b24e2bSVaishali Kulkarni 	struct LatencyMeasurementParams latencyMeasurementParams;
342*14b24e2bSVaishali Kulkarni 	struct PramParityErrorTestParams pramParityErrorTestParams;
343*14b24e2bSVaishali Kulkarni 	struct PqTxQueuePciAccess pqTxQueuePciAccess;
344*14b24e2bSVaishali Kulkarni 	struct PfcTestParams pfcTestParams;
345*14b24e2bSVaishali Kulkarni 	struct QmInterfacesTestParams qmInterfacesTestParams;
346*14b24e2bSVaishali Kulkarni 	struct SflowTestParams sFlowTestParams;
347*14b24e2bSVaishali Kulkarni 	struct CfcLoadErrorTestParams cfcLoadErrorTestParams;
348*14b24e2bSVaishali Kulkarni 	struct IntegTestEdpmIntfEnParams edpmIntfEnTestParams;
349*14b24e2bSVaishali Kulkarni 	struct EngineIsolationTestRequestParams engineIsolationTestParams;
350*14b24e2bSVaishali Kulkarni 	struct VfcStressTestParams vfcStressTestParams;
351*14b24e2bSVaishali Kulkarni 	struct UnmaskSdmTestParams unmaskSdmTestParams;
352*14b24e2bSVaishali Kulkarni 	struct QcnRlTestParams qcnRlTestParams;
353*14b24e2bSVaishali Kulkarni };
354*14b24e2bSVaishali Kulkarni 
355*14b24e2bSVaishali Kulkarni struct IntegTestData
356*14b24e2bSVaishali Kulkarni {
357*14b24e2bSVaishali Kulkarni 	struct IntegTestDataHdr hdr;
358*14b24e2bSVaishali Kulkarni 	union IntegTestDataParams params;
359*14b24e2bSVaishali Kulkarni };
360*14b24e2bSVaishali Kulkarni 
361*14b24e2bSVaishali Kulkarni 
362*14b24e2bSVaishali Kulkarni 
363*14b24e2bSVaishali Kulkarni 
364*14b24e2bSVaishali Kulkarni 
365*14b24e2bSVaishali Kulkarni enum IntegTestOpcodeEnum
366*14b24e2bSVaishali Kulkarni {
367*14b24e2bSVaishali Kulkarni 	PRAM_PARITY_ERROR_RECOVERY=0,
368*14b24e2bSVaishali Kulkarni 	SDM_TCFC_AC_TEST=1,
369*14b24e2bSVaishali Kulkarni 	XY_LOADER_PCI_ERRORS_TEST=2,
370*14b24e2bSVaishali Kulkarni 	MU_LOADER_PCI_ERRORS_TEST=3,
371*14b24e2bSVaishali Kulkarni 	TM_LOADER_PCI_ERRORS_TEST=4,
372*14b24e2bSVaishali Kulkarni 	XY_LOADER_CFC_ERRORS_TEST=5,
373*14b24e2bSVaishali Kulkarni 	MU_LOADER_CFC_ERRORS_TEST=6,
374*14b24e2bSVaishali Kulkarni 	TM_LOADER_CFC_ERRORS_TEST=7,
375*14b24e2bSVaishali Kulkarni 	X_QM_PAUSE_TX_PQ_ERRORS_TEST=8,
376*14b24e2bSVaishali Kulkarni 	X_QM_UNPAUSE_TX_PQ_ERRORS_TEST=9,
377*14b24e2bSVaishali Kulkarni 	X_QM_QUEUES_PCI_ACCESS_TEST=10,
378*14b24e2bSVaishali Kulkarni 	RECORDING_HANDLER_TEST=12,
379*14b24e2bSVaishali Kulkarni 	PFC_TX_TEST=13,
380*14b24e2bSVaishali Kulkarni 	PFC_RX_PRS_TEST=14,
381*14b24e2bSVaishali Kulkarni 	PFC_RX_NIG_TEST=15,
382*14b24e2bSVaishali Kulkarni 	QM_INTERFACES_TEST=16,
383*14b24e2bSVaishali Kulkarni 	PROP_HEADER_TEST=17,
384*14b24e2bSVaishali Kulkarni 	S_FLOW_TEST=18,
385*14b24e2bSVaishali Kulkarni 	CFC_ERRORS_TEST=19,
386*14b24e2bSVaishali Kulkarni 	M_ENGINE_ISOLATION_TEST=20,
387*14b24e2bSVaishali Kulkarni 	VFC_STRESS_TEST=30,
388*14b24e2bSVaishali Kulkarni 	SDM_AGG_INT_UNMASK_TEST=31,
389*14b24e2bSVaishali Kulkarni 	CDU_VALIDATION_TEST=32,
390*14b24e2bSVaishali Kulkarni 	QCN_RL_TEST=33,
391*14b24e2bSVaishali Kulkarni 	LATENCY_MEASURMENT_TEST=34,
392*14b24e2bSVaishali Kulkarni 	MAX_INTEGTESTOPCODEENUM
393*14b24e2bSVaishali Kulkarni };
394*14b24e2bSVaishali Kulkarni 
395*14b24e2bSVaishali Kulkarni 
396*14b24e2bSVaishali Kulkarni 
397*14b24e2bSVaishali Kulkarni 
398*14b24e2bSVaishali Kulkarni 
399*14b24e2bSVaishali Kulkarni 
400*14b24e2bSVaishali Kulkarni enum QcnRlTestCmdType
401*14b24e2bSVaishali Kulkarni {
402*14b24e2bSVaishali Kulkarni 	QCN_RL_TEST_CNM /* Simulite CNM arriveal. CNM interval and amount can be configurated. */,
403*14b24e2bSVaishali Kulkarni 	QCN_RL_TEST_PKT,
404*14b24e2bSVaishali Kulkarni 	QCN_RL_TEST_TIMER,
405*14b24e2bSVaishali Kulkarni 	QCN_RL_UNMASK_INTERRUPT,
406*14b24e2bSVaishali Kulkarni 	MAX_QCNRLTESTCMDTYPE
407*14b24e2bSVaishali Kulkarni };
408*14b24e2bSVaishali Kulkarni 
409*14b24e2bSVaishali Kulkarni 
410*14b24e2bSVaishali Kulkarni 
411*14b24e2bSVaishali Kulkarni 
412*14b24e2bSVaishali Kulkarni 
413*14b24e2bSVaishali Kulkarni 
414*14b24e2bSVaishali Kulkarni 
415*14b24e2bSVaishali Kulkarni enum VfcStressTestStatusType
416*14b24e2bSVaishali Kulkarni {
417*14b24e2bSVaishali Kulkarni 	VFC_STRESS_SUCCSES=0,
418*14b24e2bSVaishali Kulkarni 	VFC_STRESS_INIT,
419*14b24e2bSVaishali Kulkarni 	VFC_STRESS_MAC_SEARCH,
420*14b24e2bSVaishali Kulkarni 	VFC_STRESS_VLAN_SEARCH,
421*14b24e2bSVaishali Kulkarni 	VFC_STRESS_PAIR_SEARCH,
422*14b24e2bSVaishali Kulkarni 	VFC_STRESS_CLEAN,
423*14b24e2bSVaishali Kulkarni 	VFC_STRESS_MAC_NOT_FOUND,
424*14b24e2bSVaishali Kulkarni 	VFC_STRESS_MAC_NOT_SET_MTT,
425*14b24e2bSVaishali Kulkarni 	VFC_STRESS_MAC_NOT_SET_STT,
426*14b24e2bSVaishali Kulkarni 	VFC_STRESS_VLAN_NOT_FOUND,
427*14b24e2bSVaishali Kulkarni 	VFC_STRESS_VLAN_NOT_SET,
428*14b24e2bSVaishali Kulkarni 	VFC_STRESS_PAIR_NOT_FOUND,
429*14b24e2bSVaishali Kulkarni 	VFC_STRESS_PAIR_NOT_SET,
430*14b24e2bSVaishali Kulkarni 	VFC_STRESS_VLAN_CNT_NON_ZERO,
431*14b24e2bSVaishali Kulkarni 	VFC_STRESS_VFC_CNT_NON_ZERO,
432*14b24e2bSVaishali Kulkarni 	VFC_STRESS_VLAN_MOVE_FAIL,
433*14b24e2bSVaishali Kulkarni 	MAX_VFCSTRESSTESTSTATUSTYPE
434*14b24e2bSVaishali Kulkarni };
435*14b24e2bSVaishali Kulkarni 
436*14b24e2bSVaishali Kulkarni #endif /* __TESTING__ */
437