1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef __ECORE_HSI_DEBUG_TOOLS__ 37 #define __ECORE_HSI_DEBUG_TOOLS__ 38 /****************************************/ 39 /* Debug Tools HSI constants and macros */ 40 /****************************************/ 41 42 43 enum block_addr 44 { 45 GRCBASE_GRC = 0x50000, 46 GRCBASE_MISCS = 0x9000, 47 GRCBASE_MISC = 0x8000, 48 GRCBASE_DBU = 0xa000, 49 GRCBASE_PGLUE_B = 0x2a8000, 50 GRCBASE_CNIG = 0x218000, 51 GRCBASE_CPMU = 0x30000, 52 GRCBASE_NCSI = 0x40000, 53 GRCBASE_OPTE = 0x53000, 54 GRCBASE_BMB = 0x540000, 55 GRCBASE_PCIE = 0x54000, 56 GRCBASE_MCP = 0xe00000, 57 GRCBASE_MCP2 = 0x52000, 58 GRCBASE_PSWHST = 0x2a0000, 59 GRCBASE_PSWHST2 = 0x29e000, 60 GRCBASE_PSWRD = 0x29c000, 61 GRCBASE_PSWRD2 = 0x29d000, 62 GRCBASE_PSWWR = 0x29a000, 63 GRCBASE_PSWWR2 = 0x29b000, 64 GRCBASE_PSWRQ = 0x280000, 65 GRCBASE_PSWRQ2 = 0x240000, 66 GRCBASE_PGLCS = 0x0, 67 GRCBASE_DMAE = 0xc000, 68 GRCBASE_PTU = 0x560000, 69 GRCBASE_TCM = 0x1180000, 70 GRCBASE_MCM = 0x1200000, 71 GRCBASE_UCM = 0x1280000, 72 GRCBASE_XCM = 0x1000000, 73 GRCBASE_YCM = 0x1080000, 74 GRCBASE_PCM = 0x1100000, 75 GRCBASE_QM = 0x2f0000, 76 GRCBASE_TM = 0x2c0000, 77 GRCBASE_DORQ = 0x100000, 78 GRCBASE_BRB = 0x340000, 79 GRCBASE_SRC = 0x238000, 80 GRCBASE_PRS = 0x1f0000, 81 GRCBASE_TSDM = 0xfb0000, 82 GRCBASE_MSDM = 0xfc0000, 83 GRCBASE_USDM = 0xfd0000, 84 GRCBASE_XSDM = 0xf80000, 85 GRCBASE_YSDM = 0xf90000, 86 GRCBASE_PSDM = 0xfa0000, 87 GRCBASE_TSEM = 0x1700000, 88 GRCBASE_MSEM = 0x1800000, 89 GRCBASE_USEM = 0x1900000, 90 GRCBASE_XSEM = 0x1400000, 91 GRCBASE_YSEM = 0x1500000, 92 GRCBASE_PSEM = 0x1600000, 93 GRCBASE_RSS = 0x238800, 94 GRCBASE_TMLD = 0x4d0000, 95 GRCBASE_MULD = 0x4e0000, 96 GRCBASE_YULD = 0x4c8000, 97 GRCBASE_XYLD = 0x4c0000, 98 GRCBASE_PTLD = 0x590000, 99 GRCBASE_YPLD = 0x5b0000, 100 GRCBASE_PRM = 0x230000, 101 GRCBASE_PBF_PB1 = 0xda0000, 102 GRCBASE_PBF_PB2 = 0xda4000, 103 GRCBASE_RPB = 0x23c000, 104 GRCBASE_BTB = 0xdb0000, 105 GRCBASE_PBF = 0xd80000, 106 GRCBASE_RDIF = 0x300000, 107 GRCBASE_TDIF = 0x310000, 108 GRCBASE_CDU = 0x580000, 109 GRCBASE_CCFC = 0x2e0000, 110 GRCBASE_TCFC = 0x2d0000, 111 GRCBASE_IGU = 0x180000, 112 GRCBASE_CAU = 0x1c0000, 113 GRCBASE_RGFS = 0xf00000, 114 GRCBASE_RGSRC = 0x320000, 115 GRCBASE_TGFS = 0xd00000, 116 GRCBASE_TGSRC = 0x322000, 117 GRCBASE_UMAC = 0x51000, 118 GRCBASE_XMAC = 0x210000, 119 GRCBASE_DBG = 0x10000, 120 GRCBASE_NIG = 0x500000, 121 GRCBASE_WOL = 0x600000, 122 GRCBASE_BMBN = 0x610000, 123 GRCBASE_IPC = 0x20000, 124 GRCBASE_NWM = 0x800000, 125 GRCBASE_NWS = 0x700000, 126 GRCBASE_MS = 0x6a0000, 127 GRCBASE_PHY_PCIE = 0x620000, 128 GRCBASE_LED = 0x6b8000, 129 GRCBASE_AVS_WRAP = 0x6b0000, 130 GRCBASE_MISC_AEU = 0x8000, 131 GRCBASE_BAR0_MAP = 0x1c00000, 132 MAX_BLOCK_ADDR 133 }; 134 135 136 enum block_id 137 { 138 BLOCK_GRC, 139 BLOCK_MISCS, 140 BLOCK_MISC, 141 BLOCK_DBU, 142 BLOCK_PGLUE_B, 143 BLOCK_CNIG, 144 BLOCK_CPMU, 145 BLOCK_NCSI, 146 BLOCK_OPTE, 147 BLOCK_BMB, 148 BLOCK_PCIE, 149 BLOCK_MCP, 150 BLOCK_MCP2, 151 BLOCK_PSWHST, 152 BLOCK_PSWHST2, 153 BLOCK_PSWRD, 154 BLOCK_PSWRD2, 155 BLOCK_PSWWR, 156 BLOCK_PSWWR2, 157 BLOCK_PSWRQ, 158 BLOCK_PSWRQ2, 159 BLOCK_PGLCS, 160 BLOCK_DMAE, 161 BLOCK_PTU, 162 BLOCK_TCM, 163 BLOCK_MCM, 164 BLOCK_UCM, 165 BLOCK_XCM, 166 BLOCK_YCM, 167 BLOCK_PCM, 168 BLOCK_QM, 169 BLOCK_TM, 170 BLOCK_DORQ, 171 BLOCK_BRB, 172 BLOCK_SRC, 173 BLOCK_PRS, 174 BLOCK_TSDM, 175 BLOCK_MSDM, 176 BLOCK_USDM, 177 BLOCK_XSDM, 178 BLOCK_YSDM, 179 BLOCK_PSDM, 180 BLOCK_TSEM, 181 BLOCK_MSEM, 182 BLOCK_USEM, 183 BLOCK_XSEM, 184 BLOCK_YSEM, 185 BLOCK_PSEM, 186 BLOCK_RSS, 187 BLOCK_TMLD, 188 BLOCK_MULD, 189 BLOCK_YULD, 190 BLOCK_XYLD, 191 BLOCK_PTLD, 192 BLOCK_YPLD, 193 BLOCK_PRM, 194 BLOCK_PBF_PB1, 195 BLOCK_PBF_PB2, 196 BLOCK_RPB, 197 BLOCK_BTB, 198 BLOCK_PBF, 199 BLOCK_RDIF, 200 BLOCK_TDIF, 201 BLOCK_CDU, 202 BLOCK_CCFC, 203 BLOCK_TCFC, 204 BLOCK_IGU, 205 BLOCK_CAU, 206 BLOCK_RGFS, 207 BLOCK_RGSRC, 208 BLOCK_TGFS, 209 BLOCK_TGSRC, 210 BLOCK_UMAC, 211 BLOCK_XMAC, 212 BLOCK_DBG, 213 BLOCK_NIG, 214 BLOCK_WOL, 215 BLOCK_BMBN, 216 BLOCK_IPC, 217 BLOCK_NWM, 218 BLOCK_NWS, 219 BLOCK_MS, 220 BLOCK_PHY_PCIE, 221 BLOCK_LED, 222 BLOCK_AVS_WRAP, 223 BLOCK_MISC_AEU, 224 BLOCK_BAR0_MAP, 225 MAX_BLOCK_ID 226 }; 227 228 229 /* 230 * binary debug buffer types 231 */ 232 enum bin_dbg_buffer_type 233 { 234 BIN_BUF_DBG_MODE_TREE /* init modes tree */, 235 BIN_BUF_DBG_DUMP_REG /* GRC Dump registers */, 236 BIN_BUF_DBG_DUMP_MEM /* GRC Dump memories */, 237 BIN_BUF_DBG_IDLE_CHK_REGS /* Idle Check registers */, 238 BIN_BUF_DBG_IDLE_CHK_IMMS /* Idle Check immediates */, 239 BIN_BUF_DBG_IDLE_CHK_RULES /* Idle Check rules */, 240 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */, 241 BIN_BUF_DBG_ATTN_BLOCKS /* Attention blocks */, 242 BIN_BUF_DBG_ATTN_REGS /* Attention registers */, 243 BIN_BUF_DBG_ATTN_INDEXES /* Attention indexes */, 244 BIN_BUF_DBG_ATTN_NAME_OFFSETS /* Attention name offsets */, 245 BIN_BUF_DBG_BUS_BLOCKS /* Debug Bus blocks */, 246 BIN_BUF_DBG_BUS_LINES /* Debug Bus lines */, 247 BIN_BUF_DBG_BUS_BLOCKS_USER_DATA /* Debug Bus blocks user data */, 248 BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS /* Debug Bus line name offsets */, 249 BIN_BUF_DBG_PARSING_STRINGS /* Debug Tools parsing strings */, 250 MAX_BIN_DBG_BUFFER_TYPE 251 }; 252 253 254 /* 255 * Attention bit mapping 256 */ 257 struct dbg_attn_bit_mapping 258 { 259 __le16 data; 260 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF /* The index of an attention in the blocks attentions list (if is_unused_bit_cnt=0), or a number of consecutive unused attention bits (if is_unused_bit_cnt=1) */ 261 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 262 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 /* if set, the val field indicates the number of consecutive unused attention bits */ 263 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15 264 }; 265 266 267 /* 268 * Attention block per-type data 269 */ 270 struct dbg_attn_block_type_data 271 { 272 __le16 names_offset /* Offset of this block attention names in the debug attention name offsets array */; 273 __le16 reserved1; 274 u8 num_regs /* Number of attention registers in this block */; 275 u8 reserved2; 276 __le16 regs_offset /* Offset of this blocks attention registers in the attention registers array (in dbg_attn_reg units) */; 277 }; 278 279 /* 280 * Block attentions 281 */ 282 struct dbg_attn_block 283 { 284 struct dbg_attn_block_type_data per_type_data[2] /* attention block per-type data. Count must match the number of elements in dbg_attn_type. */; 285 }; 286 287 288 /* 289 * Attention register result 290 */ 291 struct dbg_attn_reg_result 292 { 293 __le32 data; 294 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) */ 295 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 296 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF /* Number of attention indexes in this register */ 297 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 298 __le16 block_attn_offset /* The offset of this registers attentions within the blocks attentions list (a value in the range 0..number of block attentions-1) */; 299 __le16 reserved; 300 __le32 sts_val /* Value read from the STS attention register */; 301 __le32 mask_val /* Value read from the MASK attention register */; 302 }; 303 304 /* 305 * Attention block result 306 */ 307 struct dbg_attn_block_result 308 { 309 u8 block_id /* Registers block ID */; 310 u8 data; 311 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3 /* Value from dbg_attn_type enum */ 312 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 313 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F /* Number of registers in the block in which at least one attention bit is set */ 314 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 315 __le16 names_offset /* Offset of this registers block attention names in the attention name offsets array */; 316 struct dbg_attn_reg_result reg_results[15] /* result data for each register in the block in which at least one attention bit is set */; 317 }; 318 319 320 321 /* 322 * mode header 323 */ 324 struct dbg_mode_hdr 325 { 326 __le16 data; 327 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 /* indicates if a mode expression should be evaluated (0/1) */ 328 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 329 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF /* offset (in bytes) in modes expression buffer. valid only if eval_mode is set. */ 330 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1 331 }; 332 333 /* 334 * Attention register 335 */ 336 struct dbg_attn_reg 337 { 338 struct dbg_mode_hdr mode /* Mode header */; 339 __le16 block_attn_offset /* The offset of this registers attentions within the blocks attentions list (a value in the range 0..number of block attentions-1) */; 340 __le32 data; 341 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) */ 342 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 343 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF /* Number of attention in this register */ 344 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 345 __le32 sts_clr_address /* STS_CLR attention register GRC address (in dwords) */; 346 __le32 mask_address /* MASK attention register GRC address (in dwords) */; 347 }; 348 349 350 351 /* 352 * attention types 353 */ 354 enum dbg_attn_type 355 { 356 ATTN_TYPE_INTERRUPT, 357 ATTN_TYPE_PARITY, 358 MAX_DBG_ATTN_TYPE 359 }; 360 361 362 /* 363 * Debug Bus block data 364 */ 365 struct dbg_bus_block 366 { 367 u8 num_of_lines /* Number of debug lines in this block (excluding signature and latency events). */; 368 u8 has_latency_events /* Indicates if this block has a latency events debug line (0/1). */; 369 __le16 lines_offset /* Offset of this blocks lines in the Debug Bus lines array. */; 370 }; 371 372 373 /* 374 * Debug Bus block user data 375 */ 376 struct dbg_bus_block_user_data 377 { 378 u8 num_of_lines /* Number of debug lines in this block (excluding signature and latency events). */; 379 u8 has_latency_events /* Indicates if this block has a latency events debug line (0/1). */; 380 __le16 names_offset /* Offset of this blocks lines in the debug bus line name offsets array. */; 381 }; 382 383 384 /* 385 * Block Debug line data 386 */ 387 struct dbg_bus_line 388 { 389 u8 data; 390 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF /* Number of groups in the line (0-3) */ 391 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0 392 #define DBG_BUS_LINE_IS_256B_MASK 0x1 /* Indicates if this is a 128b line (0) or a 256b line (1). */ 393 #define DBG_BUS_LINE_IS_256B_SHIFT 4 394 #define DBG_BUS_LINE_RESERVED_MASK 0x7 395 #define DBG_BUS_LINE_RESERVED_SHIFT 5 396 u8 group_sizes /* Four 2-bit values, indicating the size of each group minus 1 (i.e. value=0 means size=1, value=1 means size=2, etc), starting from lsb. The sizes are in dwords (if is_256b=0) or in qwords (if is_256b=1). */; 397 }; 398 399 400 /* 401 * condition header for registers dump 402 */ 403 struct dbg_dump_cond_hdr 404 { 405 struct dbg_mode_hdr mode /* Mode header */; 406 u8 block_id /* block ID */; 407 u8 data_size /* size in dwords of the data following this header */; 408 }; 409 410 411 /* 412 * memory data for registers dump 413 */ 414 struct dbg_dump_mem 415 { 416 __le32 dword0; 417 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF /* register address (in dwords) */ 418 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0 419 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF /* memory group ID */ 420 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 421 __le32 dword1; 422 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF /* register size (in dwords) */ 423 #define DBG_DUMP_MEM_LENGTH_SHIFT 0 424 #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 425 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24 426 #define DBG_DUMP_MEM_RESERVED_MASK 0x7F 427 #define DBG_DUMP_MEM_RESERVED_SHIFT 25 428 }; 429 430 431 /* 432 * register data for registers dump 433 */ 434 struct dbg_dump_reg 435 { 436 __le32 data; 437 #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */ 438 #define DBG_DUMP_REG_ADDRESS_SHIFT 0 439 #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 440 #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23 441 #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */ 442 #define DBG_DUMP_REG_LENGTH_SHIFT 24 443 }; 444 445 446 /* 447 * split header for registers dump 448 */ 449 struct dbg_dump_split_hdr 450 { 451 __le32 hdr; 452 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF /* size in dwords of the data following this header */ 453 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 454 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF /* split type ID */ 455 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 456 }; 457 458 459 /* 460 * condition header for idle check 461 */ 462 struct dbg_idle_chk_cond_hdr 463 { 464 struct dbg_mode_hdr mode /* Mode header */; 465 __le16 data_size /* size in dwords of the data following this header */; 466 }; 467 468 469 /* 470 * Idle Check condition register 471 */ 472 struct dbg_idle_chk_cond_reg 473 { 474 __le32 data; 475 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF /* Register GRC address (in dwords) */ 476 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 477 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 478 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 479 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF /* value from block_id enum */ 480 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 481 __le16 num_entries /* number of registers entries to check */; 482 u8 entry_size /* size of registers entry (in dwords) */; 483 u8 start_entry /* index of the first entry to check */; 484 }; 485 486 487 /* 488 * Idle Check info register 489 */ 490 struct dbg_idle_chk_info_reg 491 { 492 __le32 data; 493 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF /* Register GRC address (in dwords) */ 494 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 495 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 496 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 497 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF /* value from block_id enum */ 498 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 499 __le16 size /* register size in dwords */; 500 struct dbg_mode_hdr mode /* Mode header */; 501 }; 502 503 504 /* 505 * Idle Check register 506 */ 507 union dbg_idle_chk_reg 508 { 509 struct dbg_idle_chk_cond_reg cond_reg /* condition register */; 510 struct dbg_idle_chk_info_reg info_reg /* info register */; 511 }; 512 513 514 /* 515 * Idle Check result header 516 */ 517 struct dbg_idle_chk_result_hdr 518 { 519 __le16 rule_id /* Failing rule index */; 520 __le16 mem_entry_id /* Failing memory entry index */; 521 u8 num_dumped_cond_regs /* number of dumped condition registers */; 522 u8 num_dumped_info_regs /* number of dumped condition registers */; 523 u8 severity /* from dbg_idle_chk_severity_types enum */; 524 u8 reserved; 525 }; 526 527 528 /* 529 * Idle Check result register header 530 */ 531 struct dbg_idle_chk_result_reg_hdr 532 { 533 u8 data; 534 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1 /* indicates if this register is a memory */ 535 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0 536 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F /* register index within the failing rule */ 537 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 538 u8 start_entry /* index of the first checked entry */; 539 __le16 size /* register size in dwords */; 540 }; 541 542 543 /* 544 * Idle Check rule 545 */ 546 struct dbg_idle_chk_rule 547 { 548 __le16 rule_id /* Idle Check rule ID */; 549 u8 severity /* value from dbg_idle_chk_severity_types enum */; 550 u8 cond_id /* Condition ID */; 551 u8 num_cond_regs /* number of condition registers */; 552 u8 num_info_regs /* number of info registers */; 553 u8 num_imms /* number of immediates in the condition */; 554 u8 reserved1; 555 __le16 reg_offset /* offset of this rules registers in the idle check register array (in dbg_idle_chk_reg units) */; 556 __le16 imm_offset /* offset of this rules immediate values in the immediate values array (in dwords) */; 557 }; 558 559 560 /* 561 * Idle Check rule parsing data 562 */ 563 struct dbg_idle_chk_rule_parsing_data 564 { 565 __le32 data; 566 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 /* indicates if this register has a FW message */ 567 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 568 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF /* Offset of this rules strings in the debug strings array (in bytes) */ 569 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 570 }; 571 572 573 /* 574 * idle check severity types 575 */ 576 enum dbg_idle_chk_severity_types 577 { 578 IDLE_CHK_SEVERITY_ERROR /* idle check failure should cause an error */, 579 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC /* idle check failure should cause an error only if theres no traffic */, 580 IDLE_CHK_SEVERITY_WARNING /* idle check failure should cause a warning */, 581 MAX_DBG_IDLE_CHK_SEVERITY_TYPES 582 }; 583 584 585 586 /* 587 * Debug Bus block data 588 */ 589 struct dbg_bus_block_data 590 { 591 __le16 data; 592 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i is enabled. */ 593 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0 594 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF /* Number of dwords/qwords to shift right the debug data (0-3) */ 595 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4 596 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i is forced valid. */ 597 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8 598 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i frame bit is forced. */ 599 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12 600 u8 line_num /* Debug line number to select */; 601 u8 hw_id /* HW ID associated with the block */; 602 }; 603 604 605 /* 606 * Debug Bus Clients 607 */ 608 enum dbg_bus_clients 609 { 610 DBG_BUS_CLIENT_RBCN, 611 DBG_BUS_CLIENT_RBCP, 612 DBG_BUS_CLIENT_RBCR, 613 DBG_BUS_CLIENT_RBCT, 614 DBG_BUS_CLIENT_RBCU, 615 DBG_BUS_CLIENT_RBCF, 616 DBG_BUS_CLIENT_RBCX, 617 DBG_BUS_CLIENT_RBCS, 618 DBG_BUS_CLIENT_RBCH, 619 DBG_BUS_CLIENT_RBCZ, 620 DBG_BUS_CLIENT_OTHER_ENGINE, 621 DBG_BUS_CLIENT_TIMESTAMP, 622 DBG_BUS_CLIENT_CPU, 623 DBG_BUS_CLIENT_RBCY, 624 DBG_BUS_CLIENT_RBCQ, 625 DBG_BUS_CLIENT_RBCM, 626 DBG_BUS_CLIENT_RBCB, 627 DBG_BUS_CLIENT_RBCW, 628 DBG_BUS_CLIENT_RBCV, 629 MAX_DBG_BUS_CLIENTS 630 }; 631 632 633 /* 634 * Debug Bus constraint operation types 635 */ 636 enum dbg_bus_constraint_ops 637 { 638 DBG_BUS_CONSTRAINT_OP_EQ /* equal */, 639 DBG_BUS_CONSTRAINT_OP_NE /* not equal */, 640 DBG_BUS_CONSTRAINT_OP_LT /* less than */, 641 DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */, 642 DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */, 643 DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */, 644 DBG_BUS_CONSTRAINT_OP_GT /* greater than */, 645 DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */, 646 DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */, 647 DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */, 648 MAX_DBG_BUS_CONSTRAINT_OPS 649 }; 650 651 652 /* 653 * Debug Bus trigger state data 654 */ 655 struct dbg_bus_trigger_state_data 656 { 657 u8 data; 658 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF /* 4-bit value: bit i set -> dword i of the trigger state block (after right shift) is enabled. */ 659 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0 660 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF /* 4-bit value: bit i set -> dword i is compared by a constraint */ 661 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4 662 }; 663 664 /* 665 * Debug Bus memory address 666 */ 667 struct dbg_bus_mem_addr 668 { 669 __le32 lo; 670 __le32 hi; 671 }; 672 673 /* 674 * Debug Bus PCI buffer data 675 */ 676 struct dbg_bus_pci_buf_data 677 { 678 struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */; 679 struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */; 680 __le32 size /* PCI buffer size in bytes */; 681 }; 682 683 /* 684 * Debug Bus Storm EID range filter params 685 */ 686 struct dbg_bus_storm_eid_range_params 687 { 688 u8 min /* Minimal event ID to filter on */; 689 u8 max /* Maximal event ID to filter on */; 690 }; 691 692 /* 693 * Debug Bus Storm EID mask filter params 694 */ 695 struct dbg_bus_storm_eid_mask_params 696 { 697 u8 val /* Event ID value */; 698 u8 mask /* Event ID mask. 1s in the mask = dont care bits. */; 699 }; 700 701 /* 702 * Debug Bus Storm EID filter params 703 */ 704 union dbg_bus_storm_eid_params 705 { 706 struct dbg_bus_storm_eid_range_params range /* EID range filter params */; 707 struct dbg_bus_storm_eid_mask_params mask /* EID mask filter params */; 708 }; 709 710 /* 711 * Debug Bus Storm data 712 */ 713 struct dbg_bus_storm_data 714 { 715 u8 enabled /* indicates if the Storm is enabled for recording */; 716 u8 mode /* Storm debug mode, valid only if the Storm is enabled */; 717 u8 hw_id /* HW ID associated with the Storm */; 718 u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */; 719 u8 eid_range_not_mask /* 1 = EID range filter, 0 = EID mask filter. Valid only if eid_filter_en is set, */; 720 u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */; 721 union dbg_bus_storm_eid_params eid_filter_params /* EID filter params to filter on. Valid only if eid_filter_en is set. */; 722 __le32 cid /* CID to filter on. Valid only if cid_filter_en is set. */; 723 }; 724 725 /* 726 * Debug Bus data 727 */ 728 struct dbg_bus_data 729 { 730 __le32 app_version /* The tools version number of the application */; 731 u8 state /* The current debug bus state */; 732 u8 hw_dwords /* HW dwords per cycle */; 733 __le16 hw_id_mask /* The HW IDs of the recorded HW blocks, where bits i*3..i*3+2 contain the HW ID of dword/qword i */; 734 u8 num_enabled_blocks /* Number of blocks enabled for recording */; 735 u8 num_enabled_storms /* Number of Storms enabled for recording */; 736 u8 target /* Output target */; 737 u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */; 738 u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */; 739 u8 timestamp_input_en /* Indicates if timestamp recording is enabled (0/1) */; 740 u8 filter_en /* Indicates if the recording filter is enabled (0/1) */; 741 u8 adding_filter /* If true, the next added constraint belong to the filter. Otherwise, it belongs to the last added trigger state. Valid only if either filter or triggers are enabled. */; 742 u8 filter_pre_trigger /* Indicates if the recording filter should be applied before the trigger. Valid only if both filter and trigger are enabled (0/1) */; 743 u8 filter_post_trigger /* Indicates if the recording filter should be applied after the trigger. Valid only if both filter and trigger are enabled (0/1) */; 744 __le16 reserved; 745 u8 trigger_en /* Indicates if the recording trigger is enabled (0/1) */; 746 struct dbg_bus_trigger_state_data trigger_states[3] /* trigger states data */; 747 u8 next_trigger_state /* ID of next trigger state to be added */; 748 u8 next_constraint_id /* ID of next filter/trigger constraint to be added */; 749 u8 unify_inputs /* If true, all inputs are associated with HW ID 0. Otherwise, each input is assigned a different HW ID (0/1) */; 750 u8 rcv_from_other_engine /* Indicates if the other engine sends it NW recording to this engine (0/1) */; 751 struct dbg_bus_pci_buf_data pci_buf /* Debug Bus PCI buffer data. Valid only when the target is DBG_BUS_TARGET_ID_PCI. */; 752 struct dbg_bus_block_data blocks[88] /* Debug Bus data for each block */; 753 struct dbg_bus_storm_data storms[6] /* Debug Bus data for each block */; 754 }; 755 756 757 /* 758 * Debug bus filter types 759 */ 760 enum dbg_bus_filter_types 761 { 762 DBG_BUS_FILTER_TYPE_OFF /* filter always off */, 763 DBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */, 764 DBG_BUS_FILTER_TYPE_POST /* filter after trigger only */, 765 DBG_BUS_FILTER_TYPE_ON /* filter always on */, 766 MAX_DBG_BUS_FILTER_TYPES 767 }; 768 769 770 /* 771 * Debug bus frame modes 772 */ 773 enum dbg_bus_frame_modes 774 { 775 DBG_BUS_FRAME_MODE_0HW_4ST=0 /* 0 HW dwords, 4 Storm dwords */, 776 DBG_BUS_FRAME_MODE_4HW_0ST=3 /* 4 HW dwords, 0 Storm dwords */, 777 DBG_BUS_FRAME_MODE_8HW_0ST=4 /* 8 HW dwords, 0 Storm dwords */, 778 MAX_DBG_BUS_FRAME_MODES 779 }; 780 781 782 783 /* 784 * Debug bus other engine mode 785 */ 786 enum dbg_bus_other_engine_modes 787 { 788 DBG_BUS_OTHER_ENGINE_MODE_NONE, 789 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX, 790 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX, 791 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX, 792 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX, 793 MAX_DBG_BUS_OTHER_ENGINE_MODES 794 }; 795 796 797 798 /* 799 * Debug bus post-trigger recording types 800 */ 801 enum dbg_bus_post_trigger_types 802 { 803 DBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */, 804 DBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */, 805 MAX_DBG_BUS_POST_TRIGGER_TYPES 806 }; 807 808 809 /* 810 * Debug bus pre-trigger recording types 811 */ 812 enum dbg_bus_pre_trigger_types 813 { 814 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */, 815 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS /* start recording some chunks before trigger */, 816 DBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */, 817 MAX_DBG_BUS_PRE_TRIGGER_TYPES 818 }; 819 820 821 /* 822 * Debug bus SEMI frame modes 823 */ 824 enum dbg_bus_semi_frame_modes 825 { 826 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST=0 /* 0 slow dwords, 4 fast dwords */, 827 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST=3 /* 4 slow dwords, 0 fast dwords */, 828 MAX_DBG_BUS_SEMI_FRAME_MODES 829 }; 830 831 832 /* 833 * Debug bus states 834 */ 835 enum dbg_bus_states 836 { 837 DBG_BUS_STATE_IDLE /* debug bus idle state (not recording) */, 838 DBG_BUS_STATE_READY /* debug bus is ready for configuration and recording */, 839 DBG_BUS_STATE_RECORDING /* debug bus is currently recording */, 840 DBG_BUS_STATE_STOPPED /* debug bus recording has stopped */, 841 MAX_DBG_BUS_STATES 842 }; 843 844 845 846 847 848 849 /* 850 * Debug Bus Storm modes 851 */ 852 enum dbg_bus_storm_modes 853 { 854 DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */, 855 DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */, 856 DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */, 857 DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */, 858 DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */, 859 DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */, 860 DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */, 861 DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */, 862 DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */, 863 MAX_DBG_BUS_STORM_MODES 864 }; 865 866 867 /* 868 * Debug bus target IDs 869 */ 870 enum dbg_bus_targets 871 { 872 DBG_BUS_TARGET_ID_INT_BUF /* records debug bus to DBG block internal buffer */, 873 DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */, 874 DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */, 875 MAX_DBG_BUS_TARGETS 876 }; 877 878 879 880 /* 881 * GRC Dump data 882 */ 883 struct dbg_grc_data 884 { 885 u8 params_initialized /* Indicates if the GRC parameters were initialized */; 886 u8 reserved1; 887 __le16 reserved2; 888 __le32 param_val[48] /* Value of each GRC parameter. Array size must match the enum dbg_grc_params. */; 889 }; 890 891 892 /* 893 * Debug GRC params 894 */ 895 enum dbg_grc_params 896 { 897 DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */, 898 DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */, 899 DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */, 900 DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */, 901 DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */, 902 DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */, 903 DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */, 904 DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */, 905 DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */, 906 DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */, 907 DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */, 908 DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */, 909 DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */, 910 DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */, 911 DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */, 912 DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */, 913 DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */, 914 DBG_GRC_PARAM_RESERVED /* reserved */, 915 DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */, 916 DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */, 917 DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */, 918 DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */, 919 DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */, 920 DBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */, 921 DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */, 922 DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */, 923 DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */, 924 DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */, 925 DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */, 926 DBG_GRC_PARAM_DUMP_DIF /* dump DIF memories (0/1) */, 927 DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */, 928 DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */, 929 DBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */, 930 DBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */, 931 DBG_GRC_PARAM_EXCLUDE_ALL /* preset: exclude all memories from dump (1 only) */, 932 DBG_GRC_PARAM_CRASH /* preset: include memories for crash dump (1 only) */, 933 DBG_GRC_PARAM_PARITY_SAFE /* perform dump only if MFW is responding (0/1) */, 934 DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */, 935 DBG_GRC_PARAM_DUMP_PHY /* dump PHY memories (0/1) */, 936 DBG_GRC_PARAM_NO_MCP /* dont perform MCP commands (0/1) */, 937 DBG_GRC_PARAM_NO_FW_VER /* dont read FW/MFW version (0/1) */, 938 MAX_DBG_GRC_PARAMS 939 }; 940 941 942 /* 943 * Debug reset registers 944 */ 945 enum dbg_reset_regs 946 { 947 DBG_RESET_REG_MISCS_PL_UA, 948 DBG_RESET_REG_MISCS_PL_HV, 949 DBG_RESET_REG_MISCS_PL_HV_2, 950 DBG_RESET_REG_MISC_PL_UA, 951 DBG_RESET_REG_MISC_PL_HV, 952 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 953 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 954 DBG_RESET_REG_MISC_PL_PDA_VAUX, 955 MAX_DBG_RESET_REGS 956 }; 957 958 959 /* 960 * Debug status codes 961 */ 962 enum dbg_status 963 { 964 DBG_STATUS_OK, 965 DBG_STATUS_APP_VERSION_NOT_SET, 966 DBG_STATUS_UNSUPPORTED_APP_VERSION, 967 DBG_STATUS_DBG_BLOCK_NOT_RESET, 968 DBG_STATUS_INVALID_ARGS, 969 DBG_STATUS_OUTPUT_ALREADY_SET, 970 DBG_STATUS_INVALID_PCI_BUF_SIZE, 971 DBG_STATUS_PCI_BUF_ALLOC_FAILED, 972 DBG_STATUS_PCI_BUF_NOT_ALLOCATED, 973 DBG_STATUS_TOO_MANY_INPUTS, 974 DBG_STATUS_INPUT_OVERLAP, 975 DBG_STATUS_HW_ONLY_RECORDING, 976 DBG_STATUS_STORM_ALREADY_ENABLED, 977 DBG_STATUS_STORM_NOT_ENABLED, 978 DBG_STATUS_BLOCK_ALREADY_ENABLED, 979 DBG_STATUS_BLOCK_NOT_ENABLED, 980 DBG_STATUS_NO_INPUT_ENABLED, 981 DBG_STATUS_NO_FILTER_TRIGGER_64B, 982 DBG_STATUS_FILTER_ALREADY_ENABLED, 983 DBG_STATUS_TRIGGER_ALREADY_ENABLED, 984 DBG_STATUS_TRIGGER_NOT_ENABLED, 985 DBG_STATUS_CANT_ADD_CONSTRAINT, 986 DBG_STATUS_TOO_MANY_TRIGGER_STATES, 987 DBG_STATUS_TOO_MANY_CONSTRAINTS, 988 DBG_STATUS_RECORDING_NOT_STARTED, 989 DBG_STATUS_DATA_DIDNT_TRIGGER, 990 DBG_STATUS_NO_DATA_RECORDED, 991 DBG_STATUS_DUMP_BUF_TOO_SMALL, 992 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED, 993 DBG_STATUS_UNKNOWN_CHIP, 994 DBG_STATUS_VIRT_MEM_ALLOC_FAILED, 995 DBG_STATUS_BLOCK_IN_RESET, 996 DBG_STATUS_INVALID_TRACE_SIGNATURE, 997 DBG_STATUS_INVALID_NVRAM_BUNDLE, 998 DBG_STATUS_NVRAM_GET_IMAGE_FAILED, 999 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE, 1000 DBG_STATUS_NVRAM_READ_FAILED, 1001 DBG_STATUS_IDLE_CHK_PARSE_FAILED, 1002 DBG_STATUS_MCP_TRACE_BAD_DATA, 1003 DBG_STATUS_MCP_TRACE_NO_META, 1004 DBG_STATUS_MCP_COULD_NOT_HALT, 1005 DBG_STATUS_MCP_COULD_NOT_RESUME, 1006 DBG_STATUS_DMAE_FAILED, 1007 DBG_STATUS_SEMI_FIFO_NOT_EMPTY, 1008 DBG_STATUS_IGU_FIFO_BAD_DATA, 1009 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY, 1010 DBG_STATUS_FW_ASSERTS_PARSE_FAILED, 1011 DBG_STATUS_REG_FIFO_BAD_DATA, 1012 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA, 1013 DBG_STATUS_DBG_ARRAY_NOT_SET, 1014 DBG_STATUS_FILTER_BUG, 1015 DBG_STATUS_NON_MATCHING_LINES, 1016 DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET, 1017 DBG_STATUS_DBG_BUS_IN_USE, 1018 MAX_DBG_STATUS 1019 }; 1020 1021 1022 /* 1023 * Debug Storms IDs 1024 */ 1025 enum dbg_storms 1026 { 1027 DBG_TSTORM_ID, 1028 DBG_MSTORM_ID, 1029 DBG_USTORM_ID, 1030 DBG_XSTORM_ID, 1031 DBG_YSTORM_ID, 1032 DBG_PSTORM_ID, 1033 MAX_DBG_STORMS 1034 }; 1035 1036 1037 /* 1038 * Idle Check data 1039 */ 1040 struct idle_chk_data 1041 { 1042 __le32 buf_size /* Idle check buffer size in dwords */; 1043 u8 buf_size_set /* Indicates if the idle check buffer size was set (0/1) */; 1044 u8 reserved1; 1045 __le16 reserved2; 1046 }; 1047 1048 /* 1049 * Debug Tools data (per HW function) 1050 */ 1051 struct dbg_tools_data 1052 { 1053 struct dbg_grc_data grc /* GRC Dump data */; 1054 struct dbg_bus_data bus /* Debug Bus data */; 1055 struct idle_chk_data idle_chk /* Idle Check data */; 1056 u8 mode_enable[40] /* Indicates if a mode is enabled (0/1) */; 1057 u8 block_in_reset[88] /* Indicates if a block is in reset state (0/1) */; 1058 u8 chip_id /* Chip ID (from enum chip_ids) */; 1059 u8 platform_id /* Platform ID */; 1060 u8 initialized /* Indicates if the data was initialized */; 1061 u8 reserved; 1062 }; 1063 1064 1065 #endif /* __ECORE_HSI_DEBUG_TOOLS__ */ 1066